70T15L15BF [IDT]
CABGA-100, Tray;
| 型号： | 70T15L15BF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | CABGA-100, Tray |
| 文件： | 总18页 (文件大小：278K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 2.5V
16/8K X 9 DUAL-PORT
STATIC RAM
IDT70T16/5L
Features
◆
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
Busy and Interrupt Flag
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 2.5V (±100mV) power supply
Available in an 80-pin TQFP and 100-pin fpBGA
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆
◆
◆
◆
– Commercial:20/25ns(max.)
– Industrial: 25ns (max.)
Low-power operation
◆
◆
◆
◆
◆
– IDT70T16/5L
Active:200mW(typ.)
Standby: 600µW (typ.)
IDT70T16/5 easily expands data bus width to 18 bits or
◆
more using the Master/Slave select when cascading more
than one device
FunctionalBlockDiagram
OEL
OER
CER
CEL
R/WR
R/W
L
I/O0L- I/O8L
I/O0R-I/O8R
I/O
I/O
Control
Control
BUSY (2,3)
L
(2,3)
BUSY
R
(1)
(1)
13L
A
13R
A
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A0R
A0L
14
14
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
L
L
CE
OE
R/W
R
R
OE
R
R/W
L
SEM
L
(3)
SEM
R
M/S
(3)
INTL
INT
R
5663 drw 01
NOTES:
1. A13 is a NC for IDT70T15.
2. (MASTER): BUSY is output; (SLAVE): BUSY is input.
3. BUSY outputs and INT outputs are non-tri-stated push-pull drivers.
AUGUST 2004
1
DSC 5663/2
©2004 IntegratedDeviceTechnology,Inc.
IDT70T16/5L
High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
reads or writes to any location in memory. An automatic power down
featurecontrolledbyCEpermitstheon-chipcircuitryofeachporttoenter
a very low standby power mode.
FabricatedusingIDT’sCMOShigh-performancetechnology,these
devices typically operate on only 200mW of power.
The IDT70T16/5 is a high-speed 16/8K x 9 Dual-Port Static RAM.
TheIDT70T16/5isdesignedtobeusedasstand-aloneDual-PortRAMs
orasacombinationMASTER/SLAVEDual-PortRAMfor18-bit-or-more
wider systems. Using the IDT MASTER/SLAVE Dual-Port RAM ap-
proachin18-bitorwidermemorysystemapplicationsresultsinfull-speed,
error-freeoperationwithouttheneedforadditionaldiscretelogic.
This device provides two independent ports with separate control,
address,andI/Opinsthatpermitindependent,asynchronousaccessfor
TheIDT70T16/5ispackagedinan80-pinTQFP(ThinQuadFlatpack)
and a 100-pin fpBGA (fine pitch Ball Grid array) .
PinConfigurations(1,2,3,4)
07/11/02
INDEX
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
NC
1
2
NC
I/O2L
I/O3L
I/O4L
I/O5L
A5L
A4L
A3L
A2L
A1L
A0L
3
4
5
VSS
6
7
I/O6L
I/O7L
IDT70T16/5PF
INT
L
8
(5)
PN80-1
BUSY
L
9
VDD
VSS
10
11
12
13
14
15
16
17
18
19
20
NC
80-Pin TQFP
M/S
V
SS
I/O0R
I/O1R
I/O2R
(6)
Top View
BUSY
R
INT
R
A
A
A
A
A
0R
1R
2R
3R
4R
VDD
I/O3R
I/O4R
I/O5R
I/O6R
NC
NC
NC
,
5663 drw 02
NOTES:
1. A13 is a NC for IDT70T15.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 1.18 in x 1.18 in x 0.16 in.
5. This package code is used to reference the package diagram.
6. This text does not imply orientation of Part-marking.
2
6.42
IDT70T16/5L
High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinConfigurations(con't.)(1,2,3,4)
IDT70T16/5BF
BF100(5)
100-PinfpBGA
TopView(6)
08/14/02
A1
A2
A3
A6
A7
A8
A9
A4
A5
A10
A6R
A9R
A12R
VSS
NC R/W
R
NC
NC
VSS
I/O7R
B1
B2
B3
C3
B6
B7
13R
B9
B4
B5
B8
B10
(1)
A
NC
NC
A
8R
5R
2R
0R
I/O8R
A
10R
NC
OE
R
I/O6R
NC
C1
C5
C6
C2
C4
C7
C8
C9
C10
A
3R
NC
NC
A
4R
A
A
7R
CER
NC
NC I/O3R
D1
D2
D6
D9
D3
D5
D7
D8
D10
D4
A
1R INT
R
I/O5R
A
A
11R
SEM
R
NC
I/O1R
NC
NC
E5
E6
E7
E8
E9
E10
E1
E2
E3
E4
V
SS
V
SS I/O4R I/O2R I/O0R
V
DD
M/S BUSY
R
L
A
A1L
F7
F5
F6
F9
F10
F1
F2
F3
G3
H3
F8
F4
VDD
V
DD
V
SS
I/O6L I/O7L
V
SS BUSY
A0L
I/O5L
NC
G1
G5
G2
G4
G6
G8
G9
G7
G10
INT
L
NC
A
3L
NC
SEM
L
I/O3L
VSS
A
6L
NC
I/O4L
,
H7
H8
H9
H10
H5
H6
H4
H1
H2
I/O8L NC
NC I/O2L
NC
CE
L
A
10L
11L
12L
NC
A
2L
A5L
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
(1)
A13L
A4L
A8L
A
NC
NC
R/W
L
NC
VSS
I/O1L
K6
K8
K10
K5
K7
K9
K2
K4
K1
K3
VDD
NC
I/O0L
A9L
NC
VDD
NC
OEL
A7L
A
5663 drw 03
NOTES:
1. A13 is a NC for IDT70T15.
2. All VDD pins must be connected to power supply.
3. All VSS pins must be connected to ground.
4. BF-100 package body is approximately 10mm x 10mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
6.432
IDT70T16/5L
High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinNames
Left Port
Right Port
Names
Chip Enable
CE
R/W
OE
L
CE
R/W
OE
R
L
R
Read/Write Enable
Output Enable
Address
L
R
(1)
(1)
A
0L - A13L
A
0R - A13R
I/O0R - I/O8R
SEM
INT
BUSY
M/S
I/O0L - I/O8L
SEM
INT
BUSY
Data Input/Output
Semaphore Enable
Interrupt Flag
L
R
L
R
Busy Flag
L
R
Master or Slave Select
Power (2.5V)
V
DD
SS
V
Ground (0V)
5663 tbl 01
NOTE:
1. A13 is a NC for IDT70T15.
Truth Table I: Non-Contention Read/Write Control
Inputs(1)
R/W
Outputs
I/O0-8
Mode
CE
H
L
OE
X
SEM
H
X
L
High-Z
DATAIN
DATAOUT
High-Z
Deselcted: Power-Down
Write to Memory
Read Memory
X
H
L
H
X
L
H
X
H
X
Outputs Disabled
5663 tbl 02
NOTE:
1.
Condition: A0L — A13L ≠ A0R — A13R
Truth Table II: Semaphore Read/Write Control(1)
Inputs
Outputs
R/W
H
I/O0-8
Mode
- I/O
CE
H
OE
L
SEM
L
L
L
DATAOUT
Read Semaphore Flag Data Out (I/O
Write I/O into Semaphore Flag
Not Allowed
0
8)
H
X
DATAIN
0
↑
____
L
X
X
5663 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all I/Os (I/O0-I/O8). These eight semaphores are addressed by A0 - A2.
4
6.42
IDT70T16/5L
High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AbsoluteMaximumRatings(1)
MaximumOperating
TemperatureandSupplyVoltage(1)
Symbol
Rating
Commercial
& Industrial
Unit
V
Grade
Ambient
Temperature
GND
V
DD
(2 )
Terminal Voltage
with Respect to GND
-0.5 to +3.6
-55 to +125
V
TERM
Commercial
0OC to +70OC
0V
0V
2.5V
2.5V
+
+
100mV
100mV
Temperature Under Bias
oC
(3)
T
BIAS
STG
JN
OUT
Industrial
-40OC to +85OC
T
Storage Temperature
Junction Temperature
DC Output Current
-65 to +150
+150
oC
oC
5663 tbl 05
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
T
I
50
mA
5663 tbl 04
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above
those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
RecommendedDCOperating
Conditions
2. VTERM must not exceed VDD+ 0.3V.
3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected.
Symbol
Parameter
Supply Voltage
Ground
Min.
2.4
Typ.
Max.
2.6
Unit
V
V
V
DD
SS
2.5
0
0
0
V
DD+0.3(2)
0.7
V
____
V
IH
IL
Input High Voltage
Input Low Voltage
1.7
V
-0.3(1)
V
____
V
5663 tbl 06
NOTES:
Capacitance(1)(TA =+25°C, f=1.0MHz)
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed VDD + 0.3V.
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions
IN = 0V
OUT = 0V
Max. Unit
CIN
V
9
pF
(2)
OUT
C
V
10
pF
5663 tbl 07
NOTES:
1. This parameter is determined by device characteristics but is not production
tested.
2. COUT also references CI/O.
DC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)
70T16/5L
Symbol
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
Min.
Max.
Unit
µA
µA
V
___
|ILI|
V
DD = 2.6V, VIN = 0V to VDD
5
5
___
___
|ILO
|
CE = VIH, VOUT = 0V to VDD
OL = +2mA
V
V
OL
OH
I
0.4
___
Output High Voltage
IOH = -2mA
2.0
V
5663 tbl 08
NOTE:
1. At VDD < 2.0V, Input leakages are undefined.
6.452
IDT70T16/5L
High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(VDD = 2.5V ± 100mV)
70T16/5L20
Com'l Only
70T16/5L25
Com'l
& Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
Max.
Typ.(2)
Max.
Unit
IDD
Dynamic Operating
Current
(Both Ports Active)
mA
L
L
L
L
80
140
70
100
7
130
160
17
CE = VIL, Outputs Disabled
SEM = VIH
(3)
____
____
IND
f = fMAX
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
mA
mA
COM'L
IND
12
20
CE
R
SEM
and CE
L
= VIH
L = VIH
R
= SEM
(3)
____
____
12
25
f = fMAX
(1)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
f=fMAX
L
L
55
90
40
55
80
(3)
____
IND
----
100
SEMR
= SEML = VIH
I
SB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CE
CE > VDD - 0.2V,
IN > VDD - 0.2V or
IN < 0.2V, f = 0(4)
SEM = SEM > VDD-0.2V
L
and
mA
mA
COM'L
L
L
L
L
0.05
2.5
0.05
0.2
40
2.5
5.0
80
R
V
V
____
____
IND
R
L
ISB4
Full Standby Current
(One Port -
CMOS Level Inputs)
CE"A" < 0.2V and
COM'L
CE"B" > VDD - 0.2V(1)
55
90
SEM
R
= SEML > VDD-0.2V
V
IN > VDD - 0.2V or VIN < 0.2V
____
____
IND
55
100
Active Port Outputs Disabled,
f = fMAX
(3)
5663 tbl 09
NOTES:
1. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
2. DD = 2.5V, TA = +25°C, and are not production tested. IDD dc = 85mA (typ.)
V
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
4. f = 0 means no address or control lines change.
OutputLoadsand
AC Test Conditions
50Ω
50Ω
Input Pulse Levels
GND to 2.5V
3ns Max.
1.25V
,
DATAOUT
1.25V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
BUSY
INT
10pF / 5pF*
(Tester)
1.25V
5663 drw 04
Figures 1
Figure 1. AC Output Test Load
*(For tLZ, tHZ, tWZ, tOW)
5663 tbl 10
Timing of Power-Up / Power-Down
CE
t
PU
tPD
I
CC
50%
50%
I
SB
,
5663 drw 06
6
6.42
IDT70T16/5L
High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange
70T16/5L20
Com'l Only
70T16/5L25
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
t
RC
AA
ACE
ABE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
20
25
ns
ns
ns
____
____
t
Address Access Time
20
20
20
25
25
25
____
____
____
____
____
____
Chip Enable Access Time(3 )
Byte Enable Access Time(3 )
t
t
ns
ns
ns
ns
ns
ns
ns
ns
Output Enable Access Time(3)
Output Hold from Address Change
Output Low-Z Time(1,2)
t
12
13
____
____
t
3
3
____
____
t
3
3
____
____
Output High-Z Time(1,2)
t
12
15
____
____
Chip Enable to Power Up Time(1,2)
t
0
0
____
____
Chip Disable to Power Down Time(1,2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access(3)
t
20
25
____
____
t
10
10
____
____
t
20
25
ns
5663 tbl 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure1).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
Waveform of Read Cycles(5)
t
RC
ADDR
(4)
AA
t
t
(4)
ACE
CE
OE
(4)
tAOE
R/W
(1)
tOH
tLZ
(4)
DATAOUT
VALID DATA
(2)
t
HZ
BUSYOUT
(3,4)
5663 drw 05
tBDD
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY
has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last: tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6.472
IDT70T16/5L
High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage
70T16/5L20
Com'l Only
70T16/5L25
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
20
15
15
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
t
t
15
0
20
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
t
15
15
____
____
t
12
15
____
____
t
0
0
Write Enable to Output in High-Z(1,2)
Output Active from End-of-Write(1, 2,4 )
SEM Flag Write to Read Time
SEM Flag Contention Window
12
15
____
____
t
____
____
t
0
5
5
0
5
5
____
____
____
____
t
t
ns
5663 tbl 12
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 1).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over
voltage and temperature, the actual tDH will always be smaller than the actual tOW.
8
6.42
IDT70T16/5L
High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
tWC
ADDRESS
(7)
t
HZ
OE
tAW
CE or SEM(9)
(7)
t
HZ
(3)
(6)
(2)
t
WR
t
AS
tWP
R/W
(7)
t
LZ
tOW
tWZ
(4)
(4)
OUT
DATA
tDH
t
DW
IN
DATA
,
5663 drw 07
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
t
WC
ADDRESS
t
AW
CE or SEM(9)
R/W
(6)
AS
(3)
(2)
t
WR
t
tEW
t
DW
tDH
DATAIN
5663 drw 08
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 1).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be
placed on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as
the specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
6.492
IDT70T16/5L
High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
VALID ADDRESS
VALID ADDRESS
t
A0-A2
tWR
tAW
ACE
t
EW
SEM
I/O
t
OH
tDW
tSOP
DATAIN
VALID
DATAOUT
VALID(2)
tAS
tWP
t
DH
R/W
t
AOE
tSWRD
OE
Read Cycle
Write Cycle
5663 drw 09
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O8) equal to the semaphore value.
Timing Waveform of Semaphore Write Condition(1,3,4)
A0"A"-A2 "A"
MATCH
SIDE(2) "A"
R/W"A"
SEM"A"
tSPS
A0"B"-A2 "B"
MATCH
SIDE(2)
"B"
R/W"B"
SEM"B"
5663 drw 10
NOTES:
1. DOR = DOL =VIH, CER = CEL =VIH.
2. All timing is the same for left and right ports. Port“A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will obtain the semaphore flag.
10
6.42
IDT70T16/5L
High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange
70T16/5L20
Com'l Only
70T16/5L25
Com'l
& Ind
Symbol
BUSY TIMING (M/S = VIH
Parameter
Min.
Max.
Min.
Max.
Unit
)
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable LOW
BUSY Disable Time from Chip Enable HIGH
Arbitration Priority Set-up Time(2)
t
t
t
17
17
____
____
t
5
5
____
____
BUSY Disable to Valid Data(3)
t
30
30
(5)
____
____
t
Write Hold After BUSY
15
17
BUSY TIMING (M/S = VIL
)
____
____
____
____
BUSY Input to Write(4)
t
WB
0
0
ns
ns
(5)
tWH
Write Hold After BUSY
15
17
PORT-TO-PORT DELAY TIMING
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
45
35
50
35
ns
tDDD
Write Data Valid to Read Data Delay(1)
ns
5663 tbl 13
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveformof Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on Port "B" during contention on Port "A".
5. To ensure that a write cycle is completed on Port "B" after contention on Port "A".
6. 'X' in part numbers indicates power rating (S or L).
Timing Waveform of Read with BUSY(2,4,5) (M/S = VIH)
tWC
MATCH
ADDR"A"
tWP
R/W"A"
tDH
tDW
VALID
DATAIN "A"
(1)
tAPS
MATCH
ADDR"B"
tBDD
tBDA
BUSY"B"
tWDD
DATAOUT "B"
VALID
(3)
t
DDD
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S=VIL.
5663 drw 11
2. CEL = CER = VIL.
3. OE = VIL for the reading port.
4. If M/S=VIL (SLAVE), BUSY is an input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A".
6.1412
IDT70T16/5L
High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY(3)
t
WP
R/W"A"
tWB
BUSY"B"
(1)
tWH
R/W"B"
(2)
5663 drw 12
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A".
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
(2)
t
APS
CE"B"
t
BAC
t
BDC
BUSY"B"
5663 drw 13
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
ADDRESS "N"
ADDR"A"
ADDR"B"
BUSY"B"
(2)
tAPS
MATCHING ADDRESS "N"
tBAA
tBDA
5663 drw 14
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
12
6.42
IDT70T16/5L
High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange
70T16/5L20
Com'l Only
70T16/5L25
Com'l
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
ns
ns
ns
t
0
0
____
____
t
20
20
20
20
____
____
t
Interrupt Reset Time
ns
5663 tbl 14
Waveform of Interrupt Timing(1)
tWC
INTERRUPT SET ADDRESS (2)
ADDR"A"
(4)
(3)
tWR
t
AS
CE"A"
R/W"A"
INT"B"
(3)
tINS
5663 drw 15
t
RC
INTERRUPT CLEAR ADDRESS (2)
ADDR"B"
CE"B"
(3)
tAS
OE"B"
(3)
tINR
INT"B"
5663 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
6.1432
IDT70T16/5L
High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table III — Interrupt Flag(1)
Left Port
Right Port
OE
R/W
L
A13L-A0L
R/WR
A
13R-A0R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
CEL
OEL
INTL
CER
R
INTR
L
X
X
X
L
X
X
L
X
3FFF(4)
X
X
X
L
X
L
X
L(2)
H(3)
X
R
X
X
X
X
X
3FFF(4)
3FFE(4)
X
R
X
L(3)
H(2)
L
L
X
X
L
L
3FFE(4)
X
X
X
L
5663 tbl 15
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. A13 is a NC for IDT70T15, therefore Interrupt Addresses are 1FFF and 1FFE.
Truth Table IV — Address BUSY
Arbitration
Inputs
Outputs
(4)
A
OL-A13L
(1)
(1)
A
OR-A13R
Function
Normal
Normal
Normal
CE
L
CE
R
BUSY
L
BUSYR
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
H
MATCH
H
H
MATCH
(2)
(2)
Write Inhibit(3 )
5663 tbl 16
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the
IDT70T16/5 are push-pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. A13 is a NC for IDT70T15. Address comparison will be for A0 - A12.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0
- D8
Left
D0
- D8
Right
Status
No Action
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
NOTES:
0
0
1
1
0
1
1
1
0
1
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
5663 tbl 17
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70T16/5.
2. There are eight semaphore flags written to via I/O0 and read from all I/Os (I/O0 - I/O8). These eight semaphores are addressed by A0 - A2.
e. CE = VIH, SEM = VIL to access the semaphores. Refer to the semaphore Read/Write Truth Table.
14
6.42
IDT70T16/5L
High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
CE
MASTER
Dual Port
RAM
CE
SLAVE
Dual Port
RAM
BUSY (R)
BUSY (L)
BUSY (L)
BUSY (R)
MASTER
Dual Port
RAM
CE
SLAVE
Dual Port
RAM
CE
BUSY (R)
BUSY (L) BUSY (R)
BUSY (L) BUSY (R)
BUSY (L)
5663 drw 17
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70T16/5 RAMs.
the BUSY pins HIGH. If desired, unintended write operations can be
FunctionalDescription
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT70T16/5 RAM in master mode, are
push-pulltypeoutputsanddonotrequirepullupresistorstooperate. If
theseRAMsarebeingexpandedindepth,thentheBUSYindicationfor
the resulting array requires the use of an external AND gate.
The IDT70T16/5 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70T16/5 has an automatic power down
featurecontrolledbyCE.TheCEcontrolson-chippowerdowncircuitry
thatpermitstherespectiveporttogointoastandbymodewhennotselected
(CE HIGH). Whenaportisenabled, accesstotheentirememoryarray
ispermitted.
WidthExpansionBusyLogic
Master/SlaveArrays
When expanding an IDT70T16/5 RAM array in width while using
BUSYlogic, one master part is used to decide which side of the RAM
arraywillreceivea BUSYindication, andtooutputthatindication. Any
number of slaves to be addressed in the same address range as the
master use the BUSYsignal as a write inhibit signal. Thus on the
IDT70T16/5 RAM the BUSY pin is an output if the part is used as a
master (M/S pin = H), and the BUSY pin is an input if the part used as
a slave (M/S pin = L) as shown in Figure 3.
Interrupts
Iftheuserchoosestheinterruptfunction,amemorylocation(mail
box or message center) is assigned to each port. The left port
interruptflag(INTL)isassertedwhentherightportwritestomemory
location 3FFE where a write is defined as the CE = R/W = VIL per
Truth Table III. The left port clears the interrupt by an address location
3FFE access when CER =OER =VIL, R/W is a "don't care". Likewise,
the right port interrupt flag (INTR) is asserted when the left port writes
to memory location 3FFF(1FFE or 1FFF for IDT70T15) and to clear
theinterrupt flag(INTR), theright portmustaccessmemorylocation
3FFF. The message (9 bits) at 3FFE or 3FFF(1FFE or 1FFF for
IDT70T15) is user-defined since it is in an addressable SRAM
location.Iftheinterruptfunctionisnotused,addresslocations3FFE
and 3FFF (1FFE or 1FFF for IDT70T15) are not used as mail boxes
but are still part of the random access memory. Refer to Truth Table
IIIfortheinterruptoperation.
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit
decisioncouldresultwithonemasterindicatingBUSYononesideofthe
arrayandanothermasterindicatingBUSYononeothersideofthearray.
Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand
inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.
TheBUSYarbitration,onamaster,isbasedonthechipenableand
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite
pulsecanbeinitiatedwiththeR/Wsignal.Failuretoobservethistimingcan
result in a glitched internal write inhibit signal and corrupted data in the
slave.
BusyLogic
BusyLogicprovidesahardwareindicationthatbothportsoftheRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“busy”.
The BUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally
topreventthewritefromproceeding.
Semaphores
The IDT70T16/5 are extremely fast Dual-Port 16/8Kx9 Static RAMs
withanadditional8addresslocationsdedicatedtobinarysemaphoreflags.
TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-Port
RAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefinedby
thesystemdesigner’ssoftware.Asanexample,thesemaphorecanbe
usedbyoneprocessortoinhibittheotherfromaccessingaportionofthe
Dual-Port RAM or any other shared resource.
TheuseofBUSYlogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
and use any BUSYindication as an interrupt source to flag the event of
anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis
notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave
modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely
asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying
The Dual-Port RAM features a fast access time, and both ports are
completelyindependentofeachother.Thismeansthattheactivityonthe
leftportinnowayslowstheaccesstimeoftherightport. Bothportsare
6.1452
IDT70T16/5L
High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero
on that side and a one on the other side (see Truth Table V). That
semaphorecannowonlybemodifiedbythesideshowingthezero.When
aoneiswrittenintothesamelocationfromthesameside,theflagwillbe
settoaoneforbothsides(unlessasemaphorerequestfromtheotherside
ispending)andthencanbewrittentobybothsides.Thefactthattheside
which is able to write a zero into a semaphore subsequently locks out
writes from the other side is what makes semaphore flags useful in
interprocessorcommunications.(Athoroughdiscussionontheuseofthis
featurefollowsshortly.)Azerowrittenintothesamelocationfromtheother
side will be stored in the semaphore request latch for that side until the
semaphoreisfreedbythefirstside.
Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso
thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining
azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput
registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)
signalsgoactive.Thisservestodisallowthesemaphorefromchanging
stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.
Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust
cause either signal (SEM or OE) to go inactive or the output will never
change.
AsequenceWRITE/READmustbeusedbythesemaphoreinorder
to guarantee that no system level contention will occur. A processor
requestsaccesstosharedresourcesbyattemptingtowriteazerointoa
semaphorelocation.Ifthesemaphoreisalreadyinuse,thesemaphore
requestlatchwillcontainazero,yetthesemaphoreflagwillappearasone,
afactwhichtheprocessorwillverifybythesubsequentread(seeTruth
TableV).Asanexample,assumeaprocessorwritesazerototheleftport
atafreesemaphorelocation.Onasubsequentread,theprocessorwill
verifythatithaswrittensuccessfullytothatlocationandwillassumecontrol
overtheresourceinquestion.Meanwhile,ifaprocessorontherightside
attemptstowriteazerotothesamesemaphoreflagitwillfail, aswillbe
verifiedbythefactthataonewillbereadfromthatsemaphoreontheright
side during subsequent read. Had a sequence of READ/WRITE been
used instead,systemcontentionproblemscouldhaveoccurredduring
the gap between the read and write cycles.
Itisimportanttonotethatafailedsemaphorerequestmustbefollowed
byeitherrepeatedreadsorbywritingaoneintothesamelocation. The
reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram
ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother
sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame
semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch
havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip
overtotheothersideassoonasaoneiswrittenintothefirstside’srequest
latch.Thesecondside’sflagwillnowstayLOWuntilitssemaphorerequest
latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphorerequestlatch.
identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,
orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphorelocation.Semaphoresareprotectedagainstsuchambiguous
situationsandmaybeusedbythesystemprogramtoavoidanyconflicts
inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave
anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM
enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol
on-chip power down circuitry that permits the respective port to go into
standbymodewhennotselected. Thisistheconditionwhichisshownin
Truth Table I where CE and SEM are both HIGH.
SystemswhichcanbestusetheIDT70T16/5containmultipleproces-
sorsorcontrollersandaretypicallyveryhigh-speedsystemswhichare
softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom
a performance increase offered by the IDT70T16/5's hardware sema-
phores,whichprovidealockoutmechanismwithoutrequiringcomplex
programming.
Softwarehandshakingbetweenprocessorsoffersthemaximumin
systemflexibilitybypermittingsharedresourcestobeallocatedinvarying
configurations. The IDT70T16/5 does not use its semaphore flags to
control any resources through hardware, thus allowing the system
designertotalflexibilityinsystemarchitecture.
An advantage of using semaphores rather than the more common
methodsofhardwarearbitrationisthatwaitstatesareneverincurredin
either processor. This can prove to be a major advantage in very high-
speedsystems.
How the Semaphore Flags Work
Thesemaphorelogicisasetofeightlatcheswhichareindependent
oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken,
fromoneporttotheothertoindicatethatasharedresourceisinuse.The
semaphores provide a hardware assist for a use assignment method
called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore
latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft
processorwantstousethisresource,itrequeststhetokenbysettingthe
latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading
it. If it was successful, it proceeds to assume control over the shared
resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe
rightsideprocessorhassetthelatchfirst, hasthetokenandisusingthe
sharedresource.Theleftprocessorcantheneitherrepeatedlyrequest
that semaphore’s status or remove its request for that semaphore to
performanothertaskandoccasionallyattemptagaintogaincontrolofthe
tokenviathesetandtestsequence.Oncetherightsidehasrelinquished
thetoken,theleftsideshouldsucceedingainingcontrol.
ThesemaphoreflagsareactiveLOW.Atokenisrequestedbywriting
azerointoasemaphorelatchandisreleasedwhenthesamesidewrites
aonetothatlatch.
TheeightsemaphoreflagsresidewithintheIDT70T16/5inaseparate
memoryspacefromtheDual-PortRAM.This addressspaceisaccessed
byplacingaLOWinputontheSEMpin(whichactsasachipselectforthe
semaphore flags) and using the other control pins (Address, OE, and
R/W) as they would be used in accessing a standard static RAM. Each
oftheflagshasauniqueaddresswhichcanbeaccessedbyeitherside
throughaddresspinsA0–A2.Whenaccessingthesemaphores,noneof
theotheraddresspinshasanyeffect.
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphorelogicisspeciallydesignedtoresolvethisproblem.Ifsimulta-
neousrequestsaremade,thelogicguaranteesthatonlyonesidereceives
thetoken.Ifonesideisearlierthantheotherinmakingtherequest,thefirst
Whenwritingtoasemaphore,onlydatapinD0 isused.Ifalowlevel
16
6.42
IDT70T16/5L
High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
sidetomaketherequestwillreceivethetoken.Ifbothrequestsarriveat
Once the left side was finished with its task, it would write a one to
thesametime,theassignmentwillbearbitrarilymadetooneportorthe Semaphore 0 and may then try to gain access to Semaphore 1. If
other. Semaphore1wasstilloccupiedbytherightside,theleftsidecouldundo
One caution that should be noted when using semaphores is that itssemaphorerequestandperformothertasksuntilitwasabletowrite,then
semaphoresalonedonotguaranteethataccesstoaresourceissecure. readazerointoSemaphore1.Iftherightprocessorperformsasimilartask
Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused withSemaphore0,thisprotocolwouldallowthetwoprocessorstoswap
or misinterpreted, a software error can easily happen.
8K blocks of Dual-Port RAM with each other.
Initializationofthesemaphoresisnotautomaticandmustbehandled
The blocks do not have to be any particular size and can even be
viatheinitializationprogramatpower-up.Sinceanysemaphorerequest variable, depending upon the complexity of the software using the
flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth semaphoreflags.AlleightsemaphorescouldbeusedtodividetheDual-
sidesshouldhaveaonewrittenintothematinitializationfrombothsides Port RAM or other shared resources into eight parts. Semaphores can
to assure that they will be free when needed.
evenbeassigneddifferentmeaningsondifferentsidesratherthanbeing
given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaceswheretheCPUmustbelockedoutofasectionofmemoryduring
atransferandtheI/Odevicecannottolerateanywaitstates.Withtheuse
ofsemaphores,oncethetwodeviceshasdeterminedwhichmemoryarea
was“off-limits”totheCPU,boththeCPUandtheI/Odevicescouldaccess
theirassignedportionsofmemorycontinuouslywithoutanywaitstates.
Semaphoresarealsousefulinapplicationswherenomemory“WAIT”
stateisavailableononeorbothsides.Onceasemaphorehandshakehas
been performed, both processors can access their assigned RAM
segmentsatfullspeed.
Anotherapplicationisintheareaofcomplexdatastructures.Inthis
case,blockarbitrationisveryimportant.Forthisapplicationoneprocessor
mayberesponsibleforbuildingandupdatingadatastructure.Theother
processorthenreadsandinterpretsthatdatastructure.Iftheinterpreting
processorreadsanincompletedatastructure,amajorerrorconditionmay
exist.Therefore,somesortofarbitrationmustbeusedbetweenthetwo
differentprocessors.Thebuildingprocessorarbitratesfortheblock,locks
itandthenisabletogoinandupdatethedatastructure.Whentheupdate
is completed, the data structure block is released. This allows the
interpretingprocessortocomebackandreadthecompletedatastructure,
therebyguaranteeingaconsistentdatastructure.
UsingSemaphores—SomeExamples
Perhapsthesimplestapplicationofsemaphoresistheirapplicationas
resource markers for the IDT70T16/5’s Dual-Port RAM. Say the 16K x
9RAMwastobedividedintotwo8Kx9blockswhichweretobededicated
atanyonetimetoservicingeithertheleftorrightport.Semaphore0could
be used to indicate the side which would control the lower section of
memory,andSemaphore1couldbedefinedastheindicatorfortheupper
sectionofmemory.
Totakearesource, inthisexamplethelower8KofDual-PortRAM,
the processor on the left port could write and then read a zero in to
Semaphore0.Ifthistaskweresuccessfullycompleted(azerowasread
back rather than a one), the left processor would assume control of the
lower8K.Meanwhiletherightprocessorwasattemptingtogaincontrolof
theresourceaftertheleftprocessor,itwouldreadbackaoneinresponse
tothezeroithadattemptedtowriteintoSemaphore0. Atthispoint, the
softwarecouldchoosetotryandgaincontrolofthesecond8Ksectionby
writing,thenreadingazerointoSemaphore1.Ifitsucceededingaining
control,itwouldlockouttheleftside.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
0
D
0
D
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
,
5663 drw 18
Figure 4. IDT70T16/5 Semaphore Logic
6.1472
IDT70T16/5L
High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
OrderingInformation
IDT XXXXX
A
999
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
(1)
PF
BF
80-pin TQFP (PN80-1)
100-pin fpBGA (BF100)
Commercial Only
Commercial & Industrial
,
20
25
Speed in Nanoseconds
L
Low Power
70T16 144K (16K x 9) 2.5V Dual-Port RAM
70T15
72K (4K x 9) 2.5V Dual-Port RAM
5663 drw 19
NOTE:
1. Contact your local sales office for industrial temp range for other speeds, packages and powers.
DatasheetDocumentHistory
08/15/02:
08/23/04:
InitialPublicRelease
Removed"Preliminary"status
Page5 UpdatedCapacitancetable
Page 9 Updated Timing Waveform of Write Cycle No. 1, R/W Controlled Timing drawing
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for Tech Support:
831-754-4613
DualPortHelp@idt.com
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
18
6.42
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