70T3319S166BFGI [IDT]
HIGH-SPEED SYNCHRONOUS DUAL-PORT STATIC RAM;
| 型号： | 70T3319S166BFGI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED SYNCHRONOUS DUAL-PORT STATIC RAM |
| 文件： | 总27页 (文件大小：342K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 2.5V
512/256/128K X 18
SYNCHRONOUS
IDT70T3339/19/99S
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
– 1.5ns setup to clock and 0.5ns hold on all control, data,
and address inputs @ 200MHz
– Self-timedwriteallowsfastcycletime
Separate byte controls for multiplexed bus and bus
matching compatibility
Dual Cycle Deselect (DCD) for Pipelined Output Mode
2.5V ( 100mV) power supply for core
LVTTL compatible, selectable 3.3V ( 150mV) or 2.5V
( 100mV) power supply for I/Os and control signals on
each port
Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz
Available in a 256-pin Ball Grid Array (BGA) and 208-pin fine
pitch Ball Grid Array (fpBGA)
Supports JTAG features compliant with IEEE 1149.1
Green parts available, see ordering information
Features:
◆
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed data access
◆
◆
– Commercial: 3.4 (200MHz)/3.6ns (166MHz)/
4.2ns (133MHz)(max.)
◆
◆
◆
– Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Selectable Pipelined or Flow-Through output mode
Counter enable and repeat features
Dual chip enables allow for depth expansion without
additional logic
Interrupt and Collision Detection Flags
Full synchronous operation on both ports
– 5ns cycle time, 200MHz operation (14Gbps bandwidth)
– Fast 3.4ns clock to data out
◆
◆
◆
◆
◆
◆
◆
◆
◆
– Data input, address, byte enable and control registers
Functional Block Diagram
UBL
UBR
LBL
LBR
FT/PIPE
L
0a 1a
a
0b 1b
b
1b 0b
b
1a 0a
a
FT/PIPER
1/0
1/0
R/WL
R/W
R
CE0L
CE0R
1
1
CE1R
CE1L
B
B
B B
0
W W
W W
0
0
L
1
L
1
0
R
R
1/0
1/0
Dout0-8_L
Dout9-17_L
Dout0-8_R
Dout9-17_R
OE
L
OER
,
0a 1a
1b 0b 1a 0a
ab
0b
1b
0/1
FT/PIPE
L
0/1
FT/PIPER
ba
512/256/128K x 18
MEMORY
ARRAY
Din_L
I/O0R - I/O17R
I/O0L - I/O17L
Din_R
,
CLK
R
CLK
L
(1)
18R
(1)
18L
A
A
Counter/
Address
Reg.
Counter/
Address
Reg.
A
0L
REPEAT
ADS
CNTEN
A
0R
REPEAT
ADS
CNTEN
ADDR_R
ADDR_L
L
R
R
L
R
L
TDI
TCK
TMS
INTERRUPT
CE
0
R
R
CE
0
JTAG
L
COLLISION
DETECTION
LOGIC
CE1
TRST
TDO
CE1
L
R/W
R
R/W
L
COL
L
COL
R
INT
L
INTR
5652 drw 01
(2)
(2)
ZZR
ZZ
ZZ
L
CONTROL
LOGIC
NOTES:
1. Address A18 is a NC for the IDT70T3319. Also, Addresses A18 and A17 are NC's for the IDT70T3399.
2. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and
OPTx and the sleep mode pins themselves (ZZx) are not affected during sleep mode.
FEBRUARY 2018
1
DSC-5652/9
©2018 Integrated Device Technology, Inc.
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70T3339/19/99 is a high-speed 512/256/128k x 18 bit tionalorbidirectionaldataflowinbursts.Anautomaticpowerdownfeature,
synchronous Dual-Port RAM. The memory array utilizes Dual-Port controlled by CE0 and CE1, permits the on-chip circuitry of each port to
memorycellstoallowsimultaneousaccessofanyaddressfrombothports. enter a very low standby power mode.
Registersoncontrol,data,andaddressinputsprovideminimalsetupand
The IDT70T3339/19/99 can support an operating voltage of either
holdtimes.Thetiminglatitudeprovidedbythisapproachallowssystems 3.3Vor2.5Vononeorbothports,controllablebytheOPTpins.Thepower
tobedesignedwithveryshortcycletimes.Withaninputdataregister,the supply for the core of the device (VDD) is at 2.5V.
IDT70T3339/19/99hasbeenoptimizedforapplicationshavingunidirec-
6.422
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration (3,4,5,6,9)
70T3339/19/99BC
BC-256(8)
256-Pin BGA
Top View(9)
A1
A2
A3
A6
A7
A8
A9
A11
A12
A13
A14
A4
A5
A10
A15
A16
NC
TDI
NC
A
11L
A
8L
9L
7L
NC CE1L
CNTEN
L
A
5L
4L
A
2L
A
0L
A
17L(2)
A
14L
OE
L
NC
NC
B1
B2
B3
B6
B7
B9
CE0L
B11
B12
B13
B4
B5
B8
B10
B14
B15
B16
A
18L(1)
A
15L
UB
L
R/W
L
VDD
NC
NC
INT
L
NC TDO
A
12L
A
REPEAT
L
A
A
1L
C1
C5
C6
C2
C3
C4
C7
C8
C9
C10
C11
C12
C13
C16
C14
C15
COL
L
A
13L
A
10L
I/O9L
V
SS
A
16L
A
NC
LBL
CLK
L
ADS
L
A6L
A
3L
I/O8L
OPT
L
NC
D1
D2
D6
D9
D11
D3
D4
D5
D7
D8
DDQR
D10
D12
D13
D14
D15
D16
NC I/O9R
DDQL VDDQL
V
DDQL
V
DDQR
NC PIPE/FT
L
V
V
DDQR
V
VDDQL
VDDQR
VDD
NC
NC I/O8R
E5
E6
E7
E8
E9
E10
E11
E12
E13
E1
E2
E3
E4
E14
E16
E15
V
DD
V
DD
NC
V
SS
SS
SS
SS
V
SS
SS
SS
V
SS
V
DD
V
DD
V
DDQR
I/O10R I/O10L NC
V
DDQL
NC
I/O7R
I/O7L
F7
F3
F5
F6
F9
F10
F1
F2
F11
F13
F14
F15
F16
F8
F12
F4
NC
I/O11L NC I/O11R
VDD
NC
V
V
SS
I/O6R NC I/O6L
DDQR
VSS
V
V
DDQL
V
VDD
G1
G2
G3
G5
H5
G4
G6
G8
G9
G14
G15
G16
G7
G10
G12
G13
G11
NC
V
SS
NC
V
DDQR
VSS
V
V
I/O12L
I/O5L NC
DDQL
NC
VSS
V
SS
VSS
V
VSS
H11
H12
H16
H13
H6
H7
H8
H9
H10
H14
H15
H3
H4
H1
H2
V
SS
VSS
I/O5R
V
DDQL
V
SS
VSS
V
VSS
V
SS
SS
NC
NC
NC
V
DDQR
V
SS
NC I/O12R
J1
J2
J3
J4
J5
J6
J7
J8
J9
J13
J10
J11
J12
J14
J15
J16
I/O13L
ZZ
R
I/O14R I/O13R
V
DDQL
V
SS
VSS
V
SS
SS
V
SS
V
DDQR
I/O4R
V
VSS
ZZL
I/O3R I/O4L
K6
K8
K10
K12
K13
K2
K4
K5
K7
K9
K11
K15
K16
K1
K3
K14
V
SS
V
V
SS
SS
VSS
V
DDQR
NC
V
DDQL
V
SS
VSS
V
SS
VSS
NC I/O3L
NC
I/O14L
NC
L7
L8
L11
L12
L13
L5
L6
L9
L10
L3
L4
L15
L16
L1
L2
L14
NC
V
SS
VSS
VDD
V
DDQL
I/O15R
V
DDQR
V
DD
NC
V
SS
V
NC I/O2R
I/O15L NC
I/O2L
M5
M6
M7
M8
M9
M10
M11
M12
M13
M1
M2
M3
M4
M16
M14
M15
V
DD
V
DD
NC
V
SS
V
SS
V
SS
VDD
VDD
V
DDQL
I/O16R I/O16L NC
V
DDQR
NC
I/O1R I/O1L
N8
N12
N13
N16
N5
N6
DDQR
N7
DDQL
N9
N10
N11
N4
N15
N1
N2
N3
N14
V
DDQL
VDDQL
NC
VDD
PIPE/FT
R
V
DDQR
V
V
V
DDQR
V
DDQR
V
DDQL
I/O0R
NC I/O17R NC
NC
P1
P2
P3
P4
P5
P7
P8
P9
P10
P11
P12
P14
P15
P16
P6
P13
COL
R
I/O17L TMS
A16R
A13R
A7R
NC
LBR
CLKR
ADS
R
A6R
NC
NC I/O0L
A10R
A3R
R5
R6
R7
R8
R9
R10
R11
R16
R1
R2
R3
R4
R12
R13
R14
R15
NC TRST A18R(1)
A4R
A1R OPTR
A15R
A
12R
A9R
UBR
CE0R R/W
R
REPEAT
R
NC
INTR
NC
T2
T3
T1
T4
17R(2)
T5
T8
T9
T15
T16
T6
T7
T10
T11
T12
T13
2R
T14
TCK
NC
NC
A
A
14R
NC CE1R
NC
NC
A
11R
A
8R
OE
R
CNTEN
R
A
5R
A
A
0R
5652 drw 02d
NOTES:
1. Pin is a NC for IDT70T3319 and IDT70T3399.
2. Pin is a NC for IDT70T3399.
3. All VDD pins must be connected to 2.5V power supply.
4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
5. All VSS pins must be connected to ground supply.
6. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
9. Pins A15 and T15 will be VREFL and VREFR respectively for future HSTL device.
6.42
3
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(con't)(3,4,5,6,9)
1
2
3
4
5
6
7
8
9
11 12 13 14
10
16 17
15
I/O9L
VSS
INT
L
A
16L
A
12L
A
B
C
D
E
F
V
SS
NC
A
8L
NC
V
DD
A
0L
OPT
L
NC
TDO
CLK
L
CNTEN
L
A4L
(2)
(1)
NC
COLL
VSS
A9L
TDI
A
17L
NC
CE0L
V
SS
V
DDQR I/O8L
NC
ADS
L
A
13L
NC
A5L
A1L
A18L
VDDQL I/O9R
VDDQR PIPE/FT
L
A14L
A10L
UB
L
VDD
I/O8R
CE1L
V
SS
A6L
A2L
NC
VSS
R/W
L
NC
VSS
I/O10L
NC
VDDQL
A15L
A11L
LB
L
VDD
VDD
I/O7R
NC
A7L
OE
L
A3L
I/O7L
REPEAT
L
I/O11L
NC
VDDQR I/O10R
I/O6L
NC
VSS
NC
VSS
I/O6R
VDDQL I/O11R
NC
VDDQR
NC
VSS
NC
V
SS
I/O12L
NC
NC
I/O5L
V
DDQL
NC
G
H
J
VDD
VSS
I/O5R
NC
V
DDQR I/O12R
NC
VDD
70T3339/19/99BF
BF-208(7)
ZZL
VDDQL
VSS
ZZR
V
DD
VSS
VDDQR
VDD
208-Pin fpBGA
Top View(8)
I/O3R
I/O4R
I/O14R
NC
V
SS
V
DDQL
V
SS
K
L
I/O13R
V
SS
I/O14L
NC
VDDQR I/O13L
I/O4L
NC
I/O3L
NC
VSS
VDDQL
I/O15R
NC
VSS
VSS
I/O2R
NC
V
DDQR
I/O2L
NC
M
N
P
R
T
NC
VSS
VDDQL
I/O15L
I/O1R
I/O16L
I/O16R
VDDQR
TRST
A
16R
A8R
COL
R
A
12R
NC
I/O1L
VSS
VDD
CLK
R
NC
NC
A
4R
CNTEN
R
(2)
A17R
A1R
VSS
I/O17R TCK
A
13R
CE0R
CE1R
A5R
VDDQR
NC
A9R
NC
ADS
R
I/O0R
V
SS
VDDQL
(1)
VSS
I/O17L
A18R
UBR
NC
NC
VDDQL TMS
A14R
A10R
VSS
A6R
VSS
NC
R/WR
A2R
VSS
INTR
PIPE/FT
R
LBR
VDD
I/O0L
A7R
OER
A3R
VDD
NC
A15R
A11R
REPEAT
R
OPT
R
NC
A0R
U
5652 drw 02c
NOTES:
1. Pin is a NC for IDT70T3319 and IDT70T3399.
2. Pin is a NC for IDT70T3399.
3. All VDD pins must be connected to 2.5V power supply.
4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (2.5V), and 2.5V if OPT pin for that port is
set to VSS (0V).
5. All VSS pins must be connected to ground supply.
6. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
7. This package code is used to reference the package diagram.
8. This text does not indicate orientation of the actual part-marking.
9. Pins B14 and R14 will be VREFL and VREFR respectively for future HSTL device.
6.442
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port
Right Port
CE0R CE1R
R/W
OE
Names
Chip Enables (Input)(6)
Read/Write Enable (Input)
Output Enable (Input)
Address (Input)
CE0L
R/W
OE
,
CE1L
,
L
R
L
R
(5)
(5)
A
0L - A18L
A
0R - A18R
I/O0R - I/O17R
CLK
I/O0L - I/O17L
CLK
Data Input/Output
L
R
Clock (Input)
PL/FT
L
PL/FT
ADS
R
Pipeline/Flow-Through (Input)
Address Strobe Enable (Input)
Counter Enable (Input)
Counter Repeat(3)
ADS
L
R
CNTEN
REPEAT
UB
LB
L
CNTEN
REPEAT
UB
LB
R
L
R
(6)
Upper Byte Enable (I/O
Lower Byte Enable (I/O
9 - I/O17)
L
R
(6)
0
- I/O8)
L
R
V
DDQL
V
DDQR
Power (I/O Bus) (3.3V or 2.5V)(1) (Input)
Option for selecting VDDQX(1,2) (Input)
Sleep Mode pin(4) (Input)
Power (2.5V)(1) (Input)
OPT
L
OPT
R
ZZ
L
ZZ
R
V
V
DD
SS
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
2. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VDD (2.5V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VSS (0V), then that
port's I/Os and address controls will operate at 2.5V levels and VDDQX must be
supplied at 2.5V. The OPT pins are independent of one another—both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
Ground (0V) (Input)
TDI
TDI
Test Data Input
Test Data Output
TCK
TMS
TRST
Test Logic Clock (10MHz) (Input)
Test Mode Select (Input)
Reset (Initialize TAP Controller) (Input)
Interrupt Flag (Output)
3. When REPEATX is asserted, the counter will reset to the last valid address loaded
via ADSX.
INTR
INT
L
COL
R
COL
L
Collision Alert (Output)
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when
asserted. All static inputs, i.e., PL/FTx and OPTx and the sleep mode pins
themselves (ZZx) are not affected during sleep mode. It is recommended that
boundry scan not be operated during sleep mode.
5652 tbl 01
5. Address A18x is a NC for the IDT70T3319. Also, Addresses A18x and A17x are
NC's for the IDT70T3399.
6. Chip Enables and Byte Enables are double buffered when PL/FT = VIH, i.e., the
signals take two cycles to deselect.
6.42
5
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
(1,2,3,4)
Truth Table I—Read/Write and Enable Control
Upper Byte
Lower Byte
CLK
↑
CE
X
1
R/W
X
ZZ
L
I/O9-17
High-Z
High-Z
High-Z
High-Z
I/O0-8
High-Z
High-Z
High-Z
MODE
Deselected–Power Down
Deselected–Power Down
Both Bytes Deselected
Write to Lower Byte Only
Write to Upper Byte Only
Write to Both Bytes
OE
X
X
X
X
X
X
L
CE
H
X
L
0
UB
X
X
H
H
L
LB
X
X
H
L
↑
L
X
L
↑
H
H
H
H
H
H
H
H
X
X
L
↑
L
L
L
DIN
↑
L
H
L
L
L
DIN
High-Z
↑
L
L
L
L
DIN
DIN
↑
L
H
L
L
H
H
H
X
L
High-Z
DOUT
Read Lower Byte Only
Read Upper Byte Only
Read Both Bytes
↑
L
L
H
L
L
DOUT
High-Z
↑
L
L
L
L
DOUT
DOUT
↑
H
X
L
L
L
L
High-Z
High-Z
High-Z
High-Z
Outputs Disabled
X
X
X
X
X
H
Sleep Mode
5652 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, REPEAT = X.
3. OE and ZZ are asynchronous input signals.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
(1,2)
Truth Table II—Address Counter Control
Previous
Internal
Address
Internal
Address
Used
MODE
I/O(3)
ADS
L(4)
H
CNTEN REPEAT(6)
Address
CLK
↑
An
X
X
An
An
X
H
H
DI/O (n)
External Address Used
An + 1
An + 1
An
L(5)
H
DI/O(n+1) Counter Enabled—Internal Address generation
DI/O(n+1) External Address Blocked—Counter disabled (An + 1 reused)
DI/O(n) Counter Set to last valid ADS load
↑
↑
X
An + 1
X
H
H
X
X
X
L(4)
↑
5652 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, UB, LB and OE.
3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4. ADS and REPEAT are independent of all other memory control signals including CE0, CE1, UB and LB.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, UB and LB.
6. When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded
via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.
6.462
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Maximum Operating
Temperature and Supply Voltage(1)
Ambient
Grade
Commercial
Temperature
0OC to +70OC
-40OC to +85OC
GND
0V
V
+
+
DD
2.5V
2.5V
100mV
100mV
Industrial
0V
5652 tbl 04
NOTE:
1. This is the parameter TA. This is the "instant on" case temperature.
Recommended DC Operating
Conditions with VDDQ at 2.5V
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage(3)
Ground
Min.
2.4
2.4
0
Typ.
2.5
2.5
0
Max.
2.6
2.6
0
Unit
V
V
DD
DDQ
SS
V
V
V
V
Input High Volltage
(Address, Control &
Data I/O Inputs)(3)
____
V
DDQ + 100mV(2)
1.7
1.7
V
V
V
IH
IH
Input High Voltage _
JTAG
____
V
V
DD + 100mV(2)
Input High Voltage -
ZZ, OPT, PIPE/FT
____
____
____
VIH
VIL
VIL
V
DD - 0.2V
-0.3(1)
V
DD + 100mV(2)
V
V
Input Low Voltage
0.7
0.2
Input Low Voltage -
ZZ, OPT, PIPE/FT
-0.3(1)
V
5652 tbl 05a
NOTES:
1. VIL (min.) = -1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the OPT
pin for that port must be set to Vss(0V), and VDDQX for that port must be supplied as
indicated above.
Recommended DC Operating
Conditions with VDDQ at 3.3V
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage(3)
Ground
Min.
2.4
3.15
0
Typ.
2.5
3.3
0
Max.
2.6
3.45
0
Unit
V
V
DD
DDQ
SS
V
V
V
V
Input High Voltage
(Address, Control
&Data I/O Inputs)(3)
____
2.0
1.7
V
DDQ + 150mV(2)
V
V
V
IH
IH
_
Input High Voltage
JTAG
DD + 100mV(2)
____
V
V
Input High Voltage -
ZZ, OPT, PIPE/FT
____
____
____
VIH
VIL
VIL
V
DD - 0.2V
-0.3(1)
V
DD + 100mV(2)
V
V
Input Low Voltage
0.8
0.2
Input Low Voltage -
ZZ, OPT, PIPE/FT
-0.3(1)
V
5652 tbl 05b
NOTES:
1. VIL (min.) = -1.0V for pulse width less than tCYC/2, or 5ns, whichever is less.
2. VIH (max.) = VDDQ + 1.0V for pulse width less than tCYC/2 or 5ns, whichever is less.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the OPT
pin for that port must be set to VDD (2.5V), and VDDQX for that port must be supplied
as indicated above.
6.42
7
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol
Rating
Commercial
& Industrial
Unit
V
V
TERM
VDD Terminal Voltage
with Respect to GND
-0.5 to 3.6
(VDD
)
(2)
V
(VDDQ
TERM
V
DDQ Terminal Voltage
with Respect to GND
-0.3 to VDDQ + 0.3
-0.3 to VDDQ + 0.3
V
)
(2)
VTERM
(INPUTS and I/O's)
Input and I/O Terminal
Voltage with Respect to GND
V
(3)
T
BIAS
STG
JN
Temperature Under Bias
Storage Temperature
Junction Temperature
-55 to +125
-65 to +150
+150
oC
oC
T
T
oC
IOUT(For VDDQ = 3.3V) DC Output Current
50
mA
IOUT(For VDDQ = 2.5V) DC Output Current
40
mA
5652 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. This is a steady-state DC parameter that applies after the power supply has reached its
nominal operating value. Power sequencing is not necessary; however, the voltage on
any Input or I/O pin cannot exceed VDDQ during power supply ramp up.
3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.
Capacitance(1)
(TA = +25°C, f = 1.0MHz) PQFP ONLY
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
8
pF
(3)
OUT
C
V
10.5
pF
5652 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)
70T3339/19/99S
Symbol
|ILI
|ILI
|ILO
Parameter
Test Conditions
DDQ = Max., VIN = 0V to VDDQ
DD = Max. IN = 0V to VDD
Min.
Max.
10
30
Unit
µA
µA
µA
V
___
|
Input Leakage Current(1)
V
V
___
___
___
|
JTAG & ZZ Input Leakage Current(1,2)
Output Leakage Current(1,3)
, V
|
10
CE
OL = +4mA, VDDQ = Min.
OH = -4mA, VDDQ = Min.
OL = +2mA, VDDQ = Min.
OH = -2mA, VDDQ = Min.
0 = VIH or CE1 = VIL, VOUT = 0V to VDDQ
V
V
V
V
OL (3.3V) Output Low Voltage(1)
OH (3.3V) Output High Voltage(1)
OL (2.5V) Output Low Voltage(1)
OH (2.5V) Output High Voltage(1)
I
0.4
___
I
2.4
V
___
I
0.4
V
___
I
2.0
V
5652 tbl 08
NOTES:
1. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.6 for details.
2. Applicable only for TMS, TDI and TRST inputs.
3. Outputs tested in tri-state mode.
6.482
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
(3)
Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)
70T3339/19/99
70T3339/19/99
70T3339/19/99
S133
S200
Com'l Only(8)
S166
Com'l
& Ind(7)
Com'l
& Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(4)
Max.
Typ.(4)
Max.
450
510
230
275
325
365
15
Typ.(4)
260
260
140
140
200
200
5
Max. Unit
IDD
Dynamic Operating
Current (Both
Ports Active)
CEL and CER= VIL,
S
S
S
S
S
S
S
S
S
S
S
S
375
525
320
320
175
175
250
250
5
370
450
190
235
250
310
15
mA
mA
mA
mA
mA
Outputs Disabled,
___
___
(1)
IND
f = fMAX
I
SB1(6)
Standby Current
(Both Ports - TTL
Level Inputs)
CE
L
= CE
R
= VIH
COM'L
IND
205
270
(1)
f = fMAX
___
___
SB2(6)
Standby Current
(One Port - TTL
Level Inputs)
(5)
I
CE"A" = VIL and CE"B" = VIH
COM'L
IND
300
375
Active Port Outputs Disabled,
___
___
(1)
f=fMAX
ISB3
Full Standby Current
(Both Ports - CMOS
Level Inputs)
Both Ports CE
CE
L and
COM'L
IND
5
15
R
> VDDQ - 0.2V, VIN > VDDQ - 0.2V
or VIN < 0.2V, f = 0(2)
___
___
5
20
5
20
SB4(6)
Full Standby Current
(One Port - CMOS
Level Inputs)
CE"A" < 0.2V and CE"B" > VDDQ - 0.2V(5)
IN > VDDQ - 0.2V or VIN < 0.2V
I
COM'L
IND
300
375
250
250
5
325
365
15
200
200
5
250
310
15
V
___
___
(1)
Active Port, Outputs Disabled, f = fMAX
Izz
Sleep Mode Current
(Both Ports - TTL
Level Inputs)
ZZL = ZZR =
f=fMAX
V
IH
COM'L
IND
5
15
(1)
mA
___
___
5
20
5
20
5652 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS".
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 2.5V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 15mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQ - 0.2V
CEX > VDDQ - 0.2V means CE0X > VDDQ - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
6. ISB1, ISB2 and ISB4 will all reach full standby levels (ISB3) on the appropriate port(s) if ZZL and/or ZZR = VIH.
7. 166MHz I-Temp is not available in the BF-208 package.
8. 200Mhz is not available in the BF-208 package.
6.42
9
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions (VDDQ - 3.3V/2.5V)
Input Pulse Levels (Address & Controls)
Input Pulse Levels (I/Os)
Input Rise/Fall Times
GND to 3.0V/GND to 2.4V
GND to 3.0V/GND to 2.4V
2ns
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V/1.25V
1.5V/1.25V
Figures 1 and 2
5652 tbl 10
50Ω
50Ω
,
DATAOUT
1.5V/1.25
10pF
(Tester)
5652 drw 03
Figure 1. AC Output Test load.
∆
tCD
(Typical, ns)
5652 drw 04
∆
Capacitance (pF) from AC Test Load
6.1402
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(2,3)
(Read and Write Cycle Timing)
(VDD = 2.5V ± 100mV, TA = 0°C to +70°C)
70T3339/19/99
S200
70T3339/19/99
S166
Com'l
70T3339/19/99
S133
Com'l
Com'l Only(5)
& Ind(4)
& Ind
Symbol
Parameter
Min.
15
Max.
Min.
20
Max.
Min.
25
Max.
Unit
ns
t
CYC1
CYC2
CH1
CL1
CH2
CL2
SA
HA
SC
HC
SB
HB
SW
HW
SD
HD
SAD
HAD
SCN
HCN
SRPT
HRPT
OE
Clock Cycle Time (Flow-Through)(1)
Clock Cycle Time (Pipelined)(1)
Clock High Time (Flow-Through)(1)
Clock Low Time (Flow-Through)(1)
Clock High Time (Pipelined)(2)
Clock Low Time (Pipelined)(1)
Address Setup Time
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
5
6
7.5
10
ns
t
6
8
ns
t
6
8
10
ns
t
2
2.4
2.4
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
0.5
1.7
3
ns
t
2
3
ns
t
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
1.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
0.5
1.8
ns
t
Address Hold Time
ns
t
Chip Enable Setup Time
Chip Enable Hold Time
Byte Enable Setup Time
Byte Enable Hold Time
R/W Setup Time
ns
t
ns
t
ns
t
ns
t
ns
t
R/W Hold Time
ns
t
Input Data Setup Time
ns
t
Input Data Hold Time
ns
t
ns
ADS Setup Time
t
ns
ADS Hold Time
t
ns
CNTEN Setup Time
t
ns
CNTEN Hold Time
t
ns
REPEAT Setup Time
t
0.5
0.5
0.5
ns
REPEAT Hold Time
____
____
____
t
Output Enable to Data Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Clock to Data Valid (Flow-Through)(1)
Clock to Data Valid (Pipelined)(1)
Data Output Hold After Clock High
Clock High to Output High-Z
Clock High to Output Low-Z
Interrupt Flag Set Time
4.4
4.4
4.6
ns
(6)
____
____
____
t
OLZ
1
1
1
ns
(6)
OHZ
t
1
3.4
10
1
3.6
12
1
4.2
15
ns
____
____
____
t
CD1
CD2
DC
ns
____
____
____
t
3.4
3.6
4.2
ns
____
____
____
t
1
1
1
1
1
1
ns
(6)
CKHZ
t
3.4
3.6
4.2
ns
(6)
CKLZ
____
____
____
t
1
1
1
ns
____
____
____
t
INS
INR
COLS
COLR
ZZSC
ZZRC
7
7
7
7
7
7
ns
____
____
____
____
____
____
____
____
____
t
Interrupt Flag Reset Time
Collision Flag Set Time
Collision Flag Reset Time
Sleep Mode Set Cycles
Sleep Mode Recovery Cycles
ns
t
3.4
3.6
4.2
ns
t
3.4
3.6
4.2
ns
____
____
____
t
2
3
2
3
2
3
cycles
cycles
____
____
____
t
Port-to-Port Delay
Clock-to-Clock Offset
Clock-to-Clock Offset for Collision Detection
____
____
____
t
CO
4
5
6
ns
tOFS
Please refer to Collision Detection Timing Table on Page 20
5652 tbl 11
NOTES:
1. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPEX = VDD (2.5V). Flow-through parameters (tCYC1, tCD1)
apply when FT/PIPE = Vss (0V) for that port.
2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE), FT/PIPE and OPT. FT/PIPE and OPT should be
treated as DC signals, i.e. steady state during operation.
3. These values are valid for either level of VDDQ (3.3V/2.5V). See page 5 for details on selecting the desired operating voltage levels for each port.
4. 166MHz I-Temp is not available in the BF-208 package.
5. 200Mhz is not available in the BF-208 package.
6. Guaranteed by design (not production tested).
6.42
11
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation
(FT/PIPE'X' = VIH)(2)
t
CYC2
t
CH2
t
CL2
CLK
CE
0
t
SC
(3)
tHC
tSC
tHC
CE1
t
SB
tHB
tSB
tHB
(5)
UB, LB
R/
W
tHW
tSW
t
SA
tHA
ADDRESS(4)
DATAOUT
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
t
DC
t
CD2
Qn + 1
Qn + 2(5)
(1)
tCKLZ
t
OHZ
tOLZ
(1)
OE
,
t
OE
5652 drw 05
Timing Waveform of Read Cycle for Flow-through Output
(FT/PIPE"X" = VIL)(2,6)
tCYC1
tCH1
tCL1
CLK
CE
0
tSC
(3)
tHC
tSC tHC
CE1
tSB
tHB
tHB
UB, LB
tSB
R/
W
tSW tHW
tSA tHA
ADDRESS(4)
DATAOUT
An
An + 1
An + 2
An + 3
tDC
tCD1
tCKHZ
Qn
Qn + 1
Qn + 2(5)
tCKLZ
tDC
tOHZ
tOLZ
tOE
(1)
OE
,
5652 drw 06
NOTES:
1. OE is asynchronously controlled; all other inputs depicted in the above waveforms are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and REPEAT = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, UB, LB = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If UB, LB was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
6. "x" denotes Left or Right port. The diagram is with respect to that port.
6.1422
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Multi-Device Pipelined Read(1,2)
t
CYC2
t
CH2
t
CL2
CLK
ADDRESS(B1)
CE0(B1)
t
SA
t
HA
A
6
A
5
A4
A
3
A
2
A
0
A1
t
SC
t
HC
t
SC
t
HC
t
CD2
t
CD2
t
CKHZ
t
CD2
Q
0
Q3
Q
1
DATAOUT(B1)
ADDRESS(B2)
t
DC
t
CKLZ
t
DC
t
CKHZ
t
SA
t
HA
A
6
A
5
A
4
A
3
A
2
A
0
A
1
t
SC
t
HC
CE0(B2)
t
SC
t
HC
t
CD2
t
CKHZ
t
CD2
,
DATAOUT(B2)
Q
4
Q
2
t
CKLZ
t
CKLZ
5652 drw 07
Timing Waveform of a Multi-Device Flow-Through Read(1,2)
t
CYC1
tCH1
tCL1
CLK
t
SA
tH
A
A6
A5
A4
A3
A2
A0
A1
ADDRESS(B1)
t
SC
tHC
CE0(B1)
t
SC
tHC
(1)
tCD1
tCD1
t
CKHZ
t
CD1
(1)
tCD1
D0
D3
D5
D1
DATAOUT(B1)
ADDRESS(B2)
(1)
(1)
tDC
t
CKLZ
tCKLZ
t
DC
t
CKHZ
t
SA
tHA
A6
A5
A4
A3
A2
A
0
A1
t
SC
tHC
CE0(B2)
t
SC
t
HC
(1)
(1)
t
CD1
t
CKHZ
t
CD1
(1)
t
CKHZ
D4
DATAOUT(B2)
D2
(1)
,
t
CKLZ
tCKLZ
5652 drw 08
NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70T3339/19/99 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. UB, LB, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and REPEAT = VIH.
6.42
13
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Left Port Write to Pipelined Right Port Read(1,2,4)
CLK"A"
t
SW
tHW
R/W"A
"
tSA
t
HA
NO
MATC
H
ADDRESS"A"
DATAIN"A"
MATC
H
t
SD
t
HD
VALID
(3)
CO
t
CLK"B"
t
CD2
R/W"B"
t
SW
t
HW
HA
t
SA
t
NO
ADDRESS"B"
DATAOUT"B"
MATC
H
MATCH
VALID
,
tDC
5652 drw 09
NOTES:
1. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for Port "B", which is being read from. OE = VIH for Port "A", which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (ie, time from write to valid read on opposite port will be
tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (ie, time from write to valid read on opposite port
will be tCO + tCYC2 + tCD2).
4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"
Timing Waveform with Port-to-Port Flow-Through Read(1,2,4)
CLK "A"
tSW tHW
R/W "A"
tSA tHA
NO
ADDRESS "A"
DATAIN "A"
CLK "B"
MATCH
MATCH
tSD tHD
VALID
(3)
tCO
tCD1
R/W "B"
tHW
tHA
tSW
tSA
NO
MATCH
ADDRESS "B"
DATAOUT "B"
MATCH
tCD1
VALID
VALID
,
tDC
tDC
5652 drw 10
NOTES:
1. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from Port "B" read is not valid until following Port "B" clock cycle (i.e., time from write to valid read on opposite port will be
tCO + tCYC + tCD1). If tCO > minimum, then data from Port "B" read is available on first Port "B" clock cycle (i.e., time from write to valid read on opposite port will
be tCO + tCD1).
4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
6.1442
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read
(OE = VIL)(2)
tCYC2
tCH2
tCL2
CLK
CE
0
1
tSC
tHC
CE
tSB
tHB
UB, LB
t
SW tHW
R/W
tSW tHW
(3)
An + 3
An + 4
An
An +1
An + 2
An + 2
ADDRESS
t
SA
tHA
t
SD
t
HD
DATAIN
Dn + 2
tCD2
t
CD2
(1)
t
CKHZ
(4)
tCKLZ
Qn + 3
Qn
DATAOUT
READ
NOP
WRITE
READ
,
5652 drw 11
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
Timing Waveform of Pipelined Read-to-Write-to-Read ( OE Controlled)(2)
t
CYC2
tCH2
tCL2
CLK
CE
0
1
t
SC
tHC
CE
tSB
tHB
UB, LB
t
SW tHW
R/
W
t
SW tHW
(3)
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
ADDRESS
t
SA
tHA
t
SD
tHD
DATAIN
Dn + 2
t
CD2
t
CD2
t
CKLZ
(1)
Qn
Qn + 4
DATAOUT
(4)
tOHZ
OE
READ
WRITE
READ
,
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
5652 drw 12
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
6.42
15
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(2)
t
CYC1
tCH1
tCL1
CLK
CE
0
1
t
SC
tHC
CE
t
SB
tHB
UB, LB
t
SW tHW
R/W
tSW tHW
(3)
An + 4
An
An + 3
An +1
An + 2
An + 2
ADDRESS
t
SA
tHA
t
SD
tHD
DATAIN
Dn + 2
t
CD1
tCD1
t
CD1
tCD1
(1)
Qn + 3
Qn
READ
Qn + 1
DATAOUT
tDC
t
CKLZ
t
DC
tCKHZ
NOP(4)
,
READ
WRITE
5652 drw 13
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)(2)
t
CYC1
t
CH1
tCL1
CLK
CE
0
1
tSC
tHC
CE
tSB
tHB
UB, LB
tSW tHW
t
SW tHW
R/
W
(3)
An + 5
An
An + 4
An +1
An + 2
An + 3
Dn + 3
ADDRESS
t
SA
tHA
t
SD tHD
DATAIN
Dn + 2
t
OE
t
DC
t
CD1
t
CD1
t
CD1
(1)
Qn + 4
Qn
DATAOUT
tCKLZ
t
DC
tOHZ
OE
,
READ
WRITE
READ
5652 drw 14
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, UB, LB, and ADS = VIL; CE1, CNTEN, and REPEAT = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.1462
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
t
CYC2
tCH2
t
CL2
CLK
tSA
tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tCD2
,
Qn + 2(2)
Qx - 1(2)
Qx
Qn + 3
Qn + 1
Qn
DATAOUT
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
5652 drw 15
Timing Waveform of Flow-Through Read with Address Counter Advance(1)
t
CYC1
tCH1
tCL1
CLK
tSA
tHA
An
ADDRESS
t
SAD tHAD
t
SAD
t
HAD
ADS
t
SCN
tHCN
CNTEN
t
CD1
,
Qn + 3(2)
Qx(2)
Qn + 4
Qn + 1
Qn + 2
Qn
DATAOUT
tDC
READ
WITH
COUNTER
5652 drw 16
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
NOTES:
1. CE0, OE, UB, LB = VIL; CE1, R/W, and REPEAT = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then
the data output remains constant for subsequent clocks.
6.42
17
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-through or Pipelined Inputs)(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 1
An + 3
An + 4
An + 2
t
SAD tHAD
ADS
tSCN
t
HC
N
CNTEN
t
SD tHD
Dn + 4
Dn + 1
Dn + 3
Dn
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
,
5652 drw 17
Timing Waveform of Counter Repeat(2)
t
CYC2
tCH2
tCL2
CLK
t
SA tHA
(4)
An + 2
An
An + 1
ADDRESS
INTERNAL(3)
ADDRESS
LAST ADS LOAD
Ax
LAST ADS +1
An
An + 1
tSW
tHW
R/W
ADS
tSAD
tHAD
CNTEN
t
SCN tHCN
tSRPT
tHRPT
REPEAT
t
SD
tHD
D0
DATAIN
(5)
QLAST+1
Qn
QLAST
DATAOUT
,
EXECUTE(6)
REPEAT
READ
READ
READ
READ
WRITE
LAST ADS
ADDRESS
ADDRESS n ADDRESS n+1
LAST ADS
LAST ADS
ADDRESS
ADDRESS + 1
NOTES:
1. CE0, UB, LB, and R/W = VIL; CE1 and REPEAT = VIH.
CE0, UB, LB = VIL; CE1 = VIH.
5652 drw 18
2.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid
ADS load will be accessed. Extra cycles are shown here simply for clarification. For more information on REPEAT function refer to Truth Table II.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6.1482
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
(2)
Waveform of Interrupt Timing
CLK
L
tSW
tHW
R/W
L
t
SA
7FFFF
SC
t
HA
ADDRESSL(3)
CEL(1)
t
t
HC
tINS
INTR
t
INR
CLKR
tSC
tHC
CER(1)
R/WR
t
SW
SA
7FFFF
t
HW
t
HA
t
ADDRESSR(3)
5652 drw 19
NOTES:
1. CE0 = VIL and CE1 = VIH
2. All timing is the same for Left and Right ports.
3. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
(1)
Truth Table III — Interrupt Flag
Left Port
Right Port
(2)
(2)
(3,4,5)
(2)
(2)
(3,4,5)
CLK
L
R/W
L
L
CE
L
A
18L-A0L
CLK
R
R/W
R
CE
R
A
18R-A0R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
INT
X
L
INT
R
↑
↑
↑
↑
↑
↑
↑
↑
L
7FFFF
X
X
X
X
L
R
X
X
X
L
X
H
L
L
L
7FFFF
7FFFE
X
H
R
X
X
L
X
L
H
7FFFE
H
X
X
X
L
5652 tbl 12
NOTES:
1. INTL and INTR must be initialized at power-up by Resetting the flags.
2. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.
3. A18X is a NC for IDT70T3319, therefore Interrupt Addresses are 3FFFF and 3FFFE.
4. A18X and A17X are NC's for IDT70T3399, therefore Interrupt Addresses are 1FFFF and 1FFFE.
5. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
6.42
19
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
(1,2)
Waveform of Collision Timing
Both Ports Writing with Left Port Clock Leading
CLK
L
t
OFS
t
SA
t
HA
ADDRESS (4)
L
A
3
A1
A2
A
0
tCOLR
tCOLS
COL
L
(3)
t
OFS
CLK
R
t
SA
t
HA
(4)
ADDRESS
R
A
3
A
2
A
0
A1
tCOLS
tCOLR
COL
R
5652 drw 20
NOTES:
1. CE0 = VIL, CE1 = VIH.
2. For reading port, OE is a Don't care on the Collision Detection Logic. Please refer to Truth Table IV for specific cases.
3. Leading Port Output flag might output 3tCYC2 + tCOLS after Address match.
4. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
Collision Detection Timing(3,4)
tOFS (ns)
Cycle Time
NOTES:
1. Region 1
(1)
(2)
Region 1 (ns)
Region 2 (ns)
Both ports show collision after 2nd cycle for Addresses 0, 2, 4 etc.
2. Region 2
Leading port shows collision after 3rd cycle for addresses 0, 3, 6, etc.
while trailing port shows collision after 2nd cycle for addresses 0, 2, 4 etc.
3. All the production units are tested to midpoint of each region.
5ns
6ns
0 - 2.8
2.81 - 4.6
0 - 3.8
0 - 5.3
3.81 - 5.6
5.31 - 7.1
7.5ns
4. These ranges are based on characterization of a typical device.
5652 tbl 13
Truth Table IV — Collision Detection Flag
Left Port
Right Port
(1)
(1)
(2)
(1)
(1)
(2)
CLK
L
R/W
L
CE
L
A
18L-A0L
CLK
R
R/W
R
CE
R
A
18R-A0R
Function
COL
H
L
COL
R
Both ports reading. Not a valid collision.
No flag output on either port.
↑
↑
↑
↑
↑
↑
↑
H
H
L
L
MATCH
MATCH
MATCH
MATCH
H
L
L
MATCH
MATCH
MATCH
MATCH
H
Left port reading, Right port writing.
Valid collision, flag output on Left port.
L
L
L
L
L
L
L
H
Right port reading, Left port writing.
Valid collision, flag output on Right port.
H
H
L
L
Both ports writing. Valid collision. Flag
output on both ports.
↑
L
L
L
5652 tbl 14
NOTES:
1. CE0 = VIL and CE1 = VIH. R/W and CE are synchronous with respect to the clock and need valid set-up and hold times.
2. Address is for internal register, not the external bus, i.e., address needs to be qualified by one of the Address counter control signals.
6.2402
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
(1,2)
Timing Waveform - Entering Sleep Mode
R/W
(3)
(1,2)
Timing Waveform - Exiting Sleep Mode
An
An+1
(5)
R/W
OE
(5)
Dn
Dn+1
DATAOUT
(4)
NOTES:
1. CE1 = VIH.
2. All timing is same for Left and Right ports.
3. CE0 has to be deactivated (CE0 = VIH) three cycles prior to asserting ZZ (ZZx = VIH) and held for two cycles after asserting ZZ (ZZx = VIH).
4. CE0 has to be deactivated (CE0 = VIH) one cycle prior to de-asserting ZZ (ZZx = VIL) and held for three cycles after de-asserting ZZ (ZZx = VIL).
5. The device must be in Read Mode (R/W High) when exiting sleep mode. Outputs are active but data is not valid until the following cycle.
6.42
21
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
alertflagasappropriate.Intheeventthatauserinitiatesaburstaccess
onbothportswiththesamestartingaddressonbothportsandoneorboth
portswritingduringeachaccess(i.e.,imposesalongstringofcollisions
on contiguous clock cycles), the alert flag will be asserted and cleared
everyothercycle.PleaserefertotheCollisionDetectionTimingwaveform
on page 20.
Functional Description
TheIDT70T3339/19/99providesatruesynchronousDual-PortStatic
RAM interface.Registeredinputsprovideminimalset-upandholdtimes
onaddress, data, andallcriticalcontrolinputs. Allinternalregistersare
clocked on the rising edge of the clock signal, however, the self-timed
internalwritepulsewidthisindependentofthecycletime.
CollisiondetectionontheIDT70T3339/19/99representsasignificant
advanceinfunctionalityovercurrentsyncmulti-ports,whichhavenosuch
capability. InadditiontothisfunctionalitytheIDT70T3339/19/99sustains
thekeyfeaturesofbandwidthandflexibility. Thecollisiondetectionfunction
isveryusefulinthecaseofburstingdata,orastringofaccessesmadeto
sequentialaddresses,inthatitindicatesaproblemwithintheburst,giving
theusertheoptionofeitherrepeatingtheburstorcontinuingtowatchthe
alert flag to see whether the number of collisions increases above an
acceptablethresholdvalue.Offeringthisfunctiononchipalsoallowsusers
to reduce their need for arbitration circuits, typically done in CPLD’s or
FPGA’s.Thisreducesboardspaceanddesigncomplexity,andgivesthe
usermoreflexibilityindevelopingasolution.
An asynchronous output enable is provided to ease asyn-
chronousbusinterfacing.Counterenableinputsarealsoprovidedtostall
the operation of the address counters for fast interleaved
memoryapplications.
AHIGHonCE0oraLOWonCE1foroneclockcyclewillpowerdown
the internal circuitry to reduce static power consumption. Multiple chip
enablesalloweasierbankingofmultipleIDT70T3339/19/99sfordepth
expansionconfigurations. TwocyclesarerequiredwithCE0 LOWand
CE1 HIGHtore-activatetheoutputs.
Interrupts
If the user chooses the interrupt function, a memory location (mail
boxormessagecenter)isassignedtoeachport. Theleftportinterrupt
flag (INTL) is asserted when the right port writes to memory location
7FFFE (HEX), where a write is defined as CER = R/WR = VIL per the
Truth Table. The left port clears the interrupt through access of
addresslocation7FFFEwhenCEL = VIL andR/WL=VIH.Likewise,the
right port interrupt flag (INTR) is asserted when the left
port writes to memory location 7FFFF (HEX) and to clear the interrupt
flag(INTR),therightportmustreadthememorylocation7FFFF(3FFFF
or3FFFEforIDT70T3319and1FFFFor1FFFEforIDT70T3399). The
message(18bits)at7FFFEor7FFFF(3FFFFor3FFFEforIDT70T3319
and 1FFFF or 1FFFE for IDT70T3399) is user-defined since it is an
addressableSRAMlocation.Iftheinterruptfunctionisnotused,address
locations 7FFFE and 7FFFF (3FFFF or 3FFFE for IDT70T3319 and
1FFFF or 1FFFE for IDT70T3399) are not used as mail boxes, but as
partoftherandomaccessmemory.RefertoTruthTableIII fortheinterrupt
operation.
Sleep Mode
The IDT70T3339/19/99 is equipped with an optional sleep or low
power mode on both ports. The sleep mode pin on both ports is
asynchronous and active high. During normal operation, the ZZ pin is
pulledlow.WhenZZispulledhigh,theportwillentersleepmodewhere
it will meet lowest possible power conditions. The sleep mode timing
diagramshowsthemodes ofoperation:NormalOperation,NoRead/Write
Allowed and Sleep Mode.
Fornormaloperationallinputsmustmeetsetupandholdtimesprior
tosleepand afterrecoveringfromsleep.Clocksmustalsomeetcyclehigh
and low times during these periods. Three cycles prior to asserting ZZ
(ZZx=VIH)andthreecyclesafterde-assertingZZ(ZZx=VIL),thedevice
mustbedisabledviathechipenablepins.Ifawriteorreadoperationoccurs
duringtheseperiods,thememoryarraymaybecorrupted.Validityofdata
outfromtheRAMcannotbeguaranteedimmediatelyafterZZisasserted
(priortobeinginsleep).Whenexitingsleepmode,thedevicemustbein
Read mode (R/Wx = VIH)when chip enable is asserted, and the chip
enablemustbevalidforonefullcyclebeforeareadwillresultintheoutput
ofvaliddata.
DuringsleepmodetheRAMautomaticallydeselectsitself.TheRAM
disconnectsitsinternalclockbuffer.Theexternalclockmaycontinuetorun
withoutimpactingtheRAMssleepcurrent(IZZ).Alloutputswillremainin
high-Zstatewhileinsleepmode.Allinputsareallowedtotoggle.TheRAM
will not be selected and will not perform any reads or writes.
Collision Detection
Collisionisdefinedasanoverlapinaccessbetweenthetwoports
resulting in the potential for either reading or writing incorrect data to a
specificaddress. Forthespecificcases:(a)Bothportsreading-nodata
iscorrupted,lost,orincorrectlyoutput,sonocollisionflagisoutputoneither
port.(b)Oneportwriting,theotherportreading-theendresultofthewrite
willstillbevalid. However, thereadingportmightcapturedatathatisin
astateoftransitionandhencethereadingport’scollisionflagisoutput.(c)
Bothportswriting-thereisariskthatthetwoportswillinterferewitheach
other, andthedatastoredinmemorywillnotbeavalidwritefromeither
port(itmayessentiallybearandomcombinationofthetwo). Therefore,
thecollisionflagisoutputonbothports. PleaserefertoTruthTableIVfor
all of the above cases.
Thealertflag(COLX)isassertedonthe2ndor3rdrisingclockedge
oftheaffectedportfollowingthecollision,andremainslowforonecycle.
PleaserefertoCollisionDetectionTimingtableonpage20.Duringthat
nextcycle,theinternalarbitrationisengagedinresettingthealertflag(this
avoidsaspecificrequirementonthepartoftheusertoresetthealertflag).
Iftwocollisionsoccuronsubsequentclockcycles,thesecondcollisionmay
notgeneratetheappropriatealertflag.Athirdcollisionwillgeneratethe
6.2422
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Depth and Width Expansion
The IDT70T3339/19/99 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70T3339/19/99 can also be used in applications requiring
expandedwidth,asindicatedinFigure4.Throughcombiningthecontrol
signals, the devices can be grouped as necessary to accommodate
applicationsneeding36-bitsorwider.
(1)
17
A
19/A18/
A
IDT70T3339/19/99
IDT70T3339/19/99
CE
0
1
CE
0
1
CE
CE
VDD
V
DD
Control Inputs
Control Inputs
IDT70T3339/19/99
IDT70T3339/19/99
CE
1
CE
1
0
CE0
CE
UB, LB,
R/W,
Control Inputs
Control Inputs
OE,
CLK,
Figure 4. Depth and Width Expansion with IDT70T3339/19/99
ADS,
5652 drw 23
REPEAT,
CNTEN
NOTE:
1. A19 is for IDT70T3339, A18 is for IDT70T3319, A17 is for IDT70T3399.
6.42
23
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
JTAG Timing Specifications
tJCYC
t
JR
t
JF
t
JCL
tJCH
TCK
Device Inputs(1)/
TDI/TMS
tJDC
t
JS
tJH
Device Outputs(2)/
TDO
tJRSR
tJCD
TRST
,
5652 drw 24
t
JRST
NOTES:
1. Device inputs = All device inputs except TDI, TMS, and TRST.
2. Device outputs = All device outputs except TDO.
JTAG AC Electrical
Characteristics (1,2,3,4)
70T3339/19/99
Symbol
Parameter
JTAG Clock Input Period
JTAG Clock HIGH
JTAG Clock Low
JTAG Clock Rise Time
JTAG Clock Fall Time
JTAG Reset
Min.
100
40
Max.
Units
ns
____
t
JCYC
JCH
JCL
JR
JF
JRST
JRSR
JCD
JDC
JS
JH
____
____
t
ns
t
40
ns
t
3(1)
ns
____
t
3(1)
ns
____
____
t
50
ns
____
t
JTAG Reset Recovery
JTAG Data Output
JTAG Data Output Hold
JTAG Setup
50
ns
____
t
25
ns
____
t
0
ns
____
____
t
15
15
ns
t
JTAG Hold
ns
5652 tbl 15
NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at
any speed specified in this datasheet.
6.2442
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Identification Register Definitions
Instruction Field
Value
Description
Revision Number (31:28)
0x0
Reserved for version number
0x333(1)
0x33
1
IDT Device ID (27:12)
Defines IDT part number
IDT JEDEC ID (11:1)
Allows unique identification of device vendor as IDT
Indicates the presence of an ID register
ID Register Indicator Bit (Bit 0)
5652 tbl 16
NOTE:
1. Device ID for IDT70T3319 is 0x334. Device ID for IDT70T3399 is 0x335.
Scan Register Sizes
Register Name
Bit Size
Instruction (IR)
Bypass (BYR)
4
1
Identification (IDR)
32
Boundary Scan (BSR)
Note (3)
5652 tbl 17
System Interface Parameters
Instruction
Code
Description
EXTEST
0000
Forces contents of the boundary scan cells onto the device outputs(1).
Places the boundary scan register (BSR) between TDI and TDO.
BYPASS
IDCODE
1111
Places the bypass register (BYR) between TDI and TDO.
0010
Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.
0100
Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state except COLx & INTx outputs.
HIGHZ
Uses BYR. Forces contents of the boundary scan cells onto the device
outputs. Places the bypass register (BYR) between TDI and TDO.
CLAMP
0011
0001
SAMPLE/PRELOAD
Places the boundary scan register (BSR) between TDI and TDO.
SAMPLE allows data from device inputs(2) to be captured in the
boundary scan cells and shifted serially through TDO. PRELOAD allows
data to be input serially into the boundary scan cells via the TDI.
RESERVED
PRIVATE
0101, 0111, 1000, 1001,
1010, 1011, 1100
Several combinations are reserved. Do not use codes other than those
identified above.
0110,1110,1101
For internal use only.
5652 tbl 18
NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, and TRST.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local
IDT sales representative.
6.42
25
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
XXXX
A
999
A
A
A
A
Process/
Temperature
Range
Device
Type
Power Speed Package
Tube or Tray
Tape & Reel
Blank
8
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
)
I(4
)
G(3
Green
256-pin BGA (BC-256)
208-pin fpBGA (BF-208)
BC
BF
)
200
166
133
Commercial Only(2
Commercial & Industrial(1
Commercial & Industrial
)
Speed in Megahertz
Standard Power
S
9Mbit (512K x 18-bit) Synchronous Dual-Port RAM
4Mbit (256K x 18-bit) Synchronous Dual-Port RAM
2Mbit (128K x 18-bit) Synchronous Dual-Port RAM
70T3339
70T3319
70T3399
5652 drw 25
NOTES:
1. 166MHz I-Temp is not available in the BF-208 package.
2. 200Mhz is not available in the BF-208 package.
3. Greenpartsavailable.Forspecificspeeds,packagesandpowerscontactyourlocalsalesoffice.
4. Contactyour localsalesofficeforindustrialtemprangeforotherspeeds,packagesandpowers.
LEADFINISH(SnPb)partsareinEOLprocess.ProductDiscontinuationNotice-PDN#SP-17-02
IDT Clock Solution for IDT70T3339/19/99 Dual-Port
Dual-Port I/O Specitications
Clock Specifications
IDT
PLL
Clock Device
IDT
Non-PLL
Clock Device
IDT Dual-Port
Part Number
Input Duty
Cycle
Requirement
Input
Capacitance
Maximum
Frequency Tolerance
Jitter
Voltage
2.5
I/O
5T9010
5T905, 5T9050
5T907, 5T9070
70T3339/19/99
LVTTL
8pF
40%
200
75ps
5T2010
5652 tbl 19
6.2462
IDT70T3339/19/99S
High-Speed 2.5V 512/256/128K x 18 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Datasheet Document History
01/20/03:
04/25/03:
InitialDatasheet
Page 11 AddedCapacitanceDeratingdrawing
Page 12 ChangedtINS andtINR specsinACElectricalCharacteristicstable
Page 10 UpdatedpowernumbersinDCElectricalCharacteristicstable
Page 12 AddedtOFS symbolandparametertoACElectricalCharacteristicstable
Page 21 UpdatedCollisionTimingwaveform
11/11/03:
Page 22 AddedCollisionDetectionTimingtableandfootnotes
Page 26 UpdatedHIGHZfunctioninSystemInterfaceParameterstable
Page 27 AddedIDTClockSolutiontable
04/08/04:
02/07/06:
Page 22 & 23 Clarified Sleep Mode Text and Waveforms
Page 1 & 28 Removed Preliminary status
Page 6 Addedanothersentencetofootnote4torecommendthatboundaryscannotbeoperatedduringsleepmode
Page 1 Addedgreenavailabilitytofeatures
Page 7 Changed footnote 2 for Truth Table I from ADS, CNTEN, REPEAT = VIH to ADS, CNTEN, REPEAT = X
Page 27 Addedgreenindicatortoorderinginformation
07/28/08:
01/19/09:
04/20/10:
06/10/15:
Page 10 Corrected a typo in the DC Chars table footnotes
Page 28 Removed "IDT" from orderable part number
Removed the DD 144-pin TQFP (DD-144) Thin Quad Flatpack per PDN: F-08-01
Page 3 & 4 Removed the date from all of the pin configurations BC256 & BF208
Page 26 AddedT&RindicatorandindustrialtempfootnotetoOrderingInformation
ProductDiscontinuationNotice-PDN#SP-17-02
02/08/18:
Last time buy expires June 15, 2018
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
27
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