70V06S55PFGI8 [IDT]
HIGH-SPEED 3.3V 16K x 8 DUAL-PORT STATIC RAM;
| 型号： | 70V06S55PFGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 3.3V 16K x 8 DUAL-PORT STATIC RAM |
| 文件： | 总23页 (文件大小：682K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 3.3V
16K x 8 DUAL-PORT
STATIC RAM
IDT70V06S/L
Features
◆
◆
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
High-speed access
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
◆
◆
◆
◆
Interrupt Flag
– Commercial:15/20/25/35/55ns(max.)
– Industrial:20/25ns(max.)
Low-power operation
On-chip port arbitration logic
Full on-chip hardware support of semaphore signaling
between ports
◆
◆
◆
◆
◆
◆
– IDT70V06S
Fully asynchronous operation from either port
Battery backup operation—2V data retention
TTL-compatible, single 3.3V (±0.3V) power supply
Available in 68-pin PGA and PLCC, and a 64-pin TQFP
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Active:400mW(typ.)
Standby: 3.3mW (typ.)
– IDT70V06L
Active:380mW(typ.)
Standby:660µW(typ.)
◆
◆
IDT70V06 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
Green parts available, see ordering information
Functional Block Diagram
OEL
OER
CEL
CER
R/W
L
R/WR
,
I/O0L- I/O7L
I/O0R-I/O7R
I/O
Control
I/O
Control
(1,2)
(1,2)
R
BUSY
L
BUSY
A
13L
A
13R
0R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
0L
A
14
14
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
L
L
CE
OE
R/W
R
OE
R
R
R/W
L
SEM
INTL
L
SEM
R
M/S
(2)
(2)
INTR
2942 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY outputs and INT outputs are non-tri-stated push-pull.
AUGUST 2015
1
©2015 Integrated Device Technology, Inc.
DSC-2942/10
6.07
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
This device provides two independent ports with separate control,
address,andI/Opinsthatpermitindependent,asynchronousaccessfor
reads or writes to any location in memory. An automatic power down
featurecontrolledbyCEpermitstheon-chipcircuitryofeachporttoenter
a very low standby power mode.
Description
The IDT70V06 is a high-speed 16K x 8 Dual-Port Static RAM. The
IDT70V06 is designed to be used as a stand-alone 128K-bit Dual-Port
Static RAM or as a combination MASTER/SLAVE Dual-Port Static
RAM for 16-bit-or-more word systems. Using the IDT MASTER/
SLAVE Dual-Port Static RAM approach in 16-bit or wider memory
system applications results in full-speed, error-free operation without
the need for additional discrete logic.
Fabricated using CMOS high-performance technology, these de-
vices typically operate on only 400mW of power.
The IDT70V06 is packaged in a ceramic 68-pin PGA and PLCC
and a 64-pin thin quad flatpack (TQFP).
Pin Configurations(1,2,3)
INDEX
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61
60
I/O2L
I/O3L
I/O4L
I/O5L
A
A
A
A
A
A
5L
4L
3L
2L
1L
0L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
59
58
57
56
55
V
SS
I/O6L
I/O7L
IDT70V06J
J68(4)
54
53
52
51
50
49
48
47
46
45
44
INT
BUSY
V
M/S
BUSY
INT
L
VDD
L
68-Pin PLCC
Top View(5)
SS
V
SS
I/O0R
I/O1R
I/O2R
R
R
V
DD
A
A
A
A
A
0R
I/O3R
I/O4R
I/O5R
I/O6R
1R
2R
3R
4R
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2942 drw 02
INDEX
1
2
3
4
5
6
A
A
A
A
A
4L
3L
2L
1L
0L
48
47
46
I/O2L
I/O3L
I/O4L
I/O5L
45
44
43
42
41
40
VSS
INT
L
I/O6L
I/O7L
70V06PF
PN-64(4)
7
8
9
BUSY
L
V
DD
V
SS
64-Pin TQFP
Top View(5)
V
SS
M/S
BUSY
R
10
11
12
I/O0R
I/O1R
I/O2R
39
38
37
INT
R
A
A
A
A
A
0R
V
DD
13
14
15
16
1R
2R
3R
4R
36
35
34
33
I/O3R
I/O4R
I/O5R
NOTES:
1. All VDD pins must be connected to power supply.
2. All VSS pins must be connected to ground supply.
3. J68-1 package body is approximately .95 in x .95 in x .17 in
PN-64 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
2942 drw 03
2
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
51
A
50
48
A
46
A
44
BUSY
42
M/S
40
INT
38
36
11
10
09
08
07
A
4L
2L
1L
0L
A
1R
A
3R
L
R
5L
6L
8L
53
A
52
A
49
47
A
45
INT
43
41
BUSYR
39
37
35
34
L
A
4R
VSS
7L
9L
A
3L
A0R
A
2R
A
5R
6R
8R
55
A
54
A
32
33
A
A
7R
57
A
56
30
31
A
A
9R
11L
A10L
59
58
A
28
29
A
11R
A10R
V
DD
12L
IDT70V06G
G68(4)
61
60
26
27
A
06
05
04
03
02
01
N/C
A
13L
V
SS
12R
13R
68-Pin PGA
Top View(5)
63
SEM
62
24
N/C
25
A
L
CE
L
65
OE
64
22
SEM
23
CE
R
R
L
R/W
L
67
I/O0L
66
20
OE
21
R/W
R
R
N/C
1
3
5
V
7
I/O7L
9
V
68
I/O1L I/O2L I/O4L
11
I/O1R
13
V
15
18
19
SS
SS
DD I/O4R I/O7R N/C
2
4
6
8
10
12
14
16 17
I/O5L
I/O3L
I/O6L
VDD I/O0R I/O2R I/O3R I/O5R I/O6R
A
B
C
D
E
F
G
H
J
K
L
INDEX
2942 drw 04
NOTES:
1. All VDD pins must be connected to power supply.
2. All VSS pins must be connected to ground supply.
3. Package body is approximately 1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part marking.
Pin Names
Left Port
Right Port
Names
Chip Enable
CEL
CER
R/WL
R/WR
Read/Write Enable
Output Enable
Address
OEL
OER
A0L - A13L
I/O0L - I/O7L
SEML
A0R - A13R
I/O0R - I/O7R
SEMR
Data Input/Output
Semaphore Enable
Interrupt Flag
INTL
INTR
Busy Flag
BUSYL
BUSYR
M/S
Master or Slave Select
Power (3.3V)
V
V
DD
SS
Ground (0V)
2942 tbl 01
6.42
3
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Inputs(1)
/W
Outputs
I/O0-7
R
Mode
CE
H
L
OE
X
SEM
H
X
L
High-Z
DATAIN
DATAOUT
High-Z
Deselected: Power-Down
Write to Memory
X
H
L
H
X
L
H
Read Memory
X
H
X
Outputs Disabled
2942 tbl 02
NOTE:
1. A0L — A13L ≠ A0R — A13R
Truth Table II: Semaphore Read/Write Control(1)
Inputs
Outputs
I/O0-7
R/W
H
Mode
CE
H
OE
L
SEM
L
L
L
DATAOUT
Read Data in Semaphore Flag
Write I/O into Semaphore Flag
Not Allowed
H
X
DATAIN
____
0
↑
L
X
X
2942 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from I/O0 - I/O7. These eight semaphores are addressed by A0 - A2.
4
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AbsoluteMaximumRatings(1)
MaximumOperatingTemperature
andSupplyVoltage(1)
Symbol
Rating
Commercial
& Industrial
Unit
Grade
Commercial
Industrial
Ambient Temperature
0OC to +70OC
GND
0V
V
DD
(2)
V
TERM
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
3.3V
3.3V
+
+
0.3V
-40OC to +85OC
0V
0.3V
2942 tbl 05
T
BIAS
Temperature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
NOTE:
Storage
TSTG
1. This is the parameter TA. This is the "instant on" case temperature.
Temperature
IOUT
DC Output
Current
mA
2942 tbl 04
NOTES:
RecommendedDCOperating
Conditions
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
Symbol
Parameter
Supply Voltage
Ground
Min.
3.0
Typ.
Max.
3.6
Unit
V
V
V
DD
3.3
2. VTERM must not exceed VDD + 0.3V.
SS
0
0
0
V
____
V
IH
IL
Input High Voltage
Input Low Voltage
2.0
-0.3(1)
V
DD+0.3(2)
V
Capacitance(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
Output Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
____
V
0.8
V
2942 tbl 06
CIN
V
9
pF
NOTES:
1. VIL> -1.5V for pulse width less than 10ns.
2. VTERM must not exceed VDD +0.3V.
COUT
V
10
pF
2942 tbl 07
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)
70V06S
70V06L
Symbol
|ILI
|ILO
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
DD = 3.6V, VIN = 0
OUT = 0V to VDD
Min.
___
Max.
10
Min.
___
Max.
Unit
µA
µA
V
|
V
V
V
to VDD
5
5
___
___
___
___
|
10
V
OL
I
OL = +4mA
0.4
0.4
___
___
V
OH
Output High Voltage
IOH = -4mA
2.4
2.4
V
2942 tbl 08
NOTE:
1. At VDD < 2.0V input leakages are undefined.
6.42
5
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VDD = 3.3V ± 0.3V)
70V06X15
70V06X20
70V06X25
Com'l
Com'l Only
Com'l
& Ind
& Ind
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
IDD
Dynamic Operating
Current
S
L
150
215
140
200
130
190
mA
CE = V , Outputs Disabled
SEM = IVLIH
140
185
130
175
125
165
(3)
(Both Ports Active)
f = fMAX
____
____
____
____
____
____
____
____
IND
S
L
mA
mA
mA
mA
mA
mA
mA
mA
mA
130
195
125
180
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
S
L
25
20
____
____
35
30
____
____
20
15
30
25
16
13
30
25
CE
R
= CE
(3)
L
= VIH
= VIH
f = fMRAX
SEM = SEM
L
____
____
____
____
S
L
15
40
13
40
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
S
L
85
80
____
____
120
110
____
____
80
75
110
100
75
72
110
95
CEL or CE = VIH
Active PorRt Outputs Disabled,
(3)
f=fMAX
____
____
____
____
S
L
75
115
72
110
ISB3
Full Standby Current
(Both Ports -
Both Ports CE and
CE > V - 0L.2V,
COM'L
IND
S
L
1.0
0.2
____
____
5
1.0
0.2
5
1.0
0.2
5
R> VDDDD- 0.2V or
2.5
2.5
2.5
VIN < 0.2V, f = 0(4)
CMOS Level Inputs)
V
____
____
____
____
____
____
S
L
0.2
5
0.2
5
SEMR = SEML > VDD - 0.2V
ISB4
Full Standby Current
(One Port -
One Port CE or
COM'L
IND
S
L
85
80
____
____
125
105
____
____
80
75
115
100
75
70
105
90
SEMR
= DSDEM > VDD - 0.2V
CE
R
> V - L0.2V
CMOS Level Inputs)
____
____
____
____
S
L
V
> VDD - 0.L2V or VIN < 0.2V
AcINtive Port Outputs Disabled,
75
115
70
105
(3)
f = fMAX
2942 tbl 09a
70V06X35
Com'l Only
70V06X55
Com'l Only
Symbol
Parameter
Test Condition
Version
Typ.(2)
Max.
Typ.(2)
Max.
Unit
I
DD
Dynamic Operating
Current
COM'L
S
120
180
120
180
155
____
____
mA
CE = V , Outputs Disabled
SEM = IVLIH
L
115
155
115
(3)
(Both Ports Active)
f = fMAX
____
____
____
____
____
____
IND
S
L
mA
mA
mA
mA
mA
mA
mA
mA
mA
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
S
L
13
11
____
____
25
20
____
____
13
11
____
____
25
20
____
____
CER = CE = VIH
SEM = SLEM
L = VIH
f = fMRAX
(3)
S
L
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
S
L
70
65
____
____
100
90
____
____
70
65
____
____
100
90
____
____
CEL or CE = VIH
Active PorRt Outputs Disabled,
(3)
f=fMAX
S
L
ISB3
Full Standby Current
(Both Ports -
Both Ports CE and
CE > V - 0L.2V,
COM'L
IND
S
L
1.0
0.2
____
____
5
1.0
0.2
____
____
5
CMOS Level Inputs)
V
R> VDDDD- 0.2V or
2.5
2.5
VIINN < 0.2V, f = 0(4)
____
____
____
____
S
L
SEMR = SEML > VDD - 0.2V
ISB4
Full Standby Current
(One Port -
One Port CE or
COM'L
IND
S
L
65
60
____
____
100
85
____
____
65
60
____
____
100
85
____
____
CE
R
> V - L0.2V
CMOS Level Inputs)
SEM
R
= DSDEM
L > VDD - 0.2V
S
L
V
IN > VDD - 0.2V or VIN < 0.2V
Active Port Outputs Disabled,
(3)
f = fMAX
2942 tbl 09b
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. VDD = 3.3, TA = +25°C, and are not production tested. IDD DC = 115mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input levels of
GND to 3V.
4. f = 0 means no address or control lines change.
6
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
3.3V
3.3V
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns Max.
1.5V
590Ω
590Ω
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
DATAOUT
BUSY
INT
DATAOUT
1.5V
5pF*
435Ω
30pF
435Ω
Figures 1 and 2
,
2942 tbl 10
2942 drw 05
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(For tLZ, tHZ, tWZ, tOW)
*Including scope and jig.
Timing of Power-Up Power-Down
CE
tPU
tPD
ICC
ISB
,
2942 drw 06
6.42
7
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(4)
70V06X15
70V06X20
70V06X25
Com'l
Com'l Only
Com'l
& Ind
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
15
____
20
____
25
____
ns
ns
ns
t
Address Access Time
15
15
20
20
25
25
____
____
____
____
____
____
Chip Enable Access Time(3)
t
Output Enable Access Time(3)
t
10
12
13
ns
ns
ns
ns
ns
ns
ns
____
____
____
t
Output Hold from Address Change
3
3
3
____
____
____
Output Low-Z Time(1,2)
t
3
3
3
____
____
____
Output High-Z Time(1,2)
t
10
12
15
____
____
____
Chip Enable to Power Up Time(1,2)
t
0
0
0
____
____
____
Chip Disable to Power Down Time(1,2)
t
15
20
25
____
____
____
t
Semaphore Flag Update Pulse (OE or SEM)
10
10
10
____
____
____
Semaphore Address Access(3)
t
15
20
25
ns
2942 tbl 11a
70V06X35
70V06X55
Com'l Only
Com'l Only
Symbol
READ CYCLE
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
35
____
55
____
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Address Access Time
35
35
55
55
Chip Enable Access Time(3)
Output Enable Access Time(3)
Output Hold from Address Change
Output Low-Z Time(1,2)
____
____
____
____
t
t
20
____
30
____
t
3
3
____
____
t
3
____
3
____
t
Output High-Z Time(1,2)
15
____
25
____
t
Chip Enable to Power Up Time(1,2)
Chip Disable to Power Down Time(1,2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access(3)
0
____
0
____
t
35
____
50
____
t
15
____
15
____
t
35
55
ns
2942 tbl 11b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed but not tested.
3. To access SRAM, CE = VIL, SEM = VIH.
4. 'X' in part number indicates power rating (S or L).
8
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
tRC
ADDR
(4)
t
t
AA
(4)
ACE
CE
OE
(4)
tAOE
R/W
DATAOUT
BUSYOUT
(1)
t
OH
tLZ
(4)
VALID DATA
(2)
t
HZ
(3,4)
2942 drw 07
t
BDD
NOTES:
1. Timing depends on which signal is asserted las OE or CE.
2. Timing depends on which signal is de-asserted first CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6.42
9
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(5)
70V06X15
Com'l Only
70V06X20
Com'l
70V06X25
Com'l
& Ind
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
15
12
12
0
20
15
15
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
Write Pulse Width
t
t
t
12
0
15
0
20
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
Write Enable to Output in High-Z(1,2)
Output Active from End-of-Write(1, 2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
t
10
____
15
____
15
____
t
10
____
12
____
15
____
t
0
____
0
____
0
____
t
10
____
12
____
15
____
t
0
5
5
0
5
5
0
5
5
____
____
____
____
____
____
t
t
ns
2942 tbl 12a
70V06X35
Com'l Only
70V06X55
Com'l Only
Symbol
WRITE CYCLE
Parameter
Min. Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
35
30
30
0
55
45
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
t
t
t
Write Pulse Width
25
0
40
0
t
Write Recovery Time
t
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
Write Enable to Output in High-Z(1,2)
Output Active from End-of-Write(1, 2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
15
____
30
____
t
15
____
25
____
t
0
____
0
____
t
15
____
25
____
t
0
5
5
0
5
5
____
____
____
____
t
t
ns
2942 tbl 12b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. This parameter is guaranteed but not tested.
3. To access SRAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (S or L).
10
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,3,5,8)
tWC
ADDRESS
(7)
tHZ
OE
tAW
CE or SEM(9)
(6)
(3)
(2)
tAS
tWR
tWP
R/W
DATAOUT
DATAIN
(7)
t
OW
tWZ
(4)
(4)
tDW
tDH
2942 drw 08
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,3,5,8)
tWC
ADDRESS
tAW
CE or SEM(9)
R/W
(6)
AS
(3)
(2)
tWR
t
tEW
tDW
tDH
IN
DATA
2942 drw 09
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE, or R/W.
7. Timing depends on which enable signal is de-asserted first, CE, or R/W.
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access SRAM, CE = VIL and SEM = VIH. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
6.42
11
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
tOH
A0-A2
VALID ADDRESS
VALID ADDRESS
tAW
tWR
tACE
tEW
SEM
tDW
tSOP
OUT
DATA
DATA
0
DATAIN VALID
VALID(2)
tAS
tWP
tDH
R/W
tSWRD
tAOE
OE
tSOP
Write Cycle
Read Cycle
2942 drw 10
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0 - I/O7) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
SIDE(2) "A"
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
SIDE(2)
"B"
R/W"B"
SEM"B"
2942 drw 11
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. “A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/W“A” or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
12
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(6)
70V06X15
Com'l Ony
70V06X20
Com'l
70V06X25
Com'l
& Ind
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S = VIH
)
____
____
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
15
15
15
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable LOW
BUSY Disable Time from Chip Enable HIGH
Arbitration Priority Set-up Time(2)
t
t
t
15
____
17
____
17
____
t
5
____
5
____
5
____
BUSY Disable to Valid Data(3)
t
18
____
30
____
30
____
(5)
t
Write Hold After BUSY
12
15
17
BUSY TIMING (M/S = VIL
)
____
____
____
____
____
____
BUSY Input to Write(4)
t
WB
0
0
0
ns
ns
(5)
tWH
Write Hold After BUSY
12
15
17
PORT-TO-PORT DELAY TIMING
____
____
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
30
25
45
35
50
35
ns
tDDD
ns
2942 tbl 13a
70V06X35
Com'l Only
70V06X55
Com'l Only
Symbol
BUSY TIMING (M/S = VIH
Parameter
Min.
Max.
Min.
Max.
Unit
)
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
20
20
20
45
40
40
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
t
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable LOW
BUSY Disable Time from Chip Enable HIGH
Arbitration Priority Set-up Time(2)
t
t
20
____
35
____
t
5
____
5
____
BUSY Disable to Valid Data(3)
t
35
____
40
____
(5)
t
Write Hold After BUSY
25
25
BUSY TIMING (M/S = VIL
)
____
____
____
____
BUSY Input to Write(4)
t
WB
0
0
ns
ns
(5)
tWH
Write Hold After BUSY
25
25
PORT-TO-PORT DELAY TIMING
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
Write Data Valid to Read Data Delay(1)
60
45
80
65
ns
tDDD
ns
2942 tbl 13b
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Read With BUSY (M/S = VIH) or "Timing Waveform of Write With
Port-To-Port Delay (M/S=VIL)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited during contention.
5. To ensure that a write cycle is completed after contention.
6. "X" is part numbers indicates power rating (S or L).
6.42
13
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-To-Port Read and BUSY(2,4,5)
(M/S = VIH)
t
WC
MATCH
ADDR"A"
tWP
R/W"A"
t
DW
tDH
VALID
DATAIN "A"
(1)
tAPS
MATCH
ADDR"B"
BUSY"B"
tBDA
tBDD
tBAA
tWDD
VALID
DATAOUT "B"
(3)
tDDD
2942 drw 12
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. If M/S = VIL(slave) then BUSY is input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above.
5. All timing is the same for left and right port. Port "A" may be either left or right port. Port "B" is the port opposite from Port "A".
14
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY
t
WP
R/W"A"
(3)
t
WB
BUSY"B"
(1)
t
WH
(2)
R/W"B"
,
2942 drw 13
NOTES:
1. tWH must be met for both BUSY input (slave) output master.
2. BUSY is asserted on Port “B” Blocking R/W“B”, until BUSY“B” goes HIGH.
3. tWB is only for the slave version.
Waveform of BUSY Arbitration Controlled by CE Timing(1) (M/S = VIH)
ADDR"A"
ADDRESSES MATCH
and "B"
CE"A"
(2)
tAPS
CE"B"
t
BAC
tBDC
BUSY"B"
2942 drw 14
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(1) (M/S = VIH)
ADDR"A"
ADDRESS "N"
(2)
t
APS
ADDR"B"
MATCHING ADDRESS "N"
tBAA
tBDA
BUSY"B"
2942 drw 15
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.
6.42
15
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(1)
70V06X15
70V06X20
70V06X25
Com'l
Com'l Only
Com'l
& Ind
& Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
0
ns
ns
ns
t
0
____
0
____
0
____
t
15
15
20
20
20
20
____
____
____
t
Interrupt Reset Time
ns
2942 tbl 14a
70V06X35
70V06X55
Com'l Only
Com'l Only
Symbol
INTERRUPT TIMING
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
ns
ns
ns
t
0
____
0
____
t
25
25
40
40
____
____
t
Interrupt Reset Time
ns
2942 tbl 14b
NOTE:
1. 'X' in part number indicates power rating (S or L).
Waveform of Interrupt Timing(1)
tWC
INTERRUPT SET ADDRESS(2)
ADDR"A"
(3)
(4)
tAS
tWR
CE"A"
R/W"A"
INT"B"
(3)
tINS
2942 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
16
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Interrupt Timing(1) (con't.)
t
RC
INTERRUPT CLEAR ADDRESS (2)
ADDR"B"
(3)
tAS
CE"B"
OE"B"
(3)
tINR
INT"B"
2942 drw 17
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
Truth Table III — Interrupt Flag(1)
Left Port
Right Port
R/W
L
A
13L-A0L
R/W
R
A
13R-A0R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
CE
L
OE
L
INT
L
CE
R
OE
R
INTR
L
X
X
X
L
X
X
L
X
3FFF
X
X
X
X
L
X
L
L
X
X
X
L(2)
H(3)
X
R
X
X
L
3FFF
3FFE
X
R
X
X
L(3)
H(2)
X
L
L
3FFE
X
X
X
L
2942 tbl 15
NOTES:
1. Assumes BUSYL = BUSYR = VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
6.42
17
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table IV — Address BUSY
Arbitration
Inputs
Outputs
A
-A
A1133RL-A00RL
Function
Normal
Normal
Normal
(1)
(1)
CE
L
CE
R
BUSY
L
BUSYR
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
H
MATCH
H
H
MATCH
(2)
(2)
Write Inhibit(3)
2942 tbl 16
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the IDT70V06 are push
pull, not open drain outputs. On slaves the BUSYX input internally inhibits writes.
2. L if the inputs to the opposite port were stable prior to the address and enable inputs of this port. H if the inputs to the opposite port became stable after the address and enable
inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0
- D7
Left
D0
- D7
Right
Status
No Action
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
0
0
1
1
0
1
1
1
0
1
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
2942 tbl 17
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V06.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0 - I/O7). These eight semaphores are addressed by A0 -A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
Functional Description
The IDT70V06 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70V06 has an automatic power down
featurecontrolledbyCE.TheCEcontrolson-chippowerdowncircuitry
that permits the respective port to go into a standby mode when not
selected (CE = VIH). When a port is enabled, access to the entire
memory array is permitted.
(HEX). Theleftportclearstheinterruptbyreadingaddresslocation3FFE.
Likewise,therightportinterruptflag(INTR)issetwhentheleftportwrites
tomemorylocation3FFF(HEX)andtocleartheinterruptflag(INTR),the
rightportmustreadthememorylocation3FFF.Themessage(8bits)at
3FFEor3FFFisuser-defined.Iftheinterruptfunctionisnotused,address
locations3FFEand3FFFarenotusedasmailboxes, butaspartofthe
random access memory. Refer to Truth Table III for the interrupt
operation.
Interrupts
Busy Logic
If the user chooses the interrupt function, a memory location (mail
boxormessagecenter)isassignedtoeachport. Theleftportinterrupt
flag (INTL) is set when the right port writes to memory location 3FFE
Busy Logic provides a hardware indication that both ports of the
SRAM have accessed the same location at the same time. It also
18
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
CE
CE
MASTER
Dual Port
SRAM
SLAVE
Dual Port
SRAM
BUSY (L) BUSY (R)
BUSY (L) BUSY (R)
MASTER
Dual Port
SRAM
CE
SLAVE
CE
Dual Port
SRAM
BUSY (R)
BUSY (R)
BUSY (R)
BUSY (L)
BUSY (L)
BUSY (L)
2942 drw 18
Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70V06 SRAMs.
enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite
allowsoneofthetwoaccessestoproceedandsignalstheothersidethat
the SRAM is “busy”. The BUSY pincanthenbeusedtostalltheaccess
untiltheoperationon theothersideiscompleted.Ifawriteoperationhas
beenattemptedfromthesidethatreceivesaBUSYindication,thewrite
signalisgatedinternallytopreventthewritefromproceeding.
pulsecanbeinitiatedwiththeR/Wsignal. Failuretoobservethistiming
canresultinaglitchedinternalwriteinhibitsignalandcorrupteddatainthe
slave.
TheuseofBUSYlogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
anduseanyBUSYindicationasaninterruptsourcetoflagtheeventofan
illegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicisnot
desirable,theBUSYlogiccanbedisabledbyplacingthepartinslavemode
with the M/S pin. Once in slave mode the BUSY pin operates solely as
aninput. NormaloperationcanbeprogrammedbytyingtheBUSYpins
HIGH.Ifdesired,unintendedwriteoperationscanbepreventedtoaport
by tying the BUSY pin for that port LOW.
Semaphores
The IDT70V06 is an extremely fast Dual-Port 16K x 8 CMOS Static
RAM with an additional 8 address locations dedicated to binary
semaphore flags. These flags allow either processor on the left or right
sideoftheDual-PortSRAMtoclaimaprivilegeovertheotherprocessor
for functions defined by the system designer’s software. As an ex-
ample, the semaphore can be used by one processor to inhibit the
otherfromaccessingaportionoftheDual-PortSRAMoranyothershared
resource.
The BUSY outputs on the IDT 70V06 RAM in master mode, are
push-pull type outputs and do not require pull up resistors to operate.
If these RAMs are being expanded in depth, then the busy indication
for the resulting array requires the use of an external AND gate.
The Dual-Port SRAM features a fast access time, and both ports
are completely independent of each other. This means that the activity
on the left port in no way slows the access time of the right port. Both
ports are identical in function to standard CMOS Static RAM and can
be read from, or written to, at the same time with the only possible
conflict arising from the simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are pro-
tected against such ambiguous situations and may be used by the
system program to avoid any conflicts in the non-semaphore portion
of the Dual-Port SRAM. These devices have an automatic power-
downfeaturecontrolledbyCE, theDual-PortSRAMenable, andSEM,
the semaphore enable. The CE and SEM pins control on-chip power
down circuitry that permits the respective port to go into standby mode
when not selected. This is the condition which is shown in Truth Table
I where CE and SEM are both HIGH.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT70V06 SRAM array in width while using
BUSYlogic,onemasterpartisusedtodecidewhichsideoftheSRAMarray
willreceiveaBUSYindication,andtooutputthatindication.Anynumber
ofslavestobeaddressedinthesameaddressrangeasthemasteruse
theBUSYsignalasawriteinhibitsignal.ThusontheIDT70V06RAMthe
BUSYpinisanoutputifthepartisusedasamaster(M/Spin=VIH),and
theBUSYpinisaninputifthepartusedasaslave(M/Spin=VIL)asshown
in Figure 3.
Systems which can best use the IDT70V06 contain multiple
processors or controllers and are typically very high-speed systems
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the IDT70V06's
hardwaresemaphoreswithoutrequiringcomplexprogramming.
Softwarehandshakingbetweenprocessorsoffersthemaximumin
system flexibility by permitting shared resources to be allocated in
varyingconfigurations.TheIDT70V06doesnotuseitssemaphoreflags
to control any resources through hardware, thus allowing the system
If two or more master parts were used when expanding in width, a
splitdecisioncouldresultwithonemasterindicating BUSY ononeside
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for part of
the other word.
TheBUSYarbitration, onamaster, isbasedonthechipenableand
address signals only. It ignores whether an access is a read or write.
Inamaster/slavearray,bothaddressandchipenablemustbevalidlong
6.42
19
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
designertotalflexibilityinsystemarchitecture.
Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust
An advantage of using semaphores rather than the more common cause either signal (SEM or OE) to go inactive or the output will never
methods of hardware arbitration is that wait states are never incurred change.
in either processor. This can prove to be a major advantage in very
high-speed systems.
A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Table V). As an example, assume a processor
writes a zero to the left port at a free semaphore location. On a
subsequent read, the processor will verify that it has written success-
fully to that location and will assume control over the resource in
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
factthataonewillbereadfromthatsemaphoreontherightsideduring
subsequent read. Had a sequence of READ/WRITE been used
instead, system contention problems could have occurred during the
gap between the read and write cycles.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are indepen-
dent of the Dual-Port SRAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignmentmethodcalled“TokenPassingAllocation.”Inthismethod,
the state of a semaphore latch is used as a token indicating that a
shared resource is in use. If the left processor wants to use this
resource,itrequeststhetokenbysettingthelatch.Thisprocessorthen
verifiesitssuccessinsettingthelatchbyreadingit. Ifitwassuccessful,
it assumes control over the shared resource. If it was not successful
in setting the latch, it determines that the right side processor has set
the latch first, has the token and is using the shared resource. The left
processor can then either repeatedly request that semaphore’s status
or remove its request for that semaphore to perform another task and
occasionally attempt again to gain control of the token via the set and
test sequence. Once the right side has relinquished the token, the left
side should succeed in gaining control.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two sema-
phore request latches feed into a semaphore flag. Whichever latch is
first to present a zero to the semaphore flag will force its side of the
semaphore flag LOW and the other side HIGH. This condition will
continue until a one is written to the same semaphore request latch.
Should the other side’s semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the other
side as soon as a one is written into the first side’s request latch. The
second side’s flag will now stay LOW until its semaphore request latch
is written to a one. From this it is easy to understand that, if a
semaphore is requested and the processor which requested it no
longer needs the resource, the entire system can hang up until a one
is written into that semaphore request latch.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
side writes a one to that latch.
The eight semaphore flags reside within the IDT70V06 in a
separate memory space from the Dual-Port SRAM. This address
space is accessed by placing a LOW input on the SEM pin (which
acts as a chip select for the semaphore flags) and using the other
control pins (Address, OE, and R/W) as they would be used in
accessing a standard Static RAM. Each of the flags has a unique
address which can be accessed by either side through address pins
A0 – A2. When accessing the semaphores, none of the other address
pins has any effect.
The critical case of semaphore timing is when both sides request
a single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If
simultaneous requests are made, the logic guarantees that only one
side receives the token. If one side is earlier than the other in making
the request, the first side to make the request will receive the token. If
bothrequestsarriveatthesametime, theassignmentwillbearbitrarily
made to one port or the other.
Whenwritingtoasemaphore,onlydatapinD0isused.Ifalowiswritten
intoanunusedsemaphorelocation,thatflagwillbesettoazeroonthat
side and a one on the other side (see Truth Table V). That semaphore
can now only be modified by the side showing the zero. When a one is
writtenintothesamelocationfromthesameside,theflagwillbesettoa
one for both sides (unless a semaphore request from the other side is
pending)andthencanbewrittentobybothsides.Thefactthattheside
whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites
fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor
communications.(Athoroughdiscussionontheuseofthisfeaturefollows
shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe
storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis
freedbythefirstside.
One caution that should be noted when using semaphores is that
semaphores alone do not guarantee that access to a resource is
secure. As with any powerful programming technique, if semaphores
are misused or misinterpreted, a software error can easily happen.
Initialization of the semaphores is not automatic and must be
handled via the initialization program at power-up. Since any sema-
phore request flag which contains a zero must be reset to a one, all
semaphores on both sides should have a one written into them at
initialization from both sides to assure that they will be free when
needed.
Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso
thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining
azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput
registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)
signalsgoactive.Thisservestodisallowthesemaphorefromchanging
stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.
20
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
semaphoreflags.AlleightsemaphorescouldbeusedtodividetheDual-
PortSRAMorothersharedresourcesintoeightparts.Semaphorescan
evenbeassigneddifferentmeaningsondifferentsidesratherthanbeing
given a common meaning as was shown in the example above.
Semaphores are a useful form of arbitration in systems like disk
interfaces where the CPU must be locked out of a section of memory
during a transfer and the I/O device cannot tolerate any wait states.
With the use of semaphores, once the two devices has determined
which memory area was “off-limits” to the CPU, both the CPU and the
I/O devices could access their assigned portions of memory continu-
ously without any wait states.
UsingSemaphores-SomeExamples
Perhapsthesimplestapplicationofsemaphoresistheirapplicationas
resourcemarkersfortheIDT70V06’sDual-PortSRAM.Saythe16Kx8
SRAM was to be divided into two 8K x 8 blocks which were to be
dedicated at any one time to servicing either the left or right port.
Semaphore0couldbeusedtoindicatethesidewhichwouldcontrolthe
lower section of memory, and Semaphore 1 could be defined as the
indicatorfortheuppersectionofmemory.
Totakearesource,inthisexamplethelower8KofDual-PortSRAM,
the processor on the left port could write and then read a zero in to
Semaphore0.Ifthistaskweresuccessfullycompleted(azerowasread
back rather than a one), the left processor would assume control of the
lower8K.Meanwhiletherightprocessorwasattemptingtogaincontrolof
the resourceaftertheleftprocessor,itwouldreadbackaoneinresponse
tothezeroithadattemptedtowriteintoSemaphore0. Atthispoint, the
softwarecouldchoosetotryandgaincontrolofthesecond8Ksectionby
writing,thenreadingazerointoSemaphore1.Ifitsucceededingaining
control,itwouldlockouttheleftside.
Semaphores are also useful in applications where no memory
“WAIT” state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assignedSRAMsegmentsatfullspeed.
Anotherapplicationisintheareaofcomplexdatastructures.Inthis
case, block arbitration is very important. For this application one
processor may be responsible for building and updating a data
structure. The other processor then reads and interprets that data
structure. If the interpreting processor reads an incomplete data
structure, a major error condition may exist. Therefore, some sort of
arbitration must be used between the two different processors. The
building processor arbitrates for the block, locks it and then is able to
goinandupdatethedatastructure.Whentheupdateiscompleted,the
data structure block is released. This allows the interpreting processor
to come back and read the complete data structure, thereby guaran-
teeing a consistent data structure.
Once the left side was finished with its task, it would write a one to
Semaphore 0 and may then try to gain access to Semaphore 1. If
Semaphore 1 was still occupied by the right side, the left side could
undo its semaphore request and perform other tasks until it was able
to write, then read a zero into Semaphore 1. If the right processor
performsasimilartaskwithSemaphore0,thisprotocolwouldallowthe
two processors to swap 8K blocks of Dual-Port SRAM with each other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
D0
D
D
D0
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
,
2942 drw 19
Figure 4. IDT70V06 Semaphore Logic
6.42
21
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
A
A
XXXXX
A
999
A
A
Device
Type
Power Speed Package
Process/
Temperature
Range
Tube or Tray
Tape and Reel
Blank
8
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I(1)
G(2)
Green
PF
G
J
64-pin TQFP (PN64)
68-pin PGA (G68)
68-pin PLCC (J68)
15
20
25
35
55
Commercial Only
Commercial & Industrial
Commercial & Industrial
Commercial Only
Speed in Nanoseconds
Commercial Only
S
L
Standard Power
Low Power
128K (16K x 8) 3.3V Dual-Port RAM
70V06
2942 drw 20
NOTES:
1. ContactyourlocalsalesofficeforIndustrialtemprangeinotherspeeds,packagesandpowers.
2. Greenpartsareavailable,forspecificspeeds,packages,andpowers,contactyourlocalsalesoffice.
Datasheet Document History
3/10/99:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Page 2 and 3 Added additional notes to pin configurations
Changeddrawingformat
6/9/99:
11/10/99:
3/10/00:
Replaced IDT logo
Added 15 & 20ns speed grades
Upgraded DC parameters
AddedIndustrialTemperatureinformation
Changed±200mVto0mV
5/30/00:
Page 5 Increasedstoragetemperatureparameter
ClarifiedTA parameter
Page 6 DCElectricalparameters–changedwordingfrom"open"to"disabled"
22
IDT70V06S/L
High-Speed 3.3V 16K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DatasheetDocumentHistory(cont'd)
11/20/01:
Page 1 CorrectedstandbypowerdesignationfrommWtoµW
Page 2 & 3 Added date revision for pin configurations
Page 2, 3, 5 & 6 Changed naming conventions from VCC to VDD and from GND to VSS
Page 6 RemovedIndustrialtempforstandardpowerfor20nsand25nsspeedsfromDCElectricalCharacteristics
RemovedIndustrialtempfor35nsand55nsspeedsfromDCElectricalCharacteristics
Pages8,13&16RemovedIndustrialtempfor35nsand55nsspeedsfromACElectricalCharacteristics
Page 8 Replaced table 11 with table 11a to show AC Electrical Characteristics for READ CYCLE for 15, 20 & 25ns
Page 22 RemovedIndustrialtempfrom35nsand55nsinorderinginformation
Page 22 Removed "IDT" from orderable part number
10/23/08:
08/20/15:
Page 1 InFeatures:Addedtext:“Greenpartsavailable,seeorderinginformation”.
Page 2 InDescription:RemovedIDTinreferencetofabrication
Page 2 ,3 & 22 The package codes PN64-1, G68-1 & J68-1 changed to PN64, G68 & J68 respectively to match standard
packagecodes
Page 2 & 3 Removed date from all of the pin configurations 64-pin TQFP, 68-pin PGA & 68-pin PLCC configurations
Page 19 & 20 Corrected miscellaneous typo's
Page 22 AddedGreenandTape&ReelindicatorstotheOrderingInformationandupdatedfootnotes
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
DualPortHelp@idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
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