70V07L25GGI8 [IDT]
HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM;
| 型号： | 70V07L25GGI8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 3.3V 32K x 8 DUAL-PORT STATIC RAM |
| 文件： | 总19页 (文件大小：182K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT70V07S/L
HIGH-SPEED 3.3V
32K x 8 DUAL-PORT
STATIC RAM
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
Features
◆
IDT70V07 easily expands data bus width to 16 bits or more
using the Master/Slave select when cascading more than
one device
M/S = VIH for BUSY output flag on Master
M/S = VIL for BUSY input on Slave
On-chip port arbitration logic
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
◆
◆
– Commercial:25/35/55ns(max.)
– Industrial:25/35ns(max.)
Low-power operation
◆
◆
◆
Full on-chip hardware support of semaphore signaling
between ports
– IDT70V07S
Active: 300mW (typ.)
Standby: 3.3mW (typ.)
– IDT70V07L
Active: 300mW (typ.)
◆
◆
◆
◆
Fully asynchronous operation from either port
TTL-compatible, single 3.3V ( 0.3V) power supply
Available in 68-pin PGA and PLCC, and a 80-pin TQFP
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Standby: 660µW(typ.)
Interrupt Flag
◆
◆
Green parts available, see ordering information
Functional Block Diagram
OE
R
R
OE
L
CE
CEL
R/WR
R/W
L
I/O0L- I/O7L
I/O0R-I/O7R
(1,2)
I/O
Control
I/O
Control
,
(1,2)
BUSY
L
BUSY
R
A
14R
0R
A
14L
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
A
0L
15
15
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
L
L
CE
OE
R/W
R
R
OE
R
R/W
L
SEM
L
SEMR
M/S
(2)
(2)
INTR
INTL
2943 drw 01
NOTES:
1. (MASTER): BUSY is output; (SLAVE): BUSY is input.
2. BUSY and INT outputs are non-tri-stated push-pull.
MARCH 2018
1
DSC 2943/10
©2018 Integrated Device Technology, Inc.
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
address,andI/Opinsthatpermitindependent,asynchronousaccessfor
reads or writes to any location in memory. An automatic power down
featurecontrolledbyCEpermitstheon-chipcircuitryofeachporttoenter
a very low standby power mode.
Fabricatedusing CMOShigh-performancetechnology,thesedevices
typically operate on only 300mW of power.
Description
The IDT70V07 is a high-speed 32K x 8 Dual-Port Static RAM. The
IDT70V07 is designed to be used as a stand-alone 256K-bit Dual-Port
RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-
or-morewordsystems.UsingtheIDTMASTER/SLAVEDual-PortRAM
approach in 16-bit or wider memory system applications results in full-
speed,error-freeoperationwithouttheneedforadditionaldiscretelogic.
This device provides two independent ports with separate control,
TheIDT70V07ispackagedinaceramic68-pinPGAandPLCCand
a 80-pin thin quad flatpack (TQFP).
Pin Configurations(1,2,3)
10/25/01
INDEX
9
8
7
6
5
4
3
2
1 68 67 66 65 64 63 62 61
60
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
A
A
A
A
A
A
5L
4L
3L
2L
1L
0L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
IDT70V07J
J68-1(4)
INT
L
VCC
BUSY
GND
M/S
L
68-Pin PLCC
Top View(5)
GND
I/O0R
I/O1R
I/O2R
BUSY
R
INT
R
VCC
A
A
A
A
A
0R
I/O3R
I/O4R
I/O5R
I/O6R
1R
2R
3R
4R
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
2943 drw 02
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. J68-1 package body is approximately .95 in x .95 in x .17 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
10/25/01
INDEX
79
80
78 77 76 75 74 73
71 70 69 68 67 66 65 64 63 62 61
72
1
2
3
4
N/C
A5L
A4L
A3L
A2L
A1L
A0L
INTL
BUSYL
GND
M/S
BUSYR
INTR
A0R
A1R
A2R
A3R
A4R
N/C
N/C
I/O2L
I/O3L
I/O4L
I/O5L
GND
I/O6L
I/O7L
VCC
N/C
GND
I/O0R
I/O1R
I/O2R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
60
59
58
57
56
55
54
53
5
6
7
8
9
IDT70V07PF
PN80-1(4)
52
51
50
49
48
47
46
10
11
12
13
14
15
16
80-Pin TQFP
Top View(5)
45
44
43
42
41
17
18
19
20
N/C
N/C
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
2943 drw 03
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. PN80-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
3
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
10/25/01
51
A5L
52
A6L
54
A8L
56
50
A4L
48
A2L
46
A0L
44
BUSYL
42
M/S
40
INTR
38
A1R
36
A3R
11
10
09
08
07
53
A7L
49
A3L
47
A1L
45
INTL
43
GND
41
39
37
35
A4R
34
A5R
BUSYR A0R A2R
55
A9L
32
A7R
33
A6R
57
A11L
30
A9R
31
A8R
A10L
58
A12L
60
A13L
62
59
VCC
28
A11R
29
A10R
IDT70V07G
G68-1(4)
61
26
GND
27
A12R
06
05
A14L
68-Pin PGA
Top View(5)
63
SEML
24
25
A14R A13R
CEL
65
64
22
SEMR
23
CER
04
03
02
01
OEL
R/WL
66
67
20
OER
21
R/WR
I/O0L
N/C
1
3
5
7
9
68
11
13
VCC
15
18
I/O7R
19
N/C
GND
GND
I/O7L
I/O1L
I/O4L
I/O2L
I/O1R
I/O4R
,
2
4
6
8
10
12
14
16
17
I/O5L
I/O0R I/O2R I/O3R I/O5R I/O6R
VCC
E
I/O6L
I/O3L
K
A
B
C
D
F
G
H
J
L
INDEX
2943 drw 04
NOTES:
1. All VCC pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 1.18 in x 1.18 in x .16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Names
Left Port
Right Port
Names
Chip Enable
CE
R/W
OE
L
CE
R/W
OE
R
L
R
Read/Write Enable
Output Enable
Address
L
R
A
0L - A14L
A
0R - A14R
I/O0R - I/O7R
SEM
INT
I/O0L - I/O7L
SEM
INT
BUSY
Data Input/Output
Semaphore Enable
Interrupt Flag
L
R
L
R
Busy Flag
L
BUSY
M/S
R
Master or Slave Select
Power (3.3V)
V
CC
GND
Ground (0V)
2943 tbl 01
4
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table I: Non-Contention Read/Write Control
Outputs
Inputs(1)
R/W
I/O0-7
Mode
CE
H
L
OE
X
SEM
H
X
L
High-Z
DATAIN
DATAOUT
High-Z
Deselected: Power-Down
Write to Memory
X
H
L
H
X
L
H
Read Memory
X
H
X
Outputs Disabled
2943 tbl 02
NOTE:
1. A0L — A14L ≠ A0R — A14R
Truth Table II: Semaphore Read/Write Control
Inputs(1)
Outputs
R/W
I/O0-7
Mode
CE
H
OE
L
SEM
H
↑
L
L
L
DATAOUT
Read Data in Semaphore Flag
Write I/O into Semaphore Flag
H
X
DATAIN
0
____
L
X
X
Not Allowed
2943 tbl 03
NOTE:
1. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O7). These eight semaphores are addressed by A0-A2
Absolute Maximum Ratings(1)
Maximum Operating Temperature
and Supply Voltage(1)
Symbol
Rating
Commercial
& Industrial
Unit
Grade
Commercial
Industrial
Ambient Temperature
GND
Vcc
(2)
V
TERM
Terminal Voltage
-0.5 to +4.6
V
0OC to +70OC
0V
3.3V
3.3V
+
+
0.3
0.3
with Respect to GND
-40OC to +85OC
0V
(3)
T
BIAS
STG
JN
OUT
Temperature Under Bias
StorageTemperature
Junction Temperature
DC Output Current
-55 to +125
-65 to +150
+150
oC
oC
oC
2943 tbl 05
T
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
T
I
50
mA
2943 tbl 04
NOTES:
Recommended DC Operating
Conditions(2)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed Vcc + 0.3V.
Symbol
Parameter
Supply Voltage
Ground
Min.
Typ.
Max.
Unit
V
V
CC
3.0
3.3
3.6
3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected.
GND
0
0
0
V
CC+0.3(2)
0.8
V
____
V
V
IH
IL
Input High Voltage
Input Low Voltage
2.0
V
Capacitance(1)
(TA = +25°C, f = 1.0MHz) TQFP Only
-0.3(1)
V
____
2943 tbl 06
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions
IN = 0V
OUT = 0V
Max. Unit
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 0.3V.
CIN
V
9
pF
(2)
OUT
C
V
10
pF
2943 tbl 07
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. COUT also references CI/O.
5
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
70V07S
70V07L
Symbol
|ILI
|ILO
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
Min.
Max.
10
Min.
Max.
Unit
µA
µA
V
___
___
|
V
CC = 3.6V, VIN = 0V to VCC
5
5
___
___
___
___
|
10
CE = VIH, VOUT = 0V to VCC
OL = +4mA
V
OL
OH
I
0.4
0.4
___
___
V
Output High Voltage
IOH = -4mA
2.4
2.4
V
2943 tbl 08
NOTE:
1. At VCC < 2.0V, input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VCC = 3.3V ± 0.3V)
70V07X25
Com'l
& Ind
70V07X35
Com'l
& Ind
70V07X55
Com'l Only
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
S
L
100
100
170
140
90
90
140
120
90
90
140
120
mA
CE = VIL, Outputs Disabled
SEM = VIL
(3)
f = fMAX
____
____
____
____
____
____
____
____
IND
S
L
100
185
90
155
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
S
L
14
12
30
24
12
10
30
24
12
10
30
24
mA
mA
mA
mA
CE
SEM
f = fMAX
R
= CE
L
= VIH
= VIH
R
= SEM
L
(3)
____
____
____
____
____
____
____
____
S
L
12
50
10
50
(5)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
IND
S
L
50
50
95
85
45
45
87
75
45
45
87
75
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(3)
f=fMAX
SEM
____
____
____
____
____
____
____
____
S
L
R
= SEM
L
= VIH
50
105
45
95
ISB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CE
L
and
COM'L
IND
S
L
1.0
0.2
6
3
1.0
0.2
6
3
1.0
0.2
6
3
CE
R
> VCC - 0.2V,
V
IN > VCC - 0.2V or
____
____
____
____
____
____
____
____
V
IN < 0.2V, f = 0(4)
S
L
0.2
3
0.2
3
SEMR = SEML > VCC - 0.2V
ISB4
Full Standby Current
(One Port -
CMOS Level Inputs)
COM'L
IND
S
L
60
60
90
80
55
55
85
74
55
55
85
74
CE"A" < 0.2V and
CE"B" > VCC - 0.2V(5)
SEM
R = SEML > VCC - 0.2V
____
____
____
____
____
____
____
____
S
L
V
IN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled,
60
90
55
85
(3)
f = fMAX
2943 tbl 09
NOTES:
1. 'X' in part number indicates power rating (S or L).
2. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 80mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions" of input levels
of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
3.3V
3.3V
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns
590Ω
590Ω
Input Rise/Fall Times
DATAOUT
BUSY
INT
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
DATAOUT
1.5V
30pF
5pF*
435Ω
435Ω
Figures 1 and 2
2943 tbl 10
2943 drw 06
2943 drw 05
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
Figure 1. AC Output Test Load
* Including scope and jig.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(4)
70V07X25
Com'l
& Ind
70V07X35
Com'l
& Ind
70V07X55
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
25
35
55
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
t
Address Access Time
25
25
35
35
55
55
Chip Enable Access Time(3)
____
____
____
____
____
____
t
t
Output Enable Access Time
15
20
30
____
____
____
t
Output Hold from Address Change
Output Low-Z Time(1,2)
3
3
3
____
____
____
t
3
3
3
Output High-Z Time(1,2)
15
20
25
____
____
____
t
t
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
0
0
0
____
____
____
____
____
____
t
25
35
50
____
____
____
t
15
15
15
____
____
____
t
35
45
65
ns
2943 tbl 11
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.
4. 'X' in part number indicates power rating (S or L).
Timing of Power-Up Power-Down
CE
tPU
tPD
ICC
ISB
,
2943 drw 07
7
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Waveform of Read Cycles(5)
tRC
ADDR
(4)
AA
t
(4)
tACE
CE
OE
(4)
tAOE
R/W
DATAOUT
BUSYOUT
(1)
t
OH
(2)
tLZ
VALID DATA(4)
t
HZ
(3,4)
2943 drw 08
t
BDD
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is de-asserted first, CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY has no
relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage(5)
70V07X25
Com'l
& Ind
70V07X35
Com'l
& Ind
70V07X55
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tEW
tAW
tAS
Write Cycle Time
25
20
20
0
35
30
30
0
55
45
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
Address Set-up Time(3)
tWP
tWR
tDW
tHZ
Write Pulse Width
20
0
25
0
40
0
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
15
20
30
____
____
____
15
20
25
tDH
Data Hold Time(4)
0
0
0
____
____
____
Write Enable to Output in High-Z(1,2)
Output Active from End-of-Write(1,2,4)
SEM Flag Write to Read Time
SEM Flag Contention Window
15
20
25
____
____
____
tWZ
tOW
tSWRD
tSPS
____
____
____
0
5
5
0
5
5
0
5
5
____
____
____
____
____
____
ns
2943 tbl 12
NOTES:
1. Transition is measured 0mV from Low or High impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.
4. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (S or L).
8
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
t
WC
ADDRESS
(7)
tHZ
OE
tAW
CE or SEM(9)
(7)
tHZ
(3)
(6)
(2)
tWR
tAS
tWP
R/W
(7)
tLZ
t
OW
tWZ
(4)
(4)
OUT
DATA
tDH
tDW
IN
DATA
,
2943 drw 09
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
tWC
ADDRESS
tAW
CE or SEM(9)
(3)
WR
(6)
(2)
t
tAS
tEW
R/W
tDW
tDH
DATAIN
2943 drw 10
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the
bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
9. To access SRAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
9
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
tOH
A0-A2
VALID ADDRESS
VALID ADDRESS
t
AW
tWR
tACE
tEW
SEM
tDW
tSOP
OUT
DATA
DATA
0
IN
DATA VALID
VALID(2)
tAS
tWP
tDH
R/W
tSWRD
tAOE
OE
t
SOP
Write Cycle
Read Cycle
2943 drw 11
NOTES:
1. CE = VIH for the duration of the above timing (both write and read cycle).
2. “DATAOUT VALID” represents all I/O's (I/O0-I/O7) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
(2)
SIDE "A"
R/W"A"
SEM"A"
t
SPS
A0"B"-A2"B"
MATCH
(2)
SIDE
R/W"B"
SEM"B"
"B"
2943 drw 12
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/WB or SEM"B" going HIGH.
4. If tSPS is not satisfied, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
10
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6)
70V07X25
Com'l
& Ind
70V07X35
Com'l
& Ind
70V07X55
Com'l Only
Symbol
BUSY TIMING (M/S = VIH
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
)
____
____
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
25
25
25
35
35
35
45
45
45
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Arbitration Priority Set-up Time(2)
BUSY Disable to Valid Data(3)
t
t
t
25
35
45
____
____
____
t
5
5
5
____
____
____
t
35
40
50
BUSY TIMING (M/S - VIL
)
____
____
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
t
WB
0
0
0
ns
ns
tWH
20
25
25
PORT-TO-PORT DELAY TIMING
____
____
____
____
____
____
t
WDD
Write Pulse to Data Delay(1)
55
50
65
60
85
80
ns
tDDD
Write Data Valid to Read Data Delay(1)
ns
2943 tbl 13
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
Timing Waveform of Write with Port-to-Port Read and BUSY(2,4,5)
tWC
ADDR"A"
R/W"A"
MATCH
tWP
tDW
t
DH
DATAIN "A"
VALID
(1)
tAPS
ADDR"B"
MATCH
tBDA
tBDD
tBAA
BUSY"B"
tWDD
DATAOUT "B"
VALID
(3)
tDDD
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL
2943 drw 13
3. OE = VIL for the reading port.
4. If M/S = VIL (SLAVE), then BUSY is an input (BUSY"A" = VIH and BUSY"B" = "don't care", for this example).
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
11
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY
tWP
R/W"A"
tWB
BUSY"B"
(1)
t
WH
(2)
R/W"B"
2943 drw 14
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on Port "B" blocking R/W"B", until BUSY"B" goes HIGH.
Waveform of BUSY Arbitration Controlled by CE Timing(1)
ADDR"A"
ADDRESSES MATCH
and "B"
CE"A"
(2)
tAPS
CE"B"
tBAC
tBDC
BUSY"B"
2943 drw 15
Waveform of BUSY Arbitration Cycle Controlled by Address Match Timing(1)
ADDR"A"
ADDRESS "N"
(2)
tAPS
ADDR"B"
MATCHING ADDRESS "N"
tBAA
tBDA
BUSY"B"
2943 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from Port “A”.
2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted.
12
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1)
70V07X25
Com'l
& Ind
70V07X35
Com'l
& Ind
70V07X55
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
0
ns
ns
ns
t
0
0
0
____
____
____
t
25
30
30
35
40
45
____
____
____
t
Interrupt Reset Time
ns
2043 tbl 14
NOTE:
1. 'X' in part number indicates power rating (S or L).
Waveform of Interrupt Timing(1)
tWC
INTERRUPT SET ADDRESS (2)
ADDR"A"
CE"A"
(3)
(4)
tAS
tWR
R/W"A"
INT"B"
(3)
tINS
2943 drw 17
t
RC
ADDR"B"
CE"B"
INTERRUPT CLEAR ADDRESS (2)
(3)
tAS
OE"B"
(3)
tINR
INT"B"
2943 drw 18
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt Truth Table III.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
13
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Truth Table III — Interrupt Flag(1)
Left Port
Right Port
R/W
L
A14L-A0L
R/WR
A14R-A0R
Function
CEL
OEL
INTL
CER
OER
INTR
L
X
X
X
L
X
X
L
X
7FFF
X
X
X
X
L
L
X
X
X
L(2)
Set Right INT
Reset Right INT
Set Left INT Flag
Reset Left INT
R Flag
(3)
X
X
X
L
7FFF
7FFE
X
H
R Flag
X
X
L(3)
H(2)
L
X
X
X
L
L
7FFE
X
X
L Flag
2943 tbl 15
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
Truth Table IV — Address BUSY
Arbitration
Inputs
Outputs
A
0L-A14L
(1)
(1)
A0R-A14R
Function
Normal
Normal
Normal
CE
L
CE
R
BUSY
L
BUSYR
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
H
MATCH
H
H
MATCH
(2)
(2)
Write Inhibit(3)
2943 tbl 16
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V07 are push-
pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored when
BUSYR outputs are driving LOW regardless of actual logic level on the pin.
Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)
Functions
D0
- D7
Left
D0
- D7
Right
Status
No Action
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
0
0
1
1
0
1
1
1
0
1
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
2943 tbl 17
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V07.
2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0 - I/O7). These eight semaphores are addressed by A0 -A2.
3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.
14
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
programmedbytyingtheBUSYpinsHIGH.Ifdesired,unintendedwrite
operationscanbepreventedtoaportbytyingtheBUSYpinforthatport
LOW.
The BUSY outputs on the IDT 70V07 RAM in master mode, are
push-pull type outputs and do not require pull up resistors to operate.
If these RAMs are being expanded in depth, then the BUSY indication
for the resulting array requires the use of an external AND gate.
Functional Description
The IDT70V07 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT70V07 has an automatic power down
featurecontrolledbyCE.TheCEcontrolson-chippowerdowncircuitry
thatpermitstherespectiveporttogointoastandbymodewhennotselected
(CEHIGH). Whenaportisenabled, accesstotheentirememoryarray
ispermitted.
Width Expansion with BUSY Logic
Master/Slave Arrays
Interrupts
When expanding an IDT70V07 RAM array in width while using
BUSY logic, one master part is used to decide which side of the RAM
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master, use the BUSY signal as a write inhibit signal. Thus on the
IDT70V07 RAM the BUSY pin is an output if the part is used as a
master (M/S pin = VIH), and the BUSY pin is an input if the part used
as a slave (M/S pin = VIL) as shown in Figure 3.
If the user chooses the interrupt function, a memory location (mail
boxormessagecenter)isassignedtoeachport. Theleftportinterrupt
flag (INTL) is asserted when the right port writes to memory location
7FFE (HEX), where a write is defined as CER = R/WR = VIL per Truth
Table III. The left port clears the interrupt through access of address
location 7FFE when CEL = OEL = VIL, R/W is a "don't care". Likewise,
the right port interrupt flag (INTR) is asserted when the left port writes
to memory location 7FFF (HEX) and to clear the interrupt flag (INTR),
the right port must read the memory 7FFF location 7FFF. The
message (8 bits) at 7FFE or 7FFF is user-defined since it is an
addressable SRAM location. If the interrupt function is not used,
address locations 7FFE and 7FFF are not used as mail boxes, but as
part of the random access memory. Refer to Truth Table III for the
interrupt operation.
If two or more master parts were used when expanding in width, a
splitdecisioncouldresultwithonemasterindicatingBUSYononeside
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
TheBUSYarbitration,onamaster,isbasedonthechipenableand
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with the R/W signal. Failure to
observe this timing can result in a glitched internal write inhibit signal
and corrupted data in the slave.
CE
CE
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
BUSY
L
BUSY
L
BUSY
R
BUSYR
MASTER
Dual Port
RAM
SLAVE
Dual Port
RAM
CE
CE
Semaphores
BUSY
R
BUSY
L
BUSY
L
BUSY
R
BUSYR
BUSY
L
The IDT70V07 is an extremely fast Dual-Port 32K x 8 CMOS Static
RAM with an additional 8 address locations dedicated to binary
semaphore flags. These flags allow either processor on the left or right
side of the Dual-Port SRAM to claim a privilege over the other
processor for functions defined by the system designer’s software. As
an example, the semaphore can be used by one processor to inhibit
the other from accessing a portion of the Dual-Port SRAM or any other
shared resource.
,
2943 drw 19
Figure 3. Busy and chip enable routing for both width and depth expansion
with IDT70V07 RAMs.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
SRAM have accessed the same location at the same time. It also
allows one of the two accesses to proceed and signals the other side
that the SRAM is “busy”. The busy pin can then be used to stall the
access until the operation on the other side is completed. If a write
operation has been attempted from the side that receives a BUSY
indication, the write signal is gated internally to prevent the write from
proceeding.
The use of BUSY logic is not required or desirable for all applica-
tions. InsomecasesitmaybeusefultologicallyORthe BUSYoutputs
togetheranduseanyBUSYindicationasaninterruptsourcetoflagthe
event of an illegal or illogical operation. If the write inhibit function of
BUSYlogicisnotdesirable, theBUSYlogiccanbedisabledbyplacing
the part in slave mode with the M/Spin. Once in slave mode theBUSY
pinoperatessolelyasawriteinhibitinputpin. Normaloperationcanbe
The Dual-Port SRAM features a fast access time, and both ports
are completely independent of each other. This means that the activity
on the left port in no way slows the access time of the right port. Both
ports are identical in function to standard CMOS Static RAM and can
be read from, or written to, at the same time with the only possible
conflict arising from the simultaneous writing of, or a simultaneous
READ/WRITE of, a non-semaphore location. Semaphores are pro-
tected against such ambiguous situations and may be used by the
system program to avoid any conflicts in the non-semaphore portion
of the Dual-Port SRAM. These devices have an automatic power-
downfeaturecontrolledbyCE, theDual-PortSRAMenable, andSEM,
the semaphore enable. The CE and SEM pins control on-chip power
down circuitry that permits the respective port to go into standby mode
when not selected. This is the condition which is shown in Truth Table
15
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
I where CE and SEM are both HIGH.
semaphoreflagsusefulininterprocessorcommunications.(Athorough
Systems which can best use the IDT70V07 contain multiple discussionontheuseofthisfeaturefollowsshortly.)Azerowrittenintothe
processors or controllers and are typically very high-speed systems samelocationfromtheothersidewillbestoredinthesemaphorerequest
which are software controlled or software intensive. These systems
can benefit from a performance increase offered by the IDT70V07's
hardware semaphores, which provide a lockout mechanism without
requiring complex programming.
L PORT
R PORT
SEMAPHORE
REQUEST FLIP FLOP
SEMAPHORE
REQUEST FLIP FLOP
Softwarehandshakingbetweenprocessorsoffersthemaximumin
system flexibility by permitting shared resources to be allocated in
varying configurations. The IDT70V07 does not use its semaphore
flags to control any resources through hardware, thus allowing the
system designer total flexibility in system architecture.
An advantage of using semaphores rather than the more common
methods of hardware arbitration is that wait states are never incurred
in either processor. This can prove to be a major advantage in very
high-speed systems.
0
D
0
D
D
D
Q
Q
WRITE
WRITE
SEMAPHORE
READ
SEMAPHORE
READ
,
2943 drw 20
Figure 4. IDT70V07 Semaphore Logic
latchforthatsideuntilthesemaphoreisfreedbythefirstside.
How the Semaphore Flags Work
The semaphore logic is a set of eight latches which are indepen-
dent of the Dual-Port SRAM. These latches can be used to pass a flag,
or token, from one port to the other to indicate that a shared resource
is in use. The semaphores provide a hardware assist for a use
assignmentmethodcalled“TokenPassingAllocation.”Inthismethod,
thestateofasemaphorelatchisusedasatokenindicatingthatshared
resource is in use. If the left processor wants to use this resource, it
requests the token by setting the latch. This processor then verifies its
success in setting the latch by reading it. If it was successful, it
proceeds to assume control over the shared resource. If it was not
successful in setting the latch, it determines that the right side
processor has set the latch first, has the token and is using the shared
resource. The left processor can then either repeatedly request that
semaphore’s status or remove its request for that semaphore to
perform another task and occasionally attempt again to gain control of
the token via the set and test sequence. Once the right side has
relinquished the token, the left side should succeed in gaining control.
The semaphore flags are active LOW. A token is requested by
writing a zero into a semaphore latch and is released when the same
side writes a one to that latch.
The eight semaphore flags reside within the IDT70V07 in a
separate memory space from the Dual-Port SRAM. This address
space is accessed by placing a LOW input on the SEM pin (which acts
as a chip select for the semaphore flags) and using the other control
pins (Address, OE, and R/W) as they would be used in accessing a
standard Static RAM. Each of the flags has a unique address which
can be accessed by either side through address pins A0 – A2. When
accessing the semaphores, none of the other address pins has any
effect.
Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso
thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining
azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput
registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)
signalsgoactive.Thisservestodisallowthesemaphorefromchanging
stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.
Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust
cause either signal (SEM or OE) to go inactive or the output will never
change.
A sequence WRITE/READ must be used by the semaphore in
order to guarantee that no system level contention will occur. A
processor requests access to shared resources by attempting to write
a zero into a semaphore location. If the semaphore is already in use,
the semaphore request latch will contain a zero, yet the semaphore
flag will appear as one, a fact which the processor will verify by the
subsequent read (see Truth Table V). As an example, assume a
processorwritesazerototheleftportatafreesemaphorelocation. On
asubsequentread, theprocessorwillverifythatithaswrittensuccess-
fully to that location and will assume control over the resource in
question. Meanwhile, if a processor on the right side attempts to write
a zero to the same semaphore flag it will fail, as will be verified by the
factthataonewillbereadfromthatsemaphoreontherightsideduring
subsequent read. Had a sequence of READ/WRITE been used
instead, system contention problems could have occurred during the
gap between the read and write cycles.
It is important to note that a failed semaphore request must be
followed by either repeated reads or by writing a one into the same
location. The reason for this is easily understood by looking at the
simple logic diagram of the semaphore flag in Figure 4. Two sema-
phore request latches feed into a semaphore flag. Whichever latch is
first to present a zero to the semaphore flag will force its side of the
semaphore flag LOW and the other side HIGH. This condition will
continue until a one is written to the same semaphore request latch.
Should the other side’s semaphore request latch have been written to
a zero in the meantime, the semaphore flag will flip over to the other
side as soon as a one is written into the first side’s request latch. The
second side’s flag will now stay LOW until its semaphore request latch
iswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore
When writing to a semaphore, only data pin D0 is used. If a LOW
level is written into an unused semaphore location, that flag will be set
to a zero on that side and a one on the other side (see Truth Table V).
That semaphore can now only be modified by the side showing the
zero. When a one is written into the same location from the same side,
the flag will be set to a one for both sides (unless a semaphore request
fromtheothersideispending)andthencanbewrittentobybothsides.
The fact that the side which is able to write a zero into a semaphore
subsequently locks out writes from the other side is what makes
16
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
is requested and the processor which requested it no longer needs the side.
resource, the entire system can hang up until a one is written into that
Once the left side was finished with its task, it would write a one to
semaphorerequestlatch.
Semaphore 0 and may then try to gain access to Semaphore 1. If
The critical case of semaphore timing is when both sides request Semaphore 1 was still occupied by the right side, the left side could
a single token by attempting to write a zero into it at the same time. The undo its semaphore request and perform other tasks until it was able
semaphore logic is specially designed to resolve this problem. If to write, then read a zero into Semaphore 1. If the right processor
simultaneous requests are made, the logic guarantees that only one performsasimilartaskwithSemaphore0,thisprotocolwouldallowthe
side receives the token. If one side is earlier than the other in making two processors to swap 16K blocks of Dual-Port SRAM with each
the request, the first side to make the request will receive the token. If other.
bothrequestsarriveatthesametime, theassignmentwillbearbitrarily
made to one port or the other.
The blocks do not have to be any particular size and can even be
variable, depending upon the complexity of the software using the
One caution that should be noted when using semaphores is that semaphore flags. All eight semaphores could be used to divide the
semaphores alone do not guarantee that access to a resource is Dual-Port SRAM or other shared resources into eight parts. Sema-
secure. As with any powerful programming technique, if semaphores phores can even be assigned different meanings on different sides
are misused or misinterpreted, a software error can easily happen. rather than being given a common meaning as was shown in the
Initialization of the semaphores is not automatic and must be example above.
handled via the initialization program at power-up. Since any sema-
Semaphores are a useful form of arbitration in systems like disk
phore request flag which contains a zero must be reset to a one, all interfaces where the CPU must be locked out of a section of memory
semaphores on both sides should have a one written into them at during a transfer and the I/O device cannot tolerate any wait states.
initialization from both sides to assure that they will be free when With the use of semaphores, once the two devices has determined
needed.
which memory area was “off-limits” to the CPU, both the CPU and the
I/O devices could access their assigned portions of memory continu-
ously without any wait states.
Semaphores are also useful in applications where no memory
“WAIT” state is available on one or both sides. Once a semaphore
handshake has been performed, both processors can access their
assigned SRAM segments at full speed.
Anotherapplicationisintheareaofcomplexdatastructures. Inthis
case, block arbitration is very important. For this application one
processor may be responsible for building and updating a data
structure. The other processor then reads and interprets that data
structure. If the interpreting processor reads an incomplete data
structure, a major error condition may exist. Therefore, some sort of
arbitration must be used between the two different processors. The
building processor arbitrates for the block, locks it and then is able to
goinandupdatethedatastructure.Whentheupdateiscompleted,the
data structure block is released. This allows the interpreting processor
to come back and read the complete data structure, thereby guaran-
teeing a consistent data structure.
Using Semaphores—Some Examples
Perhaps the simplest application of semaphores is their applica-
tionasresourcemarkersfortheIDT70V07’sDual-PortSRAM. Saythe
32K x 8 SRAM was to be divided into two 16K x 8 blocks which were
to be dedicated at any one time to servicing either the left or right port.
Semaphore 0 could be used to indicate the side which would control
thelowersectionofmemory,andSemaphore1couldbedefinedasthe
indicator for the upper section of memory.
To take a resource, in this example the lower 16K of Dual-Port
SRAM, the processor on the left port could write and then read a zero
in to Semaphore 0. If this task were successfully completed (a zero
was read back rather than a one), the left processor would assume
controlofthelower16K.Meanwhiletherightprocessorwasattempting
to gain control of the resource after the left processor, it would read
back a one in response to the zero it had attempted to write into
Semaphore 0. At this point, the software could choose to try and gain
control of the second 16K section by writing, then reading a zero into
Semaphore1.Ifitsucceededingainingcontrol,itwouldlockouttheleft
17
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Ordering Information
XXXXX
A
999
A
A
A
A
Device
Type
Power Speed Package
Process/
Temperature
Range
Blank
8
Tube or Tray
Tape and Reel
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(2)
Green
PF
G
J
80-pin TQFP (PN80-1)
68-pin PGA (G68-1)
68-pin PLCC (J68-1)
,
25
35
55
Commercial & Industrial
Commercial & Industrial
Commercial Only
Speed in nanoseconds
S
L
Standard Power
Low Power
256K (32K x 8) 3.3V Dual-Port RAM
70V07
2943 drw 21
NOTES:
1. Contact your local sales office for Industrial temp range in other speeds, packages and powers.
2. Greenpartsavailable.Forspecificspeeds,packagesandpowerscontactyourlocalsalesoffice.
LEADFINISH(SnPb)partsareinEOLprocess.ProductDiscontinuationNotice-PDN#SP-17-02
Datasheet Document History:
03/24/99:
Initiateddatasheetdocumenthistory
Converted to new format
Cosmetic and typographical corrections
Page2and3Addedadditionalnotestopinconfigurations
Changeddrawingformatt
06/09/99:
10/14/04:
RemovedPreliminarystatus
Page 1 Added I-temp offering
Page 4 Updated Capacitance table
Increased Storage Temp parameter in Absolute Maximum Rating table
Added Junction Temp to Absolute Maximum Rating table
Page 4, 5, 6, 7 & 10 Removed I-temp footnote from tables
Page5 AddedI-temp25nspowernumberstotheDCElectricalCharacteristicstable
DC Electrical parameters–changed wording from "open" to "disabled"
Page5&6 Changedtransitionmeasurementfrom 200mVto0mVinfootnotes
Page6, 7, 10, &12AddedI-temptoallACElectricalCharacteristicstable
Page 8 Updated Timing Waveform of Write Cycle No. 1, R/WControlled Timing
Page 1 & 17 Replaced old IDTTM logo with new IDTTM logo
Page 17 Added I-temp to 25ns speed grade in ordering information
Page 18 Removed "IDT" from orderable part number
01/29/09:
01/30/09:
Page 1 Addedgreenavailabilitytofeatures
Page 18 Addedgreenindicatortoorderinginformation
06/28/12:
Page 17 AddedT&Rindicatortoorderinginformation
18
IDT70V07S/L
High-Speed 32K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Datasheet Document History (cont'd)
01/28/13:
Page 1 Added 35nstoIndustrialofferinginFeaturessection
Page 2 RemovedreferencetoIDT's fabricationofCMOShigh-performancetechnologyinDescriptionsection
Page 6 Added 35ns Industrial Chars values to the DC Elec Chars table
Page7,8,11,13, &15AddedIndustrialtothe70V07X35columnheading
Page 18 AddedIndustrialtothe35nsspeedgradeintheorderinginformation
ProductDiscontinuationNotice-PDN#SP-17-02
03/19/18:
Last time buy expires June 15, 2018
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
19
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