70V27L15BF [IDT]
CABGA-144, Tray;
| 型号： | 70V27L15BF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | CABGA-144, Tray |
| 文件： | 总21页 (文件大小：363K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 3.3V
32K x 16 DUAL-PORT
STATIC RAM
IDT70V27S/L
Features:
◆
◆
IDT70V27 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device
M/S = VIH for BUSY output flag on Master,
M/S = VIL for BUSY input on Slave
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed access
◆
◆
– Commercial:15/20/25/35/55ns(max.)
– Industrial: 20/35ns(max.)
Low-power operation
◆
◆
◆
◆
Busy and Interrupt Flags
On-chip port arbitration logic
– IDT70V27S
Full on-chip hardware support of semaphore signaling
between ports
Fully asynchronous operation from either port
LVTTL-compatible, single 3.3V (±0.3V) power supply
Available in 100-pin Thin Quad Flatpack (TQFP), and 144-
pin Fine Pitch BGA (fpBGA)
Industrial temperature range (-40°C to +85°C) is available
for selected speeds
Green parts available, see ordering information
Active:500mW(typ.)
Standby: 3.3mW (typ.)
– IDT70V27L
◆
◆
◆
Active:500mW(typ.)
Standby: 660µW (typ.)
Separate upper-byte and lower-byte control for bus
◆
◆
◆
matching capability
Dual chip enables allow for depth expansion without
◆
external logic
FunctionalBlockDiagram
R/W
L
R/WR
UB
L
UB
R
CE0L
CE0R
CE1L
CE1R
OE
R
OE
L
L
LB
R
LB
I/O8-15L
I/O0-7L
I/O8-15R
I/O0-7R
I/O
Control
I/O
Control
,
(1,2)
(1,2)
BUSY
L
BUSY
R
32Kx16
A
14R
0R
A
14L
0L
Address
Decoder
Address
Decoder
MEMORY
ARRAY
70V27
A
A
A
14L
A
A
14R
0R
A
CE0L
0L
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE0R
CE1L
OE
CE1R
OE
L
R
R/
WL
R/WR
L
L
SEM
INT
SEM
R
(2)
(2)
INT
R
M/S(2)
NOTES:
3603 drw 01
1) BUSY is an input as a Slave (M/S=VIL) and an output as a Master (M/S=VIH).
2) BUSY and INT are non-tri-state totem-pole outputs (push-pull).
SEPTEMBER 2012
6.01
1
DSC3603/12
©2012IntegratedDeviceTechnology,Inc.
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
Description:
reads or writes to any location in memory. An automatic power down
featurecontrolledby thechipenables(CE0 andCE1)permitstheon-chip
circuitry of each port to enter a very low standby power mode.
Fabricated using CMOS high-performance technology, these
devices typically operate on only 500mW of power. The IDT70V27 is
packagedina100-pinThinQuadFlatpack(TQFP) anda144-pinFine
PitchBGA(fpBGA).
The IDT70V27 is a high-speed 32K x 16 Dual-Port Static RAM,
designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a
combinationMASTER/SLAVEDual-PortRAMfor32-bitandwiderword
systems.UsingtheIDTMASTER/SLAVEDual-PortRAMapproachin32-
bitorwidermemorysystemapplicationsresultsinfull-speed,error-free
operationwithouttheneedforadditionaldiscretelogic.
Thedeviceprovidestwoindependentportswithseparatecontrol,
address,andI/Opinsthatpermitindependent,asynchronousaccessfor
PinConfigurations(1,2,3)
07/29/04
INDEX
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
A
9L
A
9R
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
A
A
A
A
NC
NC
NC
LBR
UBR
CE0R
CE1R
SEM
V
R/W
OE
V
V
10R
11R
12R
13R
14R
2
A
A
A
A
A
NC
NC
NC
LB
UB
CE0L
CE1L
SEM
V
R/W
OE
V
V
10L
11L
12L
13L
14L
3
4
5
6
7
8
9
L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
IDT70V27PF
PN100-1(4)
L
100-PIN TQFP
TOP VIEW(5)
L
R
DD
SS
L
R
L
R
SS
SS
SS
SS
I/O15L
I/O14L
I/O13L
I/O12L
I/O11L
I/O10L
I/O15R
I/O14R
I/O13R
I/O12R
I/O11R
I/O10R
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
3603 drw 02
NOTES:
1. All VDD pins must be connected to power supply.
2. All VSS pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
2
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
Pin Configurations(1,2,3) (con't.)
07/29/04
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
NC
NC
A
8L
A
5L
A
1L
INT
L
V
SS BUSY
R
A
1R
2R
A
5R
NC
NC
NC
B1
B2
B3
B4
C4
B5
C5
B6
B7
B8
B9
B10
B11
B12
B13
INT
R
A
A
6L
A
2L
NC
M/S
A
6R
NC
NC
NC
NC
NC
NC
C1
C2
C3
C6
C7
C8
C9
C10
C11
C12
C13
A10L
A
3L
A
3R
A
7R
A
9R
A
9L
NC
A
7L
NC
NC
A10R
A11R
NC
D1
D2
13L
D3
D4
A
D5
D6
D7
D8
D9
D10
D11
D12
D13
A14L
BUSY
L A0R
A
4R
A
8R
A
12R
A
A
12L
11L
A
4L
A0L
A
13R
A
14R
E1
E2
E3
E4
E10
E11
E12
E13
LB
R
LB
L
NC
NC
NC
NC
NC
NC
F1
F2
F3
F4
F10
F11
CE0R
G11
F12
CE1R
G12
F13
CE1L CE0L
UB
L
SEM
L
SEMR
UB
R
IDT70V27BF
BF144-1(4)
G1
G2
G3
G4
G10
G13
NC
V
DD
VDD
V
DD
NC
V
SS
NC
VSS
144-Pin fpBGA
Top View(5)
H1
H2
H3
H4
H10
H11
H12
H13
NC
NC
OEL
OER
R/W
L
NC
R/W
R
VSS
J1
J2
J3
J4
J10
J11
J12
J13
I/O13R
V
SS
I/O15L I/O14L I/013L
I/O14R I/O15R
K11 K12
V
SS
K1
K2
K3
K4
L4
K5
K6
K7
K8
K9
K10
K13
,
NC
NC
NC
NC
I/O6L I/O3L I/O0R I/O3R I/O6R I/O11R NC
NC I/O12R
I/O12L
L1
L2
L3
L5
I/O5L
L6
I/O2L
L7
L8
L9
I/O5R
L10
L11
L12
L13
V
SS
I/O11L I/O10L
NC
V
DD
NC
NC
NC I/O10R
M1
M2
M3
M4
M5
I/O4L
M6
M7
M8
M9
M10
M11
M12
M13
I/O9L
NC
NC
V
DD
V
SS
I/O0L I/O2R I/O4R I/O7R I/O8R
NC
I/O9R
N1
N2
N3
N4
I/O7L
N5
N6
I/O1L
N7
V
N8
N9
N10
DD
N11
N12
N13
NC
NC
NC
NC
DD
NC
V
NC
NC
I/O8L
I/O1R
3603 drw 02a
NOTES:
1. All VDD pins must be connected to power supply.
2. All VSS pins must be connected to ground supply.
3. Package body is approximately 12mm x 12mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
PinNames
Left Port
Right Port
CE0R, CE1R
R/W
OE
Names
Chip Enable
CE0L, CE1L
R/W
L
R
Read/Write Enable
Output Enable
OEL
R
A
0L - A14L
I/O0L - I/O15L
SEM
UB
LB
INT
BUSY
A
0R - A14R
I/O0R - I/O15R
SEM
UB
LB
INT
BUSY
M/S
Address
Data Input/Output
Semaphore Enable
Upper Byte Select
Lower Byte Select
Interrupt Flag
L
R
L
R
L
R
L
R
Busy Flag
L
R
Master or Slave Select
Power (3.3V)
V
V
DD
ss
Ground (0V)
3603 tbl 01
3
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
Truth Table I – Chip Enable(1,2,3)
CE
1
Mode
CE
CE0
V
IL
V
IH
Port Selected (TTL Active)
L
< 0.2V
>VDD -0.2V
X
Port Selected (CMOS Active)
Port Deselected (TTL Inactive)
Port Deselected (TTL Inactive)
Port Deselected (CMOS Inactive)
Port Deselected (CMOS Inactive)
V
IH
X
VIL
H
>VDD -0.2V
X
X
<0.2V
3603 tbl 02
NOTES:
1. Chip Enable references are shown above with the actual CE0 and CE1 levels, CE is a reference only.
2. Port "A" and "B" references are located where CE is used.
3. "H" = VIH and "L" = VIL
Truth Table II – Non-Contention Read/Write Control
Inputs(1)
Outputs
(2)
R/W
X
I/O8-15
I/O0-7
High-Z
High-Z
High-Z
DATAIN
DATAIN
High-Z
Mode
Deselected: Power-Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
CE
OE
X
X
X
X
X
L
UB
X
H
L
LB
X
H
H
L
SEM
H
H
High-Z
High-Z
X
X
H
L
L
H
DATAIN
High-Z
L
L
H
L
H
L
L
L
H
DATAIN
DATAOUT
High-Z
L
H
H
H
X
L
H
L
H
Read Upper Byte Only
L
L
H
L
H
DATAOUT Read Lower Byte Only
DATAOUT Read Both Bytes
L
X
L
L
H
DATAOUT
High-Z
H
X
X
X
High-Z
Outputs Disabled
3603 tbl 03
NOTES:
1. A0L — A14L ≠ A0R — A14R.
2. Refer to Chip Enable Truth Table.
Truth Table III – Semaphore Read/Write Control
Inputs(1)
Outputs
(2)
R/W
H
I/O8-15
I/O0-7
Mode
CE
OE
L
UB
X
LB
X
SEM
H
X
L
L
DATAOUT
DATAOUT
DATAOUT Read Data in Semaphore Flag
DATAOUT Read Data in Semaphore Flag
H
L
H
H
↑
↑
X
H
X
L
X
X
X
X
X
H
L
X
H
X
L
L
L
L
L
DATAIN
DATAIN
Write I/O
0
0
into Semaphore Flag
into Semaphore Flag
DATAIN
DATAIN
Write I/O
______
______
Not Allowed
Not Allowed
______
______
L
X
X
3603 tbl 04
NOTES:
1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O15). These eight semaphore flags are addressed by A0-A2.
2. Refer to Chip Enable Truth Table.
4
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
AbsoluteMaximumRatings(1)
MaximumOperatingTemperature
andSupplyVoltage(1)
Commercial
Symbol
Rating
Unit
& Industrial
Ambient
Grade
Commercial
Temperature
0OC to +70OC
-40OC to +85OC
GND
0V
VDD
(2)
V
TERM
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
3.3V
3.3V
+
0.3V
Industrial
0V
+
0.3V
Temperature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
T
BIAS
3603 tbl 06
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
Storage
Temperature
TSTG
IOUT
DC Output
Current
mA
3603 tbl 05
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
RecommendedDCOperating
Conditions(1)
Symbol
Parameter
Supply Voltage
Ground
Min.
Typ.
Max.
Unit
V
V
V
DD
SS
3.0
3.3
3.6
2. VTERM must not exceed VDD + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V.
0
0
0
V
DD+0.3V(2)
0.8
V
____
V
IH
IL
Input High Voltage
Input Low Voltage
2.0
V
-0.3(1)
V
____
V
Capacitance(1)
3603 tbl 07
NOTES:
1. VIL > -1.5V for pulse width less than 10ns.
VDD
(TA = +25°C, f = 1.0mhz)TQFP ONLY
2. VTERM must not exceed
+ 0.3V.
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions
IN = 0V
OUT = 0V
Max. Unit
CIN
V
9
pF
pF
(2)
OUT
C
V
10
NOTES:
1. This parameter is determined by device characterization but is not
production tested.
2. COUT also reference CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)
70V27S
70V27L
Symbol
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
DD = 3.6V, VIN = 0V to VDD
Min.
Max.
10
Min.
Max.
Unit
µA
µA
V
___
___
___
___
|ILI|
V
5
5
___
___
|ILO
|
10
CE = VIH, VOUT = 0V to VDD
OL = 4mA
OH = -4mA
V
OL
OH
I
0.4
0.4
___
___
V
Output High Voltage
I
2.4
2.4
V
3603 tbl 09
NOTE:
1. At VDD < 2.0V, input leakages are undefined.
5
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,6) (VDD = 3.3V ± 0.3V)
70V27X15
70V27X20
70V27X25
Com'l Only
Com'l & Ind
Com'l Only
Typ.(2)
Typ.(2)
Typ.(2)
Symbol
Parameter
Test Condition
Version
COM'L
Max.
Max.
255
Max.
Unit
Dynamic Operating
Current
(Both Ports Active)
S
L
170
170
260
225
165
165
145
145
245
210
mA
CE = VIL, Outputs Disabled
SEM = VIH
IDD
220
(3)
f = fMAX
____
____
____
____
____
____
____
____
____
____
IND'L
COM'L
IND'L
S
L
165
230
ISB1
Standby Current
(Both Ports - TTL Level
Inputs)
S
L
44
44
70
60
39
39
60
50
27
27
50
40
mA
mA
CE
L
= CER = VIH
SEM
R
= SEM
L
= VIH
(3)
f = fMAX
____
____
____
____
____
____
____
____
____
____
S
L
39
55
(5)
ISB2
Standby Current
(One Port - TTL Level
Inputs)
COM'L
IND'L
S
L
115
115
160
145
105
105
155
140
90
90
150
135
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(3)
f=fMAX
____
____
____
____
____
____
____
____
____
____
S
L
SEM
R
= SEM
L
= VIH
105
150
I
SB3
Full Standby Current
(Both Ports - All
CMOS Level Inputs)
Both Ports CE
CE
L
and
mA
mA
COM'L
IND'L
S
L
1.0
0.2
6
3
1.0
0.2
6
3
1.0
0.2
6
3
R
> VDD - 0.2V
IN > VDD - 0.2V or
V
____
____
____
____
____
____
____
____
____
____
IN < 0.2V, f = 0(4)
S
L
V
0.2
6
SEM
R
= SEML > VDD - 0.2V
ISB4
Full Standby Current
(One Port - All CMOS
Level Inputs)
CE"A" < 0.2V and
COM'L
IND'L
S
L
115
115
155
140
105
105
150
135
90
90
145
130
CE"B" > VDD - 0.2V(5)
SEM
R
= SEML > VDD - 0.2V
____
____
____
____
____
____
____
____
____
____
S
L
V
IN > VDD - 0.2V or VIN < 0.2V
105
145
Active Port Outputs Disabled
f = fMAX(3)
3603 tbl 10a
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. VDD = 3.3V, TA = +25°C, and are not production tested. IDD DC = 90mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Refer to Chip Enable Truth Table.
6
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,6) (VDD = 3.3V ± 0.3V)
70V27X35
70V27X55
Com'l & Ind
Com'l Only
Typ.(2)
Typ.(2)
Symbol
Parameter
Test Condition
Version
COM'L
Max.
Max.
Unit
Dynamic Operating Current
(Both Ports Active)
S
L
135
135
235
190
125
125
225
180
mA
CE = VIL, Outputs Disabled
IDD
SEM = VIH
f = fMAX
(3)
____
____
____
____
____
____
IND'L
COM'L
IND'L
S
L
135
235
ISB1
Standby Current
(Both Ports - TTL Level
Inputs)
S
L
22
22
45
35
15
15
40
30
mA
mA
CE
L
= CER = VIH
SEM
R
= SEM
L
= VIH
(3)
f = fMAX
____
____
____
____
____
____
S
L
22
45
(5)
ISB2
Standby Current
(One Port - TTL Level
Inputs)
COM'L
IND'L
S
L
85
85
140
125
75
75
140
125
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
(3)
f=fMAX
____
____
____
____
____
____
S
L
SEM
R
= SEM
L
= VIH
85
140
I
SB3
Full Standby Current (Both Both Ports CE
L
and
mA
mA
COM'L
IND'L
S
L
1.0
0.2
6
3
1.0
0.2
6
3
Ports - All CMOS Level
Inputs)
CER > VDD - 0.2V
V
IN > VDD - 0.2V or
IN < 0.2V, f = 0(4)
____
____
____
____
____
____
S
L
V
0.2
6
SEM
R
= SEML > VDD - 0.2V
ISB4
Full Standby Current
(One Port - All CMOS
Level Inputs)
CE"A" < 0.2V and
COM'L
IND'L
S
L
85
85
135
120
75
75
135
120
CE"B" > VDD - 0.2V(5)
SEM
R
= SEML > VDD - 0.2V
____
____
____
____
____
____
S
L
V
IN > VDD - 0.2V or VIN < 0.2V
85
135
Active Port Outputs Disabled
f = fMAX(3)
3603 tbl 10b
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. VDD = 3.3V, TA = +25°C, and are not production tested. IDD DC = 90mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input
levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Refer to Chip Enable Truth Table.
3.3V
3.3V
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns Max.
1.5V
590Ω
590Ω
Input Rise/Fall Times
DATAOUT
BUSY
INT
DATAOUT
Input Timing Reference Levels
Output Reference Levels
Output Load
30pF
5pF*
435Ω
435Ω
1.5V
Figures 1 and 2
3603 tbl 11
3603 drw 04
Figure 2. Output Test Load
(for tLZ, tHZ, tWZ, tOW)
Figure 1. AC Output Test Load
*Including scope and jig
7
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
AC Electrical Characteristics Over the Operating
TemperatureandSupplyVoltageRange(4)
70V27X15
70V27X20
70V27X25
Com'l Only
Com'l & Ind
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
t
RC
AA
ACE
ABE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
15
20
25
ns
ns
ns
____
____
____
t
Address Access Time
15
15
15
20
20
20
25
25
25
____
____
____
____
____
____
____
____
____
Chip Enable Access Time(3)
t
Byte Enable Access Time(3)
Output Enable Access Time
Output Hold from Address Change
t
ns
ns
ns
ns
t
10
12
15
____
____
____
t
3
3
3
____
____
____
Output Low-Z Time(1,2)
t
3
3
3
____
____
____
Output High-Z Time(1,2)
t
12
12
15
ns
ns
ns
ns
____
____
____
Chip Enable to Power Up Time(2,5)
t
0
0
0
____
____
____
Chip Disable to Power Down Time(2,5)
Semaphore Flag Update Pulse (OE or SEM)
Semaphore Address Access Time
t
15
20
25
____
____
____
t
10
10
15
____
____
____
t
15
20
35
ns
3603 tbl 12a
70V27X35
Com'l & Ind
70V27X55
Com'l Only
Symbol
READ CYCLE
Parameter
Min.
Max.
Min. Max.
Unit
____
____
t
RC
AA
ACE
ABE
AOE
OH
LZ
HZ
PU
PD
SOP
SAA
Read Cycle Time
35
55
ns
ns
ns
____
____
t
Address Access Time
35
35
35
55
55
55
____
____
Chip Enable Access Time(3)
t
____
____
____
____
Byte Enable Access Time(3)
Output Enable Access Time
Output Hold from Address Change
t
ns
ns
ns
ns
t
20
30
____
____
t
3
3
____
____
Output Low-Z Time(1,2)
t
3
3
____
____
Output High-Z Time(1,2)
t
20
25
ns
ns
ns
ns
____
____
Chip Enable to Power Up Time(2,5)
Chip Disable to Power Down Time(2,5)
t
0
0
____
____
t
45
50
____
____
t
Semaphore Flag Update Pulse (OE or SEM)
15
15
____
____
t
Semaphore Address Access Time
45
65
ns
3603 tbl 12b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE= VIH and SEM = VIL.
4. 'X' in part numbers indicates power rating (S or L).
5. Refer to Chip Enable Truth Table.
8
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
Waveform of Read Cycles(5)
tRC
ADDR
(4)
t
t
AA
(4)
ACE
CE(6)
OE
(4)
tAOE
(4)
tABE
UB, LB
R/W
DATAOUT
BUSYOUT
t
OH
(1)
tLZ
VALID DATA(4)
(2)
tHZ
(3,4)
3603 drw 05
tBDD
Timing of Power-Up Power-Down
CE(6)
tPU
tPD
ICC
50%
50%
ISB
,
3603 drw 06
NOTES:
1. Timing depends on which signal is asserted last: CE, OE, LB, or UB.
2. Timing depends on which signal is de-asserted first: CE, OE, LB, or UB.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5. SEM = VIH.
6. Refer to Chip Enable Truth Table.
9
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(5)
70V27X15
70V27X20
70V27X25
Com'l Only
Com'l & Ind
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
15
12
12
0
20
15
15
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
t
t
Address Set-up Time(3)
Write Pulse Width
t
____
____
____
____
____
____
____
____
____
t
12
0
15
0
20
0
t
Write Recovery Time
Data Valid to End-of-Write
t
10
15
15
(1,2)
____
____
____
t
10
10
15
Output High-Z Time
____
____
____
(4)
t
0
0
0
ns
ns
ns
ns
Data Hold Time
____
____
____
(1,2)
t
10
10
15
Write Enable to Output in High-Z
(1, 2,4)
____
____
____
t
0
5
5
0
5
5
0
5
5
Output Active from End-of-Write
SEM Flag Write to Read Time
SEM Flag Contention Window
____
____
____
____
____
____
t
t
ns
3603 tbl 13a
70V27X35
Com'l & Ind
70V27X55
Com'l Only
Symbol
WRITE CYCLE
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
SWRD
SPS
Write Cycle Time
35
30
30
0
55
45
45
0
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to End-of-Write(3)
Address Valid to End-of-Write
t
t
Address Set-up Time(3)
Write Pulse Width
t
____
____
____
____
____
____
t
25
0
40
0
t
Write Recovery Time
Data Valid to End-of-Write
t
20
30
(1,2)
____
____
t
20
25
Output High-Z Time
____
____
(4)
t
0
0
ns
ns
ns
ns
Data Hold Time
Write Enable to Output in High-Z (1,2)
____
____
t
20
25
____
____
(1,2,4)
t
0
5
5
0
5
5
Output Active from End-of-Write
____
____
____
____
t
SEM Flag Write to Read Time
SEM Flag Contention Window
t
ns
3603 tbl 13b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time. Refer to Chip Enable
Truth Table.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage
and temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part numbers indicates power rating (S or L).
10
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)
t
WC
ADDRESS
(7)
t
HZ
OE
t
AW
CE or SEM (9,10)
UB or LB(9)
R/W
(3)
(2)
(6)
AS
tWR
t
tWP
(7)
tOW
tWZ
(4)
(4)
DATAOUT
DATAIN
tDW
tDH
3603 drw 07
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing(1,5)
t
WC
ADDRESS
tAW
CE or SEM(9,10)
UB or LB(9)
R/W
(6)
AS
(3)
(2)
t
tEW
t
WR
tDW
tDH
DATAIN
3603 drw 08
NOTES:
1. R/W or CE or UB and LB must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a LOW CE and a LOW R/W for memory array writing cycle.
3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last, CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure
2).
8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP.
9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
10. Refer to Chip Enable Truth Table.
11
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
Timing Waveform of Semaphore Read after Write Timing, Either Side(1)
tSAA
A0-A2
VALID ADDRESS
VALID ADDRESS
tAW
tWR
tACE
tEW
SEM
tOH
tSOP
tDW
OUT
DATA
VALID(2)
I/O
IN
DATA VALID
tAS
tWP
tDH
R/W
tSWRD
tAOE
OE
Write Cycle
Read Cycle
3603 drw 09
NOTES:
1. CE = VIH or UB and LB = VIH for the duration of the above timing (both write and read cycle), refer to Chip Enable Truth Table.
2. "DATAOUT VALID" represents all I/O's (I/O0-I/O15) equal to the semaphore value.
Timing Waveform of Semaphore Write Contention(1,3,4)
A0"A"-A2"A"
MATCH
(2)
SIDE
“A”
R/W"A"
SEM"A"
tSPS
A0"B"-A2"B"
MATCH
(2)
SIDE
“B”
R/W"B"
SEM"B"
3603 drw 10
NOTES:
1. DOR = DOL = VIL, CER = CEL = VIH, or both UB & LB = VIH (refer to Chip Enable Truth Table).
2. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.
4. If tSPS is not satisfied, there is no guarantee which side will be granted the semaphore flag.
12
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltageRange(6)
70V27X15
70V27X20
70V27X25
Com'l Only
Com'l & Ind
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/S=VIH
)
____
____
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
15
15
15
20
20
20
25
25
25
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time(2)
t
t
t
15
20
25
____
____
____
t
5
5
5
____
____
____
BUSY Disable to Valid Data(3)
t
17
35
35
____
____
____
(5)
t
12
15
20
Write Hold After BUSY
BUSY TIMING (M/S=VIL
)
____
____
____
____
____
____
BUSY Input to Write(4)
t
WB
0
0
0
ns
ns
(5)
tWH
12
15
20
Write Hold After BUSY
PORT-TO-PORT DELAY TIMING
____
____
____
____
____
____
Write Pulse to Data Delay(1)
t
WDD
30
25
45
30
55
50
ns
Write Data Valid to Read Data Delay(1)
tDDD
ns
3603 tbl 14a
70V27X35
Com'l & Ind
70V27X55
Com'l Only
Symbol
BUSY TIMING (M/S=VIH
Parameter
Min.
Max.
Min. Max.
Unit
)
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
APS
BDD
WH
35
35
35
45
45
45
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable Low
BUSY Disable Time from Chip Enable High
Arbitration Priority Set-up Time (2)
BUSY Disable to Valid Data(3)
t
t
t
35
45
____
____
t
5
5
____
____
t
40
50
____
____
Write Hold After BUSY(5)
t
25
25
BUSY TIMING (M/S=VIL
)
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
t
WB
0
0
ns
ns
tWH
25
25
PORT-TO-PORT DELAY TIMING
____
____
____
____
Write Pulse to Data Delay(1)
t
WDD
65
60
85
80
ns
Write Data Valid to Read Data Delay(1)
tDDD
ns
3603 tbl 14b
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
13
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
TimingWaveformof WritewithPort-to-PortReadandBUSY(2,5) (M/S =VIH)(4)
tWC
ADDR"A"
R/W"A"
MATCH
tWP
tDW
tDH
DATAIN "A"
VALID
(1)
t
APS
ADDR"B"
MATCH
tBAA
tBDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
(3)
tDDD
3603 drw 11
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).
2. CEL = CER = VIL (refer to Chip Enable Truth Table).
3. OE = VIL for the reading port.
4. If M/S = VIL (SLAVE), then BUSY is an input. Then for this example BUSY "A"= VIH and BUSY "B"= input is shown above.
5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform Write with BUSY (M/S = VIL)
tWP
R/W"A"
(3)
t
WB
BUSY"B"
(1)
t
WH
(2)
R/W"B"
,
,
3603 drw 12
NOTES:
1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB is only for the "Slave" version.
14
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
Waveform of BUSY Arbitration Controlled by CE Timing(M/S = VIH)(1,3)
ADDR"A"
and "B"
ADDRESSES MATCH
CE"A"
(2)
tAPS
CE"B"
tBAC
tBDC
BUSY"B"
3603 drw 13
Waveform of BUSY Arbitration Cycle Controlled by Address Match
Timing(M/S = VIH)(1)
ADDRESS "N"
ADDR"A"
ADDR"B"
BUSY"B"
(2)
APS
t
MATCHING ADDRESS "N"
t
BAA
tBDA
3603 drw 14
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. If tAPS is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.
3. Refer to Chip Enable Truth Table.
AC Electrical Characteristics Over the
Operating TemperatureandSupplyVoltageRange(1)
70V27X15
70V27X20
70V27X25
Com'l Only
Com'l & Ind
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
0
ns
ns
ns
ns
t
0
0
0
____
____
____
t
15
25
20
20
25
35
____
____
____
t
Interrupt Reset Time
3603 tbl 15a
70V27X35
Com'l & Ind
70V27X55
Com'l Only
Symbol
INTERRUPT TIMING
Parameter
Min.
Max.
Min. Max.
Unit
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
ns
ns
ns
t
0
0
____
____
t
30
35
40
45
____
____
t
Interrupt Reset Time
ns
3603 tbl 15b
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
15
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
Waveform of Interrupt Timing(1,5)
tWC
INTERRUPT SET ADDRESS (2)
ADDR"A"
CE"A"
(4)
(3)
tAS
tWR
R/W"A"
INT"B"
(3)
tINS
3603 drw 15
tRC
INTERRUPT CLEAR ADDRESS (2)
ADDR"B"
CE"B"
(3)
t
AS
OE"B"
(3)
t
INR
INT"B"
3603 drw 16
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
5. Refer to Chip Enable Truth Table.
Truth Table IV — Interrupt Flag(1,4)
Left Port
Right Port
R/W
L
A
14L-A0L
7FFF
X
R/W
R
A
14R-A0R
Function
CE
L
OE
L
INT
L
CE
R
OE
R
INTR
L(2)
H(3)
X
L
L
X
X
L
X
X
X
X
X
L
X
X
Set Right INT
Reset Right INT
Set Left INT Flag
Reset Left INT
R Flag
X
X
X
L
7FFF
7FFE
X
R Flag
L(3)
H(2)
X
X
X
X
L
L
X
L
L
7FFE
X
X
X
X
L Flag
3603 tbl 16
NOTES:
1. Assumes BUSYL = BUSYR =VIH.
2. If BUSYL = VIL, then no change.
3. If BUSYR = VIL, then no change.
4. Refer to Chip Enable Truth Table.
16
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
Truth Table V — Address BUSY Arbritration(4)
Inputs
Outputs
A
0L-A14L
(1)
(1)
A
0R-A14R
Function
Normal
CE
L
CE
R
BUSY
L
BUSYR
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
H
Normal
MATCH
H
H
Normal
MATCH
(2)
(2)
Write Inhibit(3)
3603 tbl 17
NOTES:
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the IDT70V27 are
push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address
and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
4. Refer to Chip Enable Truth Table.
Truth Table VI — Example of Semaphore Procurement Sequence(1,2)
Functions
D0 - D15 Left
D0 - D15 Right
Status
No Action
1
0
0
1
1
0
1
1
1
0
1
1
1
1
0
0
1
1
0
1
1
1
Semaphore free
Left Port Writes "0" to Semaphore
Right Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "1" to Semaphore
Right Port Writes "0" to Semaphore
Right Port Writes "1" to Semaphore
Left Port Writes "0" to Semaphore
Left Port Writes "1" to Semaphore
Left port has semaphore token
No change. Right side has no write access to semaphore
Right port obtains semaphore token
No change. Left port has no write access to semaphore
Left port obtains semaphore token
Semaphore free
Right port has semaphore token
Semaphore free
Left port has semaphore token
Semaphore free
3603 tbl 18
NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V27.
2. There are eight semaphore flags written to via I/O0 and read from all the I/O's (I/O0-I/O15). These eight semaphores are addressed by A0 - A2.
FunctionalDescription
7FFE when CEL = OEL = VIL, R/W is a "don't care". Likewise, the right
portinterruptflag(INTR)isassertedwhentheleftportwritestomemory
location 7FFF (HEX) and to clear the interrupt flag (INTR), the
rightportmustreadthememorylocation7FFF.Themessage(16bits)at
7FFEor7FFFisuser-definedsinceitisanaddressableSRAMlocation.
Iftheinterruptfunctionisnotused,addresslocations7FFEand7FFFare
notusedasmailboxes,butaspartoftherandomaccessmemory.Refer
toTruthTableIVfortheinterruptoperation.
TheIDT70V27providestwoportswithseparatecontrol,addressand
I/Opinsthatpermitindependentaccessforreadsorwritestoanylocation
in memory. The IDT70V27 has an automatic power down feature
controlledbyCE0 andCE1. TheCE0 andCE1 controltheon-chippower
downcircuitrythatpermitstherespectiveporttogointoastandbymode
whennotselected(CEHIGH).Whenaportisenabled,accesstotheentire
memoryarrayispermitted.
Interrupts
BusyLogic
Iftheuserchoosestheinterruptfunction,amemorylocation(mailbox
ormessagecenter)isassignedtoeachport. Theleftportinterruptflag
(INTL) is asserted when the right port writes to memory location 7FFE
(HEX),whereawriteisdefinedas CER =R/WR =VIL pertheTruthTable
IV. Theleftportclearstheinterruptthroughaccessofaddresslocation
BusyLogicprovidesahardwareindicationthatbothportsoftheRAM
haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe
twoaccessestoproceedandsignalstheothersidethattheRAMis“Busy”.
TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon
17
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom
thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally
topreventthewritefromproceeding.
Semaphores
The IDT70V27 is a fast Dual-Port 32K x 16 CMOS Static RAM with
anadditional8addresslocationsdedicatedtobinarysemaphoreflags.
TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-Port
RAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefinedby
thesystemdesigner’ssoftware.Asanexample,thesemaphorecanbe
usedbyoneprocessortoinhibittheotherfromaccessingaportionofthe
Dual-Port RAM or any other shared resource.
TheuseofBUSYlogicisnotrequiredordesirableforallapplications.
InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether
and use anyBUSYindication as an interrupt source to flag the event of
anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis
notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave
modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely
asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
TheBUSYoutputsontheIDT70V27RAMinmastermode,arepush-
pulltypeoutputsanddonotrequirepullupresistorstooperate. Ifthese
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
The Dual-Port RAM features a fast access time, and both ports are
completelyindependentofeachother.Thismeansthattheactivityonthe
leftportinnowayslowstheaccesstimeoftherightport. Bothportsare
identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,
orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphorelocation.Semaphoresareprotectedagainstsuchambiguous
situationsandmaybeusedbythesystemprogramtoavoidanyconflicts
inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave
anautomaticpower-downfeaturecontrolledbyCE theDual-PortRAM
enable,andSEM,thesemaphoreenable.The CEandSEMpinscontrol
on-chip power down circuitry that permits the respective port to go into
standbymodewhennotselected. Thisistheconditionwhichisshownin
Truth Table II where CE and SEM are both HIGH.
Width Expansion with BUSY Logic
Master/SlaveArrays
A15
SystemswhichcanbestusetheIDT70V27containmultipleprocessors
or controllers and are typically very high-speed systems which are
softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom
a performance increase offered by the IDT70V27's hardware sema-
phores,whichprovidealockoutmechanismwithoutrequiringcomplex
programming.
Softwarehandshakingbetweenprocessorsoffersthemaximumin
systemflexibilitybypermittingsharedresourcestobeallocatedinvarying
configurations.TheIDT70V27doesnotuseitssemaphoreflagstocontrol
anyresourcesthroughhardware,thusallowingthesystemdesignertotal
flexibilityinsystemarchitecture.
CE
0
CE0
MASTER
Dual Port RAM
SLAVE
Dual Port RAM
BUSY
R
BUSY
R
BUSY
L
BUSYL
CE1
CE1
MASTER
Dual Port RAM
SLAVE
Dual Port RAM
BUSY
R
BUSY
L
BUSY
L
BUSYR
BUSY
R
BUSY
L
,
3603 drw 17
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT70V27 RAMs.
An advantage of using semaphores rather than the more common
methodsofhardwarearbitrationisthatwaitstatesareneverincurredin
either processor. This can prove to be a major advantage in very high-
speedsystems.
WhenexpandinganIDT70V27RAMarrayinwidthwhileusingBUSY
logic, one master part is used to decide which side of the RAM array
willreceiveaBUSYindication,andtooutputthatindication.Anynumber
ofslavestobeaddressedinthesameaddressrangeasthemaster,use
thebusysignalasawriteinhibitsignal.ThusontheIDT70V27RAMthe
BUSYpinisanoutputifthepartisusedasamaster(M/Spin=VIH),and
theBUSY pin is an input if the part is used as a slave (M/S pin = VIL) as
shown in Figure 3.
How the Semaphore Flags Work
Thesemaphorelogicisasetofeightlatcheswhichareindependent
oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken,
fromoneporttotheothertoindicatethatasharedresourceisinuse.The
semaphores provide a hardware assist for a use assignment method
called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore
latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft
processorwantstousethisresource,itrequeststhetokenbysettingthe
latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading
it. If it was successful, it proceeds to assume control over the shared
resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe
rightsideprocessorhassetthelatchfirst, hasthetokenandisusingthe
sharedresource.Theleftprocessorcantheneitherrepeatedlyrequest
thatsemaphore’sstatusorremoveitsrequestforthatsemaphoretoperform
anothertaskandoccasionallyattemptagaintogaincontrolofthetokenvia
thesetandtestsequence.Oncetherightsidehasrelinquishedthetoken,
theleftsideshouldsucceedingainingcontrol.
Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit
decisioncouldresultwithonemasterindicatingBUSYononesideofthe
arrayandanothermasterindicatingBUSYononeothersideofthearray.
Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand
inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.
TheBUSYarbitration,onamaster,isbasedonthechipenableand
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite
pulsecanbeinitiatedwitheithertheR/Wsignalorthebyteenables. Failure
toobservethistimingcanresultinaglitchedinternalwriteinhibitsignaland
corrupteddataintheslave.
18
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
Thesemaphoreflagsareactivelow.Atokenisrequestedbywriting
azerointoasemaphorelatchandisreleasedwhenthesamesidewrites
aonetothatlatch.
usedinstead,systemcontentionproblemscouldhaveoccurredduringthe
gap between the read and write cycles.
Itisimportanttonotethatafailedsemaphorerequestmustbefollowed
byeitherrepeatedreadsorbywritingaoneintothesamelocation.The
TheeightsemaphoreflagsresidewithintheIDT70V27inaseparate
memoryspacefromtheDual-PortRAM.Thisaddressspaceisaccessed
byplacingalowinputontheSEMpin(whichactsasachipselectforthe
semaphore flags) and using the other control pins (Address, OE, and
R/W)astheywouldbeusedinaccessingastandardStaticRAM. Each
oftheflagshasauniqueaddresswhichcanbeaccessedbyeitherside
throughaddresspinsA0–A2.Whenaccessingthesemaphores,noneof
theotheraddresspinshasanyeffect.
L PORT
SEMAPHORE
R PORT
SEMAPHORE
REQUEST FLIP FLOP
REQUEST FLIP FLOP
0
D
0
D
D
D
Q
Q
WRITE
WRITE
Whenwritingtoasemaphore,onlydatapinD0 isused.Ifalowlevel
iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero
onthatsideandaoneontheotherside(seeTableVI).Thatsemaphore
can now only be modified by the side showing the zero. When a one is
writtenintothesamelocationfromthesameside,theflagwillbesettoa
one for both sides (unless a semaphore request from the other side is
pending)andthencanbewrittentobybothsides.Thefactthattheside
whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites
fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor
communications. (Athoroughdiscussionontheuseofthisfeaturefollows
shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe
storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis
freedbythefirstside.
Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso
thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining
azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput
registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)
signalsgoactive.Thisservestodisallowthesemaphorefromchanging
stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.
Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust
cause either signal (SEM or OE) to go inactive or the output will never
change.
AsequenceWRITE/READmustbeusedbythesemaphoreinorder
to guarantee that no system level contention will occur. A processor
requestsaccesstosharedresourcesbyattemptingtowriteazerointoa
semaphorelocation.Ifthesemaphoreisalreadyinuse,thesemaphore
requestlatchwillcontainazero,yetthesemaphoreflagwillappearasa
one, a fact which the processor will verify by the subsequent read (see
TableVI).Asanexample,assumeaprocessorwritesazerototheleftport
atafreesemaphorelocation.Onasubsequentread,theprocessorwill
verifythatithaswrittensuccessfullytothatlocationandwillassumecontrol
overtheresourceinquestion.Meanwhile,ifaprocessorontherightside
attemptstowriteazerotothesamesemaphoreflagitwillfail, aswillbe
verifiedbythefactthataonewillbereadfromthatsemaphoreontheright
sideduringthesubsequentread. HadasequenceofREAD/WRITEbeen
SEMAPHORE
READ
SEMAPHORE
READ
3603 drw 18
Figure 4. IDT70V27 Semaphore Logic
reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram
ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed
into a semaphore flag. Whichever latch is first to present a zero to the
semaphoreflagwillforceitssideofthesemaphoreflaglowandtheother
side high. This condition will continue until a one is written to the same
semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch
havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip
overtotheothersideassoonasaoneiswrittenintothefirstside’srequest
latch.Thesecondside’sflagwillnowstaylowuntilitssemaphorerequest
latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphorerequestlatch.
The critical case of semaphore timing is when both sides request a
single token by attempting to write a zero into it at the same time. The
semaphorelogicisspeciallydesignedtoresolvethisproblem.Ifsimulta-
neousrequestsaremade,thelogicguaranteesthatonlyonesidereceives
thetoken.Ifonesideisearlierthantheotherinmakingtherequest,thefirst
sidetomaketherequestwillreceivethetoken.Ifbothrequestsarriveat
thesametime,theassignmentwillbearbitrarilymadetooneportorthe
other.
One caution that should be noted when using semaphores is that
semaphoresalonedonotguaranteethataccesstoaresourceissecure.
Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused
or misinterpreted, a software error can easily happen.
Initializationofthesemaphoresisnotautomaticandmustbehandled
viatheinitializationprogramatpower-up.Sinceanysemaphorerequest
flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth
sidesshouldhaveaonewrittenintothematinitializationfrombothsides
to assure that they will be free when needed.
19
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
OrderingInformation
XXXXX
A
999
A
A
A
A
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
8
Tube or Tray
Tape and Reel
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(2)
Green
144-pin fpBGA (BF144-1)
100-pin TQFP (PN100-1)
BF
PF
Commercial Only
Commercial & Industrial
Commercial Only
Commercial & Industrial
Commercial Only
15
20
25
35
55
Speed in nanoseconds
S
L
Standard Power
Low Power
512K (32K x 16) 3.3V Dual-Port RAM
70V27
3603drw19
NOTES:
1. Industrial temperature range is available on selected TQFP packages in low power.
For other speeds, packages and powers contact your sales office.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
DatasheetDocumentHistory
12/03/98:
InitiatedDocumentHistory
Convertedtonewformat
Typographicalandcosmeticchanges
AddedfpBGAinformation
Added 15ns and 20ns speed grades
UpdatedDCElectricalCharacteristics
Addedadditionalnotestopinconfigurations
Fixed typo in Table III
Changedpackagebodyheightfrom1.1mmto1.4mm
Changed660mWto660µW
Replaced IDT logo
04/02/99:
08/01/99:
08/30/99:
04/25/00:
Page 5
Page 3
Page 1
Page 2
Madepincorrection
Changed±200mVto0mVinnotes
Datasheet Document History continued on page 21
20
IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM
Commercial and Industrial Temperature Range
DatasheetDocumentHistory(cont'd)
01/12/01:
08/02/04:
Page 1
Page 6
Fixed page numbering; copyright
Increasedstoragetemperatureparameter
ClarifiedTA Parameter
DCElectricalparameters–changedwordingfrom"open"to"disabled"
RemovedPreliminarystatus
RemovedGU-108packageoffering
Addeddaterevisionforpinconfigurations
ChangednamingconventionfromVCC toVDD andfromGNDtoVSS
UpdatedCapacitancetable
Page 7 & 8
Page 1, 4 & 20
Page 2 & 3
Page 2 - 7
Page 5
Page 6
Page 6 - 7
Added I- temp for low power for 20ns speed to DC Electrical Characteristics
Removed I-temp for 25ns & 55ns speeds and removed I-temp for 35ns standard power
fromDCElectricalCharacteristics
Page 7
Page 8, 10, 13
& 15
ChangedInputRise/FallTimesfrom5nsto3ns
RemovedI-tempfor25ns&55nsspeedsfromACElectricalCharacteristicsforRead,
Write,BusyandInterrupt
Page 6 - 8, 10,
13 & 15
RemovedI-tempnotefromalltablefootnotes
01/20/06:
Page 1
Addedgreenavailabilitytofeatures
Page 20
Page 20
Page 20
Page 20
Addedgreenindicatortoorderinginformation
Addeddiesteppingindcatortoorderinginformation
Removed "IDT" from orderable part number
AddedT&RindicatortoandremovedWsteppingfromorderinginformation
Corrected miscellaneoustypo's
09/21/06:
10/23/08:
09/27/12:
Page 2,17 & 19
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
21
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