70V3569S4DRG [IDT]
Dual-Port SRAM, 16KX36, 4.2ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM, GREEN, PLASTIC, QFP-208;
| 型号： | 70V3569S4DRG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 16KX36, 4.2ns, CMOS, PQFP208, 28 X 28 MM, 3.50 MM, GREEN, PLASTIC, QFP-208 时钟 静态存储器 输出元件 内存集成电路 |
| 文件： | 总17页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 3.3V 16K x 36
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
IDT70V3569S
Features:
◆
– Data input, address, byte enable and control registers
– Self-timedwriteallowsfastcycletime
Separate byte controls for multiplexed bus and bus
matching compatibility
LVTTL- compatible, single 3.3V (±150mV) power supply for
core
LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os and control signals on each port
Industrial temperature range (-40°C to +85°C) is
available for selected speeds
Available in a 208-pin Plastic Quad Flatpack (PQFP),
208-ball fine-pitch Ball Grid Array, and 256-pin Ball
GridArray
True Dual-Port memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
◆
◆
◆
◆
◆
◆
– Commercial:4.2/5/6ns(max.)
– Industrial: 5ns (max)
Pipelined output mode
◆
◆
◆
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
– Fast 4.2ns clock to data out
◆
– 1.8ns setup to clock and 0.7ns hold on all control, data, and
address inputs @ 133MHz
◆
Green parts availble, see ordering instructions
FunctionalBlockDiagram
BE3L
BE3R
BE2R
BE1R
BE0R
BE2L
BE1L
BE0L
R/W
L
R/WR
B
B
B
B
B
B B B
W W W W W WW W
0
L
1
L
2
L
3
L
3
R
2
1
0
R
CE0L
R R
CE0R
CE1L
CE1R
OE
L
OER
Dout0-8_L
Dout0-8_R
Dout9-17_R
Dout18-26_R
Dout27-35_R
Dout9-17_L
Dout18-26_L
Dout27-35_L
16K x 36
MEMORY
ARRAY
I/O0L- I/O35L
Din_L
I/O0R - I/O35R
Din_R
,
CLK
L
CLKR
A
13L
A
A
13R
0R
Counter/
Address
Reg.
Counter/
Address
Reg.
A
0L
L
ADDR_L
ADDR_R
CNTRST
ADS
CNTEN
CNTRST
ADS
CNTEN
R
R
L
L
R
4831 tbl 01
OCTOBER 2014
1
DSC 4831/13
©2014 Integrated Device Technology, Inc.
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Description:
TheIDT70V3569isahigh-speed16Kx36bitsynchronousDual-Port inbursts.Anautomaticpowerdownfeature,controlledbyCE0andCE1,
RAM. The memory array utilizes Dual-Port memory cells to allow permitstheon-chipcircuitryofeachporttoenteraverylowstandbypower
simultaneousaccessofanyaddressfrombothports.Registersoncontrol, mode.
data,andaddressinputsprovideminimalsetupandholdtimes.Thetiming
The 70V3569 can support an operating voltage of either 3.3V or
latitudeprovidedbythisapproachallowssystemstobedesignedwithvery 2.5V on one or both ports, controllable by the OPT pins. The power
shortcycletimes.Withaninputdataregister,theIDT70V3569hasbeen supply for the core of the device (VDD) remains at 3.3V.
optimizedforapplicationshavingunidirectionalorbidirectionaldataflow
PinConfiguration(1,2,3,4)
12/12/01
A8
A9
BE1L
A11
A12
A13
A14
A17
A1
A2
A3
A6
A7
A10
A15
A16
A4
A5
A
8L
CLK
L
CNTEN
L
A4L
A
0L
V
SS
IO19L IO18L
VSS
NC
A
12L
VDD
OPT
L
I/O17L
NC
NC
B1
B2
B3
B6
B7
B9
CE0L
B11
B12
B13
B17
B4
B5
B8
B10
B14
B15
B16
I/O20R
V
SS I/O18R
A
13L
A
9L
ADS
L
A
5L
A
1L
I/O15R
V
SS
NC
BE2L
V
SS
V
SS
V
DDQR I/O16L
C1
C5
C6
C2
C3
C4
C7
C8
C9
C10
C11
C12
C13
C16
C14
C15
C17
VDDQL
NC
NC
I/O19R
V
DDQR
VDD
A10L BE3L CE1L
VSS
R/W
L
A6L
A2L
I/O15L
V
DD I/O16R
VSS
D1
D2
D6
D9
D11
CNTRSTL
D3
D5
D7
D8
D10
D12
D13
D14 D15
D16
D17
D4
I/O22L
V
SS
A
11L
V
DD
I/O21L
NC
A
7L BE0L
OE
L
A
3L
VDD I/O17R
VDDQL I/O14L I/O14R
I/O20L
E1
E2
E3
E4
E14
E16
E17
E15
I/O23L I/O22R
VDDQR I/O21R
I/O12L
V
SS I/O13L
I/O13R
F1
F2
F3
F14
F15
F16
F17
F4
VDDQL I/O23R I/O24L
VSS I/O12R I/O11L VDDQR
V
SS
G1
I/O26L
G2
G4
G14
G15
G16
G3
G17
V
SS
I/O24R
I/O9L
VDDQL I/O10L
I/O25L
I/O11R
H3
H4
H1
H2
H16
H17
H14
H15
70V3569BF
BF-208(5)
VDDQR I/O25R
V
DD I/O26R
V
SS I/O10R
V
DD IO9R
J1
J2
J3
J4
J14
J15
J16
J17
VDDQL
V
DD
VSS
V
SS
V
SS
VDD
V
SS
VDDQR
208-Pin fpBGA
Top View(6)
K2
K4
K15
K16
K1
K3
K14
K17
V
SS
V
SS
VDDQL I/O8R
I/O7R
I/O28R
I/O27R
VSS
L3
L4
L15
L16
L17
L1
L2
L14
V
DDQR I/O27L
I/O7L
V
SS
I/O8L
I/O29R I/O28L
I/O6R
M1
M2
M3
M4
M16
M17
DDQR
M14
M15
VDDQL I/O29L I/O30R
V
SS
I/O5R V
V
SS
I/O6L
N16
N17
N4
N15
N1
N2
N3
N14
I/O4R I/O5L
VDDQL
I/O30L
I/O31L
V
SS I/O31R
I/O3R
P1
P2
P3
P4
P5
P7
P8
P9
P10
P11
P12
P14
P15
P16
P17
P6
P13
I/O32R I/O32L
V
DDQR I/O35R NC
A12R
A8R BE1R
V
DD CLK
R
CNTEN
R
I/O2L I/O3L
VSS I/O4L
NC
A4R
R5
R6
R7
R8
R9
R10
R11
R16
R1 R2
R3
R4
R12
R13
R14
R17
R15
NC
A13R
A9R
BE2R CE0R
V
SS ADS
R
I/O1R
V
VDDQL
VSS I/O33L I/O34R NC
A
5R
A1R
V
SS
DDQR
T2
I/O34L
T3
T1
T4
T5
T8
T9
T15
T16
T17
T6
T7
T10
T11
T12
T13
T14
V
DDQL
I/O33R
V
SS
NC
BE3R CE1R
I/O0R
V
SS I/O2R
NC
A
10R
V
SS R/W
R
A
6R
A
2R
V
SS
U1
U2
SS I/O35L
U3
U4
U5
U6
U7
U17
U8
BE0R
U9
U10
U12
U13
U14
U16
U15
V
V
DD
NC
NC
A
11R
A
7R
I/O1L
V
DD
OE
R
A
3R
A0R
V
DD
I/O0L
OPT
R
,
4831 drw 02c
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 15mm x 15mm x 1.4mm, with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
2
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration(1,2,3,4) (con't.)
70V3569BC
BC-256(5)
256-Pin BGA
Top View(6)
12/12/01
A1
A2
A3
A6
A7
A8
A9
A11
A12
A13
A14
A4
A5
A10
A15
A16
NC
NC
NC
A
11L
A
8L
BE2L CE1L
CNTEN
L
A
5L
4L
A
2L
A
0L
NC
NC
OE
L
NC
NC
B1
B2
B3
B6
B7
C7
D7
B9
CE0L
B11
B12
B13
B4
B5
B8
B10
B14
B15
B16
I/O18L NC
NC
A
12L
A
9L
CNTRST
L
A
A
1L
NC
NC
BE3L
R/W
L
V
DD I/O17L NC
C1
C5
C6
C2
C3
C4
C8
C9
C10
C11
C12
C13
C16
C14
C15
I/O18R
A13L
A
10L
I/O19L
VSS
NC
A7L
BE1L BE0L CLK
L
ADS
L
A
6L
A
3L
I/O16L
OPT
L
I/O17R
D1
D2
D6
DDQL
D9
D11
D3
D5
DDQL
D8
D10
D12
D13
D14
D15
D16
D4
I/O20R I/O19R
V
V
DDQL
VDDQR
I/O20L
V
V
DDQR
VDDQR
VDDQL
V
DDQR
VDD I/O15R I/O15L I/O16R
VDD
E5
E6
E7
E8
E9
E10
E11
E12
E13
E1
E2
E3
E4
DDQL
E14
E16
E15
V
DD
V
DD
SS
SS
V
SS
V
SS
V
SS
V
SS
VDD
V
DD
V
DDQR
I/O13L
I/O21R I/O21L I/O22L
V
I/O14R
I/O14L
F7
F5
F6
F9
G9
H9
F10
F1
F2
F3
F11
F13
F14
F15
F16
F8
F12
F4
V
SS
I/O23L I/O22R I/O23R
V
DD
V
V
SS
V
SS
I/O12R I/O13R I/O12L
DDQR
VSS
V
VDDQL
V
SS
SS
SS
V
DD
G1
G2
G3
G5
H5
G4
G6
G8
G14
G15
G16
G7
G10
G12
G13
G11
I/O24R
V
SS
I/O24L
VDDQR
V
V
VSS
I/O25L
I/O10L I/O11L I/O11R
H16
V
SS
V
SS
V
SS
V
DDQL
VSS
H11
H12
H13
H7
H8
H10
H14
H15
H6
H3
I/O26R
H4
H1
H2
VSS
V
SS
I/O10R
V
DDQL
V
SS
V
V
SS
V
SS
SS
I/O9R IO9L
VDDQR
V
SS
VSS
I/O26L I/O25R
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
J11
J12
J13
J14
J15
J16
I/O27L
V
SS
I/O28R I/O27R
VDDQL
V
SS
SS
V
SS
V
SS
SS
VSS
V
DDQR
I/O8R
V
VSS
V
SS
I/O7R I/O8L
K6
K8
K10
K12
K13
K2
K4
K5
K7
K9
K11
K15
K16
K1
K3
K14
V
V
V
SS
SS
V
SS
V
DDQR
I/O6R
I/O29L
VDDQL
V
SS
V
SS
V
SS
VSS
I/O6L I/O7L
I/O29R
I/O28L
L7
L8
L11
L12
L13
L5
L6
L9
L10
L3
L4
L15
L16
L1
L2
L14
V
SS
V
SS
VSS
V
DD
V
DDQL
I/O30R
VDDQR
V
DD
V
SS
V
SS
V
I/O4R I/O5R
I/O30L I/O31R
I/O5L
M5
M6
M7
M8
M9
M10
M11
M12
M13
M1 M2
M3
M4
M16
M14
M15
V
DD
V
DD
VSS
VSS
VSS
V
SS
VDD
V
DD
V
DDQL
I/O32R I/O32L I/O31L
VDDQR
I/O4L
I/O3R I/O3L
N8
N12
N13
N16
N5
N6
DDQR
N7
N9
N10
N11
N4
N15
N1
N2
N3
N14
VDDQL
VDDQL
I/O2R
VDD
V
DD
VDDQR
V
V
DDQL
V
DDQR
VDDQR
VDDQL
I/O1R
I/O33L I/O34R I/O33R
I/O2L
P1
P2
P3
P4
P5
P7
P8
P9
P10
P11
P12
P14
P15
P16
P6
P13
I/O35R I/O34L NC
NC
A13R
A
7R BE1R BE0R CLK
R
ADS
R
A
6R
I/O0L I/O0R I/O1L
A
10R
A3R
R5
R6
R7
R8
R9
R10
R11
R16
R1
R2
R3
R4
R12
R13
R14
R15
,
NC
A
12R
A
9R
BE3R CE0R R/W
R
CNTRST
R
NC
I/O35L NC
NC
NC
A
4R
A1R OPTR
NC
T2
T3
T1
T4
T5
T8
T9
T15
T16
T6
T7
T10
T11
T12
T13
T14
NC
NC
NC
NC
NC
BE2R CE1R
NC
NC
A
11R
A8R
OER
CNTEN
R
A5R
A2R
A0R
4831 drw 02d
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
,
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
3
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration(1,2,3,4) (con't.)
12/12/01
I/O16L
156
1
2
3
4
5
6
I/O19L
I/O19R
I/O20L
I/O20R
I/O16R
155
I/O15L
154
I/O15R
153
VSS
VDDQL
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
VDDQL
VSS
I/O14L
I/O14R
I/O13L
I/O13R
7
8
9
I/O21L
I/O21R
I/O22L
I/O22R
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
VSS
VDDQR
VDDQR
VSS
I/O12L
I/O12R
I/O11L
I/O11R
I/O23L
I/O23R
I/O24L
I/O24R
VSS
VDDQL
VDDQL
VSS
I/O10L
I/O10R
I/O9L
I/O25L
I/O25R
I/O26L
I/O26R
I/O9R
V
V
V
V
V
V
V
V
SS
V
DDQR
SS
DD
DD
70V3569DR
DR-208
DDQR
DD
V
V
V
(5)
DD
SS
V
V
SS
SS
SS
SS
VDDQL
DDQL
208-Pin PQFP
VSS
I/O8R
I/O8L
I/O7R
I/O7L
I/O27R
I/O27L
I/O28R
I/O28L
(6)
Top View
VSS
VDDQR
VDDQR
VSS
I/O6R
I/O6L
I/O5R
I/O5L
I/O29R
I/O29L
I/O30R
I/O30L
VSS
VDDQL
VDDQL
VSS
I/O4R
I/O4L
I/O3R
I/O3L
I/O31R
I/O31L
I/O32R
I/O32L
VSS
VDDQR
VDDQR
VSS
I/O2R
I/O2L
I/O1R
I/O1L
I/O33R
I/O33L
I/O34R
I/O34L
,
4831 drw 02a
NOTES:
1. All VDD pins must be connected to 3.3V power supply.
2. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is
set to VIL (0V).
3. All VSS pins must be connected to ground supply.
4. Package body is approximately 28mm x 28mm x 3.5mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
6.42
4
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
PinNames
Left Port
Right Port
Names
Chip Enables
CE0L
R/W
OE
,
CE1L
CE0R, CE1R
L
R/WR
Read/Write Enable
Output Enable
L
OER
A
0L - A13L
A
0R - A13R
Address
I/O0L - I/O35L
CLK
I/O0R - I/O35R
CLK
Data Input/Output
Clock
L
R
Address Strobe Enable
Counter Enable
ADS
CNTEN
CNTRST
BE0L - BE3L
L
ADS
CNTEN
CNTRST
BE0R - BE3R
R
L
R
Counter Reset
L
R
NOTES:
1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
Byte Enables (9-bit bytes)
Power (I/O Bus) (3.3V or 2.5V)
2. OPTX selects the operating voltage levels for the I/Os and controls on that port.
If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that
port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied
at 2.5V. The OPT pins are independent of one another—both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.
(1)
V
DDQL
VDDQR
(1,2)
OPT
L
OPTR
Option for selection VDDQX
(1)
V
V
DD
SS
Power (3.3V)
Ground (0V)
4831 tbl 01
Truth Table I—Read/Write and Enable Control(1,2,3,4)
Byte 3
I/O27-35
Byte 2
I/O18-26
Byte 1
I/O9-17
Byte 0
I/O0-8
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
↑
CE
X
1
R/W
X
X
X
L
MODE
OE
CE
0
BE
3
BE
2
BE
1
BE0
X
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
X
H
H
H
H
L
X
X
H
H
H
L
X
X
H
H
L
X
X
H
L
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z Deselected–Power Down
High-Z Deselected–Power Down
X
L
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
High-Z
All Bytes Deselected
Write to Byte 0 Only
Write to Byte 1 Only
Write to Byte 2 Only
Write to Byte 3 Only
Write to Lower 2 Bytes Only
Write to Upper 2 bytes Only
Write to All Bytes
X
DIN
X
H
H
H
L
L
DIN
High-Z
High-Z
High-Z
X
H
H
L
L
DIN
High-Z
High-Z
X
H
H
L
L
DIN
High-Z
High-Z
X
H
L
L
High-Z
DIN
DIN
X
H
L
H
L
L
D
IN
IN
D
IN
IN
High-Z
High-Z
X
L
L
L
D
D
DIN
DIN
L
H
H
H
L
H
H
L
H
L
L
H
H
H
H
H
H
H
X
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
DOUT
Read Byte 0 Only
L
H
H
H
L
DOUT
High-Z Read Byte 1 Only
High-Z Read Byte 2 Only
High-Z Read Byte 3 Only
L
H
H
L
DOUT
High-Z
High-Z
L
H
H
L
DOUT
High-Z
High-Z
L
H
L
High-Z
DOUT
DOUT
Read Lower 2 Bytes Only
High-Z Read Upper 2 Bytes Only
Read All Bytes
High-Z Outputs Disabled
L
H
L
H
L
DOUT
D
OUT
OUT
High-Z
L
H
L
L
DOUT
D
DOUT
DOUT
L
L
L
L
High-Z
High-Z
High-Z
4831 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.
6.42
5
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Truth Table II—Address Counter Control(1,2)
Previous
Address
Addr
Used
Address
CLK(6)
I/O(3)
MODE
ADS CNTEN CNTRST
X
X
X
0
An
X
X
L(4)
H
D
I/O(0)
I/O (n) External Address Used
I/O(p) External Address Blocked—Counter disabled (Ap reused)
DI/O(p+1) Counter Enabled—Internal Address generation
Counter Reset to Address 0
↑
↑
↑
↑
An
An
X
L(4)
H
X
D
Ap
Ap
Ap
H
H
D
Ap + 1
H
L(5)
H
4831 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.
3. Outputs are in Pipelined mode: the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other memory control signals including CE0, CE1 and BEn
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.
RecommendedDCOperating
Conditions with VDDQ at 2.5V
RecommendedOperating
TemperatureandSupplyVoltage(1)
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage(3)
Ground
Min. Typ.
3.15 3.3
2.375 2.5
Max.
3.45
2.625
0
Unit
V
Ambient
Grade
Commercial
Temperature
0OC to +70OC
-40OC to +85OC
GND
0V
V
+
+
DD
V
DD
DDQ
SS
3.3V
3.3V
150mV
150mV
V
V
V
0
0
V
Industrial
0V
Input High Voltage(3)
(Address & Control Inputs)
1.7
V
____
4831 tbl 04
V
V
DDQ + 125mV(2)
V
IH
NOTES:
1. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
____
____
V
IH
IL
Input High Voltage - I/O(3)
Input Low Voltage
1.7
DDQ + 125mV(2)
0.7
V
V
-0.3(1)
V
4831 tbl 05a
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDDQ + 125mV.
3. To select operation at 2.5V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VIL (0V), and VDDQX for that port must be
supplied as indicated above.
AbsoluteMaximumRatings(1)
Symbol
Rating
Commercial
& Industrial
Unit
(2)
V
TE RM
Terminal Vol tage
with Respect to
GND
-0.5 to +4.6
V
RecommendedDCOperating
Conditions with VDDQ at 3.3V
Temperature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
T
BIAS
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage(3)
Ground
Min. Typ.
3.15 3.3
3.15 3.3
Max.
Unit
V
Storage
Temperature
TSTG
V
DD
DDQ
SS
3.45
V
3.45
V
IOUT
DC Output Current
mA
V
0
0
0
V
4831 tbl 06
NOTES:
Input High Voltage
2.0
V
V
DDQ + 150mV(2)
V
____
V
IH
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time or
4ns maximum, and is limited to < 20mA for the period of VTERM > VDD + 150mV.
(Address & Control Inputs)(3)
V
IH
IL
Input High Voltage - I/O(3)
Input Low Voltage
2.0
DDQ + 150mV(2)
0.8
V
V
____
____
V
-0.3(1)
4831 tbl 05b
NOTES:
1. VIL > -1.5V for pulse width less than 10 ns.
2. VTERM must not exceed VDDQ + 150mV.
3. To select operation at 3.3V levels on the I/Os and controls of a given port, the
OPT pin for that port must be set to VIH (3.3V), and VDDQX for that port must be
supplied as indicated above.
6.42
6
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Capacitance(1)
(TA = +25°C, F = 1.0MHZ) PQFP ONLY
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
8
pF
(3 )
OUT
C
V
10.5
pF
4831 tbl 07
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV)
70V3569S
Symbol
Parameter
Input Leakage Current(1)
Output Leakage Current
Test Conditions
VDDQ = Max., VIN = 0V to VDDQ
Min.
Max.
10
Unit
µA
µA
V
___
___
___
|ILI|
|ILO
|
10
CE
OL = +4mA, VDDQ = Min.
OH = -4mA, VDDQ = Min.
OL = +2mA, VDDQ = Min.
OH = -2mA, VDDQ = Min.
0 = VIH or CE1 = VIL, VOUT = 0V to VDDQ
V
OL (3.3V) Output Low Voltage(2)
OH (3.3V) Output High Voltage(2)
OL (2.5V) Output Low Voltage(2)
OH (2.5V) Output High Voltage(2)
I
0.4
___
V
I
2.4
V
___
V
I
0.4
V
___
V
I
2.0
V
4831 tbl 08
NOTE:
1. At VDD < - 2.0V input leakages are undefined.
2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.4 for details.
6.42
7
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(3) (VDD = 3.3V ± 150mV)
70V3569S4
Com'l Only
70V3569S5
Com'l
& Ind
70V3569S6
Com'l Only
Symbol
Parameter
Test Condition
= VIL
Outputs Disabled,
f = fMAX
Version
COM'L
Typ.(4)
375
Max.
460
Typ.(4)
Max.
360
415
145
175
260
300
Typ.(4)
245
245
95
Max. Unit
IDD
Dynamic Operating
Current (Both
Ports Active)
mA
mA
mA
mA
CE
L
and CE
R
,
S
S
S
S
S
S
285
285
105
105
190
190
310
360
125
150
225
260
____
____
(1)
IND
ISB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
f = fMAX
L = CER = VIH
(1)
COM'L
IND
145
190
____
____
95
(5)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
COM'L
IND
265
325
175
175
____
____
(1)
f=fMAX
ISB3
Full Standby Current Both Ports CE
L and
> VDDQ - 0.2V,
VIN > VDDQ - 0.2V or VIN < 0.2V,
COM'L
IND
S
S
6
15
6
6
15
30
6
6
15
30
(Both Ports - CMOS CE
R
Level Inputs)
____
____
f = 0(2)
ISB4
Full Standby Current
(One Port - CMOS
Level Inputs)
mA
CE"A" < 0.2V and
COM'L
IND
S
S
265
325
180
180
260
300
170
170
225
260
CE"B" > VDDQ - 0.2V(5)
V
IN > VDDQ - 0.2V or VIN < 0.2V,
Active Port, Outputs Disabled,
____
____
(1)
f = fMAX
4831 tbl 09
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQ - 0.2V
CEX > VDDQ - 0.2V means CE0X > VDDQ - 0.2V or CE1X - 0.2V
"X" represents "L" for left port or "R" for right port.
6.42
8
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
2.5V
AC Test Conditions
Input Pulse Levels (Address & Controls)
Input Pulse Levels (I/Os)
Input Rise/Fall Times
GND to 3.0V/GND to 2.35V
GND to 3.0V/GND to 2.35V
3ns
833Ω
DATAOUT
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V/1.25V
1.5V/1.25V
5pF*
770Ω
Figures 1, 2, and 3
4831 tbl 10
,
3.3V
590Ω
5pF*
50Ω
50Ω
,
DATAOUT
1.5V/1.25
DATAOUT
10pF
(Tester)
4831 drw 03
435Ω
Figure 1. AC Output Test load.
,
4831 drw 04
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
10.5pF is the I/O capacitance of this
device, and 10pF is the AC Test Load
Capacitance.
7
6
5
4
3
ΔtCD
(Typical, ns)
2
1
•
•
•
•
,
20.5
50
80 100
200
30
-1
Capacitance (pF)
4831 drw 05
Figure 3. Typical Output Derating (Lumped Capacitive Load).
·
6.42
9
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating
Temperature Range (Read and Write Cycle Timing)(1,2)
(VDD = 3.3V ± 150mV, TA = 0°C to +70°C)
70V3569S4
Com'l Only
70V3569S5
Com'l
70V3569S6
Com'l Only
& Ind
Symbol
Parameter
Clock Cycle Time (Pipelined)
Clock High Time (Pipelined)
Clock Low Time (Pipelined)
Clock Rise Time
Min.
7.5
3
Max.
Min.
10
Max.
Min.
12
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
____
____
____
____
____
____
t
CYC2
CH2
CL2
t
4
5
t
3
4
5
____
____
____
tR
3
3
3
____
____
____
tF
Clock Fall Time
3
3
3
____
____
____
t
SA
HA
SC
HC
SB
HB
SW
HW
SD
HD
SAD
HA D
SCN
HCN
SRST
Address Setup Time
1.8
0.7
1.8
0.7
1.8
0.7
1.8
0.7
1.8
0.7
1.8
0.7
1.8
0.7
1.8
2.0
0.7
2.0
0.7
2.0
0.7
2.0
0.7
2.0
0.7
2.0
0.7
2.0
0.7
2.0
2.0
1.0
2.0
1.0
2.0
1.0
2.0
1.0
2.0
1.0
2.0
1.0
2.0
1.0
2.0
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
Address Hold Time
t
Chip Enable Setup Time
Chip Enable Hold Time
Byte Enable Setup Time
Byte Enable Hold Time
R/W Setup Time
t
t
t
t
t
R/W Hold Time
t
Input Data Setup Time
Input Data Hold Time
t
t
ADS Setup Time
t
ADS Hold Time
t
CNTEN Setup Time
t
CNTEN Hold Time
t
CNTRST Setup Time
t
HRST
0.7
0.7
1.0
CNTRST Hold Time
(1)
____
____
____
tOE
Output Enable to Data Valid
Output Enable to Output Low-Z
Output Enable to Output High-Z
Clock to Data Valid (Pipelined)
Data Output Hold After Clock High
Clock High to Output High-Z
Clock High to Output Low-Z
4
5
6
____
____
____
t
OL Z
OHZ
CD2
DC
CKHZ
CKLZ
0
0
0
t
1
4
1
4.5
1
5
____
____
____
t
4.2
5
6
____
____
____
t
1
1
1
1
1
1
1
1.5
1
t
3
4.5
6
____
____
____
t
Port-to-Port Delay
Clock-to-Clock Offset
____
____
____
tCO
6
8
10
ns
4831 tbl 11
NOTES:
1. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE).
2. These values are valid for either level of VDDQ (3.3V/2.5V). See page 4 for details on selecting the desired I/O voltage levels for each port.
6.42
10
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Pipelined Operation(2)
t
CYC2
tCH2
tCL2
CLK
CE
0
t
SC
tHC
t
SC
SB
t
HC
HB
(3)
CE1
t
SB
tHB
t
t
(5)
BE(0-3)
R/W
tHW
tSW
tSA
tHA
ADDRESS(4)
DATAOUT
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
t
DC
tCD2
Qn + 1
Qn + 2 (5)
(1)
tCKLZ
t
OHZ
tOLZ
OE (1)
tOE
NOTES:
4831 drw 06
1. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
2. ADS = VIL, CNTEN and CNTRST = VIH.
3. The output is disabled (High-Impedance state) by CE0 = VIH, CE1 = VIL, BEn = VIH following the next rising edge of the clock. Refer to
Truth Table 1.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
5. If BEn was HIGH, then the appropriate Byte of DATAOUT for Qn + 2 would be disabled (High-Impedance state).
Timing Waveform of a Multi-Device Pipelined Read(1,2)
t
CYC2
t
CH2
tCL2
CLK
ADDRESS(B1)
CE0(B1)
t
SA
tHA
A6
A5
A4
A3
A
2
A
0
A1
tSC
tHC
t
SC
tHC
tCD2
tCD2
tCKHZ
tCD2
Q
0
Q3
Q
1
DATAOUT(B1)
ADDRESS(B2)
tDC
tCKLZ
tDC
tCKHZ
tSA
tHA
A6
A5
A4
A3
A2
A
0
A1
tSC
tHC
CE0(B2)
tSC
tHC
tCD2
tCKHZ
tCD2
DATAOUT(B2)
Q4
Q2
tCKLZ
t
CKLZ
NOTES:
4831 drw 07
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3569 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. BEn, OE, and ADS = VIL; CE1(B1), CE1(B2), R/W, CNTEN, and CNTRST = VIH.
6.42
11
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Left Port Write to Pipelined
Right Port Read(1,2)
CLK
L
t
SW
tHW
R/W
L
t
SA
MATCH
SD HD
VALID
t
HA
NO
MATCH
ADDRESS
L
t
t
DATAINL
(3)
CO
t
CLKR
tCD2
R/WR
t
SW
SA
t
HW
t
tHA
NO
MATCH
ADDRESS
R
MATCH
VALID
DATAOUTR
t
DC
4831 drw 08
NOTES:
1. CE0, BEn, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
2. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
3. If tCO < minimum specified, then data from right port read is not valid until following right port clock cycle (ie, time from write to valid read on opposite port will
be tCO + 2 tCYC2 + tCD2). If tCO > minimum, then data from right port read is available on first right port clock cycle (ie, time from write to valid read on opposite
port will be tCO + tCYC + tCD2).
Timing Waveform of Pipelined Read-to-Write-to-Read
(OE = VIL)(2)
tCYC2
tCH2
tCL2
CLK
CE0
tSC
tHC
CE1
tSB
tHB
BEn
tSW tHW
R/W
tSW tHW
ADDRESS(3)
An + 3
An + 4
An
An +1
An + 2
An + 2
t
SA
tHA
t
SD
tHD
DATAIN
Dn + 2
tCD2
tCD2
(1)
tCKHZ
tCKLZ
Qn + 3
Qn
DATAOUT
READ
NOP(4)
WRITE
READ
4831 drw 09
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH. "NOP" is "No Operation".
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers
are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.42
12
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(2)
t
CYC2
tCH2
tCL2
CLK
CE
0
tSC
tHC
CE1
tSB
tHB
BE
n
tSW tHW
R/W
tSW tHW
(3)
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
ADDRESS
t
SA
tHA
t
SD
tHD
DATAIN
Dn + 2
tCD2
tCD2
t
CKLZ
(1)
Qn
Qn + 4
DATAOUT
(4)
tOHZ
OE
READ
WRITE
READ
4831 drw 10
NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2. CE0, BEn, and ADS = VIL; CE1, CNTEN, and CNTRST = VIH.
3. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference use
only.
4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.
Timing Waveform of Pipelined Read with Address Counter Advance(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
t
SAD tHAD
ADS
t
SAD tHAD
CNTEN
tSCN tHCN
tCD2
Qn + 2(2)
Qx - 1(2)
Qx
Qn + 3
Qn + 1
Qn
DATAOUT
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
4831 drw 11
NOTES:
1. CE0, OE, BEn = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data output remains
constantforsubsequentclocks.
6.42
13
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An(7)
An + 4
An + 2
An + 1
An + 3
t
SAD tHAD
ADS
tSCN tHCN
CNTEN
t
SD tHD
Dn + 4
Dn + 1
Dn + 3
Dn
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
4831 drw 12
Timing Waveform of Counter Reset(2)
t
CYC2
tCH2
tCL2
CLK
tSA tHA
(4)
An + 2
An
An + 1
ADDRESS
INTERNAL(3)
ADDRESS
Ax
0
1
An
An + 1
tSW tHW
R/
W
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tSRST
tHRST
CNTRST
tSD
tHD
D0
DATAIN
(5)
Qn
Q
1
Q0
DATAOUT
COUNTER(6)
RESET
WRITE
ADDRESS 0
READ
READ
READ
READ
ADDRESS 1
ADDRESS 0
ADDRESS n ADDRESS n+1
NOTES:
1. CE0, BEn, and R/W = VIL; CE1 and CNTRST = VIH.
CE0, BEn = VIL; CE1 = VIH.
4831 drw 13
2.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for reference
use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle: ADDR 0 will be accessed. Extra cycles
are shown here simply for clarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance. The ‘An +1’Address is
written to during this cycle.
6.42
14
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
FunctionalDescription
Depth and Width Expansion
TheIDT70V3569providesatruesynchronousDual-PortStaticRAM
interface. Registered inputs provide minimal set-up and hold times on
address,data,andallcriticalcontrolinputs.Allinternalregistersareclocked
ontherisingedgeoftheclock signal,however,theself-timedinternalwrite
pulseisindependentoftheLOWtoHIGHtransitionoftheclocksignal.
An asynchronous output enable is provided to ease asyn-
chronousbusinterfacing.Counterenableinputsarealsoprovidedtostall
the operation of the address counters for fast interleaved
memoryapplications.
The IDT70V3569 features dual chip enables (refer to Truth
Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
TheIDT70V3569canalsobeusedinapplicationsrequiringexpanded
width,asindicatedinFigure4.Throughcombiningthecontrolsignals,the
devices can be grouped as necessary to accommodate applications
needing 72-bits or wider.
A HIGHonCE0oraLOWonCE1foroneclockcyclewillpowerdown
the internal circuitry to reduce static power consumption. Multiple chip
enablesalloweasierbankingofmultipleIDT70V3569sfordepthexpan-
sion configurations. Two cycles are required with CE0 LOW and CE1
HIGH tore-activatetheoutputs.
A15
IDT70V3569
IDT70V3569
CE0
CE0
CE1
CE1
VDD
VDD
Control Inputs
Control Inputs
IDT70V3569
IDT70V3569
CE1
CE1
CE0
CE0
BE,
R/W,
Control Inputs
Control Inputs
OE,
CLK,
ADS,
CNTRST,
CNTEN
4831 drw 14
Figure 4. Depth and Width Expansion with IDT70V3569
6.42
15
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
OrderingInformation
NOTES:
1. Contact your local sales office for Industrial temp range in other speeds, packages and powers.
2. Greenpartsavailable. Forspecificspeeds, packagesandpowerscontactyourlocalsalesoffice.
DatasheetDocumentHistory
1/8/99:
3/12/99:
4/28/99:
6/8/99:
InitialPublicRelease
AddedfpBGApackage
Fixed typo on page 10
Changeddrawingformat
Page 2 Changedpackagebodydimensions
Page 3 Fixed typo
6/15/99:
8/4/99:
Page 5 Deleted note 6 for Table II
Page 2 Fixed typographical error
Page 6 Improved power number
Upgraded speed to 133MHz, added 2.5V I/O capability
Page 4 Corrected I/O numbers in Truth Table I
Replaced IDT logo
10/14/99:
10/19/99:
11/12/99:
4/10/00:
AddednewBGApackages,addedfull2.5Vinterfacecapability
Continued on page 17
6.42
16
IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
DatasheetDocumentHistory(cont'd)
01/12/01:
Page 6 Updated Truth Table II
Increatedstoragetemperatureparameter
ClarifiedTA Parameter
Page 8 DCElectricalparameters–changedwordingfrom"open"to"disabled"
Removednote7onDCElectricalCharacteristicstable
RemovedPreliminarystatus
04/10/01:
12/12/01:
AddedIndustrialTemperatureRangesandremovedrelatednotes
Page 2, 3 & 4 Added date revision to pin configurations
Page 6 Removedindustrialtempfootnotefromtable04
Page8&10 Removedindustrialtempfor6nsfromDC&ACElectricalCharacteristics
Page 16 Removedindustrialtempfrom6nsinorderinginformation
Addedindustrialtempfootnote
Page 1 & 17 Replaced TM logo with ® logo
3/23/05:
Page 1 Added green availability to features
Page16Addedgreenindicatortoorderinginformation
Page 1 & 17 Replaced old IDT TM with new IDT TM logo
Page 5 Changed footnote 2 for Truth Table I from ADS, CNTEN, CNTRST = VIH to ADS, CNTEN, CNTRST = X
Page 8 Corrected a typo in the DC Chars table
Page 16 Removed "IDT" from orderable part number
Page 16 Added Tape and Reel to the Ordering Information
02/08/06:
07/25/08:
10/23/08:
10/08/14:
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
17
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