70V657S15BCGI8_技术文档

IDT70V659/58/57S

HIGH-SPEED 3.3V

128/64/32K x 36

ASYNCHRONOUS DUAL-PORT

STATIC RAM

LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018

Features

◆

True Dual-Port memory cells which allow simultaneous

Full on-chip hardware support of semaphore signaling

between ports

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

Supports JTAG features compliant to IEEE 1149.1

LVTTL-compatible, single 3.3V (±150mV) power supply for

core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

Available in a 208-pin Plastic Quad Flatpack, 208-ball fine

pitch Ball Grid Array, and 256-ball Ball Grid Array

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

access of the same memory location

High-speed access

◆

– Commercial:10/12/15ns(max.)

– Industrial:12/15ns(max.)

Dual chip enables allow for depth expansion without

external logic

IDT70V659/58/57 easily expands data bus width to 72 bits

or more using the Master/Slave select when cascading

more than one device

M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

Busy and Interrupt Flags

◆

On-chip port arbitration logic

Green parts available, see ordering information

Functional Block Diagram

BE3L

BE3R

BE2R

BE2L

BE1L

BE0L

BE1R

BE0R

R/WL

R/

WR

B B B B B B B B

E E E E E E E E

0

L

1

L

2

L

3

L

3

2 1

0

CE0L

CE1L

CE0R

CE1R

R R R R

OEL

OER

Dout0-8_L

Dout0-8_R

Dout9-17_L

Dout9-17_R

Dout18-26_R

Dout27-35_R

Dout18-26_L

Dout27-35_L

128/64/32K x 36

MEMORY

ARRAY

I/O0L- I/O35L

Di n_L

Di n_R

I/O0R -I/O35R

(1)

16 L

A

16R

Address

Decoder

A

Address

Decoder

ADDR_L

ADDR_R

A0R

A0L

CE0L

CE1L

ARBITRATION

CE0R

CE1R

INTERRUPT

SEMAPHORE

LOGIC

OE

L

OE

R

R/W

L

R/W

R

(2,3)

L

(2,3)

R

BUSY

SEM

INT

BUSY

SEM

M/S

L

R

(3)

INT

R

TMS

TCK

TDI

JTAG

TDO

TRST

NOTES:

4869 drw 01

1. A16 is a NC for IDT70V658. Also, Addresses A16 and A15 are NC's for IDT70V657.

2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).

3. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

JUNE 2018

1

DSC-4869/8

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Description

The IDT70V659/58/57 is a high-speed 128/64/32K x 36 Asynchro- address,andI/Opinsthatpermitindependent,asynchronousaccessfor

nousDual-PortStaticRAM.TheIDT70V659/58/57isdesignedtobeused reads or writes to any location in memory. An automatic power down

asastand-alone4/2/1MbitDual-PortRAMorasacombinationMASTER/ feature controlled by the chip enables (either CE⁰or CE1) permit the

SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT on-chip circuitry of each port to enter a very low standby power mode.

MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory

The 70V659/58/57 can support an operating voltage of either 3.3V

systemapplicationsresultsinfull-speed,error-freeoperationwithoutthe or2.5Vononeorbothports,controlledbytheOPTpins.Thepowersupply

needforadditionaldiscretelogic.

for the core of the device (VDD) remains at 3.3V.

This device provides two independent ports with separate control,

2

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

PinConfigurations^{(3,4,5,6,7,8)}

03/19/04

I/O16L

156

1

2

3

4

5

6

I/O19L

I/O19R

I/O20L

I/O20R

I/O16R

155

I/O15L

154

I/O15R

153

V

SS

VDDQL

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

DDQL

VSS

I/O14L

I/O14R

I/O13L

I/O13R

7

8

9

I/O21L

I/O21R

I/O22L

I/O22R

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

V

SS

V

DDQR

VSS

I/O12L

I/O12R

I/O11L

I/O11R

I/O23L

I/O23R

I/O24L

I/O24R

V

SS

VDDQL

DDQL

VSS

I/O10L

I/O10R

I/O9L

I/O25L

I/O25R

I/O26L

I/O26R

70V659/58/57DR

DR-208⁽⁷⁾

I/O9R

V

SS

V

DDQR

DD

VSS

V

DD

SS

V

SS

208-Pin PQFP

Top View⁽⁸⁾

SS

VDDQL

DDQL

VSS

I/O8R

I/O8L

I/O7R

I/O7L

I/O27R

I/O27L

I/O28R

I/O28L

V

SS

V

DDQR

VSS

I/O6R

I/O6L

I/O5R

I/O5L

I/O29R

I/O29L

I/O30R

I/O30L

V

SS

VDDQL

DDQL

VSS

I/O4R

I/O4L

I/O3R

I/O3L

I/O31R

I/O31L

I/O32R

I/O32L

V

SS

V

DDQR

VSS

I/O2R

I/O2L

I/O1R

I/O1L

I/O33R

I/O33L

I/O34R

I/O34L

4869 drw 02a

NOTES:

1. Pin is a NC for IDT70V658 and IDT70V657.

2. Pin is a NC for IDT70V657.

3. All VDD pins must be connected to 3.3V power supply.

4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (3.3V) and 2.5V if OPT pin for that port is

set to V^SS(0V).

5. All VSS pins must be connected to ground.

6. Package body is approximately 28mm x 28mm x 3.5mm.

7. This package code is used to reference the package diagram.

8. This text does not indicate orientation of the actual part-marking.

3

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Pin Configurations^{(3,4,5,6,7,8)}(con't.)

70V659/58/57BC

BC-256⁽⁷⁾

256-Pin BGA

Top View⁽⁸⁾

03/19/04

A1

A2

A3

A6

A7

A8

A9

A11

A12

A13

A14

A4

A5

A10

A15

A16

NC

TDI

NC

A

11L

A

8L

9L

7L

BE2L CE1L

INT

L

A

5L

A

2L

A

0L

NC

A

14L

OE

L

NC

B1

B2

B3

B6

B7

B9

CE0L

B11

B12

B13

B4

B5

B8

B10

B14

B15

B16

(2)

I/O18L NC TDO

A

12L

10L

A

NC

A

4L

A

1L

A15L

NC

BE3L

R/W

L

NC I/O17L NC

C1

C5

C6

C2

C3

C4

C7

C8

C9

C10

C11

C12

C13

C16

C14

C15

(1)

I/O18R

A

13L

A

I/O19L

V

SS

A16L

A

BE1L BE0L SEM

L

BUSY

L

A

6L

A

3L

I/O16L

OPT

L

I/O17R

D1

D2

D6

DDQL

D9

D11

D3

D5

D7

DDQR

D8

D10

D12

D13

D14

D15

D16

D4

I/O20R I/O19R

V

DDQL

VDDQR

DDQL

I/O20L

VDDQL

V

DDQR

V

DDQR

V

DD I/O15R I/O15L I/O16R

V

DD

E5

E6

E7

E8

E9

E10

E11

E12

E13

E1

E2

E3

E4

DDQL

E14

E16

E15

V

DD

V

DD

SS

V

SS

V

SS

V

SS

V

SS

V

DD

V

DD

VDDQR

I/O21R I/O21L I/O22L

V

I/O13L

I/O14R

I/O14L

F7

F1

F2

F3

F5

F6

F9

F10

F14

F15

F16

F11

F13

F8

F12

F4

V

I/O23L I/O22R I/O23R

V

DD

V

VSS

V

SS

VDDQR I/O12R I/O13R I/O12L

VDDQL

V

SS

V

DD

G1

G5

H5

G2

G4

G6

G8

G9

G3

G14

G15

G16

G7

G10

G12

G13

G11

I/O24R

V

SS

I/O24L

VDDQR

V

I/O25L

V

SS

V

SS

V

SS

V

DDQL I/O10L I/O11L I/O11R

V

SS

H11

H12

H16

H13

H7

H8

H9

H10

H14

H15

H3

H4

H6

H1

H2

VSS

V

SS

I/O10R

V

DDQL

I/O9R IO9L

V

SS

V

VSS

I/O26R

VDDQR

V

VSS

I/O26L I/O25R

J1

J5

J2

J3

J4

J6

J7

J8

J9

J13

J10

J11

J12

J14

J15

J16

I/O27L

I/O28R I/O27R

VDDQL

V

SS

V

SS

V

SS

V

SS

VDDQR

VSS

V

SS

VSS

I/O8R

I/O7R I/O8L

K6

K8

K10

K12

K13

K2

K4

K5

L5

K7

L7

K9

K11

K15

K16

K1

K3

K14

V

SS

V

SS

V

SS

V

SS

V

DDQR

I/O6R

V

SS

V

SS

V

SS

V

I/O29L

V

DDQL

I/O6L I/O7L

I/O29R

I/O28L

L8

L11

L12

L13

L6

L9

L10

L3

L4

L15

L16

L1

L2

L14

V

SS

V

SS

V

DD

V

DDQL

I/O5L

I/O30R

VDDQR

V

DD

V

SS

V

SS

V

I/O4R I/O5R

I/O30L I/O31R

M5

M6

M7

M8

M9

M10

M11

M12

M13

M1 M2

M3

M4

M16

M14

M15

V

DD

V

DD

V

SS

V

SS

VSS

V

DD

V

DD

V

DDQL

I/O3R I/O3L

I/O32R I/O32L I/O31L

VDDQR

I/O4L

N8

DDQL

N12

N16

N13

N4

N5

N6

DDQR

N7

N9

N10

N11

N15

N1

N2

N3

N14

V

DDQL

I/O2R

I/O1R

V

DD

V

DD

VDDQR

V

DDQL

V

DDQR

V

DDQR

V

DDQL

I/O33L I/O34R I/O33R

I/O2L

P1

P2

P3

P4

16R

P5

P7

P8

P9

P10

P11

P12

P14

P15

P16

P6

P13

(1)

I/O35R I/O34L TMS

A

13R

A

7R BE1R BE0R SEM

R

BUSY

R

A

6R

I/O0L I/O0R I/O1L

A

10R

A

3R

R5

R6

R7

R8

R9

R10

R11

R16

R1

R2

R3

R4

R12

R13

R14

R15

,

(2)

A

15R

A

12R

A

9R

BE3R CE0R R/W

R

M/S

NC

I/O35L NC TRST NC

A4R

A

1R OPT

R

NC

T2

T3

T1

T4

T5

T8

T9

T15

T16

T6

T7

T10

T11

T12

T13

T14

TCK

NC

A14R

BE2R CE1R

NC

A

11R

A

8R

OE

R

INT

R

A

5R

A

2R

A0R

4869 drw 02c

,

NOTES:

1. Pin is a NC for IDT70V658 and IDT70V657.

2. Pin is a NC for IDT70V657.

3. All VDD pins must be connected to 3.3V power supply.

4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (3.3V), and 2.5V if OPT pin for that port is

set to V^SS(0V).

5. All VSS pins must be connected to ground supply.

6. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

7. This package code is used to reference the package diagram.

8. This text does not indicate orientation of the actual part-marking.

4

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Pin Configuration^{(3,4,5,6,7,8)}(con't.)

03/19/04

1

2

3

4

5

6

7

8

9

11 12 13 14

10

16 17

15

(1)

I/O19L

A

12L

V

DD

SS

A

B

C

D

E

F

I/O18L

V

SS

A

8L

A

0L

I/O17L

VSS

A4

L

OPTL

TDO

NC

A

16L

BE1L

SEM

L

INTL

A

B

C

D

E

F

I/O20R

V

SS

A

9L

I/O18R

I/O15R

A5

L

I/O16L

TDI

NC

A

13L

A

1L

VDDQR

V

SS

DD

CE0L

BUSY

L

BE2L

BE3L

A

10L

VSS

I/O19R

V

DD

A

14L

CE1L

A6L

A

2L

I/O16R I/O15L

V

DDQL

VDDQR

R/WL

(2)

I/O22L

VSS

I/O17R

I/O12L

I/O21L

A

11L

7L

V

DD

V

DDQL

I/O14L I/O14R

I/O13L

I/O20L

A

15L

NC

VDD

BE0L

A3L

OE

L

I/O23L I/O22R

VDDQR I/O21R

I/O13R

I/O12R

V

SS

V

DDQL

I/O23R

VSS

VDDQR

I/O24L

I/O25L

V

SS

I/O11L

I/O10L

I/O26L

V

SS

I/O9L

VDDQL

I/O24R

I/O25R

I/O11R

I/O10R

G

H

J

G

H

J

70V659/58/57BF

BF-208⁽⁷⁾

V

DD

I/O26R

V

DDQR

V

DD

I/O9R

V

SS

V

DD

VDDQL

V

SS

V

SS

VDDQR

V

DD

V

SS

VSS

208-Ball BGA

Top View⁽⁸⁾

V

DDQL

I/O7R

I/O6R

VSS

I/O8R

I/O28R

VSS

I/O27R

K

L

V

SS

K

L

I/O29R I/O28L

VDDQR

I/O27L

I/O7L

I/O6L

V

SS

I/O8L

V

DDQL

I/O30R

VSS

I/O29L

V

SS

I/O5R

I/O4R

VDDQR

M

N

P

R

T

M

N

P

R

T

I/O31L

I/O32R

VSS

I/O3R

I/O2L

V

DDQL

I/O31R I/O30L

I/O5L

I/O4L

(1)

I/O3L

I/O32L

I/O33L

VDDQR

V

DD

INT

R

A

4R

VSS

TRST

A

12R

A8R

I/O35R

TCK

A

16R

BE1R

SEMR

V

SS

V

DDQL

I/O1R

VDDQR

V

SS

A

5R

A

1R

2R

A

13R

A9R

NC

V

SS

I/O34R

BE2R

BE3R

CE0R

BUSYR

I/O0R

V

SS

VSS

A

I/O2R

I/O1L

A6R

A

14R

A10R

CE1R

I/O33R I/O34L

V

DDQL TMS

R/WR

V

DD

(2)

15R

OPT

R

I/O0L

V

DD

A

3R

A

0R

A

11R

A7R

V

SS

V

DD

M/S

I/O35L

NC

BE0R

OER

A

U

4869 drw 02b

NOTES:

1. Pin is a NC for IDT70V658 and IDT70V657.

2. Pin is a NC for IDT70V657.

3. All VDD pins must be connected to 3.3V power supply.

4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (3.3V) and 2.5V if OPT pin for that port is

set to V^SS(0V).

5. All VSS pins must be connected to ground.

6. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.

7. This package code is used to reference the package diagram.

8. This text does not indicate orientation of the actual part-marking.

5

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

PinNames

Left Port

Right Port

CE1R

Names

Chip Enables - (Input)

CE^0L

R/W

OE

,

CE1L

CE0R

R/W

OE

,

L

R

Read/Write Enable - (Input)

Output Enable - (Input)

Address - (Input)

L

R

(3)

A

0L - A16L

A0R - A16R

I/O^0L- I/O35L

I/O0R - I/O35R

Data Input/Output

Semaphore Enable - (Input)

Interrupt Flag - (Output)

Busy Flag - (Output)⁽⁴⁾

Byte Enables (9-bit bytes) - (Input)

SEM

INT

BUSY

BE0L - BE3L

L

SEM

INT

BUSY

BE0R - BE3R

R

L

R

L

R

(1)

VDDQL

VDDQR

Power (I/O Bus) (3.3V or 2.5V) - (Input)

(1,2)

OPTL

OPTR

Option for selecting VDDQX - (Input)

M/S

Master or Slave Select - (Input)

(1)

VDD

Power (3.3V) - (Input)

V

SS

Ground (0V) - (Input)

Test Data Input

NOTES:

1. V^DD, OPTX, and VDDQX must be set to appropriate operating levels prior to

applying inputs on I/O^X.

TDI

TDO

TCK

TMS

TRST

2. OPT^Xselects the operating voltage levels for the I/Os and controls on that port.

If OPT^Xis set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V

levels and V^DDQXmust be supplied at 3.3V. If OPTX is set to VIL (0V), then that

port's I/Os and controls will operate at 2.5V levels and V^DDQXmust be supplied

at 2.5V. The OPT pins are independent of one another—both ports can operate

at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V

with the other at 2.5V.

Test Data Output

Test Logic Clock (10MHz)

Test Mode Select

Reset (Initialize TAP Controller)

4869 tbl 01

3. Addresses A¹⁶x is a NC for IDT70V658. Also, Addresses A16x and A15x are

NC's for IDT70V657.

4. BUSY is an input as a slave (M/S = V^IL).

6

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Truth Table I—Read/Write and Enable Control^(1,2)

Byte 3

I/O27-35

Byte 2

I/O18-26

Byte 1

I/O9-17

Byte 0

I/O0-8

CE

X

1

R/W

X

L

MODE

OE

X

L

SEM CE

0

BE

3

BE

2

BE

1

BE0

H

X

L

X

H

L

X

H

L

X

H

L

X

H

L

High-Z

High-Z Deselected–Power Down

L

H

High-Z

All Bytes Deselected

Write to Byte 0 Only

Write to Byte 1 Only

Write to Byte 2 Only

Write to Byte 3 Only

Write to Lower 2 Bytes Only

Write to Upper 2 bytes Only

Write to All Bytes

DIN

H

L

D

IN

High-Z

H

L

D

IN

High-Z

H

L

D

IN

High-Z

H

L

High-Z

DIN

H

L

H

L

D

IN

D

IN

High-Z

L

D

DIN

H

L

H

L

H

L

H

X

High-Z

DOUT

Read Byte 0 Only

L

H

L

DOUT

High-Z Read Byte 1 Only

High-Z Read Byte 2 Only

High-Z Read Byte 3 Only

L

H

L

DOUT

High-Z

L

H

L

DOUT

High-Z

L

H

L

High-Z

DOUT

Read Lower 2 Bytes Only

High-Z Read Upper 2 Bytes Only

Read All Bytes

High-Z Outputs Disabled

L

H

L

H

L

D

OUT

D

OUT

High-Z

L

D

DOUT

H

L

High-Z

4869 tbl 02

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

2. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.

Truth Table II – Semaphore Read/Write Control⁽¹⁾

Inputs⁽¹⁾

BE

Outputs

(2)

R/W

H

I/O^1-35

I/O

0

Mode

CE

OE

L

BE

3

2

BE

1

BE

0

SEM

H

L

X

L

X

L

X

L

DATAOUT

DATAOUT Read Data in Semaphore Flag⁽³⁾

X

DATAIN

Write I/O

0 into Semaphore Flag

↑

______

X

Not Allowed

4869 tbl 03

NOTES:

1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O35). These eight semaphore flags are addressed by A0-A2.

2. CE = L occurs when CE⁰= VIL and CE1 = VIH.

3. Each byte is controlled by the respective BEn. To read data BEn = VIL.

7

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

RecommendedDCOperating

Conditions with VDDQ at 2.5V

Conditions with VDDQ at 3.3V

Symbol

Parameter

Core Supply Voltage

I/O Supply Voltage⁽³⁾

Ground

Min. Typ.

Max.

Unit

V

Symbol

Parameter

Core Supply Voltage

I/O Supply Voltage⁽³⁾

Ground

Min. Typ.

3.15 3.3

Max.

Unit

V

DD

DDQ

SS

3.15 3.3

3.45

V

DD

DDQ

SS

3.45

V

2.4

0

2.5

2.6

V

3.45

V

0

V

0

V

Input High Voltage⁽³⁾

(Address & Control Inputs)

1.7

V

DDQ + 150mV⁽²⁾

V

____

V

DDQ + 100mV⁽²⁾

V

IH

Input High Voltage

2.0

V

IH

(Address & Control Inputs)⁽³⁾

DDQ + 150mV⁽²⁾

0.8

V

____

V

IH

IL

Input High Voltage - I/O⁽³⁾

Input Low Voltage

1.7

DDQ + 100mV⁽²⁾

0.7

V

IH

IL

Input High Voltage - I/O⁽³⁾

Input Low Voltage

2.0

V

-0.5⁽¹⁾

V

-0.3⁽¹⁾

V

4869 tbl 06

4869 tbl 07

NOTES:

1. VIL > -1.5V for pulse width less than 10 ns.

2. VTERM must not exceed VDDQ + 100mV.

1. VIL > -1.5V for pulse width less than 10 ns.

2. VTERM must not exceed VDDQ + 150mV.

3. To select operation at 2.5V levels on the I/Os and controls of a given port, the 3. To select operation at 3.3V levels on the I/Os and controls of a given port, the

OPT pin for that port must be set to V^SS(0V), and VDDQX for that port must be

supplied as indicated above.

OPT pin for that port must be set to V^DD(3.3V), and VDDQX for that port must be

supplied as indicated above.

Capacitance⁽¹⁾

MaximumOperating

TemperatureandSupplyVoltage⁽¹⁾

(TA = +25°C, F = 1.0MHZ) PQFP ONLY

Ambient

Symbol

Parameter

Input Capacitance

Output Capacitance

Conditions

IN = 0V

OUT = 0V

Max. Unit

Grade

Commercial

Temperature

0^OC to +70^OC

-40^OC to +85^OC

GND

0V

V

+

DD

CIN

V

8

pF

3.3V

150mV

(2)

OUT

C

V

10.5

pF

Industrial

0V

4869 tbl 08

NOTES:

4869 tbl 04

NOTE:

1. These parameters are determined by device characterization, but are not

production tested.

1. This is the parameter TA. This is the "instant on" case temperature.

2. COUT also references CI/O.

AbsoluteMaximumRatings⁽¹⁾

Symbol

Rating

Commercial

& Industrial

Unit

(2)

TERM

V

DD Terminal Voltage

-0.5 to + 4.6

V

(VDD

)

with Respect to GND

Temperature Under Bias

Storage Temperature

Junction Temperature

NOTES:

(3)

T

BIAS

STG

JN

-55 to +125

-65 to +150

+150

^oC

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS

may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above

those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may

affect reliability.

T

^oC

2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time

or 4ns maximum, and is limited to < 20mA for the period of VTERM > VDD

+ 150mV.

I

OUT(For VDDQ = 3.3V) DC Output Current

50

mA

IOUT(For VDDQ = 2.5V) DC Output Current

40

mA

3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.

4869 tbl 05

8

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV)

70V659/58/57S

Min. Max.

Symbol

|I^LI

|I^LO

Parameter

Input Leakage Current⁽¹⁾

Output Leakage Current

Test Conditions

DDQ = Max., VIN = 0V to VDDQ

CE

OL = +4mA, VDDQ = Min.

OH = -4mA, VDDQ = Min.

OL = +2mA, VDDQ = Min.

OH = -2mA, VDDQ = Min.

Unit

µA

V

___

|

V

10

|

0

= VIH or CE1 = VIL, VOUT = 0V to VDDQ

V

OL (3.3V) Output Low Voltage⁽²⁾

OH (3.3V) Output High Voltage⁽²⁾

OL (2.5V) Output Low Voltage⁽²⁾

OH (2.5V) Output High Voltage⁽²⁾

I

0.4

___

V

I

2.4

V

___

V

I

0.4

V

___

V

I

2.0

V

4869 tbl 09

NOTE:

1. At VDD < - 2.0V input leakages are undefined.

2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.6 for details.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range⁽³⁾(VDD = 3.3V ± 150mV)

70V659/58/57S10 70V659/58/57S12 70V659/58/57S15

Com'l Only

Com'l

& Ind

Com'l

& Ind

Symbol

Parameter

Test Condition

= VIL

Version

COM'L

Typ.⁽⁴⁾

340

Max.

500

Typ.⁽⁴⁾

Max.

465

515

125

150

325

365

Typ.⁽⁴⁾

300

350

75

Max. Unit

IDD

Dynamic Operating

Current (Both

Ports Active)

mA

CE

L

and CE

R

,

S

315

365

90

440

490

100

125

315

350

Outputs Disabled

____

(1)

IND

f = fMAX

ISB1

Standby Current

(Both Ports - TTL

Level Inputs)

CE

f = fMAX

L

= CE

R

= VIH

COM'L

IND

115

165

(1)

____

115

200

225

100

175

200

(5)

ISB2

Standby Current

(One Port - TTL

Level Inputs)

CE^"A"= VIL and CE"B" = VIH

Active Port Outputs Disabled,

COM'L

IND

225

340

____

(1)

f=fMAX

ISB3

Full Standby Current Both Ports CE

(Both Ports - CMOS CE

Level Inputs)

L and

> VDDQ - 0.2V,

VIN > VDDQ - 0.2V or VIN < 0.2V,

COM'L

IND

S

3

15

3

6

15

3

6

15

R

____

f = 0⁽²⁾

ISB4

Full Standby Current

(One Port - CMOS

Level Inputs)

mA

CE^"A"< 0.2V and

COM'L

IND

S

220

335

195

220

320

360

170

195

310

345

CE^"B"> VDDQ - 0.2V⁽⁵⁾

V

IN > VDDQ - 0.2V or VIN < 0.2V,

Active Port, Outputs Disabled,

____

(1)

f = fMAX

4869 tbl 10

NOTES:

1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, using "AC TEST CONDITIONS" at input

levels of GND to 3V.

2. f = 0 means no address or control lines change. Applies only to input at CMOS level standby.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ).

5. CE^X= VIL means CE0X = VIL and CE1X = VIH

CEX = VIH means CE0X = VIH or CE1X = VIL

CEX < 0.2V means CE0X < 0.2V and CE1X > VDDQ - 0.2V

CE^X> VDDQ - 0.2V means CE0X > VDDQ - 0.2V or CE1X - 0.2V

"X" represents "L" for left port or "R" for right port.

9

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

2.5V

AC Test Conditions (VDDQ - 3.3V/2.5V)

Input Pulse Levels

GND to 3.0V / GND to 2.5V

2ns Max.

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

833Ω

1.5V/1.25V

DATAOUT

Figures 1 and 2

4869 tbl 11

5pF*

770Ω

,

3.3V

590Ω

5pF*

50Ω

,

DATAOUT

1.5V/1.25

10pF

435Ω

(Tester)

4869 drw 03

Figure 1. AC Output Test load.

,

4869 drw 04

Figure 2. Output Test Load

(For t^CKLZ, tCKHZ, tOLZ, and tOHZ).

*Including scope and jig.

10.5pF is the I/O capacitance of this

device, and 10pF is the AC Test Load

Capacitance.

7

6

5

4

3

∆tAA

(Typical, ns)

2

1

,

30

20.5

50

80 100

200

-1

Figure 3. Typical Output Derating (Lumped Capacitive Load).

Capacitance (pF)

4869 drw 05

10

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange⁽⁵⁾

70V659/58/57S10 70V659/58/57S12 70V659/58/57S15

Com'l Only

Com'l

& Ind

Com'l

& Ind

Symbol

Parameter

Min. Max.

Min.

Max.

Min.

Max.

Unit

READ CYCLE

____

t

RC

AA

ACE

ABE

AOE

OH

LZ

HZ

PU

PD

SOP

SAA

Read Cycle Time

10

12

15

ns

____

t

Address Access Time

10

5

12

6

15

7

Chip Enable Access Time⁽³⁾

Byte Enable Access Time⁽³⁾

Output Enable Access Time

____

t

5

6

7

____

t

Output Hold from Address Change

Output Low-Z Time ^(1,2)

3

0

3

0

3

0

____

t

Output High-Z Time^(1,2)

4

6

8

t

Chip Enable to Power Up Time⁽²⁾

Chip Disable to Power Down Time⁽²⁾

Semaphore Flag Update Pulse (OE or SEM)

Semaphore Address Access Time

0

____

t

10

4

10

6

15

8

____

t

3

10

3

12

3

20

ns

4869 tbl 12

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltage⁽⁵⁾

70V659/58/57S10 70V659/58/57S12 70V659/58/57S15

Com'l Only

Com'l

& Ind

Com'l

& Ind

Symbol

Parameter

Min. Max.

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

____

t^WC

t^EW

t^AW

t^AS

Write Cycle Time

10

8

12

10

0

15

12

0

ns

Chip Enable to End-of-Write⁽³⁾

Address Valid to End-of-Write

Address Set-up Time⁽³⁾

Write Pulse Width

8

0

t^WP

tWR

t^DW

t^DH

8

10

0

12

0

Write Recovery Time

Data Valid to End-of-Write

Data Hold Time⁽⁴⁾

0

6

8

10

0

Write Enable to Output in High-Z^(1,2)

Output Active from End-of-Write^(1,2,4)

SEM Flag Write to Read Time

SEM Flag Contention Window

4

____

t^WZ

____

tOW

t^SWRD

t^SPS

0

5

0

5

0

5

____

ns

4869 tbl 13

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. Thisparameterisguaranteedbydevicecharacterization,butisnotproductiontested.

3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.

4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage

and temperature, the actual tDH will always be smaller than the actual tOW.

5. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.

11

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Waveform of Read Cycles⁽⁵⁾

tRC

ADDR

(4)

t

AA

(4)

ACE

CE

OE

(4)

tAOE

(4)

tABE

BEn

R/W

tOH

(1)

tLZ

VALID DATA⁽⁴⁾

DATAOUT

BUSYOUT

(2)

tHZ

.

(3,4)

4869 drw 06

t

BDD

NOTES:

1. Timing depends on which signal is asserted last, OE, CE or BEn.

2. Timing depends on which signal is de-asserted first CE, OE or BEn.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

Timing of Power-Up Power-Down

CE

t

PU

tPD

ICC

50%

.

4869 drw 07

ISB

12

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing^(1,5,8)

tWC

ADDRESS

(7)

tHZ

OE

tAW

CE or SEM⁽⁹⁾

BEn⁽⁹⁾

R/W

(3)

(2)

(6)

tWR

tAS

tWP

(7)

tOW

t

WZ

(4)

DATAOUT

DATAIN

tDW

tDH

4869 drw 08

Timing Waveform of Write Cycle No. 2, CE Controlled Timing^(1,5)

t

WC

ADDRESS

t

AW

CE or SEM⁽⁹⁾

BEn⁽⁹⁾

(6)

AS

(3)

(2)

tWR

tEW

t

R/W

tDW

tDH

DATAIN

4869 drw 09

NOTES:

1. R/W or CE or BEn = VIH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.

3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

(Figure 2).

8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be

placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the

specified tWP.

9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.

13

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side⁽¹⁾

tSAA

A0-A2

VALID ADDRESS

tAW

tWR

tACE

t

EW

SEM/BEn⁽¹⁾

tOH

tSOP

t

DW

OUT

DATA

VALID⁽²⁾

I/O

IN

DATA VALID

tAS

tWP

tDH

R/W

tSWRD

tAOE

OE

tSOP

Write Cycle

Read Cycle

4869 drw 10

NOTES:

1. CE = VIH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table). Refer also to Truth Table II for appropriate BE controls.

2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O35) equal to the semaphore value.

Timing Waveform of Semaphore Write Contention^(1,3,4)

A0"A"-A2"A"

MATCH

(2)

SIDE "A"

R/W"A"

SEM"A"

tSPS

A0"B"-A2"B"

MATCH

(2)

SIDE

R/W"B"

SEM"B"

"B"

4869 drw 11

NOTES:

1. DOR = DOL = VIL, CEL = CER = VIH. Refer to Truth Table II for appropriate BE controls.

2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".

3. This parameter is measured from R/W^"A"or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.

4. If tSPS is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.

14

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange

70V659/58/57S10 70V659/58/57S12 70V659/58/57S15

Com'l Only

Com'l

& Ind

Com'l

& Ind

Symbol

BUSY TIMING (M/S=VIH

Parameter

Unit

Min.

Max.

Min.

Max.

Min.

Max.

)

____

t

BAA

BDA

BAC

BDC

APS

BDD

WH

10

12

15

ns

BUSY Access Time from Address Match

BUSY Disable Time from Address Not Matched

BUSY Access Time from Chip Enable Low

BUSY Disable Time from Chip Enable High

Arbitration Priority Set-up Time⁽²⁾

t

10

12

15

____

t

5

____

BUSY Disable to Valid Data⁽³⁾

t

10

12

15

t

Write Hold After BUSY⁽⁵⁾

8

10

12

____

BUSY TIMING (M/S=VIL

)

____

BUSY Input to Write⁽⁴⁾

Write Hold After BUSY⁽⁵⁾

t

WB

0

8

0

ns

tWH

10

12

PORT-TO-PORT DELAY TIMING

____

t

WDD

Write Pulse to Data Delay⁽¹⁾

22

20

25

22

30

25

ns

tDDD

Write Data Valid to Read Data Delay⁽¹⁾

ns

4869 tbl 14

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of the Max. spec, tWDD – tWP (actual), or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

15

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

TimingWaveformof WritewithPort-to-PortReadandBUSY (M/S =VIH)^(2,4,5)

tWC

MATCH

ADDR"A"

tWP

R/W"A"

tDW

tDH

VALID

DATAIN "A"

(1)

tAPS

MATCH

ADDR"B"

t

BAA

tBDA

tBDD

BUSY"B"

tWDD

DATAOUT "B"

VALID

(3)

tDDD

.

4869 drw 12

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).

2. CE^L= CER = VIL.

3. OE = VIL for the reading port.

4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

Timing Waveform of Write with BUSY (M/S = VIL)

tWP

R/W"A"

(3)

WB

t

BUSY"B"

(1)

tWH

(2)

R/W"B"

4869 drw 13

NOTES:

1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

3. tWB is only for the 'slave' version.

16

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Waveform of BUSY Arbitration Controlled by CE Timing(M/S = VIH)⁽¹⁾

ADDR"A"

ADDRESSES MATCH

and "B"

CE"A"

(2)

t

APS

CE"B"

t

BAC

tBDC

BUSY"B"

4869 drw 14

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing(M/S = VIH)⁽¹⁾

ADDR"A"

ADDRESS "N"

(2)

t

APS

ADDR"B"

MATCHING ADDRESS "N"

tBAA

tBDA

BUSY"B"

4869 drw 15

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange

70V659/58/57S10

Com'l Only

70V659/58/57S12

Com'l

70V659/58/57S15

Com'l

& Ind

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

INTERRUPT TIMING

____

t

AS

WR

INS

INR

Address Set-up Time

Write Recovery Time

Interrupt Set Time

0

ns

t

0

____

t

10

12

15

____

t

Interrupt Reset Time

ns

4869 tbl 15

17

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Waveform of Interrupt Timing⁽¹⁾

tWC

INTERRUPT SET ADDRESS⁽²⁾

ADDR"A"

(4)

(3)

tWR

tAS

CE"A"

R/W"A"

INT"B"

(3)

t

INS

4869 drw 16

tRC

INTERRUPT CLEAR ADDRESS ⁽²⁾

ADDR"B"

CE"B"

(3)

t

AS

OE"B"

(3)

tINR

INT"B"

4869 drw 17

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. Refer to Interrupt Truth Table.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

Truth Table III — Interrupt Flag^(1,4)

Left Port

Right Port

(5,6)

R/W

L

A

16L-A0L

R/W

R

A

16R-A0R

Function

Set Right INT Flag

Reset Right INT Flag

Set Left INT Flag

Reset Left INT Flag

CE

L

OE

L

INT

L

CE

R

OE

R

INTR

L

X

L

X

L

X

1FFFF

X

L

X

L⁽²⁾

H⁽³⁾

X

R

X

L

1FFFF

1FFFE

X

R

X

L⁽³⁾

H⁽²⁾

L

X

L

1FFFE

X

L

4869 tbl 16

NOTES:

1. Assumes BUSY^L= BUSYR =VIH.

2. If BUSY^L= VIL, then no change.

3. If BUSY^R= VIL, then no change.

4. INT^Land INTR must be initialized at power-up.

5. A16x is a NC for IDT70V658, therefore Interrupt Addresses are FFFF and FFFE.

6. A16x and A15x are NC's for IDT70V657, therefore Interrupt Addresses are 7FFF and 7FFE.

18

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Truth Table IV —

AddressBUSY Arbitration

Inputs

Outputs

(4)

A

OL-A16L

(1)

A

OR-A16R

Function

Normal

CE

X

L

CE

R

BUSY

L

BUSYR

X

NO MATCH

MATCH

H

X

H

X

H

L

MATCH

H

L

MATCH

(2)

Write Inhibit⁽³⁾

4869 tbl 17

NOTES:

1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the

IDT70V659/58/57 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address

and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSY^Loutputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

when BUSY^Routputs are driving LOW regardless of actual logic level on the pin.

4. A16X is a NC for IDT70V658, therefore Address comparison will be for A0 - A15. Also, A16X and A15X are NC's for IDT70V657, therefore Address comparison will

be for A0 - A14.

Truth Table V — Example of Semaphore Procurement Sequence^(1,2,3)

Functions

D0

- D35 Left

D0

- D35 Right

Status

No Action

1

0

1

0

1

0

1

0

1

0

1

Semaphore free

Left Port Writes "0" to Semaphore

Right Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "1" to Semaphore

Right Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

Left port has semaphore token

No change. Right side has no write access to semaphore

Right port obtains semaphore token

No change. Left port has no write access to semaphore

Left port obtains semaphore token

Semaphore free

Right port has semaphore token

Semaphore free

Left port has semaphore token

Semaphore free

4869 tbl 18

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V659/58/57.

2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O35). These eight semaphores are addressed by A0 - A2.

3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.

Interrupts

FunctionalDescription

Iftheuserchoosestheinterruptfunction,amemorylocation(mail box

ormessagecenter)isassignedtoeachport. Theleftportinterruptflag

(INTL)isassertedwhentherightportwritestomemorylocation1FFFE

(HEX)(FFFEforIDT70V658and 7FFEforIDT70V657), whereawrite

isdefinedasCER=R/WR=VIL pertheTruthTableIII.Theleftportclears

the interrupt through access of address location 1FFFE (FFFE for

IDT70V658 and 7FFE for IDT70V657) when CEL = OEL = VIL, R/W is

The IDT70V659/58/57 provides two ports with separate control,

addressandI/Opinsthatpermitindependentaccessforreadsorwrites

toanylocationinmemory.TheIDT70V659/58/57hasanautomaticpower

down feature controlled by CE. The CE0 and CE1 control the on-chip

powerdowncircuitrythatpermitstherespectiveporttogointoastandby

mode when not selected (CE= HIGH). When a port is enabled, access

totheentirememoryarrayispermitted.

19

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

a"don'tcare".Likewise,therightportinterruptflag(INTR)isassertedwhen numberofslavestobeaddressedinthesameaddressrangeasthemaster

theleftportwritestomemorylocation1FFFF(HEX)(FFFFforIDT70V658 usetheBUSYsignalasawriteinhibitsignal.ThusontheIDT70V659/58/

and7FFFforIDT70V657)andtocleartheinterruptflag(INT^R),theright 57RAMtheBUSYpinisanoutputifthepartisusedasamaster(M/Spin

port must read the memory location 1FFFF (FFFF for IDT70V658 and = VIH), and the BUSY pin is an input if the part used as a slave (M/S pin

7FFF for IDT70V657). The message (36 bits) at 1FFFE (FFFE for = VIL) as shown in Figure 3.

IDT70V658 and 7FFE for IDT70V657)or 1FFFF (FFFF for IDT70V658

and 7FFF for IDT70V657) is user-defined since it is an addressable

SRAM location. If the interrupt function is not used, address locations

1FFFE (FFFE for IDT70V658 and 7FFE for IDT70V657) and 1FFFF

(FFFF for IDT70V658 and 7FFF for IDT70V657) are not used as mail

boxes,butaspartoftherandomaccessmemory.RefertoTruthTableIII

fortheinterruptoperation.

Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit

decisioncouldresultwithonemasterindicatingBUSYononesideofthe

array and another master indicating BUSY on one other side of

thearray.Thiswouldinhibitthewriteoperationsfromoneportforpartof

awordandinhibitthewriteoperationsfromtheotherportforthe otherpart

of the word.

The BUSY arbitration on a master is based on the chip enable and

address signals only. It ignores whether an access is a read or write. In

a master/slave array, both address and chip enable must be valid long

enoughforaBUSYflagtobeoutputfromthemasterbeforethe actualwrite

pulsecanbeinitiatedwiththeR/Wsignal.Failureto observethistiming

canresultinaglitchedinternalwriteinhibitsignalandcorrupteddatainthe

slave.

BusyLogic

BusyLogicprovidesahardwareindicationthatbothportsoftheRAM

haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe

twoaccessestoproceedandsignalstheothersidethattheRAMis“Busy”.

TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon

theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom

thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally

topreventthewritefromproceeding.

Semaphores

TheIDT70V659/58/57isanextremelyfastDual-Port128/64/32Kx

36CMOSStaticRAMwithanadditional8addresslocationsdedicatedto

binarysemaphoreflags.Theseflagsalloweitherprocessorontheleftor

right sideoftheDual-PortRAMtoclaimaprivilegeovertheotherprocessor

forfunctionsdefinedbythesystemdesigner’ssoftware.Asanexample,

the semaphore can be used by one processor to inhibit the other from

accessingaportionoftheDual-PortRAMoranyothersharedresource.

TheDual-PortRAMfeaturesafastaccesstime,withbothportsbeing

completelyindependentofeachother.Thismeansthatthe activityonthe

leftportinnowayslowstheaccesstimeoftherightport. Bothportsare

identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom

orwrittentoatthesametimewiththeonlypossibleconflictarisingfromthe

simultaneous writing of, or a simultaneous READ/WRITE of, a non-

semaphorelocation.Semaphoresareprotectedagainstsuchambiguous

situationsandmaybeusedbythesystemprogramtoavoidanyconflicts

inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave

anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM

enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol

on-chip power down circuitry that permits the respective port to go into

standbymodewhennotselected.

TheuseofBUSYlogicisnotrequiredordesirableforallapplications.

InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether

and use any BUSY indication as an interrupt source to flag the event of

anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis

notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave

modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely

asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying

the BUSY pins HIGH. If desired, unintended write operations can be

prevented to a port by tying the BUSY pin for that port LOW.

The BUSY outputs on the IDT70V659/58/57 RAM in master mode,

arepush-pulltypeoutputsanddonotrequirepullupresistorstooperate.

If these RAMs are being expanded in depth, then the BUSY indication

for the resulting array requires the use of an external AND gate.

(1,2)

17

A

CE0

MASTER

Dual Port RAM

SLAVE

Dual Port RAM

BUSY

R

BUSY

R

BUSY

L

BUSYL

SystemswhichcanbestusetheIDT70V659/58/57containmultiple

processors or controllers and are typically very high-speed systems

which are software controlled or software intensive. These systems

canbenefitfromaperformanceincreaseofferedbytheIDT70V659/58/

57shardwaresemaphores,whichprovidealockoutmechanismwithout

requiringcomplexprogramming.

Softwarehandshakingbetweenprocessorsoffersthemaximumin

systemflexibilitybypermittingsharedresourcestobeallocatedinvarying

configurations. The IDT70V659/58/57 does not use its semaphore

flagstocontrolanyresourcesthroughhardware,thusallowingthesystem

designertotalflexibilityinsystemarchitecture.

CE

1

CE1

MASTER

Dual Port RAM

SLAVE

Dual Port RAM

BUSY

L

BUSY

L

BUSYR

BUSY

R

.

Figure 3. Busy and chip enable routing for both width and⁴⁸d⁶e⁹p^drt^wh¹⁸

expansion with IDT70V659/58/57 RAMs.

NOTES:

1. A16 for IDT70V658.

2. A15 for IDT70V657.

Width Expansion with Busy Logic

Master/SlaveArrays

An advantage of using semaphores rather than the more common

methodsofhardwarearbitrationisthatwaitstatesareneverincurredin

either processor. This can prove to be a major advantage in very high-

speedsystems.

When expanding an IDT70V659/58/57 RAM array in width while

usingBUSYlogic,onemasterpartisusedtodecidewhichsideoftheRAMs

array will receive a BUSY indication, and to output that indication. Any

20

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

requestlatchwillcontainazero,yetthesemaphoreflagwillappearasone,

afactwhichtheprocessorwillverifybythesubsequentread(seeTable

V).Asanexample,assumeaprocessorwritesazerototheleftportata

freesemaphorelocation.On usedinstead,systemcontentionproblems

couldhaveoccurredduringthegapbetweenthereadandwritecycles.

Itisimportanttonotethatafailedsemaphorerequestmustbefollowed

How the Semaphore Flags Work

Thesemaphorelogicisasetofeightlatcheswhichareindependent

oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken,

from one port to the other to indicate that a shared resource

isinuse.Thesemaphoresprovideahardwareassistforauseassignment

methodcalled“TokenPassingAllocation.”Inthismethod,thestateofa

semaphorelatchisusedasatokenindicatingthatasharedresourceis

inuse.Iftheleftprocessorwantstousethisresource,itrequeststhetoken

bysettingthelatch.Thisprocessorthenverifiesitssuccessinsettingthe

latchbyreadingit. Ifitwassuccessful,itproceedstoassumecontrolover

thesharedresource.Ifitwasnotsuccessfulinsettingthelatch,itdetermines

thattherightsideprocessorhassetthelatchfirst, hasthetokenandisusing

thesharedresource.Theleftprocessorcantheneitherrepeatedlyrequest

that semaphore’s status or remove its request for that semaphore to

performanothertaskandoccasionallyattemptagaintogaincontrolofthe

tokenviathesetandtestsequence.Oncetherightsidehasrelinquished

byeitherrepeatedreadsorbywritingaoneintothesamelocation. The

reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram

ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed

into a semaphore flag. Whichever latch is first to present a zero to the

semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother

sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame

semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch

havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip

overtotheothersideassoonasaoneiswrittenintothefirstside’srequest

latch.Thesecondside’sflagwillnowstayLOWuntilitssemaphorerequest

latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore

is requested and the processor which requested it no longer needs the

thetoken,theleftsideshouldsucceedingainingcontrol.

ThesemaphoreflagsareactiveLOW.Atokenisrequestedbywriting

resource, the entire system can hang up until a one is written into that

semaphorerequestlatch.

azerointoasemaphorelatchandisreleasedwhenthesamesidewrites

aonetothatlatch.

The eight semaphore flags reside within the IDT70V659/58/57 in a

separatememoryspacefromtheDual-PortRAM.Thisaddressspaceis

accessedbyplacingalowinputontheSEMpin(whichactsasachipselect

forthesemaphoreflags)andusingtheothercontrolpins(Address,CE,

R/WandBEo)astheywouldbeusedinaccessingastandardStaticRAM.

Eachoftheflagshasauniqueaddresswhichcanbeaccessedbyeither

sidethroughaddresspinsA0–A2.Whenaccessingthesemaphores,none

oftheotheraddresspinshasanyeffect.

L PORT

R PORT

SEMAPHORE

REQUEST FLIP FLOP

SEMAPHORE

REQUEST FLIP FLOP

0

D

0

D

Q

WRITE

Whenwritingtoasemaphore,onlydatapinD0 isused.Ifalowlevel

iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero

on that side and a one on the other side (see Truth Table V). That

semaphorecannowonlybemodifiedbythesideshowingthezero.When

aoneiswrittenintothesamelocationfromthesameside,the flagwillbe

settoaoneforbothsides(unlessasemaphorerequestfromtheotherside

ispending)andthencanbewrittentobybothsides.Thefactthattheside

whichisabletowriteazerointoasemaphoresubsequentlylocksoutwrites

fromtheothersideiswhatmakessemaphoreflagsusefulininterprocessor

communications.(Athoroughdiscussionontheuseofthisfeaturefollows

shortly.)Azerowrittenintothesamelocationfromtheothersidewillbe

storedinthesemaphorerequestlatchforthatsideuntilthesemaphoreis

freedbythefirstside.

Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso

thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining

azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput

registerwhenthatside'ssemaphoreselect(SEM,BEn)andoutputenable

(OE) signals go active. This serves to disallow the semaphore from

changingstateinthemiddleofareadcycleduetoawritecyclefromthe

otherside.Becauseofthislatch,arepeatedreadofasemaphoreinatest

loopmustcauseeithersignal(SEMorOE)togoinactiveortheoutputwill

neverchange. However, duringreads BEnfunctionsonlyasanoutput

forsemaphore.Itdoesnothaveanyinfluenceonthesemaphore control

logic.

SEMAPHORE

READ

SEMAPHORE

READ

4869 drw 19

Figure 4. IDT70V659/58/57 Semaphore Logic

The critical case of semaphore timing is when both sides request a

single token by attempting to write a zero into it at the same time. The

semaphorelogicisspeciallydesignedtoresolvethisproblem.Ifsimulta-

neousrequestsaremade,thelogicguaranteesthatonlyonesidereceives

thetoken.Ifonesideisearlierthantheotherinmakingtherequest,thefirst

sidetomaketherequestwillreceivethetoken.Ifbothrequestsarriveat

thesametime,theassignmentwillbearbitrarilymadetooneportorthe

other.

One caution that should be noted when using semaphores is that

semaphoresalonedonotguaranteethataccesstoaresourceissecure.

Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused

or misinterpreted, a software error can easily happen.

Initializationofthesemaphoresisnotautomaticandmustbehandled

viatheinitializationprogramatpower-up.Sinceanysemaphorerequest

flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth

sidesshouldhaveaonewrittenintothematinitializationfrombothsides

to assure that they will be free when needed.

AsequenceWRITE/READmustbeusedbythesemaphoreinorder

to guarantee that no system level contention will occur. A processor

requestsaccesstosharedresourcesbyattemptingtowriteazerointoa

semaphorelocation.Ifthesemaphoreisalreadyinuse,thesemaphore

21

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

JTAGTimingSpecifications

t

JCYC

t

JR

tJF

t

JCL

tJCH

TCK

Device Inputs⁽¹⁾/

TDI/TMS

tJDC

tJS

tJH

Device Outputs⁽²⁾/

TDO

t

JRSR

tJCD

TRST

x

4869 drw 20

t

JRST

NOTES:

1. Device inputs = All device inputs except TDI, TMS, and TRST.

2. Device outputs = All device outputs except TDO.

JTAG AC Electrical

Characteristics^(1,2,3,4)

Symbol

Parameter

JTAG Clock Input Period

JTAG Clock HIGH

JTAG Clock Low

JTAG Clock Rise Time

JTAG Clock Fall Time

JTAG Reset

Min.

100

40

Max.

Units

ns

____

t

JCYC

JCH

JCL

JR

JF

JRST

JRSR

JCD

JDC

JS

JH

____

t

ns

t

40

ns

t

3⁽¹⁾

ns

____

t

3⁽¹⁾

ns

____

t

50

ns

____

t

JTAG Reset Recovery

JTAG Data Output

JTAG Data Output Hold

JTAG Setup

50

ns

____

t

25

ns

____

t

0

ns

____

t

15

ns

t

JTAG Hold

ns

4869 tbl 19

NOTES:

1. Guaranteed by design.

2. 30pF loading on external output signals.

3. Refer to AC Electrical Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at

any speed specified in this datasheet.

22

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Identification Register Definitions

Instruction Field

Value

Description

Revision Number (31:28)

0x0

Reserved for version number

0x303⁽¹⁾

0x33

1

IDT Device ID (27:12)

IDT JEDEC ID (11:1)

ID Register Indicator Bit (Bit 0)

NOTE:

Defines IDT part number

Allows unique identification of device vendor as IDT

Indicates the presence of an ID register

4869 tbl 20

1. Device ID for IDT70V658 is 0x30B. Device ID for IDT70V657 is 0x323.

ScanRegisterSizes

Register Name

Bit Size

Instruction (IR)

Bypass (BYR)

4

1

Identification (IDR)

32

Boundary Scan (BSR)

Note (3)

4869 tbl 21

SystemInterfaceParameters

Instruction

Code

Description

EXTEST

0000

Forces contents of the boundary scan cells onto the device outputs⁽¹⁾

Places the boundary scan register (BSR) between TDI and TDO.

.

BYPASS

IDCODE

1111

Places the by pass registe r (BYR) betwe en TDI and TDO.

0010

Loads the ID register (IDR) with the vendor ID code and places the

register between TDI and TDO.

0100

Places the bypass register (BYR) between TDI and TDO. Forces all

device output drivers to a High-Z state.

HIGHZ

Uses BYR. Forces contents of the boundary scan cells onto the device

outputs. Places the bypass register (BYR) between TDI and TDO.

CLAMP

0011

0001

SAMPLE/PRELOAD

Places the boundary scan register (BSR) between TDI and TDO.

SAMPLE allows data from device inputs⁽²⁾and outputs⁽¹⁾to be captured

in the boundary scan cells and shifted serially through TDO. PRELOAD

allows data to be input serially into the b oundary scan cells via the TDI.

RESERVED

All other codes

Several combinations are reserved. Do not use codes other than those

identified above.

4869 tbl 22

NOTES:

1. Device outputs = All device outputs except TDO.

2. Device inputs = All device inputs except TDI, TMS, and TRST.

3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local

IDT sales representative.

23

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Ordering Information

XXXXX

A

999

A

Device

Type

Power Speed

Package

Process/

Temperature

Range

Tube or Tray

Tape and Reel

Blank

8

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

Blank

I⁽¹⁾

G⁽²⁾

Green

208-ball fpBGA (BF208)

208-pin PQFP (DR208)

256-ball BGA (BC256)

BF

DR

BC

10

12

15

Commercial Only

Commercial & Industrial

Speed in nanoseconds

S

Standard Power

70V659

70V658

70V657

4Mbit (128K x 36) 3.3V Asynchronous Dual-Port RAM

2Mbit (64K x 36) 3.3V Asynchronous Dual-Port RAM

1Mbit (32K x 36) 3.3V Asynchronous Dual-Port RAM

4869 drw 21

NOTES:

1. Contact your local sales office for Industrial temp range in other speeds, packages and powers.

2. Greenpartsavailable.Forspecificspeeds,packagesandpowerscontactyourlocalsalesoffice.

LEADFINISH(SnPb)partsareinEOLprocess.ProductDiscontinuationNotice-PDN#SP-17-02

DatasheetDocumentHistory:

06/02/00:

08/11/00:

06/20/01:

InitialPublicOffering

Page 6, 13 & 20 Inserted additional BEn information

Page 14 Increased BUSY TIMING parameters tBDA, tBAC, tBDC and tBDD for all speeds

Page 21 ChangedmaximumvalueforJTAGACElectricalCharacteristicsfortJCD from20nsto25ns

Page 2, 3 & 4 Added date revision for pin configurations

Page 8, 10, 14 & 16 Removed I-temp 15ns speed from DC & AC Electrical Characteristics

Page23 RemovedI-temp15nsspeedfromorderinginformation

Added I-temp footnote

12/17/01:

Page 1 & 23 Replaced TM logo with ® logo

03/19/04:

03/22/05:

Consolidatedmultipledevicesintoonedatasheet

Removed"Preliminary"Status

Page 1 Added green availability to features

Page 24 Added green indicator to ordering information

Page 1 & 24 Replaced old IDT ^TMwith new IDT TM logo

Page 9 Corrected a typo in the DC Chars table

07/25/08:

Page 24 Removed "IDT" from orderable part number

Page 24 AddedT&RindicatortoOrderingInformation

ProductDiscontinuationNotice-PDN#SP-17-02

10/23/08:

06/18/18:

Last time buy expires June 15, 2018

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

for Tech Support:

408-284-2794

DualPortHelp@idt.com

800-345-7015 or 408-284-8200

fax: 408-284-2775

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

24


型号：	70V657S15BCGI8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	HIGH-SPEED 3.3V 128/64/32K x 36 ASYNCHRONOUS DUAL-PORT STATIC RAM
文件：	总24页 (文件大小：234K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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