70V9079S9PFG8 [IDT]
HIGH-SPEED 3.3V 64/32K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM;
| 型号： | 70V9079S9PFG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | HIGH-SPEED 3.3V 64/32K x 8 SYNCHRONOUS DUAL-PORT STATIC RAM |
| 文件： | 总19页 (文件大小：168K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH-SPEED 3.3V
64/32K x 8 SYNCHRONOUS
DUAL-PORT STATIC RAM
IDT70V9089/79S/L
◆
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
Full synchronous operation on both ports
– 4ns setup to clock and 1ns hold on all control, data, and
addressinputs
Features:
◆
◆
◆
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
– Commercial:6.5/7.5/9/12/15ns(max.)
– Industrial: 12ns (max.)
◆
–
–
Data input, address, and control registers
Fast 6.5ns clock to data out in the Pipelined output mode
◆
Low-power operation
– IDT70V9089/79S
– Self-timedwriteallowsfastcycletime
10nscycletime,100MHzoperationinthePipelinedoutputmode
Active:429mW(typ.)
Standby: 3.3mW (typ.)
– IDT70V9089/79L
Active:429mW(typ.)
Standby: 1.32mW (typ.)
Flow-Through or Pipelined output mode on either port via
the FT/PIPE pin
–
◆
◆
LVTTL- compatible, single 3.3V (±0.3V) power supply
Industrial temperature range (–40°C to +85°C) is
available for selected speeds
Available in a 100 pin Thin Quad Flatpack (TQFP) package
Green parts available, see ordering information
◆
◆
◆
FunctionalBlockDiagram
R/W
OE
L
L
R/W
OE
R
R
CE
CE10LL
CE0R
CE1R
1
1
0
0
0/1
0/1
1
0
1
0
0/1
0/1
FT/PIPE
L
FT/PIPE
R
,
I/O0L - I/O7L
I/O0R - I/O7R
I/O
I/O
Control
Control
(1)
(1)
A15R
A
15L
Counter/
Address
Reg.
Counter/
Address
Reg.
A
C0LRK
R
R
MEMORY
ARRAY
A
0L
CLK
ADS
L
L
L
ADS
CNTEN
R
CNTEN
CNTRST
R
CNTRST
L
3750 drw 01
NOTE:
1. A15X is a NC for IDT70V9079.
JULY 2014
1
DSC 3750/12
©2014 Integrated Device Technology, Inc.
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description:
With an input data register, the IDT70V9089/79 has been opti-
mized for applications having unidirectional or bidirectional data flow
in bursts. An automatic power down feature, controlled by CE0 and
CE1, permits the on-chip circuitry of each port to enter a very low
standby power mode. Fabricated using CMOS high-performance
technology, these devices typically operate on only 429mW of
power.
The IDT70V9089/79 is a high-speed 64/32K x 8 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allowsimultaneousaccessofanyaddressfrombothports.Registerson
control,data,andaddressinputsprovideminimalsetupandholdtimes.
The timing latitude provided by this approach allows systems to be
designedwithveryshortcycletimes.
PinConfigurations(2,3,4)
10/30/13
Index
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
NC
NC
1
NC
NC
75
74
2
A
A
A
A
A
A
A
A
A
7R
3
A
A
A
7L
8L
9L
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
8R
4
9R
5
10R
11R
12R
13R
14R
15R
A
A
A
A
A
10L
11L
12L
13L
6
7
8
9
14L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
IDT70V9089/79PF
(1)
(1)
(5)
A
15L
PN100
NC
NC
100-PIN TQFP
VSS
VDD
(6)
TOP VIEW
NC
NC
NC
NC
CE0R
CE1R
NC
NC
NC
NC
CE0L
CE1L
CNTRST
R
CNTRST
L
L
L
R/W
OE
FT/PIPE
R
R/W
OE
FT/PIPE
R
R
L
VSS
NC
NC
24
25
NC
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
3750 drw 02
NOTES:
1. A15X is a NC for IDT70V9079.
2. All Vcc pins must be connected to power supply.
3. All GND pins must be connected to ground.
4. Package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
2
6.42
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
PinNames
Left Port
Right Port
CE0R, CE1R
R/W
OE
Names
Chip Enables
CE0L, CE1L
R/W
OE
L
R
Read/Write Enable
Output Enable
Address
L
R
(1)
(1)
A
0L - A15L
A
0R - A15R
I/O0R - I/O7R
CLK
I/O0L - I/O7L
CLK
Data Input/Output
Clock
L
R
Address Strobe
Counter Enable
Counter Reset
Flow-Through/Pipeline
Power (3.3V)
Ground (0V)
ADS
CNTEN
CNTRST
FT/PIPE
L
ADS
CNTEN
CNTRST
FT/PIPE
R
L
R
L
R
NOTE:
1. A15X is a NC for IDT70V9079.
L
R
2. LB and UB are single buffered regardless of state of FT/PIPE.
3. CEo and CE1 are single buffered when FT/PIPE = VIL,
CEo and CE1 are double buffered when FT/PIPE = VIH,
i.e. the signals take two cycles to deselect.
V
V
DD
SS
3750 tbl 01
Truth Table I—Read/Write and
EnableControl(1,2,3)
Mode
CLK
CE
1
R/
W
I/O0-7
High-Z
High-Z
DATAIN
OE
CE
H
X
0
↑
X
X
X
Deselected - Power Down
Deselected - Power Down
Write
↑
X
L
X
L
↑
X
L
H
↑
L
L
H
H
X
DATAOUT Read
High-Z Outputs Disabled
H
X
L
H
3750 tbl 02
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
Truth Table II—Address Counter Control(1,2,3)
Previous
Internal
Address
Internal
Address
Used
External
Address
MODE
CLK
↑
I/O(3)
DI/O (n) External Address Used
ADS CNTEN CNTRST
An
X
X
An
An
L(4)
H
X
H
H
An + 1
An + 1
L(5)
H
D
I/O(n+1) Counter Enabled—Internal Address generation
↑
↑
X
An + 1
X
H
H
D
I/O(n+1) External Address Blocked—Counter disabled (An + 1 reused)
X
A0
X
X
L(4)
DI/O(0)
Counter Reset to Address 0
↑
3750 tbl 03
NOTES:
1. "H" = VIH, "L" = VIL, "X" = Don't Care.
2. CE0 and OE = VIL; CE1 and R/W = VIH.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS and CNTRST are independent of all other signals including CE0 and CE1.
5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0 and CE1.
6.432
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
RecommendedDCOperating
RecommendedOperating
TemperatureandSupplyVoltage(1)
Ambient
Conditions
Symbol
Parameter
Min.
3.0
Typ.
Max.
Unit
V
Grade
Temperature
0OC to +70OC
-40OC to +85OC
GND
VDD
VDD
SS
Supply Voltage
Ground
3.3
3.6
Commercial
0V
3.3V
3.3V
+
0.3V
V
0
0
0
V
Industrial
0V
+
0.3V
____
V
IH
IL
Input High Voltage
Input Low Voltage
2.2
V
DD + 0.3V(1)
0.8
V
3750 tbl 04
____
V
-0.3(2)
V
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
3750 tbl 05
NOTES:
1. VTERM must not exceed VDD +0.3V.
2. VIL > -1.5V for pulse width less than 10ns.
AbsoluteMaximumRatings(1)
Capacitance (TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
Output Capacitance
Conditions(2 )
IN = 3dV
OUT = 3dV
Max. Unit
Symbol
Rating
Commercial
& Industrial
Unit
CIN
V
9
pF
(2)
VTERM
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
-55 to +125
V
(3 )
OUT
C
V
10
pF
3750 tbl 07
NOTES:
TBIAS
Temperature
Under Bias
oC
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. COUT also references CI/O.
T
STG
JN
OUT
Storage Temperature
Junction Temperature
DC Output Current
-65 to +150
+150
oC
oC
T
I
50
mA
3750 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VTERM must not exceed VDD +0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > VDD + 0.3V.
3. Ambient Temperature Under Bias. Chip Deselected.
4
6.42
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V ± 0.3V)
70V9089/79S
70V9089/79L
Symbol
|ILI
|ILO
Parameter
Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
Test Conditions
DD = 3.3V, VIN = 0V t
CE
OL = +4mA
OH = -4mA
Min.
Max.
10
Min.
Max.
Unit
µA
µA
V
___
___
___
___
|
V
o
V
DD
5
5
___
___
|
10
0
= VIH or CE1 = VIL, VOUT = 0V to VDD
V
V
OL
OH
I
0.4
0.4
___
___
Output High Voltage
I
2.4
2.4
V
3750 tbl 08
NOTE:
1. At VDD < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(6) (VDD = 3.3V ± 0.3V)
70V9089/79X6
Com'l Only
70V9089/79X7
Com'l Only
70V9089/79X9
Com'l Only
Typ.(4)
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(4)
Max.
Max.
Typ.(4)
Max.
Unit
I
CC
Dynamic Operating
Current
(Both Ports Active)
S
L
220
220
395
350
200
200
335
290
180
180
260
225
mA
CE
L
and CER = VIL
Outputs Disabled
(1)
f = fMAX
____
____
____
____
____
____
____
____
____
____
____
____
IND
S
L
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
S
L
70
70
145
130
60
60
115
100
50
50
75
65
mA
mA
CE
L
and CER = VIH
(1)
f = fMAX
____
____
____
____
____
____
____
____
____
____
____
____
S
L
I
I
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
S
L
150
150
280
250
130
130
240
210
110
110
170
150
CE"A" = VIL and
(3)
CE"B" = VIH
Active Port Outputs Disabled,
____
____
____
____
____
____
____
____
____
____
____
____
(1)
IND
S
L
f=fMAX
SB3
SB4
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CE
R
and
mA
mA
COM'L
IND
S
L
1.0
0.4
5
3
1.0
0.4
5
3
1.0
0.4
5
3
CE
L
> VDD - 0.2V
V
V
IN > VDD - 0.2V or
IN < 0.2V, f = 0(2)
____
____
____
____
____
____
____
____
____
____
____
____
S
L
Full Standby Current
(One Port -
CMOS Level Inputs)
COM'L
IND
S
L
140
140
270
240
120
120
230
200
100
100
160
140
CE"A" < 0.2V and
CE"B" > VDD - 0.2V(5)
V
V
IN > VDD - 0.2V or
IN < 0.2V, Active Port
____
____
____
____
____
____
____
____
____
____
____
____
S
L
(1)
Outputs Disabled, f = fMAX
3750 tbl 09a
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 90mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6. 'X' in part number indicates power rating (S or L).
6.452
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(6) (VDD = 3.3V ± 0.3V)(Cont'd)
70V9089/79X12
Com'l & Ind
70V9089/79X15
Com'l Only
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(4)
Max.
Typ.(4)
Max.
Unit
I
CC
Dynamic Operating
Current
(Both Ports Active)
S
L
150
150
240
215
130
130
220
185
mA
CE
L
and CER = VIL
Outputs Disabled
(1)
f = fMAX
____
____
____
____
____
____
IND
S
L
150
215
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
IND
S
L
40
40
65
60
30
30
55
35
mA
mA
CE
L
and CER = VIH
(1)
f = fMAX
____
____
____
____
____
____
S
L
40
60
I
I
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
S
L
100
100
160
140
90
90
150
130
CE"A" = VIL and
(3)
CE"B" = VIH
Active Port Outputs Disabled,
____
____
____
____
____
____
(1)
IND
S
L
f=fMAX
100
150
SB3
SB4
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CE
R
and
mA
mA
COM'L
IND
S
L
1.0
0.4
5
3
1.0
0.4
5
3
CE
L
> VDD - 0.2V
V
IN > VDD - 0.2V or
IN < 0.2V, f = 0(2)
____
____
____
____
____
____
S
L
V
0.4
3
Full Standby Current
(One Port -
CMOS Level Inputs)
COM'L
IND
S
L
90
90
150
130
80
80
140
120
CE"A" < 0.2V and
CE"B" > VDD - 0.2V(5)
V
IN > VDD - 0.2V or
____
____
____
____
____
____
S
L
VIN < 0.2V, Active Port
(1)
90
140
Outputs Disabled, f = fMAX
3750 tbl 09b
NOTES:
1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 90mA (Typ).
5. CEX = VIL means CE0X = VIL and CE1X = VIH
CEX = VIH means CE0X = VIH or CE1X = VIL
CEX < 0.2V means CE0X < 0.2V and CE1X > VDD - 0.2V
CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V
"X" represents "L" for left port or "R" for right port.
6. 'X' in part number indicates power rating (S or L).
6
6.42
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
Figures 1,2 and 3
3750 tbl 10
3.3V
3.3V
590Ω
590Ω
DATAOUT
DATAOUT
30pF
435Ω
5pF*
435Ω
3750 drw 03
3750 drw 04
Figure 2. Output Test Load
(For tCKLZ, tCKHZ, tOLZ, and tOHZ).
*Including scope and jig.
Figure 1. AC Output Test load.
8
7
6
5
10 pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
tCD
tCD
(Typical, ns)
1
,
4
3
2
1
2
0
20 40 60 80 100 120 140 160 180 200
Capacitance (pF)
-1
,
3750 drw 05
Figure 3. Typical Output Derating (Lumped Capacitive Load).
6.472
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3,4) (VDD = 3.3V ± 0.3, TA = 0°C to +70°C)
70V9089/79X6
Com'l Only
70V9089/79X7
Com'l Only
70V9089/79X9
Com'l Only
Symbol
Parameter
Clock Cycle Time (Flow-Through)(2)
Min.
19
Max.
Min.
22
Max.
Min.
25
15
12
12
6
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CYC1
Clock Cycle Time (Pipelined)(2)
Clock High Time (Flow-Through)(2)
Clock Low Time (Flow-Through)(2)
Clock High Time (Pipelined)(2)
Clock Low Time (Pipelined)(2)
Clock Rise Time
10
12
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
CYC2
CH1
CL1
CH2
CL2
R
6.5
6.5
4
7.5
7.5
5
4
5
6
____
____
____
3
3
3
____
____
____
F
Clock Fall Time
3
3
3
____
____
____
SA
Address Setup Time
3.5
0
4
0
4
0
4
0
4
0
4
0
4
0
4
4
1
4
1
4
1
4
1
4
1
4
1
4
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
HA
Address Hold Time
SC
Chip Enable Setup Time
Chip Enable Hold Time
R/W Setup Time
3.5
0
HC
SW
3.5
0
HW
SD
R/W Hold Time
Input Data Setup Time
Input Data Hold Time
ADS Setup Time
3.5
0
HD
SAD
HAD
SCN
HCN
SRST
HRST
OE
3.5
0
ADS Hold Time
3.5
0
CNTEN Setup Time
CNTEN Hold Time
3.5
CNTRST Setup Time
0
0
1
CNTRST Hold Time
____
____
____
Output Enable to Data Valid
Output Enable to Output Low-Z(1)
Output Enable to Output High-Z(1)
Clock to Data Valid (Flow-Through)(2)
Clock to Data Valid (Pipelined)(2)
Data Output Hold After Clock High
Clock High to Output High-Z(1)
Clock High to Output Low-Z(1)
6.5
7.5
9
____
____
____
OLZ
OHZ
CD1
CD2
DC
2
2
2
1
7
1
7
1
7
____
____
____
15
18
20
____
____
____
6.5
7.5
9
____
____
____
2
2
2
2
2
2
2
2
2
CKHZ
CKLZ
9
9
9
____
____
____
Port-to-Port Delay
____
____
____
____
____
____
t
t
CWDD
CCS
Write Port Clock High to Read Data Delay
Clock-to-Clock Setup Time
24
9
28
10
35
15
ns
ns
3750 tbl 11a
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
This parameter is guaranteed by device characterization, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a
DC signal, i.e. steady state during operation.
4. 'X' in part number indicates power rating (S or L).
8
6.42
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the Operating Temperature Range
(Read and Write Cycle Timing)(3,4) (VDD = 3.3V ± 0.3)
70V9089/79X12
Com'l & Ind
70V908979X15
Com'l Only
Symbol
Parameter
Clock Cycle Time (Flow-Through)(2)
Min.
30
20
12
12
8
Max.
Min.
35
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
____
____
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CYC1
Clock Cycle Time (Pipelined)(2)
Clock High Time (Flow-Through)(2)
Clock Low Time (Flow-Through)(2)
Clock High Time (Pipelined)(2)
Clock Low Time (Pipelined)(2)
Clock Rise Time
25
____
____
____
____
____
____
____
____
____
____
CYC2
CH1
CL1
CH2
CL2
R
12
12
10
8
10
____
____
3
3
____
____
F
Clock Fall Time
3
3
____
____
SA
Address Setup Time
4
1
4
1
4
1
4
1
4
1
4
1
4
4
1
4
1
4
1
4
1
4
1
4
1
4
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
HA
Address Hold Time
SC
Chip Enable Setup Time
Chip Enable Hold Time
R/W Setup Time
HC
SW
HW
R/W Hold Time
SD
Input Data Setup Time
Input Data Hold Time
HD
SAD
HAD
SCN
HCN
SRST
HRST
OE
ADS Setup Time
ADS Hold Time
CNTEN Setup Time
CNTEN Hold Time
CNTRST Setup Time
1
1
CNTRST Hold Time
____
____
Output Enable to Data Valid
Output Enable to Output Low-Z(1)
Output Enable to Output High-Z(1)
Clock to Data Valid (Flow-Through)(2)
Clock to Data Valid (Pipelined)(2)
Data Output Hold After Clock High
Clock High to Output High-Z(1)
Clock High to Output Low-Z(1)
12
15
____
____
OLZ
OHZ
CD1
CD2
DC
2
2
1
7
1
7
____
____
25
30
____
____
12
15
____
____
2
2
2
2
2
2
CKHZ
CKLZ
9
9
____
____
Port-to-Port Delay
____
____
____
____
t
CWDD
CCS
Write Port Clock High to Read Data Delay
Clock-to-Clock Setup Time
40
15
50
20
ns
t
ns
3750 tbl 11b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
This parameter is guaranteed by device characterization, but is not production tested.
2. The Pipelined output parameters (tCYC2, tCD2) apply to either or both left and right ports when FT/PIPE = VIH. Flow-through parameters (tCYC1, tCD1) apply when
FT/PIPE = VIL for that port.
3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (OE) and FT/PIPE. FT/PIPE should be treated as a
DC signal, i.e. steady state during operation.
4. 'X' in part number indicates power rating (S or L).
6.492
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle for Flow-Through Output
(FT/PIPE"X" = VIL)(3,6)
t
CYC1
tCH1
tCL1
CLK
CE0
tSC
tHC
tHC
tSC
(4)
CE1
R/W
t
HW
t
SW
SA
t
HA
t
ADDRESS(5)
An
An + 1
An + 2
An + 3
t
DC
(1)
t
CD1
tCKHZ
Qn
Qn + 1
Qn + 2
DATAOUT
(1)
(1)
t
DC
t
CKLZ
(1)
t
OHZ
t
OLZ
OE(2)
tOE
3750 drw 06
Timing Waveform of Read Cycle for Pipelined Output (FT/PIPE"X" = VIH)(3,6)
t
CYC2
tCH2
tCL2
CLK
CE
0
tSC
tHC
tSC
tHC
(4)
CE1
R/W
tHW
tSW
tSA
tHA
ADDRESS(5)
DATAOUT
An
An + 1
An + 2
Qn
An + 3
(1 Latency)
tDC
tCD2
Qn + 1
Qn + 2
(1)
(1)
tCKLZ
(1)
t
OHZ
tOLZ
(2)
OE
tOE
3750 drw 07
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
3. ADS = VIL and CNTRST = VIH.
4. The output is disabled (High-impedance state) by CE0 = VIH or CE1 = VIL following the next rising edge of clock. Refer to Truth Table 1.
5. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
6. "x" denotes Left or Right port. The diagram is with respect to that port.
10
6.42
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of a Bank Select Pipelined Read(1,2)
t
CYC2
t
CH2
tCL2
CLK
ADDRESS(B1)
CE0(B1)
t
SA
tHA
A6
A5
A4
A3
A
2
A
0
A1
t
SC
tHC
t
SC
tHC
(3)
tCD2
t
CKHZ
tCD2
t
CD2
Q
0
Q3
Q
1
DATAOUT(B1)
ADDRESS(B2)
(3)
(3)
tCKHZ
t
DC
t
CKLZ
t
DC
tSA
tHA
A6
A5
A4
A3
A2
A
0
A1
t
SC
tHC
CE0(B2)
t
SC
tHC
(3)
CKHZ
t
CD2
t
t
CD2
(3)
DATAOUT(B2)
Q4
Q2
(3)
t
CKLZ
t
CKLZ
3750 drw 08
Timing Waveform of a Bank Select Flow-Through Read(6)
t
CYC1
tCH1
tCL1
CLK
tSA
tHA
A6
A5
A4
A3
A2
A0
A1
ADDRESS(B1)
t
SC
tHC
CE0(B1)
t
SC
tHC
(1)
t
CD1
tCD1
t
CKHZ
t
CD1
(1)
tCD1
D0
D3
D5
D1
DATAOUT(B1)
ADDRESS(B2)
(1)
(1)
tDC
t
CKLZ
tCKLZ
t
DC
t
CKHZ
tSA
tHA
A6
A5
A4
A3
A2
A
0
A1
t
SC
tHC
CE0(B2)
t
SC
t
HC
(1)
(1)
t
CD1
(1)
tCKHZ
tCD1
t
CKHZ
D4
DATAOUT(B2)
D2
(1)
t
CKLZ
tCKLZ
3750 drw 08a
NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9089/79 for this waveform,
and are setup for depth expansion in this example. ADDRESS(B1) = ADDRESS(B2) in this situation.
2. OE and ADS = VIL; CE1(B1), CE1(B2), R/W and CNTRST = VIH.
3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4. CE0 and ADS = VIL; CE1 and CNTRST = VIH.
5. OE = VIL for the Right Port, which is being read from. OE = VIH for the Left Port, which is being written to.
6. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
6.1412
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform Port-to-Port Flow-Through Read(1,2,3,5)
CLK "A"
tSW
tHW
R/W "A"
ADDRESS "A"
DATAIN "A"
CLK "B"
t
SA
MATCH
SD HD
VALID
tHA
NO
MATCH
t
t
(4)
t
CCS
tCD1
R/W "B"
t
HW
HA
t
SW
t
tSA
NO
MATCH
ADDRESS "B"
DATAOUT "B"
MATCH
(4)
t
CD1
t
CWDD
VALID
VALID
tDC
tDC
3750 drw 09
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. CE0 and ADS = VIL; CE1 and CNTRST = VIH.
3. OE = VIL for the Port "B", which is being read from. OE = VIH for the Port "A", which is being written to.
4. If tCCS < maximum specified, then data from right port READ is not valid until the maximum specified for tCWDD.
If tCCS > maximum specified, then data from right port READ is not valid until tCCS + tCD1. tCWDD does not apply in this case.
5. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".
12
6.42
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read-to-Write-to-Read (OE = VIL)(3)
t
CYC2
t
CH2
t
CL2
CLK
CE0
tSC
tHC
CE1
tSW tHW
R/W
tSW tHW
ADDRESS(4)
An + 4
An + 3
An
An +1
An + 2
An + 2
tSA
tHA
tSD
tHD
DATAIN
Dn + 2
(1)
tCD2
t
CD2
(1)
(2)
tCKLZ
tCKHZ
Qn + 3
Qn
DATAOUT
READ
NOP(5)
WRITE
READ
3750 drw 10
Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)(3)
t
CYC2
t
CH2
tCL2
CLK
CE0
tSC
tHC
CE1
tSW tHW
R/W
tSW
tHW
ADDRESS(4)
DATAIN
An + 4
An
An +1
An + 2
An + 3
Dn + 3
An + 5
t
SA
tHA
t
SD
tHD
Dn + 2
(1)
CKLZ
t
CD2
tCD2
t
(2)
Qn
Qn + 4
DATAOUT
(1)
t
OHZ
OE
READ
WRITE
READ
3750 drw 11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1 and CNTRST = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
6.1432
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = VIL)(3)
t
CYC1
t
CH1
tCL1
CLK
CE0
tSC
tHC
CE1
tSW tHW
R/W
tSW tHW
(4)
An + 4
An
An + 3
An +1
An + 2
An + 2
ADDRESS
tSA
tHA
tSD tHD
DATAIN
Dn + 2
tCD1
tCD1
tCD1
tCD1
(2)
Qn + 3
Qn
READ
Qn + 1
DATAOUT
(1)
(1)
tDC
t
DC
tCKLZ
t
CKHZ
NOP(5)
READ
WRITE
3750 drw 12
TimingWaveformofFlow-ThroughRead-to-Write-to-Read(OE Controlled)(3)
tCYC1
CH1
t
tCL1
CLK
CE0
tSC
tHC
CE1
tSW tHW
tSW tHW
R/W
ADDRESS(4)
DATAIN
An + 5
An
An + 4
An +1
An + 2
An + 3
Dn + 3
t
SA
tHA
tSD tHD
Dn + 2
tOE
tDC
tCD1
tCD1
tCD1
(2)
Qn + 4
Qn
DATAOUT
(1)
CKLZ
(1)
t
tDC
tOHZ
OE
READ
WRITE
READ
3750 drw 13
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3. CE0 and ADS = VIL; CE1 and CNTRST = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.
14
6.42
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Pipelined Read with Address Counter Advance(1)
t
CYC2
tCH2
t
CL2
CLK
tSA
tHA
An
ADDRESS
tSAD tHAD
ADS
tSAD tHAD
CNTEN
tSCN tHCN
tCD2
Qn + 2(2)
Qn + 3
Qx - 1(2)
Qn + 1
Qn
Qx
DATAOUT
tDC
READ
EXTERNAL
ADDRESS
READ
WITH
COUNTER
COUNTER
HOLD
READ WITH COUNTER
3750 drw 14
Timing Waveform of Flow-Through Counter Read with
AddressCounterAdvance(1)
t
CYC1
t
CH1
tCL1
CLK
t
SA
tHA
An
ADDRESS
tSAD tHAD
tSAD
tHAD
ADS
tSCN
tHCN
CNTEN
t
CD1
Qn + 3(2)
Qx(2)
Qn + 4
Qn + 1
Qn + 2
Qn
DATAOUT
tDC
READ
WITH
READ
EXTERNAL
ADDRESS
READ WITH COUNTER
COUNTER
HOLD
COUNTER
3750 drw 15
NOTES:
1. CE0 and OE = VIL; CE1, R/W, and CNTRST = VIH.
2. If there is no address change via ADS = VIL (loading a new address) or CNTEN = VIL (advancing the address), i.e. ADS = VIH and CNTEN = VIH, then the data
output remains constant for subsequent clocks.
6.1452
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Address Counter Advance
(Flow-Through or Pipelined Outputs)(1)
t
CYC2
tCH2
tCL2
CLK
tSA
tHA
An
ADDRESS
INTERNAL(3)
ADDRESS
An + 4
An(7)
An + 2
An + 1
An + 3
tSAD tHAD
ADS
CNTEN
tSD tHD
Dn + 4
Dn + 1
Dn + 3
Dn
Dn + 1
Dn + 2
DATAIN
WRITE
EXTERNAL
ADDRESS
WRITE
WITH COUNTER
WRITE
COUNTER HOLD
WRITE WITH COUNTER
3750 drw 16
Timing Waveform of Counter Reset (Pipelined Outputs)(2)
t
CYC2
tCH2
tCL2
CLK
tSA tHA
(4)
An + 2
An
An + 1
ADDRESS
INTERNAL(3)
ADDRESS
Ax(6)
0
An + 1
1
An
tSW tHW
R/W
ADS
t
SAD
SCN
tHAD
CNTEN
t
tHCN
tSRST
tHRST
CNTRST
DATAIN
tSD
t
HD
D
0
(5)
Qn
Q1
Q0
DATAOUT
COUNTER(6)
RESET
WRITE
ADDRESS 0
READ
ADDRESS 0
READ
READ
READ
ADDRESS 1
ADDRESS n ADDRESS n+1
NOTES:
3750 drw 17
1. CE0 and R/W = VIL; CE1 and CNTRST = VIH.
CE0 = VIL; CE1 = VIH.
2.
3. The "Internal Address" is equal to the "External Address" when ADS = VIL and equals the counter output when ADS = VIH.
4. Addresses do not have to be accessed sequentially since ADS = VIL constantly loads the address on the rising edge of the CLK; numbers are for
reference use only.
5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. ADDR0 will be accessed. Extra cycles are shown here simply
forclarification.
7. CNTEN = VIL advances Internal Address from ‘An’ to ‘An +1’. The transition shown indicates the time required for the counter to advance.
The ‘An +1’ address is written to during this cycle.
16
6.42
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
FunctionalDescription
Depth and Width Expansion
The IDT70V9089/79 provides a true synchronous Dual-Port Static
The IDT70V9089/79 features dual chip enables (refer to Truth
RAMinterface.Registeredinputsprovideminimalset-upandholdtimes Table I) in order to facilitate rapid and simple depth expansion with
onaddress, data, andallcriticalcontrolinputs. Allinternalregistersare no requirements for external logic. Figure 4 illustrates how to control
clocked on the rising edge of the clock signal, however, the self-timed the various chip enables in order to expand two devices in depth.
internalwritepulseisindependentoftheLOWtoHIGHtransitionoftheclock
signal.
The IDT70V9089/79 can also be used in applications requiring
expandedwidth,asindicatedinFigure4.Sincethebanksareallocated
An asynchronous output enable is provided to ease asynchronous atthediscretionoftheuser,theexternalcontrollercanbesetuptodrive
bus interfacing. Counter enable inputs are also provided to stall the the input signals for the various devices as required to allow for 16-
operationofthecounterregistersforfastinterleavedmemoryapplications. bit or wider applications.
AHIGHonCE0oraLOWonCE1 foroneclockcyclewillpowerdown
the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70V9089/79's for depth
expansionconfigurations.WhenthePipelinedoutputmodeisenabled,two
cycles are required with CE0 LOW and CE1 HIGH to re-activate the
outputs.
(1)
A
16/A15
IDT70V9089/79
Control Inputs
IDT70V9089/79
Control Inputs
CE
0
1
CE
0
1
CE
CE
V
DD
V
DD
IDT70V9089/79
Control Inputs
IDT70V9089/79
Control Inputs
CE
1
0
CE
1
0
CE
CE
,
CNTRST
CLK
ADS
CNTEN
R/W
3750 drw 18
OE
Figure 4. Depth and Width Expansion with IDT70V9089/79
NOTE:
1. A16 is for IDT70V9089. A15 is for IDT70V9079.
6.1472
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
OrderingInformation
A
XXXXX
99
A
A
A
A
Device
Type
Power Speed
Package
Process/
Temperature
Range
Blank
8
Tube or Tray
Tape & Reel
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Blank
I
)
G(1
Green
PF
100-pin TQFP (PN100)
Commercial Only
Commercial Only
Commercial Only
Commercial & Industrial
Commercial Only
6
7
9
12
15
Speed in nanoseconds
Standard Power
Low Power
S
L
512K (64K x 8-Bit) Synchronous Dual-Port RAM
256K (32K x 8-Bit) Synchronous Dual-Port RAM
3750 drw 19
70V9089
70V9079
NOTE:
1. Green parts available. For specific speeds, packages and powers contact your sales office.
Ordering Information for Flow-through Devices
Old Flow-through Part
New Combined Part
70V908S/L25
70V9089S/L12
70V9089S/L15
70V908S/L30
3750 tbl 12
Old Flow-through Part
70V907S/L25
New Combined Part
70V9079S/L12
70V907S/L30
70V9079S/L15
3750 tbl 13
IDT Clock Solution for IDT70V9089/79 Dual-Port
Dual-Port I/O Specitications
Clock Specifications
Input Duty
IDT
PLL
Clock Device
IDT
IDT Dual-Port
Part Number
Non-PLL Clock
Input
Capacitance
Maximum
Jitter
Voltage
3.3
I/O
Cycle
Requirement
Device
Frequency Tolerance
49FCT3805
49FCT3805D/E
74FCT3807
2305
2308
2309
70V9089/79
LVTTL
9pF
40%
100
150ps
74FCT3807D/E
3750 tbl 14
18
6.42
IDT70V9089/79S/L
High Speed 3.3V 64/32K x 8 Synchronous Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Datasheet Document History
01/18/99:
Initiated datasheet document history
Convertedtonewformat
Cosmeticandtypographicalcorrections
Addedadditionalnotestopinconfigurations
AddedDepthandWidthExpansionsection.
Deleted note 6 for Table II
Page 14
Page 3
06/11/99:
11/12/99:
03/31/00:
Replaced IDT logo
CombinedPipelined70V9089familyandFlow-through70V908familyofferingsintoonedatasheet
Changed±200mVinwaveformnotesto0mV
Addedcorrespondingpartchartwithorderinginformation
Changed information in Truth Table II
Increasedstoragetemperatureparameters
ClarifiedTAparameter
DCElectricalparameters–changedwordingfrom"open"to"disabled"
RemovedPreliminaryStatus
01/10/01:
01/15/04:
Page 3
Page 4
Page 5
Consolidatedmultipledevicesintoonedatasheet
Changed naming conventions from VCC to VDD and from GND to Vss
RemovedI-tempfootnotefromtables
Page 2
Page 4
Addeddaterevisiontopinconfiguration
AddedJunctionTemperaturetoAbsoluteMaximumRatingsTable
AddedAmbientTemperaturefootnote
Page 5
Page 7
Page 16
AddedI-tempnumbersfor9nsspeedtotheDCElectricalCharacteristicsTable
Added 6ns & 7ns speeds DC power numbers to the DC Electrical Characteristics Table
Added I-temp for 9ns speed to AC Electrical Characteristics Table
Added6ns&7nsspeedsACtimingnumberstotheACElectricalCharacteristicsTable
Added 6ns & 7ns speeds grade and 9ns I-temp to ordering information
Added IDT Clock Solution Table
Pages 1 & 17
Pages 1 & 19
Page 5
Page 8
Page 1
Replaced ® IDT logo with TM new logo
05/11/04:
12/01/05:
Added7nsspeedgradetoorderinginformation
Added7nsspeedDCpowernumberstotheDCElectricalCharacteristicsTable
Added7nsspeedACtimingnumberstotheACElectricalCharacteristicsTable
Addedgreenpartsavailabilitytofeatures
Page 18
Page 18
Page 8
Addedgreenindicatortoorderinginformation
Removed "IDT" from orderable part number
InordertocorrecttheheadernotesoftheACElectCharsTableandalignthemwiththeIndustrialtemprange
values located in the table, the commercial TA header note has been removed
01/19/09:
07/26/10:
Pages 10-14
Page 1
Inordertocorrectthefootnotesoftimingdiagrams,CNTEN hasbeenremovedtoreconcilethefootnoteswith
the CNTEN logic definition found in Truth Table II - Address Counter Control
07/15/14:
Replaced Industrial 9ns with 12ns. Replaced Low Power Operation Standby from 600mW (typ) to
1.32mW (typ) in the Features
Page 2
Corrected some text typos
Page 5
Page 6
Pages 8 & 9
Removed the 9ns Industrial temp power values for the S & L offering in the DC Elec Chars table
Added the 12ns Industrial temp power value for the L offering in the DC Elec Chars table
Updated the column headings of the AC Elec Chars table to indicate the Commercial and Industrial
speed grade offerings
Page 18
Updated all the Commercial and Industrial speed grade offerings and added
Tape & Reel to Ordering Information
Page 2 & 18
Page 18
The label PN100-1 changed to PN100 to match the standard package code
Corrected Old Flow-through Part number in table 13 to 70V907S/L25 & L30
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.1492
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