7125620PZG8 [IDT]
CMOS Static RAM 256K (32K x 8-Bit);
| 型号： | 7125620PZG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | CMOS Static RAM 256K (32K x 8-Bit) |
| 文件： | 总8页 (文件大小：69K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS Static RAM
256K (32K x 8-Bit)
IDT71256SA
Features
Description
◆
32K x 8 advanced high-speed CMOS static RAM
Commercial (0° to 70°C) and Industrial (-40° to 85°C)
temperature options
The IDT71256SA is a 262,144-bit high-speed Static RAM
organized as 32K x 8. It is fabricated using high-performance, high-
reliability CMOS technology. This state-of-the-art technology, com-
bined with innovative circuit design techniques, provides a cost-
effective solution for high-speed memory needs.
The IDT71256SA has an output enable pin which operates as fast
as 6ns, with address access times as fast as 12ns. All bidirectional
inputs and outputs of the IDT71256SA are TTL-compatible and
operation is from a single 5V supply. Fully static asynchronous
circuitry is used, requiring no clocks or refresh for operation.
The IDT71256SA is packaged in 28-pin 300-mil Plastic DIP, 28-
pin 300 mil Plastic SOJ and TSOP.
◆
◆
Equal access and cycle times
–
–
Commercial: 12ns
Commercial and Industrial: 15/20/25ns
◆
◆
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
TTL-compatible
Low power consumption via chip deselect
Commercial product available in 28-pin 300-mil Plastic DIP,
300 mil Plastic SOJ and TSOP packages
Industrial product available in 28-pin 300 mil Plastic SOJ
◆
◆
◆
and TSOP packages
FunctionalBlockDiagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
262,144-BIT
MEMORY
ARRAY
ADDRESS
DECODER
A10
A11
A12
A13
A14
,
8
8
I/O0 - I/O
7
I/O CONTROL
2948 drw 01
CS
WE
OE
CONTROL
LOGIC
NOVEMBER2014
1
DSC-2948/11
©2014 Integrated Device Technology, Inc.
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
AbsoluteMaximumRatings(1)
PinConfigurations
Symbol
Rating
Value
Unit
V
CC
1
2
28
27
A
A
A
A
A
A
A
A
A
14
12
V
V
CC
Supply Voltage
-0.5 to +7.0
V
WE
Relative to GND
3
A13
7
6
5
4
3
2
1
0
0
1
2
26
25
24
TE RM
Terminal Voltage
Relative to GND
-0.5 to VCC+0.5
V
A8
4
5
A
9
A11
6
23
22
TBIAS
Temperature Under Bias
Storage Temperature
Power Dissipation
-55 to +125
-55 to +125
1.0
oC
oC
W
SO28
P28
OE
7
A10
8
21
20
TSTG
CS
9
P
T
I/O
I/O
I/O
I/O
I/O
7
10
11
12
13
14
A
19
18
6
5
4
3
I/O
I/O
I/O
IOUT
DC Output Current
50
mA
17
16
15
2948 tbl 02
NOTE:
GND
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2948 drw 02
DIP/SOJ
Top View
22
23
24
25
26
27
28
1
21
20
19
18
17
16
15
14
13
12
11
10
9
A
CS
10
OE
A11
Truth Table(1,2)
I/O
I/O
I/O
I/O
I/O
7
A9
6
5
4
3
A8
A13
Function
DATAOUT Read Data
I/O
CS
OE
WE
WE
VCC
SO28
L
L
H
A14
GND
2
A12
I/O
I/O
I/O
2
1
0
,
3
L
X
L
DATAIN
High-Z
High-Z
High-Z
Write Data
A
A
A
A
A
7
6
5
4
3
4
5
A0
A1
A2
L
H
X
H
Outputs Disabled
Deselected - Standby (ISB)
6
7
8
H
X
2948 drw 02a
(3)
HC
V
X
X
Deselected - Standby (ISB1)
2948 tbl 03
NOTES:
TSOP
1. H = VIH, L = VIL, x = Don't care.
2. VLC = 0.2V, VHC = VCC –0.2V.
3. Other inputs ≥VHC or ≤VLC.
Top View
RecommendedDCOperating
Conditions
RecommendedOperating
TemperatureandSupplyVoltage
Symbol
Parameter
Min. Typ.
Max.
5.5
0
Unit
V
Grade
Commercial
Industrial
Temperature
0OC to +70OC
-40OC to +85OC
GND
Vcc
V
CC
Supply Voltage
4.5
0
5.0
0V
4.5V ± 5.5V
4.5V ± 5.5V
GND
Ground
0
V
0V
____
V
IH
IL
Input High Voltage
Input Low Voltage
2.2
V
CC +0.5
0.8
V
2948 tbl 01
V
-0.5(1)
V
____
2948 tbl 04
NOTE:
1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.
2
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics
(VCC = 5.0V ± 10%)
IDT71256SA
Symbol
|ILI
|ILO
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Test Conditions
CC = Max., VIN = GND to VCC
CC = Max., CS = VIH, VOUT = GND to VCC
Min.
Max.
Unit
µA
µA
V
___
|
V
V
5
5
___
___
|
V
OL
OH
I
OL = 8mA, VCC = Min.
0.4
___
V
Output High Voltage
I
OH = -4mA, VCC = Min.
2.4
V
2948 tbl 05
DCElectricalCharacteristics(1)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC–0.2V)
Symbol
Parameter
71256SA12
71256SA15
71256SA20
71256SA25
Unit
ICC
Dynamic Operating Current
160
150
145
145
mA
(2)
CS < VIL, Outputs Open, VCC = Max., f = fMAX
I
SB
Standby Power Supply Current (TTL Level)
50
15
40
15
40
15
40
15
mA
mA
(2)
CS > VIH, Outputs Open, VCC = Max., f = fMAX
ISB1
Standby Power Supply Current (CMOS Level)
CS > VHC, Outputs Open, VCC = Max., f = 0(2),
VIN < VLC or VIN > VHC
2948 tbl 06
NOTES:
1. All values are maximum guaranteed values.
2. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
Capacitance
AC Test Conditions
Input Pulse Levels
(TA = +25°C, f = 1.0MHz, SOJ package)
GND to 3.0V
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max.
Unit
Input Rise/Fall Times
3ns
1.5V
C
IN
V
7
7
pF
Input Timing Reference Levels
Output Reference Levels
AC Test Load
1.5V
C
I/O
V
pF
2948 tbl 08
See Figures 1 and 2
NOTE:
2948 tbl 07
1. This parameter is guaranteed by device characterization, but not production
tested.
5V
5V
480Ω
480Ω
OUT
DATA
OUT
DATA
5pF*
255Ω
30pF*
255Ω
.
,
2948 drw 03
2948 drw 04
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
*Including jig and scope capacitance.
6.42
3
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics (VCC = 5.0V ± 10%)
71256SA12
71256SA15
71256SA20
Min. Max.
71256SA25
Min. Max.
Min. Max.
Min.
Max.
Symbol
Parameter
Unit
Read Cycle
____
____
____
____
t
RC
AA
ACS
Read Cycle Time
12
15
20
25
ns
ns
ns
ns
____
____
____
____
t
Address Access Time
12
15
20
25
____
____
____
____
t
Chip Select Access Time
12
15
20
25
____
____
____
____
(1)
CLZ
Chip Select to Output in Low-Z
Chip Select to Output in High-Z
Output Enable to Output Valid
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power Up Time
Chip Deselect to Power Down Time
4
4
4
4
t
(1)
0
6
0
7
0
10
0
11
ns
ns
ns
ns
ns
ns
ns
tCHZ
____
____
____
____
tOE
6
7
10
11
____
____
____
____
(1)
(1)
0
0
3
0
0
3
0
0
3
0
0
3
tOLZ
6
6
8
10
tOHZ
____
____
____
____
tOH
____
____
____
____
(1)
PU
0
0
0
0
t
(1)
PD
____
____
____
____
12
15
20
25
t
Write Cycle
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
AW
CW
AS
WP
WR
DW
DH
Write Cycle Time
12
9
15
10
10
0
20
15
15
0
25
20
20
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Address Valid to End-of-Write
Chip Select to End-of-Write
Address Set-up Time
Write Pulse Width
t
9
t
0
t
8
10
0
15
0
20
0
t
Write Recovery Time
Data Valid to End-of-Write
Data Hold Time
0
t
6
7
11
0
13
0
t
0
0
____
____
____
____
(1)
OW
Output Active from End-of-Write
4
4
4
4
t
(1)
WHZ
Write Enable to Output in High-Z
0
6
0
6
0
10
0
11
ns
t
2948 tbl 09
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
4
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1(1)
tRC
ADDRESS
tAA
OE
CS
tOE
(5)
tOLZ
(5)
(3)
tOHZ
tACS
(5)
(5)
t
CLZ
t
CHZ
HIGH IMPEDANCE
DATAOUT
DATA OUT VALID
t
PD
tPU
I
CC
SB
V
CC SUPPLY
CURRENT
I
2948 drw 05
,
Timing Waveform of Read Cycle No. 2(1,2,4)
tRC
ADDRESS
tAA
tOH
tOH
DATAOUT VALID
DATAOUT
PREVIOUS DATAOUT VALID
2948 drw 06
,
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
6.42
5
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
tWC
ADDRESS
tAW
CS
(2)
tWR
t
AS
tWP
WE
(5)
CHZ
(5)
WHZ
t
t
(5)
OW
t
HIGH IMPEDANCE
(3)
(3)
DATAOUT
DATAIN
tDH
tDW
DATAIN VALID
2948 drw 07
,
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4)
tWC
ADDRESS
tAW
CS
tWR
tCW
t
AS
WE
tDW
tDH
DATAIN
DATAIN VALID
2948 drw 08
,
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as
short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
6
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
OrderingInformation
X
71256
SA
XX
XXX
X
X
Device Power Speed Package
Type
Process/
Temperature
Range
Tube or Tray
Tape and Reel
Blank
8
Blank
I
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G
Green
TP
Y
PZ
300-mil Plastic DIP (P28)
300-mil SOJ (SO28)
TSOP Type I (SO28)
12(1)
15
Speed in nanoseconds
20
25
2948 drw 09
NOTE:
1. Availablein commercialtemperaturerangeonly.
6.42
7
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit)
Commercial and Industrial Temperature Ranges
DatasheetDocumentHistory
1/7/00
Updated to new format
Revised Industrial Temperature range offerings
RemovedNoteNo.1forWriteCyclediagrams,renumberedfootnotesandnotes
AddedDatasheetDocumentHistory
Pg. 1, 3, 4, 7
Pg. 6
Pg. 8
08/09/00
02/01/01
09/30/04
02/20/07
Notrecommendedfornewdesigns
Removed"Notrecommendedfornewdesigns"
Pg. 7
Pg. 7
Added"Restrictedhazardoussubstancedevice"toorderinginformations.
AddedTTgenerationdiesteptodatasheetorderinginformation.
Obsoleted 28-pin 600 mil and removed TT generation die step from Ordering information.
Added Tape and Reel to Ordering information and updated description of Restricted
hazardous substance device to Green
04/28/11 Pg. 1, 2, 7
11/03/14
Pg. 1 & 8
Pg. 2 & 8
Removed 12ns I-temp offering in Features. Added note regarding 12ns commercial only on
the Ordering information page. Removed IDT as a reference for fabrication in Description.
Removed package extensions from pinouts and from Ordering information.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
sramhelp@idt.com
408-284-4532
800-345-7015 or
408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
8
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