7133LA35GI [IDT]
Dual-Port SRAM, 2KX16, 35ns, CMOS, CPGA68, 1.180 X 1.180 INCH, 0.160 INCH HEIGHT, CERAMIC, PGA-68;
| 型号： | 7133LA35GI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 2KX16, 35ns, CMOS, CPGA68, 1.180 X 1.180 INCH, 0.160 INCH HEIGHT, CERAMIC, PGA-68 静态存储器 |
| 文件： | 总16页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT7133SA/LA
IDT7143SA/LA
HIGH SPEED
2K X 16 DUAL-PORT
SRAM
Features
◆
◆
High-speed access
BUSY output flag on IDT7133; BUSY input on IDT7143
Fully asynchronous operation from either port
◆
◆
◆
◆
–
–
–
Military:25/35/45/55/70/90ns(max.)
Industrial:25/35/55ns(max.)
Commercial:20/25/35/45/55/70/90ns(max.)
Battery backup operation–2V data retention
TTL-compatible; single 5V (±10%) power supply
Available in 68-pin ceramic PGA, Flatpack, PLCC and 100-
pin TQFP
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available
for selected speeds
◆
Low-power operation
–
IDT7133/43SA
◆
◆
Active:1150mW(typ.)
Standby: 5mW (typ.)
IDT7133/43LA
–
◆
Green parts available, see ordering information
Active:1050mW(typ.)
Standby: 1mW (typ.)
◆
◆
◆
Description
Versatile control for write: separate write control for lower
and upper byte of each port
MASTER IDT7133 easily expands data bus width to 32 bits
or more using SLAVE IDT7143
The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static RAMs.
The IDT7133is designedtobe usedas a stand-alone 16-bitDual-Port
On-chip port arbitration logic (IDT7133 only)
Functional Block Diagram
R/WRUB
R/WLUB
CER
CE
L
R/WLLB
R/WRLB
OE
R
OE
L
I/O8L - I/O15L
I/O0L - I/O7L
(1)
I/O8R - I/O15R
I/O
CONTROL
I/O
CONTROL
I/O0R - I/O7R
(1)
R
BUSY
BUSY
L
A
10R
A
10L
MEMORY
ARRAY
ADDRESS
DECODER
ADDRESS
DECODER
A
0L
A
0R
11
11
ARBITRATION
LOGIC
CE
R
CE
L
(IDT7133 ONLY)
2746 drw 01
NOTE:
1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor.
IDT7143 (SLAVE): BUSY is input.
OCTOBER 2008
1
DSC 2746/13
©2008IntegratedDeviceTechnology,Inc.
IDT7133SA/LA,IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
RAM or as a “MASTER” Dual-Port RAM together with the IDT7143 port to enter a very low standby power mode.
“SLAVE”Dual-Portin32-bit-or-morewordwidthsystems.UsingtheIDT
FabricatedusingIDT’s CMOShigh-performance technology, these
MASTER/SLAVEDual-PortRAMapproachin32-bit-or-widermemory devices typically operate on only 1,150mW of power. Low-power (LA)
systemapplicationsresultsinfull-speed,error-freeoperationwithoutthe versions offer battery backup data retention capability, with each port
needforadditionaldiscretelogic.
typicallyconsuming200µWfora2Vbattery.
Both devices provide two independent ports with separate control,
The IDT7133/7143 devices have identical pinouts. Each is packed
address, and I/O pins that permit independent, asynchronous access in a 68-pin ceramic PGA, 68-pin flatpack, 68-pin PLCC and 100-pin
for reads or writes to any location in memory. An automatic power TQFP. Military grade product is manufactured in compliance with the
down feature, controlled by CE, permits the on-chip circuitry of each latest revision of MIL-PRF-38535 QML, making it ideally suited to
military temperature applications demanding the highest level of
performance and reliability.
Pin Configurations(1,2,3)
INDEX
9
8
7
6
5
4
3
2
68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
I/O9L
I/O10L
I/O11L
I/O12L
I/O13L
I/O14L
I/O15L
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
A
A
A
A
A
A
A
6L
5L
4L
3L
2L
1L
0L
1
IDT7133/43
J68-1 / F68-1(4)
V
CC(1)
BUSY
CE
CE
BUSY
L
(2)
GND
I/O0R
I/O1R
I/O2R
I/O3R
I/O4R
I/O5R
I/O6R
I/O7R
L
68-Pin PLCC/Flatpack
(5)
R
Top View
R
A0R
A1R
A2R
A3R
A4R
A5R
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
,
2746 drw 02
Index
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
N/C
N/C
N/C
1
N/C
N/C
N/C
N/C
75
2
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
3
N/C
4
A
A
A
A
A
A
5L
4L
3L
2L
1L
0L
I/O10L
I/O11L
I/O12L
I/O13L
GND
5
6
7
8
9
IDT7133/43PF
PN100-1
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
I/O14L
I/O15L
(4)
N/C
BUSY
GND
L
VCC
100-Pin TQFP
GND
I/O0R
I/O1R
I/O2R
(5)
Top View
N/C
BUSY
N/C
R
A
A
A
A
A
0R
1R
2R
3R
4R
VCC
I/O3R
I/O4R
I/O5R
I/O6R
N/C
N/C
N/C
N/C
NOTES:
1. Both VCC pins must be connected to the power supply to ensure reliable
operation.
2. Both GND pins must be connected to the ground supply to ensure reliable
operation.
N/C
N/C
N/C
N/C
3. J68-Package body is approximately 0.95 in x 0.95 in x 0.17 in.
F68-Package body is approximately 1.18 in x 1.18 in x 0.16 in.
PN100-Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
,
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
2746 drw 03
6.42
2
IDT7133SA/LA,IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
51
50
48
46
44
42
40
38
36
11
10
09
08
07
06
05
04
03
02
01
BUSY
L
CER
A
6L
A
5L
A
3L
A
1L
A
0R
A
2R
A4R
53
55
52
54
56
49
47
45
43
41
39
37
35
32
34
33
31
29
CEL
BUSYR
A
7L
A
2L
A
0L
A
1R
A
3R
A5R
A6R
A
8L
A4L
A
10L
A
9L
A
8R
A7R
57
30
OE
L
R/WLLB
A
10R
A9R
59
(1)
58
28
V
CC
R/WLUB
OE
R
R/WRLB
IDT7133/43G
GU68-1(4)
61
60
26
27
GND(2)
I/O1L
I/O0L
R/WRUB
68-Pin PGA
Top View(5)
63
I/O3L
62
24
25
I/O2L
I/O14R
I/O15R
65
I/O5L
64
22
23
I/O4L
I/O13R
I/O12R
67
I/O7L
68
I/O8L
66
20
21
I/O6L
I/O10R I/O11R
18 19
I/O8R I/O9R
17
1
3
5
7
9
11
13
I/O3R
14
15
I/O5R
16
)
I/O9L
I/O11L
I/O13L
I/O15L GND(2 I/O1R
2
4
6
8
10
I/O0R
12
I/O2R
(1)
VCC
I/O7R
I/O10L
I/O12L
I/O14L
I/O4R
I/O6R
Pin 1
Designator
A
B
C
D
E
F
G
H
J
K
L
2746 drw 04
NOTES:
1. Both VCC pins must be connected to the power supply to ensure reliable operation.
2. Both GND pins must be connected to the ground supply to ensure reliable operation.
3. Package body is approximately 1.18 in x 1.18 in x 0.16 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Names
Left Port
Right Port
Names
Chip Enable
CEL
CER
R/WLUB
R/WLLB
R/WRUB
R/WRLB
Upper Byte Read/Write Enable
Lower Byte Read/Write Enable
Output Enable
OEL
OER
A
0L - A10L
A
0R - A10R
I/O0R - I/O15R
BUSY
Address
I/O0L - I/O15L
Data Input/Output
Busy Flag
BUSY
L
R
VCC
Power
GND
Ground
2746 tbl 01
3
6.42
IDT7133SA/LA,IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Maximum Operating
Temperature and Supply Voltage(1,2)
Symbol
Rating
Commercial
& Industrial
Military
Unit
Grade
Ambient
Temperature
GND
Vcc
(2)
V
TERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
-0.5 to +7.0
V
Military
-55OC to +125OC
0OC to +70OC
0V
0V
0V
5.0V
+
+
+
10%
Temperature
Under Bias
-55 to +125
-65 to +150
2.0
-65 to +135
-65 to +150
2.0
oC
oC
W
Commercial
Industrial
5.0V
5.0V
10%
T
BIAS
-40OC to +85OC
10%
Storage
Temperature
TSTG
2746 tbl 04
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
(3)
P
T
Power
Dissipation
DC Output
Current
50
50
mA
IOUT
2746 tbl 02
NOTES:
Recommended DC Operating
Conditions
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Symbol
Parameter
Supply Voltage
GND Ground
Min.
Typ. Max. Unit
VCC
4.5
5.0
5.5
0
V
V
V
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
0
0
____
V
IH
Input High Voltage
Input Low Voltage
2.2
6.0(2)
0.8
____
VIL
-0.5(1)
V
2746 tbl 05
NOTES:
Capacitance (TA = +25°C, f = 1.0mhz)
1. VIL (min.) = -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
Symbol
Parameter(1)
Input Capacitance
Output Capacitance
Conditions(2)
Max. Unit
C
IN
VIN = 3dV
11
11
pF
COUT
VOUT = 3dV
pF
2746 tbl 03
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dVreferences the interpolatedcapacitance whenthe inputandoutputswitchfrom
0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (Either port, VCC = 5.0V ± 10%)
7133SA
7143SA
7133LA
7143LA
Symbol
|ILI
|ILO
Parameter
Test Conditions
Min.
Max.
Min.
Max.
Unit
µA
µA
V
(1)
___
___
|
Input Leakage Current
V
CC = 5.5V, VIN = 0V to VCC
10
10
5
5
___
___
___
___
___
___
|
Output Leakage Current
Output Low Voltage (I/O
CE = VIH, VOUT = 0V to VCC
VOL
0-I/O15
)
IOL = 4mA
0.4
0.5
0.4
0.5
Open Drain Output Low Voltage
IOL = 16mA
V
VOL
(BUSY)
___
___
VOH
Output High Voltage
IOH = -4mA
2.4
2.4
V
2746 tbl 06
NOTE:
1. At Vcc < 2.0V, input leakages are undefined.
6.42
4
IDT7133SA/LA,IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Operating
Temperature and Supply Voltage Range(2) (VCC = 5.0V ± 10%)
7133X20
7143X20
7133X25
7143X25
7133X35
7143X35
Com'l, Ind
& Military
Com'l Only
Com'l, Ind
& Military
Symbol
Parameter
Test Condition
CE = VIL, Outputs Disabled
Version
COM'L
Typ.(1) Max.
Typ.(1) Max.
Typ.(1) Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
S
L
250
230
310
280
250
230
300
270
240
210
295
250
mA
(3)
f = fMAX
____
____
____
____
MIL &
IND
S
L
250
230
330
300
240
220
325
295
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
S
L
25
25
80
70
25
25
80
70
25
25
70
60
mA
mA
mA
mA
CE
L
and CE
R
= VIH
(3)
f = fMAX
____
____
____
____
MIL &
IND
S
L
25
25
90
80
25
25
75
65
(4)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
S
L
140
120
200
180
140
100
200
170
120
100
180
160
CE"A" = VIL and CE"B" = VIH
(3)
f=fMAX
Active Port Outputs Disabled
____
____
____
____
MIL &
IND
S
L
140
100
230
190
120
100
200
180
ISB3
Full Standby Current
Both Ports CE
CE > VCC - 0.2V
IN > VCC - 0.2V or
IN < 0.2V, f = 0(4)
L
and
COM'L
S
L
1.0
0.2
15
5
1.0
0.2
15
4
1.0
0.2
15
4
(Both Ports
-
R
CMOS Level Inputs)
V
V
____
____
____
____
MIL &
IND
S
L
1.0
0.2
30
10
1.0
0.2
30
10
ISB4
Full Standby Current
(One Port -
CMOS Level Inputs)
COM'L
S
L
140
120
190
170
140
120
190
170
120
100
170
150
CE"A" < 0.2V and
(5)
CE"B" > VCC - 0.2V
V
IN > VCC - 0.2V or VIN < 0.2V
____
____
____
____
MIL &
IND
S
L
140
120
220
200
120
100
190
170
Active Port Outputs Disabled
(3)
f = fMAX
2746 tbl 07a
7133X45
7133X55
7133X70/90
7143X70/90
Com'l &
7143X45
Com'l &
Military
7143X55
Com'l, Ind
& Military
Military
Symbol
Parameter
Test Condition
Version
Typ.(1) Max.
Typ.(1) Max.
Typ.(1) Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
COM'L
S
L
230
210
290
250
230
210
285
250
230
210
280
250
mA
CE = VIL, Outputs Disabled
(3)
f = fMAX
MIL &
IND
S
L
230
210
320
290
230
210
315
285
230
210
310
280
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
S
L
25
25
75
65
25
25
70
60
25
25
70
60
mA
mA
mA
mA
CE
L and CER = VIH
(3)
f = fMAX
MIL &
IND
S
L
25
25
80
70
25
25
80
70
25
25
75
65
(4)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
S
L
120
100
190
170
120
100
180
160
120
100
180
160
CE"A" = VIL and CE"B" = VIH
(3)
f=fMAX
Active Port Outputs Disabled
MIL &
IND
S
L
120
100
210
190
120
100
210
190
120
100
200
180
ISB3
Full Standby Current
Both Ports CE
CE > VCC - 0.2V
IN > VCC - 0.2V or
IN < 0.2V, f = 0(4)
L and
COM'L
S
L
1.0
0.2
15
4
1.0
0.2
15
4
1.0
0.2
15
4
(Both Ports
-
R
CMOS Level Inputs)
V
V
MIL &
IND
S
L
1.0
0.2
30
10
1.0
0.2
30
10
1.0
0.2
30
10
ISB4
Full Standby Current
(One Port -
CMOS Level Inputs)
COM'L
S
L
120
100
180
160
120
100
170
150
120
100
170
150
CE"A" < 0.2V and
(5)
CE"B" > VCC - 0.2V
VIN > VCC - 0.2V or VIN < 0.2V
MIL &
IND
S
L
120
100
200
180
120
100
200
180
120
100
190
170
Active Port Outputs Disabled
f = fMAX
(3)
2746 tbl 07b
NOTES:
1. VCC = 5V, TA = +25°C for Typ., and are not production tested. ICCDC = 180mA (typ.)
2. 'X' in part number indicates power rating (SA or LA)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using “AC Test Conditions" of input levels of
GND to 3V.
4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
5
6.42
IDT7133SA/LA,IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
Data Retention Characteristics
(LA Version Only) VLC = 0.2V, VHC = VCC - 0.2V
7133LA/7143LA
Symbol
Parameter
CC for Data Retention
Test Condition
Min.
2.0
___
Typ.(1)
Max.
Unit
V
___
___
VDR
V
V
CC = 2V
CE > VHC
IN > VHC or < VLC
I
CCDR
Data Retention Current
µA
MIL. & IND.
100
4000
___
V
COM'L.
100
1500
(3)
CDR
___
___
t
Chip Deselect to Data Retention Time
Operation Recovery Time
0
V
(3)
(2)
___
___
t
R
t
RC
V
2746 tbl 08
NOTES:
1. Vcc = 2V, TA = +25°C, and are not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed by device characterization but is not production tested.
Data Retention Waveform
DATA RETENTION MODE
DR > 2V
VCC
4.5V
V
4.5V
tCDR
tR
VDR
CE
VIH
VIH
2746 drw 05
AC Test Conditions
Input Pulse Levels
5V
GND to 3.0V
1250Ω
Input Rise/Fall Times
5ns Max.
1.5V
Input Timing Reference Levels
Output Reference Levels
Output Load
DATAOUT
1.5V
775Ω
30pF
Figures 1, 2 and 3
2746 tbl 09
Figure 1. AC Output Test Load
5V
5V
270Ω
1250Ω
BUSY
DATAOUT
775Ω
30pF
5pF*
2746 drw 06
Figure 2. Output Load
Figure 3. BUSY Output Load
(for tLZ, tHZ, tWZ, tOW)
(IDT7133 only)
*Including scope and jig
6.42
6
IDT7133SA/LA,IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(3)
7133X20
7143X20
7133X25
7143X25
Com'l, Ind
& Military
7133X35
7143X35
Com'l, Ind
& Military
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
Read Cycle Time
20
25
35
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
t
Address Access Time
20
20
25
25
35
35
____
____
____
____
____
____
t
Chip Enable Access Time
t
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
12
15
20
____
____
____
t
0
0
0
____
____
____
t
0
0
0
Output High-Z Time(1,2)
12
15
20
____
____
____
t
t
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
0
0
0
____
____
____
____
____
____
t
20
50
50
ns
2746 tbl 10a
7133X45
7133X55
7143X55
Com'l, Ind
& Military
7133X70/90
7143X45
Com'l &
Military
7143X70/90
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
tRC
tAA
tACE
tAOE
tOH
tLZ
Read Cycle Time
45
55
70/90
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
Address Access Time
45
45
55
55
70/90
70/90
____
____
____
____
____
____
Chip Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,2)
25
30
40/40
____
____
____
0
0
0/0
____
____
____
0
5
5/5
Output High-Z Time(1,2)
20
20
25/25
____
____
____
tHZ
tPU
tPD
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
0
0
0/0
____
____
____
____
____
____
50
50
50/50
ns
2746 tbl 10b
NOTES:
1. Transition is measured 0mV fromLow or High-impedance voltage with load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. 'X' in part number indicates power rating (SA or LA).
7
6.42
IDT7133SA/LA,IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE(5)
tRC
ADDRESS
t
AA
tOH
tOH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
BUSYOUT
(3,4)
2746 drw 07
tBDD
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE(5)
(4)
tACE
CE
OE
(4)
(2)
tAOE
tHZ
(1)
(2)
tLZ
tHZ
DATAOUT
VALID DATA
(1)
tLZ
tPU
tPD
ICC
CURRENT
50%
50%
ISB
2746 drw 08
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is deasserted first, OE or CE.
3. tBDD delay is required only in a case where the opposite port is completing a write operation to the same address location. For simultaneous read operations, BUSY has no
relationship to valid output data.
4. Start of valid data depends on which timing becomes effective last, tAOE, tACE, tAA, or tBDD.
5. R/W = VIH, and the address is valid prior to or coincidental with CE transition LOW.
6.42
8
IDT7133SA/LA,IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(5)
7133X20
7143X20
7133X25
7143X25
7133X35
7143X35
Com'l Only
Com'l, Ind
& Military
Com'l, Ind
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
Write Cycle Time(3)
20
15
15
0
25
20
20
0
35
25
25
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
t
t
t
15
0
20
0
25
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
t
15
15
20
____
____
____
t
12
15
20
____
____
____
t
0
0
0
(1,2)
____
____
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1, 2,4)
12
15
20
____
____
____
t
0
0
0
ns
2746 tbl 11a
7133X45
7133X55
7133X70/90
7143X45
Com'l &
Military
7143X55
Com'l, Ind
& Military
7143X70/90
Com'l &
Military
Symbol
WRITE CYCLE
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
Write Cycle Time(3)
45
30
30
0
55
40
40
0
70/90
50/50
50/50
0/0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
t
t
t
30
0
40
0
50/50
0/0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(4)
t
20
25
30/30
____
____
____
t
20
20
25/25
____
____
____
t
5
5
5/5
(1,2)
____
____
____
t
Write Enable to Output in High-Z
20
20
25/25
____
____
____
t
Output Active from End-of-Write(1, 2,4)
5
5
5/5
ns
2746 tbl 11b
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage from the Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization but not production tested.
3. For MASTER/SLAVE combination, tWC = tBAA + tWR + tWP, since R/W = VIL must occur after tBAA.
4. The specification for tDH must be met by the device supplying write data to the RAM under all operation conditions. Although tDH and tOW values will very over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
5. 'X' in part number indicates power rating (SA or LA).
9
6.42
IDT7133SA/LA,IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(6)
7133X20
7133X25
7143X25
Com'l, Ind
& Military
7133X35
7143X35
Com'l, Ind
& Military
7143X20
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (For MASTER 71V33)
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
WDD
DDD
BDD
APS
WH
20
20
20
17
40
30
20
20
20
20
50
35
30
30
25
25
60
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address
BUSY Disable Time from Address
t
t
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
t
(1)
t
Write Pulse to Data Delay
t
Write Data Valid to Read Data Delay(1)
BUSY Disable to Valid Data(2)
Arbitration Priority Set-up Time(3)
Write Hold After BUSY(5)
t
25
30
35
____
____
____
t
5
5
5
____
____
____
t
20
20
25
BUSY INPUT TIMING (For SLAVE 71V43)
____
____
____
____
____
____
BUSY Input to Write(4)
t
WB
WH
WDD
DDD
0
0
0
ns
ns
ns
t
Write Hold After BUSY(5)
20
20
25
(1)
____
____
____
t
Write Pulse to Data Delay
40
30
50
35
60
45
Write Data Valid to Read Data Delay(1)
ns
____
____
____
t
2746 tbl 12a
7133X45
7133X55
7143X55
Com'l, Ind
& Military
7133X70/90
7143X45
Com'l &
Military
7143X70/90
Com'l &
Military
Symbol
BUSY TIMING (For MASTER 71V33)
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
WDD
DDD
BDD
APS
WH
40
40
30
25
80
55
40
40
35
30
80
55
45/45
45/45
35/35
30/30
90/90
70/70
ns
ns
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address
BUSY Disable Time from Address
t
t
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
t
(1)
t
Write Pulse to Data Delay
t
Write Data Valid to Read Data Delay(1)
BUSY Disable to Valid Data(2)
Arbitration Priority Set-up Time(3)
Write Hold After BUSY(5)
t
40
40
40/40
____
____
____
t
5
5
5/5
____
____
____
t
30
30
30/30
BUSY INPUT TIMING (For SLAVE 71V43)
____
____
____
____
____
____
BUSY Input to Write(4)
Write Hold After BUSY(5)
t
WB
WH
WDD
DDD
0
0
0/0
ns
ns
ns
t
30
30
30/30
(1)
____
____
____
t
Write Pulse to Data Delay
80
55
80
55
90/90
70/70
Write Data Valid to Read Data Delay(1)
ns
____
____
____
t
2746 tbl 12b
NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write with Port-to-Port Read and Busy".
2. tBDD is calculated parameter and is greater of 0, tWDD - tWP (actual) or tDDD - tDW (actual).
3. To ensure that the earlier of the two ports wins.
4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part number indicates power rating (SA or LA).
6.42
10
IDT7133SA/LA,IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (R/W Controlled Timing)(1,5,8)
tWC
ADDRESS
OE
(6)
tAS
(3)
tWR
tAW
CE
(7)
(2)
tHZ
tWP
R/W(9)
(7)
(7)
t
WZ
tHZ
tLZ
tOW
(4)
(4)
DATAOUT
DATAIN
t
DH
tDW
2746 drw 09
Write Cycle No. 2 (CE Controlled Timing)(1,5)
tWC
ADDRESS
tAW
CE
(6)
(2)
tAS
t
EW
tWR
R/W(9)
tDW
tDH
DATAIN
2746 drw 10
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the I/O pins are in the output state, and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. Timing depends on which enable signal is de-asserted first, CE or OE.
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed
on the bus for the required tDW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the
specified tWP.
9. R/W for either upper or lower byte.
11
6.42
IDT7133SA/LA,IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY(1,2,3)
t
WC
MATCH
ADDR"A"
R/W"A"
tWP
tDW
tDH
VALID
DATAIN"A"
(1)
APS
t
MATCH
ADDR"B"
tBDA
tBDD
BUSY"B"
tWDD
DATAOUT "B"
VALID
(4)
DDD
t
2746 drw 11
NOTES:
1. To ensure that the earlier of the two ports wins, tAPS is ignored for Slave (IDT7143).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
Timing Waveform of Write with BUSY(3)
tWP
R/W"A"
tWB
BUSY"B"
(1)
tWH
R/W"B"
(2)
,
2746 drw 12
NOTES:
1. tWH must be met for both BUSY input (IDT7143, slave) and output (IDT7133, master).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6.42
12
IDT7133SA/LA,IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
ADDR"A" AND "B"
ADDRESSES MATCH
CE"A"
(2)
APS
t
CE"B"
t
BAC
tBDC
BUSY"B"
2746 drw 13
Timing Waveform of BUSY Arbitration Controlled by Addresses(1)
tRC
tWC
OR
ADDR "A"
ADDR "B"
BUSY "B"
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
(2)
tAPS
tBAA
tBDA
2746 drw 14
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
2. If tAPS is not satisfied, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted
(IDT7133 only).
13
6.42
IDT7133SA/LA,IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
Functional Description
The IDT7133/43 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT7133/43 has an automatic power down
featurecontrolledbyCE.TheCEcontrolson-chippowerdowncircuitry
that permits the respective port to go into a standby mode when not
selected (CE HIGH). When a port is enabled, access to the entire
memory array is permitted. Non-contention READ/WRITE conditions
are illustrated in Truth Table 1.
LEFT
RIGHT
R/W
R/W
R/W
R/W
IDT7133
MASTER
,
BUSY
BUSY
BUSY
BUSY
270Ω
270Ω
V
CC
VCC
R/W
R/W
IDT7143
SLAVE
Busy Logic
Busy Logic provides a hardware indication that both ports of the
RAMhaveaccessedthesamelocationatthesametime. Italsoallows
one of the two accesses to proceed and signals the other side that the
RAMis “busy”. The BUSY pincanthenbe usedtostallthe access until
the operation on the other side is completed. If a write operation has
been attempted from the side that receives a BUSY indication, the
write signal is gated internally to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applica-
2746 drw 15
BUSY
BUSY
Figure 4. Busy and chip enable routing for both width and depth expansion
with the IDT7133 (MASTER) and the IDT7143 (SLAVE).
Expanding the data bus width to 32 bits or more in a Dual-Port RAM
tions. Insome cases itmaybe usefultologicallyORthe BUSY outputs systemimpliesthatseveralchipswillbeactiveatthesametime.Ifeach
togetheranduseanyBUSYindicationasaninterruptsourcetoflagthe chip includes a hardware arbitrator, and the addresses for each chip
event of an illegal or illogical operation. If the write inhibit function of arrive at the same time, it is possible that one will activate its BUSYL
BUSY logic is not desirable, the BUSY logic can be disabled by using while another activates its BUSYR signal. Both sides are now BUSY
the IDT7143 (SLAVE). In the IDT7143, the BUSY pin operates solely and the CPUs will await indefinitely for their port to become free.
as a write inhibit input pin. Normal operation can be programmed by
To avoid the “Busy Lock-Out” problem, IDT has developed a
tyingtheBUSY pins HIGH. Ifdesired, unintendedwrite operations can MASTER/SLAVEapproachwhereonlyonehardwarearbitrator,inthe
be prevented to a port by tying the BUSY pin for that port LOW. The MASTER, is used. The SLAVE has BUSY inputs which allow an
BUSY outputs on the IDT 7133 RAM are open drain and require pull- interface to the MASTER with no external components and with a
up resistors.
speed advantage over other systems.
WhenexpandingDual-PortRAMs inwidth,thewritingoftheSLAVE
RAMs must be delayed until after the BUSY input has settled.
Otherwise,theSLAVEchipmaybeginawritecycleduringacontention
situation. Conversely, the write pulse must extend a hold time past
BUSY to ensure that a write cycle takes place after the contention is
resolved.ThistimingisinherentinallDual-Portmemorysystemswhere
morethanonechipisactiveatthesametime.
The write pulse to the SLAVE should be delayed by the maximum
arbitration time of the MASTER. If, then, a contention occurs, the write
totheSLAVEwillbeinhibitedduetoBUSYfromtheMASTER.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an IDT7133/43 RAM array in width while using
BUSY logic, one master part is used to decide which side of the RAM
array will receive a BUSY indication, and to output that indication. Any
number of slaves to be addressed in the same address range as the
master, use the BUSY signal as a write inhibit signal. Thus on the
IDT7133RAMtheBUSYpinisanoutputandontheIDT7143RAM,the
BUSY pin is an input (see Figure 3).
6.42
14
IDT7133SA/LA,IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
Truth Table I – Non-Contention Read/Write Control(4)
(1)
LEFT OR RIGHT PORT
R/WLB
R/WUB
I/O0-7
Z
I/O8-15
Z
Function
CE
H
H
L
OE
X
X
X
L
X
X
L
L
X
X
L
Port Disabled and in Power Down Mode, ISB2, ISB4
Z
Z
CER = CEL = VIH, Power Down Mode, ISB1 or ISB3
DATAIN
DATAIN
DATAIN
DATAOUT
Data on Lower Byte and Upper Byte Written into Memory (2)
H
L
Data on Lower Byte Written into Memory(2), Data in Memory Output on
Upper Byte(3)
H
L
L
L
Data in Memory Output on Lower Byte(3), Data on Upper Byte Written into
Memory(2)
DATAOUT
DATAIN
L
H
H
H
H
L
L
L
L
L
H
H
L
DATAIN
Z
Data on Lower Byte Written into Memory(2)
Z
DATAOUT
Z
DATAIN
DATAOUT
Z
Data on Upper Byte Written into Memory (2)
Data in Memory Output on Lower Byte and Upper Byte
H
H
H
High Impedance Outputs
2746 tbl 13
NOTES:
1. A0L - A10L≠A0R - A10R
2. If BUSY = LOW, data is not written.
3. If BUSY = LOW, data may not be valid, see tWDD and tDDD timing.
4. "H" = HIGH, "L" = LOW, "X" = Don’t Care, "Z" = High-Impedance, "LB" = Lower Byte, "UB" = Upper Byte
Truth Table II — Address BUSY
Arbitration
Inputs
Outputs
A
0L-A10L
(1)
(1)
A
0R-A10R
Function
Normal
Normal
Normal
CE
L
CE
R
BUSY
L
BUSYR
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
H
H
MATCH
H
MATCH
(2)
(2)
Write Inhibit(3)
2746 tbl 14
NOTES:
1. Pins BUSYL and BUSYR are both outputs on the IDT7133 (MASTER). Both are
inputs on the IDT7143 (SLAVE). On Slaves the BUSY input internally inhibits
writes.
2. "L" if the inputs to the opposite port were stable prior to the address and enable
inputs of this port. “H” if the inputs to the opposite port became stable after the
address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR
= VIL will result BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of actual logic level on
the pin.
15
6.42
IDT7133SA/LA,IDT7143SA/LA
High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
Ordering Information
XXXX
XX
XX
X
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
Blank
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Military (-55°C to +125°C)
I
B
Compliant to MIL-PRF-38535 QML
68-pin PLCC (J68-1)
J
68-pin PGA (GU68-1)
68-pin Flatplack (F68-1)
100-pin TQFP (PN100-1)
G
F
PF
Commercial Only
20
25
35
45
55
70
90
Commercial, Industrial & Military
Commercial, Industrial & Military
Commercial & Military
,
Speed in nanoseconds
Commercial, Industrial & Military
Commercial & Military
Commercial & Military
LA
SA
Low Power
Standard Power
7133 32K (2K x 16-Bit) MASTER Dual-Port RAM
7143 32K (2K x 16-Bit) SLAVE Dual-Port RAM
2746 drw 16
NOTES:
1. Contact your local sales office for industrial temp. range for other speeds, packages and powers.
2. Green parts available. For specific speeds, packages and powers contact your local sales office.
DatasheetDocumentHistory
12/18/98:
Initiateddatasheetdocumenthistory
Convertedtonewformat
Cosmeticandtypographicalcorrections
Addedadditionalnotestopinconfigurations
correctedPN100pinout
Page 2
02/17/99:
030/9/99:
06/09/99:
10/01/99:
11/10/99:
04/01/00:
Corrected PF ordering code
Cosmeticandtypographicalcorrections
Changeddrawingformat
AddedIndustrialTemperatureRanges andremovedcorrespondingnotes
Replaced IDT logo
Changed±500mVto0mVinnotes
Fixed overbar in pinout
Page 2
Page 4
06/26/00:
Increasedstoragetemperatureparameters
ClarifiedTAparameter
Page 5
Page 1
Page 16
Page 16
DCElectricalparameters–changedwordingfrom"open"to"disabled"
Addedgreenavailabilitytofeatures
Addedgreenindicatorfororderinginformation
Removed "IDT" from orderable part number
01/31/06:
10/21/08:
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-284-2794
DualPortHelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
16
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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