7142LA25FG8 [IDT]
Dual-Port SRAM, 2KX8, 25ns, CMOS, CQFP48, 0.750 X 0.750 INCH, 0.110 INCH HEIGHT, GREEN, CERAMIC, FLAT PACK-48;
| 型号： | 7142LA25FG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Dual-Port SRAM, 2KX8, 25ns, CMOS, CQFP48, 0.750 X 0.750 INCH, 0.110 INCH HEIGHT, GREEN, CERAMIC, FLAT PACK-48 静态存储器 |
| 文件： | 总17页 (文件大小：265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HIGH SPEED
2K x 8 DUAL PORT
STATIC RAM
IDT7132SA/LA
IDT7142SA/LA
LEAD FINISH (SnPb) ARE IN EOL PROCESS - LAST TIME BUY EXPIRES JUNE 15, 2018
◆
MASTERIDT7132easilyexpandsdatabuswidthto16-or-more
bits using SLAVE IDT7142
Features
◆
High-speed access
◆
◆
◆
◆
◆
On-chip port arbitration logic (IDT7132 only)
BUSY output flag on IDT7132; BUSY input on IDT7142
Battery backup operation —2V data retention (LA only)
TTL-compatible, single 5V ±10% power supply
Available in 48-pin DIP, LCC and Flatpack, and 52-pin PLCC
packages
Military product compliant to MIL-PRF-38535 QML
Industrial temperature range (–40°C to +85°C) is available for
selected speeds
– Commercial:20/25/35/55/100ns(max.)
– Industrial: 25ns (max.)
– Military:25/35/55/100ns(max.)
Low-power operation
◆
–
IDT7132/42SA
Active: 325mW (typ.)
Standby: 5mW (typ.)
– IDT7132/42LA
Active:325mW(typ.)
Standby: 1mW (typ.)
◆
◆
◆
Green parts available, see ordering information
Functional Block Diagram
OE
R
OE
CE
R/W
L
L
CER
L
R/W
R
I/OOL-I/O7L
I/OOR-I/O7R
I/O
Control
I/O
Control
m
(1,2)
(1,2)
BUSY
L
BUSY
R
A
10L
A
10R
0R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
0L
A
11
11
ARBITRATION
LOGIC
CE
OE
R/W
R
R
CE
OE
R/W
L
L
L
R
2692 drw 01
NOTES:
1. IDT7132 (MASTER): BUSY is open drain output and requires pullup resistor of 270Ω.
IDT7142 (SLAVE): BUSY is input.
2. Open drain output: requires pullup resistor of 270Ω.
JULY 2018
1
DSC-2692/22
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Description
TheIDT7132/IDT7142arehigh-speed2Kx8Dual-PortStaticRAMs.
TheIDT7132isdesignedtobeusedasastand-alone8-bitDual-PortRAM
orasa“MASTER”Dual-PortRAMtogetherwiththeIDT7142“SLAVE”
Dual-Portin16-bit-or-morewordwidthsystems.UsingtheIDTMASTER/
SLAVE Dual-Port RAM approach in 16-or-more-bit memory system
applicationsresultsinfull-speed,error-freeoperationwithouttheneedfor
additionaldiscretelogic.
a very low standby power mode.
Fabricated using CMOS high-performance technology, these
devices typically operate on only 325mW of power. Low-power (LA)
versionsofferbatterybackupdataretentioncapability,witheachDual-
Port typically consuming 200µW from a 2V battery.
The IDT7132/7142 devices are packaged in a 48-pin sidebraze or
plastic DIPs, 48-pin LCCs, 52-pin PLCCs, and 48-lead flatpacks.
Military grade product is manufactured in compliance with the latest
revision of MIL-PRF-38535 QML, making it ideally suited to military
temperature applications demanding the highest level of performance
and reliability.
Both devices provide two independent ports with separate control,
address,andl/Opinsthatpermitindependent,asynchronousaccessfor
reads or writes to any location in memory. An automatic power down
feature,controlledbyCEpermitstheon-chipcircuitryofeachporttoenter
Pin Configurations(1,2,3)
V
CC
CE
L
L
L
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CE
R/W
BUSY
R
R/W
2
INDEX
R
BUSY
3
A
OE
10L
R
4
A
10R
OE
L
5
6 5 4 3 2
48 47 46 45 44 43
A0L
A1L
A2L
A3L
A4L
A5L
A6L
A7L
A8L
A9L
R
6
1
A
A
A
A
A
A
A
0R
1R
2R
3R
4R
5R
A
1L
2L
3L
4L
5L
6L
7L
8L
9L
7
42
IDT7132
/7142
A
A
A
A
A
A
A
A
A
A
0R
7
A
A
A
A
A
A
A
A
8
41
40
39
38
37
36
35
34
33
32
31
1R
2R
3R
4R
5R
6R
7R
8R
9R
8
P or C
9
9
10
11
12
13
14
15
16
17
18
19
10
11
12
13
14
15
16
17
18
IDT7132/42L48 or F
L48(4)
&
P48(4)
&
F48(4)
C48(4)
6R
48-Pin LCC/ Flatpack
Top View(5)
A
7R
8R
48-Pin
DIP
I/O0L
I/O1L
I/O2L
I/O3L
I/O4L 20
I/O5L 21
I/O6L 22
I/O7L 23
GND 24
A
I/O7R
I/O6R
I/O5R
I/O4R
I/O3R
I/O2R
I/O1R
I/O0R
Top
A9R
I/O0L
I/O1L
I/O2L
View(5)
I/O7R
I/O6R
19 20 21 22 23 24 25 26 27 28 29 30
,
2692 drw 03
,
2692 drw 02
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. P48-1 package body is approximately .55 in x 2.43 in x .18 in.
C48-2 package body is approximately .62 in x 2.43 in x .15 in.
L48-1 package body is approximately .57 in x .57 in x .68 in.
F48-1 package body is approximately .75 in x .75 in x .11 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Capacitance(1) (TA = +25°C,f = 1.0MHz)
Symbol
Parameter
Input Capacitance
Output Capacitance
Conditions(2)
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
11
11
pF
COUT
V
pF
2692 tbl 00
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 3V to 0V.
2
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
INDEX
7 6
5
4
3
2
52 51 50 49 48 47
1
8
46
45
44
43
42
41
40
39
38
37
36
35
34
OE
R
A
A
A
A
A
A
A
A
A
1L
2L
3L
4L
5L
6L
7L
8L
9L
9
A
A
A
A
A
A
A
A
A
A
0R
10
11
12
13
14
15
16
17
18
19
20
1R
2R
3R
4R
5R
6R
7R
8R
9R
IDT7132/42J
J52(4)
52-Pin PLCC
Top View(5)
I/O0L
I/O1L
I/O2L
I/O3L
N/C
I/O7R
21 22 23 24 25 26 27 28 29 30 31 32 33
2692 drw 04
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. Package body is approximately .75 in x .75 in x .17 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Recommended Operating
Temperature and Supply Voltage(1,2)
Ambient
Absolute Maximum Ratings(1)
Grade
Temperature
-55OC to+125OC
0OC to +70OC
-40OC to +85OC
GND
Vcc
Commercial
Military
0V
5.0V
+
+
+
10%
Symbol
Rating
Military
Unit
& Industrial
Commercial
Industrial
0V
5.0V
5.0V
10%
(2)
V
TERM
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
-0.5 to +7.0
V
0V
10%
2692 tbl 02
NOTES:
T
BIAS
Temperature
Under Bias
-55 to +125
-65 to +150
50
-65 to +135
-65 to +150
50
oC
oC
1. This is the parameter TA. This is the "instant on" case temperature.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
Storage
Temperature
TSTG
DC Output
Current
mA
IOUT
Recommended DC Operating
Conditions
2692 tbl 01
NOTES:
Symbol
Parameter
Min.
Typ.
Max. Unit
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
V
CC
Supply Voltage
4.5
5.0
5.5
0
V
V
V
GND
Ground
0
0
V
IH
IL
Input High Voltage
Input Low Voltage
2.2
6.0(2)
0.8
____
2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 10%.
-0.5(1)
V
____
V
2692 tbl 03
NOTES:
1. VIL (min.) = -1.5V for pulse width less than 10ns.
2. VTERM must not exceed Vcc + 10%.
3
6.42
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,5,8) (VCC = 5.0V ± 10%)
7132X20(2)
7142X20(2)
Com'l Only
7132X25(7)
7142X25(7)
Com'l, Ind
& Military
7132X35
7142X35
Com'l &
Military
Symbol
Parameter
Test Condition
= VIL
Version
COM'L
Typ.
Max.
Typ.
Max.
Typ.
Max.
Unit
ICC
Dynamic Operating Current
(Both Ports Active)
SA
LA
110
110
250
200
110
110
220
170
80
80
165
120
mA
CE
L
= CE
R
,
Outputs Disabled
(3)
f = fMAX
____
____
____
____
MIL &
IND
SA
LA
110
110
280
220
80
80
230
170
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
SA
LA
30
30
65
45
30
30
65
45
25
25
65
45
mA
mA
mA
CE
L = CER = VIH,
(3)
f = fMAX
____
____
____
____
MIL &
IND
SA
LA
30
30
80
60
25
25
80
60
(6)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
SA
LA
65
65
165
125
65
65
150
115
50
50
125
90
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled
(3)
f=fMAX
____
____
____
____
MIL &
IND
SA
LA
65
65
160
125
50
50
150
115
ISB3
Full Standby Current (Both
Ports - All
CMOS Level Inputs)
COM'L
SA
LA
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
4
CE
L and CER > VCC -0.2V
V
IN > VCC -0.2V or VIN < 0.2V, f = 0(4)
____
____
____
____
MIL &
IND
SA
LA
1.0
0.2
30
10
1.0
0.2
30
10
CE"A" < 0.2V andCE"B" > VCC -0.2V(6)
ISB4
Full Standby Current
(One Port - All
CMOS Level Inputs)
COM'L
SA
LA
60
60
155
115
60
60
145
105
45
45
110
85
mA
V
IN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled
____
____
____
____
(3)
MIL &
IND
SA
LA
60
60
155
115
45
45
145
105
f = fMAX
2692 tbl 04a
7132X55
7132X100
7142X55
Com'l &
Military
7142X100
Com'l &
Military
Symbol
Parameter
Test Condition
Version
Typ.
Max.
Typ.
Max.
Unit
ICC
Dynamic Operating
Current
(Both Ports Active)
COM'L
SA
65
65
155
110
65
65
155
110
mA
CEL = CER = VIL,
LA
Outputs Disabled
(3)
f = fMAX
MIL &
IND
SA
LA
65
65
190
140
65
65
190
140
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
COM'L
SA
LA
20
20
65
35
20
20
55
35
mA
mA
mA
CE
L = CER = VIH,
(3)
f = fMAX
MIL &
IND
SA
LA
20
20
65
45
20
20
65
45
(6)
ISB2
Standby Current
(One Port - TTL
Level Inputs)
COM'L
SA
LA
40
40
110
75
40
40
110
75
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled
(3)
f=fMAX
MIL &
IND
SA
LA
40
40
125
90
40
40
125
90
ISB3
Full Standby Current
(Both Ports - All
CMOS Level Inputs)
COM'L
SA
LA
1.0
0.2
15
4
1.0
0.2
15
4
CE
L and CER > VCC -0.2V
V
IN > VCC -0.2V or VIN < 0.2V, f = 0(4)
MIL &
IND
SA
LA
1.0
0.2
30
10
1.0
0.2
30
10
CE"A" < 0.2V and CE"B" > VCC -0.2V(6)
ISB4
Full Standby Current
(One Port - All
CMOS Level Inputs)
COM'L
SA
LA
40
40
100
70
40
40
95
70
mA
V
IN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled
(3)
MIL &
IND
SA
LA
40
40
110
85
40
40
110
80
f = fMAX
2692 tbl 04b
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
2. PLCC Package only
3. At f = fMax, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC TEST CONDITIONS” of input levels
of GND to 3V.
4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
5. Vcc = 5V, TA=+25°C for Typ and is not production tested. Vcc DC = 100mA (Typ)
6. Port "A" may be either left or right port. Port "B" is opposite from port "A".
7. Not available in DIP packages.
8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
4
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range (VCC = 5.0V ± 10%)
7132SA
7142SA
7132LA
7142LA
Symbol
|ILI
Parameter
Test Conditions
Min.
Max.
Min.
Max.
Unit
Input Leakage Current(1)
___
___
|
V
V
CC = 5.5V,
10
5
µA
IN = 0V to VCC
___
___
|ILO
|
Output Leakage Current
Output Low Voltage
10
5
V
CC = 5.5V,
µA
V
CE = VIH, VOUT = 0V to VCC
___
___
___
___
V
V
OL
IOL = 4mA
0.4
0.5
0.4
0.5
Open Drain Output
Low Voltage (BUSY)
IOL = 16mA
OL
V
___
___
V
OH
Output High Voltage
IOH = -4mA
2.4
2.4
V
2692 tbl 05
NOTE:
1. At Vcc < 2.0V leakages are undefined.
Data Retention Characteristics (LA Version Only)
Symbol
Parameter
Test Condition
Min.
Typ.(1)
Max.
Unit
V
___
___
V
DR
V
CC for Data Retention
V
CC = 2.0V
2.0
___
I
CCDR
Data Retention Current
µA
CE > VCC -0.2V
Mil. & Ind.
Com'l.
100
4000
___
V
V
IN > VCC -0.2V or
IN < 0.2V
100
1500
µA
ns
(3)
___
___
t
CDR
Chip Deselect to Data Retention Time
Operation Recovery Time
0
(3)
(2)
RC
___
___
t
R
t
ns
2692 tbl 06
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time
3. This parameter is guaranteed but not production tested.
Data Retention Waveform
DATA RETENTION MODE
VCC
VDR
2.0V
≥
4.5V
4.5V
tCDR
tR
VDR
CE
VIH
VIH
,
2692 drw 05
5
6.42
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
3ns Max.
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
1.5V
Figures 1, 2, and 3
2692 tbl 07
5V
5V
1250Ω
1250Ω
,
DATAOUT
DATAOUT
775Ω
30pF*
775Ω
5pF*
*100pF for 55 and 100ns versions
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for tHZ, tLZ, tWZ, and tOW)
* Including scope and jig
5V
270Ω
BUSY
30pF*
*100pF for 55 and 100ns versions
2692 drw 06
Figure 3. BUSY AC Output Test Load
6
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(3,5)
7132X20(2)
7142X20(2)
Com'l Only
7132X25(2)
7132X35
7142X35
Com'l &
Military
7142X25(2)
Com'l, Ind
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
Read Cycle Time
20
25
35
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
t
Address Access Time
Chip Enable Access Time
Output Enable Access Time
20
20
25
25
35
35
____
____
____
____
____
____
t
t
11
12
20
____
____
____
t
Output Hold from Address Change
Output Low-Z Time(1,4)
3
3
3
____
____
____
t
0
0
0
Output High-Z Time(1,4)
10
10
15
____
____
____
t
t
Chip Enable to Power Up Time(4)
Chip Disable to Power Down Time(4)
0
0
0
____
____
____
____
____
____
t
20
25
35
ns
2692 tbl 08a
7132X55
7132X100
7142X55
Com'l &
Military
7142X100
Com'l &
Military
Symbol
READ CYCLE
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
Read Cycle Time
55
100
ns
ns
ns
ns
ns
ns
ns
ns
____
____
t
Address Access Time
55
55
100
100
____
____
____
____
t
Chip Enable Access Time
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time(1,4)
t
25
40
____
____
t
3
10
____
____
t
5
5
Output High-Z Time(1,4)
25
40
____
____
t
t
Chip Enable to Power Up Time(4)
Chip Disable to Power Down Time(4)
0
0
____
____
____
____
t
50
50
ns
2692 tbl 08b
NOTES:
1. Transition is measured 0mV from Low or High-Impedance Voltage Output Test Load (Figure 2).
2. PLCC package only.
3. 'X' in part numbers indicates power rating (SA or LA).
4. This parameter is guaranteed by device characterization, but is not production tested.
5. Industrial temperature: for specific speeds, packages and powers contact your sales office.
7
6.42
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1)
tRC
ADDRESS
tAA
tOH
tOH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
BUSYOUT
2692 drw 07
(2,3)
BDDH
t
Timing Waveform of Read Cycle No. 2, Either Side(1)
tACE
CE
OE
(3)
(5)
tHZ
tAOE
(5)
HZ
(4)
t
t
LZ
VALID DATA
DATAOUT
(4)
LZ
(3)
t
tPD
t
PU
ICC
CURRENT
50%
50%
ISS
2692 drw 08
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations, BUSY has
no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
4. Timing depends on which signal is asserted last, OE or CE.
5. Timing depends on which signal is de-asserted first, OE or CE.
8
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range(5,6)
7132X20(2)
7142X20(2)
Com'l Only
7132X25(2)
7142X25(2)
Com'l, Ind
& Military
7132X35
7142X35
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
Write Cycle Time(3)
20
15
15
0
25
20
20
0
35
30
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width(4)
t
t
t
15
0
15
0
25
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1)
Data Hold Time
t
10
12
15
____
____
____
t
10
10
15
____
____
____
t
0
0
0
____
____
____
t
Write Enable to Output in High-Z(1)
Output Active from End-of-Write(1)
10
10
15
____
____
____
t
0
0
0
ns
2692 tbl 09
7132X55
7132X100
7142X55
Com'l &
Military
7142X100
Com'l &
Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
Write Cycle Time(3)
55
40
40
0
100
90
90
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
t
t
t
Write Pulse Width(4)
30
0
55
0
t
Write Recovery Time
t
Data Valid to End-of-Write
Output High-Z Time(1)
20
40
____
____
t
25
40
____
____
t
Data Hold Time
0
0
____
____
t
Write Enable to Output in High-Z(1)
Output Active from End-of-Write(1)
30
40
____
____
t
0
0
ns
2692 tbl 10
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization
but is not production tested.
2. PLCC package only.
3. For Master/Slave combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA.
4. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the
bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
5. 'X' in part numbers indicates power rating (SA or LA).
6. Industrial temperature: for specific speeds, packages and powers contact your sales office.
9
6.42
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)(1,5,8)
tWC
ADDRESS
OE
(7)
HZ
t
tAW
CE
(6)
AS
(3)
tWR
(2)
WP
(7)
(4)
t
t
t
HZ
R/W
(7)
t
OW
tWZ
(4)
OUT
DATA
tDW
tDH
IN
DATA
2692 drw 09
Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)(1,5)
tWC
ADDRESS
CE
tAW
(6)
(2)
EW
(3)
tWR
tAS
t
R/W
tDW
tDH
IN
DATA
2692 drw 10
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the
bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
10
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(7,8)
7132X20(1)
7142X20(1)
Com'l Only
7132X25(2)
7132X35
7142X35
Com'l &
Military
7142X25(2)
Com'l, Ind
& Military
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY Timing (For Master IDT7132 Only)
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
WDD
WH
DDD
APS
BDD
20
20
20
20
20
20
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address
BUSY Disable Time from Address
t
t
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Pulse to Data Delay(2)
t
t
50
50
60
t
Write Hold After BUSY(6)
12
15
20
____
____
____
t
Write Data Valid to Read Data Delay(2)
Arbitration Priority Set-up Time(3)
BUSY Disable to Valid Data(4)
35
35
35
____
____
____
____
____
____
t
5
5
5
____
____
____
t
25
35
35
BUSY Timing (For Slave IDT7142 Only)
____
____
____
____
____
____
t
WB
WH
WDD
DDD
Write to BUSY Input(5)
0
0
0
ns
ns
ns
t
Write Hold After BUSY(6)
12
15
20
____
____
____
t
Write Pulse to Data Delay(2)
Write Data Valid to Read Data Delay(2)
40
30
50
35
60
35
____
____
____
t
ns
2692 tbl 11a
7132X55
7132X100
7142X55
Com'l &
Military
7142X100
Com'l &
Military
Symbol
BUSY Timing (For Master IDT7132 Only)
Parameter
Min.
Max.
Min.
Max.
Unit
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
WDD
WH
DDD
APS
BDD
30
30
30
30
50
50
50
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address
BUSY Disable Time from Address
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Pulse to Data Delay(2)
t
t
t
t
80
120
(6)
____
____
t
Write Hold After BUSY
20
20
t
Write Data Valid to Read Data Delay(2)
Arbitration Priority Set-up Time(3)
BUSY Disable to Valid Data(4)
55
100
____
____
____
____
t
5
5
____
____
t
50
65
BUSY Timing (For Slave IDT7142 Only)
Write to BUSY Input(5)
____
____
____
____
t
WB
WH
WDD
DDD
0
0
ns
ns
ns
(6)
t
Write Hold After BUSY
20
20
Write Pulse to Data Delay(2)
Write Data Valid to Read Data Delay(2)
80
55
120
100
____
____
t
____
____
t
ns
2692 tbl 11b
NOTES:
1. PLCC package only.
2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and BUSY.”
3. To ensure that the earlier of the two ports wins.
4. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
5. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
6. To ensure that a write cycle is completed on port "B" after contention on port "A".
7. 'X' in part numbers indicates power rating (SA or LA).
8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
11
6.42
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write with Port-to-Port Read and BUSY(2,3,4)
tWC
ADDR"A"
MATCH
t
WP
R/W"A"
t
DW
tDH
DATAIN"A"
VALID
(1)
APS
t
MATCH
ADDR"B"
BUSY"B"
tBDD
tBDA
tBAA
tWDD
DATAOUT"B"
VALID
tDDD
2692 drw 11
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for Slave (IDT7142).
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port "A" may be either the left or right port. Port "B" is opposite from port "A".
Timing Waveform of Write with BUSY(4)
tWP
R/W"A"
(3)
tWB
BUSY"B"
(1)
tWH
,
R/W"B"
(2)
2692 drw 12
NOTES:
1. tWH must be met for both BUSY Input (IDT7142, slave) or Output (IDT7132, master).
2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.
3. tWB applies only to the slave version (IDT7142).
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
12
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
ADDR
ADDRESSES MATCH
"A" and "B"
CE"B"
(2)
tAPS
CE"A"
tBAC
tBDC
BUSY"A"
2692 drw 13
Timing Waveform of BUSY Arbitration Controlled
by Address Match Timing(1)
tRC or tWC
ADDR"A"
ADDR"B"
BUSY"B"
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
(2)
APS
t
tBAA
tBDA
2692 drw 14
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7132 only).
Truth Tables
Table I. Non-Contention Read/Write Control(4)
Left or Right Port(1)
R/W
X
D
0-7
Function
Port Disabled and in Power-Down Mode, ISB2 or ISB4
CE = CE = VIH, Power-Down Mode, ISB1 or ISB3
CE
H
H
L
OE
X
Z
Z
X
X
R
L
L
X
DATAIN
DATAOUT
Z
Data on Port Written into Memory(2)
Data in Memory Output on Port(3)
High Impedance Outputs
H
L
L
X
L
H
2692 tbl 12
NOTES:
1. A0L - A10L ≠ A0R - A10R
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
13
6.42
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
TheBUSYoutputsontheIDT7132RAMmasterareopendraintype
outputs and require open drain resistors to operate. If these RAMs are
beingexpandedindepth,thentheBUSYindicationfortheresultingarray
does not require the use of an external AND gate.
Table II — Address BUSY
Arbitration
Inputs
Outputs
(1)
(1)
BUSY
L
BUSYR
A
OL-A10L
CEL
CER
A
OR-A10R
Function
Normal
Width Expansion with Busy Logic
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
H
Master/Slave Arrays
Normal
When expanding an SRAM array in width while using BUSY logic,
one master part is used to decide which side of the SRAM array will
receive a BUSY indication, and to output that indication. Any number
of slaves to be addressed in the same address range as the master,
use the BUSY signal as a write inhibit signal. Thus on the IDT7132/
IDT7142SRAMstheBUSYpinisanoutputifthepartisMaster(IDT7132),
and the BUSY pin is an input if the part is a Slave (IDT7142) as shown
in Figure 3.
MATCH
H
H
Normal
MATCH
(2)
(2)
Write Inhibit(3)
2692 tbl 13
NOTES:
1. Pins BUSYL and BUSYR are both outputs for IDT7132 (master). Both are inputs for
IDT7142 (slave). BUSYX outputs on the IDT7132 are open drain, not push-pull
outputs. On slaves the BUSYX input internally inhibits writes.
2. 'L'iftheinputstotheoppositeportwerestablepriortotheaddressandenableinputs
of this port. 'H' if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will
result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of actual logic level on
the pin.
SLAVE
Dual Port
SRAM
5V
270Ω
MASTER
Dual Port
SRAM
CE
CE
5V
BUSY
L
BUSY
L
BUSY
R
BUSYR
270Ω
MASTER
Dual Port
SRAM
SLAVE
Dual Port
SRAM
CE
CE
Functional Description
BUSY
R
BUSY
L
BUSYR
BUSY
L
BUSY
R
The IDT7132/IDT7142 provides two ports with separate control,
address and I/O pins that permit independent access for reads or
writes to any location in memory. The IDT7132/IDT7142 has an
automatic power down feature controlled by CE. The CE controls on-
chip power down circuitry that permits the respective port to go into a
standby mode when not selected (CE = VIH). When a port is enabled,
access to the entire memory array is permitted.
BUSY
L
2692 drw 15
Figure 4. Busy and chip enable routing for both width and depth
expansion with IDT7132 (Master) and (Slave) IDT7142 SRAMs.
If two or more master parts were used when expanding in width, a
splitdecisioncouldresultwithonemasterindicating BUSYononeside
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
TheBUSYarbitration, onaMaster, isbasedonthechipenableand
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with either the R/Wsignal or the byte
enables. Failure to observe this timing can result in a glitched internal
write inhibit signal and corrupted data in the slave.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
RAM have accessed the same location at the same time. It also allows
one of the two accesses to proceed and signals the other side that the
RAMis“Busy”. The BUSY pincanthenbeusedtostalltheaccessuntil
the operation on the other side is completed. If a write operation has
been attempted from the side that receives a busy indication, the write
signal is gated internally to prevent the write from proceeding.
The use of BUSY Logic is not required or desirable for all applica-
tions. In some cases it may be useful to logically OR the BUSYoutputs
togetheranduseanyBUSYindicationasaninterruptsourcetoflagthe
event of an illegal or illogical operation.
14
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Ordering Information
999
XXXX
A
A
A
A
A
Process/
Temperature
Range
Device
Type
Power Speed Package
Tube
Tape and Reel
BLANK
8
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Military (-55°C to +125°C)
BLANK
I(1)
B
Compliant to MIL-PRF-38535 QML
G(2)
Green
P(4)
C
48-pin Plastic DIP (P48)
48-pin Sidebraze DIP (C48)
52-pin PLCC (J52)
J
L48
F
48-pin LCC (L48)
48-pin Ceramic Flatpack (F48)
20
Commercial PLCC Only
Commercial, Industrial & Military
Commercial & Military
25(3)
35
Speed in nanoseconds
55
100
Commercial & Military
Commercial & Military
LA
SA
Low Power
Standard Power
7132
7142
16K (2K x 8-Bit) MASTER Dual-Port RAM
16K (2K x 8-Bit) SLAVE Dual-Port RAM
2692 drw 16
NOTES:
1. Industrialtemperaturerangeisavailable.Forspecificspeeds,packagesandpowerscontactyoursalesoffice.
2. Greenpartsavailable.Forspecificspeeds,packagesandpowerscontactyourlocalsalesoffice.
LEADFINISH(SnPb)partsareinEOLprocess.ProductDiscontinuationNotice-PDN#SP-17-02
3. 25nsspeedgradenotavailableinDIPpackages.
4. For“P”,PlasticDIP,whenorderinggreenpackage,thesuffixis“PDG”.
Datasheet Document History
03/24/99:
Initiateddatasheetdocumenthistory
Convertedtonewformat
Cosmeticandtypographicalcorrections
Addedadditionalnotestopinconfigurations
Changeddrawingformat
Changed Busy Logic and Width Expansion copy
Replaced IDT logo
Pages 2 and 3
Page 14
06/08/99:
08/26/99:
11/10/99:
01/12/00:
Pages 1 and 2
Page 1
Moved full "Description" to page 2 and adjusted page layouts
Added "(LAonly)" to paragraph
Page 2
Page 3
Fixed P48-1 body package description
Increasedstoragetemperatureparameters
ClarifiedTA parameter
Page 4
Page 6
Page 14
DCElectricalparameters–changedwordingfrom"open"to"disabled"
Added asteriks to Figures 1 and 3 in drw 06
Correctedpartnumbers
Changed±500mVto0mVinnotes
DatasheetDocumentHistorycontinuedonpage16
15
6.42
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Datasheet Document History (cont'd)
06/11/04:
01/17/06:
Page 6
Page 4, 7, 9,
11 & 15
Page 5
Page 6
Corrected errors in Figure 3 by changing 1250Ω to 270Ω and removing "or Int" and Int
ClarifiedIndustrialtempofferingfor25ns
RemovedINTfromVOL parameterinDCElectricalCharacteristicstable
UpdatedACTestConditionsInputRise/FallTimesfrom5nsto3ns
Addedgreenavailabilitytofeatures
Page 1
Page 15
Page 16
Page 15
Page 14
Page 2
Addedgreenindicatortoorderinginformation
Replaced IDT address with new
Removed "IDT" from orderable part number
Corrected BUSY description to indicate open drain outputs
Removed IDT in reference to fabrication
10/21/08:
09/20/10:
10/03/14:
Page 15
Page 2, 3 & 15
Added Tape and Reel to Ordering Information
The package codes P48-1, C48-2, J52-1, L48-1 & F48-1 changed to P48, C48, J52,
L48 & F48 respectively to match standard package codes
Add annotation (3) to 25ns speed grade to indicate that 25ns is not available in DIP
packages
Page 15
10/08/14:
11/20/15:
Page 15
Page 15
Correctedatypo
Added(4) footnoteannotationtothe"P"packageintheOrderingInformation.
Added footnote 4, For “P”, Plastic DIP, when ordering green package, the suffix is “PDG”.
UpdatedLpackageintheOrderingInformationtoL48
ProductDiscontinuationNotice-PDN#SP-17-02
Last time buy expires June 15, 2018
07/03/18:
16
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