71P74804S200BQG [IDT]
CABGA-165, Tray;
| 型号： | 71P74804S200BQG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | CABGA-165, Tray 时钟 静态存储器 内存集成电路 |
| 文件： | 总21页 (文件大小：274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
18Mb Pipelined
QDR™II SRAM
Burst of 4
IDT71P74804
IDT71P74604
Features
Description
The IDT QDRIITM Burst of four SRAMs are high-speed synchro-
nous memories with independent, double-data-rate (DDR), read and
write data ports. This scheme allows simultaneous read and write
access for the maximum device throughput, with four data items passed
with each read or write. Four data word transfers occur per clock
cycle, providing quad-data-rate (QDR) performance. Comparing this
with standard SRAM common I/O (CIO), single data rate (SDR) de-
vices, a four to one increase in data access is achieved at equivalent
clock speeds. Considering that QDRII allows clock speeds in excess of
standard SRAM devices, the throughput can be increased well beyond
four to one in most applications.
•
•
18Mb Density (1Mx18, 512kx36)
Separate, Independent Read and Write Data Ports
Supports concurrent transactions
-
•
•
•
Dual Echo Clock Output
4-Word Burst on all SRAM accesses
MultiplexedAddress Bus One Read or One Write request per
clock cycle
•
DDR (Double Data Rate) Data Bus
-
-
Four word burst data per two clock cycles on each port
Four word transfers per clock cycle
•
•
Depth expansion through Control Logic
HSTL (1.5V) inputs that can be scaled to receive signals from
1.4V to 1.9V.
Using independent ports for read and write data access, simplifies
system design by eliminating the need for bi-directional buses. All buses
associated with the QDRII are unidirectional and can be optimized for
signal integrity at very high bus speeds. The QDRII has scalable output
impedance on its data output bus and echo clocks, allowing the user to
tune the bus for low noise and high performance.
The QDRII has a single SDR address bus with read addresses
and write addresses multiplexed. The read and write addresses inter-
leave with each occurring a maximum of every other cycle. In the event
that no operation takes place on a cycle, the subsequest cycle may
begin with either a read or write. During write operations, the writing of
individual bytes may be blocked through the use of byte write control
signals.
•
Scalable output drivers
-
Can drive HSTL, 1.8V TTL or any voltage level from 1.4V
to 1.9V.
-
Output Impedance adjustable from 35Ω to 70Ω
•
•
•
1.8V Core Voltage (VDD)
165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package
JTAG Interface
Functional Block Diagram
(Note1)
DATA
D
REG
WRITE DRIVER
(Note2)
(Note2)
ADD
SA
REG
(Note 4)
(Note 4)
(Note1)
18M
MEMORY
ARRAY
Q
R
CTRL
LOGIC
W
(Note3)
BWx
CQ
K
CLK
GEN
K
CQ
C
SELECT OUTPUT CONTROL
C
6111 drw16
Notes
1) Represents 18 data signal lines for x18 and 36 signal lines for x36.
2) Represents 18 address signal lines for x18 and 17 address signal lines for x36.
3) Represents 2 signal lines for x18 and 4 signal lines for x36.
4) Represents 36 signal lines for x18 and 72 signal lines for x36.
SEPTEMBER 2008
1
DSC-6111/02
©2008 Integrated Device Technology, Inc. QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc.
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Commercial Temperature Range
The QDRII has echo clocks, which provide the user with a clock (or K, K if C, C are disabled). The rising edge of C generates the rising
that is precisely timed to the data output, and tuned with matching imped- edge of CQ, and the falling edge of CQ. The rising edge ofC generates
ance and signal quality. The user can use the echo clock for down- the rising edge ofCQ and the falling edge of CQ. This scheme improves
stream clocking of the data. Echo clocks eliminate the need for the user the correlation of the rising and falling edges of the echo clock and will
to produce alternate clocks with precise timing, positioning, and signal
qualities to guarantee data capture. Since the echo clocks are gener-
ated by the same source that drives the data output, the relationship to
the data is not significantly affected by voltage, temperature and process,
as would be the case if the clock were generated by an outside source.
All interfaces of the QDRII SRAM are HSTL, allowing speeds be-
yond SRAM devices that use any form of TTL interface. The interface
can be scaled to higher voltages (up to 1.9V) to interface with 1.8V
systems if necessary. The device has a VDDQ and a separate Vref,
allowing the user to designate the interface operational voltage, inde-
pendent of the device core voltage of 1.8V VDD. The output impedance
control allows the user to adjust the drive strength to adapt to a wide
range of loads and transmission lines.
improve the duty cycle of the individual signals.
The echo clock is very closely aligned with the data, guaranteeing
that the echo clock will remain closely correlated with the data, within the
tolerances designated.
Read and Write Operations
QDRII devices internally store the 4 words of the burst as a single,
wide word and will retain their order in the burst. There is no ability to
address to the single word level or reverse the burst order; however, the
byte write signals can be used to prevent writing any individual bytes, or
combined to prevent writing one word of the burst.
Read and write operations may be interleaved with each occurring
on every other clock cycle. In the event that two reads or two writes are
requested on adjacent clock cycles, the operation in progress will com-
plete and the second request will be ignored. In the event that both a
read and write are requested simultaneously, the read operation will win
and the write operation will be ignored.
Read operations are initiated by holding the read port select (R) low,
and presenting the read address to the address port during the rising
edge of K which will latch the address. The data will then be read and will
appear at the device output at the designated time in correspondence
The device is capable of sustaining full bandwidth on both the input
and output ports simultaneously. All data is in four word bursts, with
addressing capability to the burst level.
Clocking
The QDRII SRAM has two sets of input clocks, namely the K, K
clocks and the C, C clocks. In addition, the QDRII has an output “echo”
clock, CQ, CQ.
The K andKclocks are the primary device input clocks. The K clock
is, used to clock in the control signals (R, WandBWx), the address, first
and third words of the data burst during a write operation. The K clock
is used to clock in the control signals (BWx) and the second and fourth
words of the data burst during a write operation. The K andK clocks are
with the C and C clocks.
Write operations are initiated by holding the write port select (W) low
and presenting the designated write address to the address bus. The
QDRII SRAM will receive the address on the rising edge of clock K. On
also used internally by the SRAM. In the event that the user disables the the following rising edge of K clock, the QDRII SRAM will receive the first
C and C clocks, the K andK clocks will be used to clock the data out of
the output register and generate the echo clocks.
data item of the four word burst on the data bus. Along with the data, the
byte write (BWx) inputs will be accepted, indicating which bytes of the
data inputs should be written to the SRAM. On the following rising edge
of K, the next word of the write burst and BWx will be accepted. The
subsequent K and K rising edges will receive the last two words of the
four word burst, with their BWx enables.
Output Enables
The QDRII SRAM automatically enables and disables the Q[X:0]
outputs. When a valid read is in progress, and data is present at the
output, the output will be enabled. If no valid data is present at the output
(read not active), the output will be disabled (high impedance). The
echo clocks will remain valid at all times and cannot be disabled or turned
off. During power-up the Q outputs will come up in a high impedance
The C andC clocks may be used to clock the data out of the output
register during read operations and to generate the echo clocks. C and
C must be presented to the SRAM within the timing tolerances. The
output data from the QDRII will be closely aligned to the C and C input,
through the use of an internal DLL. When C is presented to the QDRII
SRAM, the DLL will have already internally clocked the first data word to
arrive at the device output simultaneously with the arrival of theC clock.
The C and second data word of the burst will also correspond. The third
and fourth data words will follow on the next clock cycle of C and C,
respectively.
Single Clock Mode
The QDRII SRAM may be operated with a single clock pair. C and
C may be disabled by tying both signals high, forcing the outputs and
echo clocks to be controlled instead by the K and K clocks.
DLL Operation
state.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin on
the SRAM and Vss to allow the SRAM to adjust its output drive imped-
ance. The value of RQ must be 5X the value of the intended drive
impedance of the SRAM. The allowable range of RQ to guarantee
impedance matching with a tolerance of +/- 10% is between 175 ohms
and 350 ohms, with VDDQ = 1.5V. The output impedance is adjusted
every 1024 clock cycles to correct for drifts in supply voltage and tem-
perature. If the user wishes to drive the output impedance of the SRAM
to it’s lowest value, the ZQ pin may be tied to VDDQ.
The DLL in the output structure of the QDRII SRAM can be used to
closely align the incoming clocks C and C with the output of the data,
generating very tight tolerances between the two. The user may disable
the DLLby holding Doff low. With the DLLoff, the C andC (or K and K
if C and C are not used) will directly clock the output register of the
SRAM. With the DLL off, there will be a propagation delay from the time
the clock enters the device until the data appears at the output.
Echo Clock
The echo clocks, CQ andCQ, are generated by the C and C clocks
6.242
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
Advance Information
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
Commercial Temperature Range
18 Mb QDR II SRAM Burst of 4
Pin Definitions
Symbol
Pin Function
Description
Data input signals, sampled on the rising edge of K and K clocks during valid write operations
1M x 18 -- D[17:0]
D[X:0]
Input Synchronous
512K x 36 -- D[35:0]
Byte Write Select 0, 1, 2, and 3 are active LOW. Sampled on the rising edge of the K and again on the rising edge of K clocks
during write operations. Used to select which byte is written into the device during the current portion of the write operations.
Bytes not written remain unaltered. All the byte writes are sampled on the same edge as the data. Deselecting a Byte Write
Select will cause the corresponding byte of data to be ignored and not written in to the device.
BW
BW
0
, BW
1
Input Synchronous
Input Synchronous
2, BW
3
1M x 18 -- BW
0
controls D[8:0] and BW
1
controls D[17:9]
512K x 36 -- BW
0
controls D[8:0], BW
1
controls D[17:9], BW2 controls D[26:18] and BW3 controls D[35:27]
Address inputs are sampled on the rising edge of K clock during active read or write operations. These address inputs are
multiplexed so a read and write can be initiated on alternate clock cycles. These inputs are ignored when the appropriate port is
deselected.
SA
Data Output signals. These pins drive out the requested data during a Read operation. Valid data is driven out on the rising edge
Q[X:0]
W
Output Synchronous of both the C and C clocks during Read operations or K and K when operating in single clock mode. When the Read port is
deselected, Q[X:0] are automatically three-stated.
Write Control Logic active Low. Sampled on the rising edge of the positive input clock (K). When asserted active, a write operation
is initiated. Deasserting will deselect the Write port, causing D[X:0] to be ignored. If a write operation has successfully been
initiated, it will continue to completion, ignoring the W on the following clock cycle. This allows the user to continuously hold W low
while bursting data into the SRAM.
Input Synchronous
Read Control Logic, active LOW. Sampled on the rising edge of Positive Input Clock (K). When active, a read operation is
initiated. Deasserting will cause the Read port to be deselected. When deselected, the pending access is allowed to
Input Synchronous complete and the output drivers are automatically three-stated following the next rising edge of the C clock. Each read access
consists of a burst of four sequential transfer. If a read operation has successfully been initiated, it will continue to completion,
ignoring the R on the following clock cycle. This allows the user to continuously hold R low while bursting data from the SRAM.
R
Positive Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used
C
together to deskew the flight times of various devices on the board back to the controller. See application example for further
Input Clock
details.
Negative Output Clock Input. C is used in conjunction with C to clock out the Read data from the device. C and C can be used
together to deskew the flight times of various devices on the board back to the controller. See application example for further
details.
Input Clock
C
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device and to drive out data
through Q[X:0] when in single clock mode. All accesses are initiated on the rising edge of K.
K
K
Input Clock
Input Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and to drive out data
through Q[X:0] when in single clock mode.
Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous data outputs and
can be used as a data valid indication. These signals are free running and do not stop when the output data is three-stated.
CQ, CQ
Output Clock
Input
Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus impedance. Q[X:0]
output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and ground. Alternately, this pin can be
connected directly to VDDQ, which enables the minimum impedance mode. This pin cannot be connected directly to GND or left
unconnected.
ZQ
6111 tbl 02a
6.42
3
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Commercial Temperature Range
Pin Definitions continued
Symbol Pin Function
Description
DLL Turn Off. When low this input will turn off the DLL inside the device. The AC timings with the
DLL turned off will be different from those listed in this data sheet. There will be an increased
propagation delay from the incidence of C and C to Q, or K and K to Q as configured. The
propagation delay is not a tested parameter, but will be similar to the propagation delay of other
SRAM devices in this speed grade.
Input
Doff
TDO
TCK
TDI
Output
Input
Input
Input
TDO pin for JTAG.
TCK pin for JTAG.
TDI pin for JTAG. An internal resistor will pull TDI to VDD when the pin is unconnected.
TMS pin for JTAG. An internal resistor will pull TMS to VDD when the pin is unconnected.
TMS
NC
No Connect No connects inside the package. Can be tied to any voltage level
Input Reference Voltage input. Static input used to set the reference level for HSTL inputs and Outputs
VREF
Reference as well as AC measurement points.
Power
V
DD
Power supply inputs to the core of the device. Should be connected to a 1.8V power supply.
Supply
Ground
VSS
Ground for the device. Should be connected to ground of the system.
Power
Supply
Power supply for the outputs of the device. Should be connected to a 1.5V power supply for
HSTL or scaled to the desired output voltage.
VDDQ
6111 tbl 02b
6.442
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
Advance Information
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
Commercial Temperature Range
18 Mb QDR II SRAM Burst of 4
Pin Configuration IDT71P74804 (1M x 18)
1
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
2
3
4
W
5
6
K
7
8
R
9
10
11
V
SS/
NC/
SA (1)
V
SS/
NC
SA
NC
NC
NC
NC
NC
NC
CQ
A
B
C
D
E
F
BW
1
SA (3)
SA (2)
Q9
D9
SA
NC
SA
K
SA
NC
Q8
BW
0
NC
D10
VSS
NC
SA
VSS
Q7
D8
D11
Q10
VSS
VSS
VSS
VSS
VSS
NC
D7
NC
Q11
VDDQ
VSS
VSS
VSS
VDDQ
D6
Q6
Q12
D12
VDDQ
VDD
VSS
VDD
VDDQ
NC
NC
Q5
D13
Q13
VDDQ
VDD
VSS
VDD
VDDQ
D5
G
H
J
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
V
DDQ
NC
NC
NC
NC
NC
NC
SA
VREF
ZQ
NC
NC
D14
VDDQ
VDD
VSS
VDD
VDDQ
Q4
D4
Q14
VDDQ
VDD
VSS
VDD
VDDQ
D3
Q3
K
L
Q15
D15
VDDQ
VSS
VSS
VSS
VDDQ
NC
Q2
NC
D16
VSS
VSS
VSS
VSS
VSS
Q1
D2
M
N
P
R
D17
Q16
VSS
SA
SA
SA
SA
C
SA
SA
SA
VSS
NC
D1
NC
Q17
SA
SA
SA
SA
D0
Q0
TCK
SA
TMS
TDI
C
6111 tbl 12b
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A3 is reserved for the 36Mb expansion address.
2. A10 is reserved for the 72Mb expansion address. This must be tied or driven to VSS on the 1M x 18 QDRII Burst of 4 (71P74804) devices.
3. A2 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 1M x 18 QDRII Burst of 4 (71P74804) devices.
6.42
5
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Commercial Temperature Range
Pin Configuration IDT71P74604 (512K x 36)
1
2
3
4
W
5
BW
BW
6
K
7
8
R
9
10
11
V
SS
/
NC/
NC/
VSS
CQ
A
B
C
D
E
F
CQ
2
3
BW
1
SA (4)
SA (2)
SA (1)
SA (3)
Q27
Q18
D18
SA
K
SA
D17
Q17
Q8
BW
0
D
27
Q
28
D
19
V
SS
SA
NC
SA
V
SS
D
16
Q
7
D8
D28
D20
Q19
VSS
VSS
VSS
VSS
VSS
Q16
D15
D7
Q29
D29
Q20
VDDQ
VSS
VSS
VSS
VDDQ
Q15
D6
Q6
Q30
Q21
D21
VDDQ
VDD
VSS
VDD
VDDQ
D14
Q14
Q5
D
30
D
22
Q
22
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
Q
13
D
13
D5
G
H
J
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
Doff
D31
Q31
D23
VDDQ
VDD
VSS
VDD
VDDQ
D12
Q
4
D4
Q
32
D
32
Q
23
V
DDQ
V
DD
V
SS
V
DD
V
DDQ
Q
12
D
3
Q3
K
L
Q33
Q24
D24
VDDQ
VSS
VSS
VSS
VDDQ
D11
Q11
Q2
D
33
Q
34
D
25
V
SS
V
SS
V
SS
SA
C
V
SS
V
SS
D
10
Q
1
D2
M
N
P
R
D34
D26
Q25
VSS
SA
SA
SA
SA
SA
SA
VSS
Q10
D9
D1
Q35
D35
Q26
SA
SA
SA
SA
Q
9
D0
Q0
TDO
TCK
SA
SA
TMS
TDI
C
6111 tbl 12c
165-ball FBGA Pinout
TOP VIEW
NOTES:
1. A9 is reserved for the 36Mb expansion address.
2. A3 is reserved for the 72Mb expansion address.
3. A10 is reserved for the 144Mb expansion address. This must be tied or driven to VSS on the 512K x 36 QDRII Burst of 4 (71P74604) devices.
4. A2 is reserved for the 288Mb expansion address. This must be tied or driven to VSS on the 512K x 36 QDRII Burst of 4 (71P74604) devices.
6.642
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
Advance Information
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
Commercial Temperature Range
18 Mb QDR II SRAM Burst of 4
Absolute Maximum Ratings(1) (2)
Capacitance (TA = +25°C, f = 1.0MHz)(1)
Symbol
Parameter
Conditions
Max.
Unit
Symbol
Rating
Value
Unit
C
IN
Input Capacitance
5
6
7
pF
V
TERM
Supply Voltage on VDD with
Respect to GND
–0.5 to +2.9
V
V
DD = 1.8V
CCLK
Clock Input Capacitance
Output Capacitance
pF
VDDQ = 1.5V
VTERM
Supply Voltage on VDDQ with
Respect to GND
–0.5 to VDD +0.3
–0.5 to VDD +0.3
–0.5 to VDDQ +0.3
V
V
V
CO
pF
6111 tbl 06
NOTE:
VTERM
Voltage on Input terminals with
respect to GND
1. Tested at characterization and retested after any design or process
change that may affect these parameters.
VTERM
Voltage on Output and I/O
terminals with respect to GND.
T
BIAS
Temperature Under Bias
Storage Temperature
–55 to +125
–65 to +150
+ 20
°C
°C
Recommended DC Operating and
Temperture Conditions
TSTG
IOUT
Continuous Current into Outputs
mA
Symbol
Parameter
Min.
Typ.
Max.
Unit
6111 tbl 05
Power Supply
Voltage
NOTES:
V
DD
1.7
1.8
1.9
V
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGSmaycausepermanentdamagetothedevice. Thisisastress
ratingonlyandfunctionaloperationofthedeviceattheseoranyother
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditionsforextendedperiodsmayaffectreliability.
VDDQ
I/O Supply Voltage
Ground
1.4
0
1.5
0
1.9
0
V
V
VSS
Input Reference
Voltage
VREF
0.68
0
V
DDQ/2
0.95
+70
V
2. VDDQ must not exceed VDD during normal operation.
Ambient
Temperature
o
c
TA
25
(1)
6111 tbl 04
NOTE:
Write Descriptions(1,2)
1. During production testing, the case temperarure equals the ambient
temperature.
Signal
BW0
BW
1
BW2
BW3
Write Byte 0
Write Byte 1
Write Byte 2
Write Byte 3
L
X
X
X
X
L
X
X
X
X
L
X
X
X
X
L
6111 tbl 09
NOTES:
1) All byte write (BWx) signals are sampled on
the rising edge of K and again on K. The data that is present on the
data bus in the designated byte will be latched into the input if
the corresponding BWxis held low. The rising edge of K
will sample the first and third bytes of the four word burst and
the rising edge of K will sample the second and fourth bytes
of the four word burst.
2) The availability of the BWx on designated devices is de
scribed in the pin description table.
3) The QDRII Burst of four SRAM has data forwarding. Aread request
that is initiated on the cycle following a write request to the same
address will produce the newly written data in response to the read
request.
6.42
7
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Commercial Temperature Range
Application Example
6.842
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
Advance Information
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
Commercial Temperature Range
18 Mb QDR II SRAM Burst of 4
DC Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range(VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
Parameter
Symbol
Test Conditions
Min
Max
Unit
Note
µA
Input Leakage Current
Output Leakage Current
I
IL
V
DD = Max VIN = VSS to VDDQ
-2
-2
+2
+2
Output Disabled
µA
IOL
250MH
Z
-
-
-
-
-
-
-
-
-
1100
950
850
850
750
650
375
335
300
V
I
DD = Max,
OUT = 0mA (outputs open),
Cycle Time > tKHKH Min
Operating Current
(x36): DDR
I
DD
200MHz
167MHz
mA
1
1
2
250MH
Z
VDD = Max,
Operating Current
(x18): DDR
IDD
IOUT = 0mA (outputs open),
200MHz
167MHz
mA
mA
Cycle Time > tKHKH Min
250MH
Z
Device Deselected (in NOP state)
IOUT = 0mA (outputs open),
Standby Current: NOP
ISB1
200MHz
167MHz
f=Max,
All Inputs <0.2V or > VDD -0.2V
Output High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
RQ = 250Ω, IOH = -15mA
RQ = 250Ω, IOL = 15mA
V
DDQ/2-0.12
DDQ/2-0.12
DDQ-0.2
SS
V
DDQ/2+0.12
DDQ/2+0.12
DDQ
V
V
V
V
3,7
4,7
5
V
OH1
OL1
OH2
OL2
V
V
V
IOH = -0.1mA
V
V
V
IOL = 0.1mA
V
0.2
6
V
6111 tbl 10c
NOTES:
1. Operating Current is measured at 100% bus utilization.
2. Standby Current is only after all pending read and write burst operations are completed.
3. Outputs are impedance-controlled. IOH = -(VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This
parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.
4. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This
parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.
5. This measurement is taken to ensure that the output has the capability of pulling to the VDDQ rail, and is not intended to be used as an
impedance measurement point.
6. This measurement is taken to ensure that the output has the capability of pulling to Vss, and is not intended to be used as an impedance
measurement point.
7. Programmable Impedance Mode.
6.42
9
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Commercial Temperature Range
Input Electrical Characteristics Over the Operating Temperature and
Supply Voltage Range (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)
Parameter
Input High Voltage, DC
Input Low Voltage, DC
Input High Voltage, AC
Input Low Voltage, AC
NOTES:
Symbol
Min
Max
Unit Notes
V
IH (DC
IL (DC)
IH (AC)
IL (AC)
)
V
REF +0.1
V
DDQ +0.3
V
V
V
V
1,2
1,3
4,5
V
-0.3
V
REF -0.1
V
V
REF +0.2
-
V
-
V
REF -0.2
4,5
6111 tbl 10d
1. These are DC test criteria. DC design criteria is VREF + 50mV. TheAC VIH/VILlevels are defined separately for measuring timing
parameters.
2. VIH (Max) DC = VDDQ+0.3, VIH (Max) AC = VDD +0.5V (pulse width <20% tKHKH (min))
3. VIL (Min) DC = -0.3V, VIL (Min) AC = -0.5V (pulse width <20% tKHKH (min))
4. This conditon is forAC function test only, not forAC parameter test.
5. To maintain a valid level, the transitioning edge of the input must:
a) Sustain a constant slew rate from the currentAC level through the targetAC level, VIL(AC) or VIH(AC)
b) Reach at least the targetAC level.
c)After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)
Overshoot Timing
Undershoot Timing
20% tKHKH (MIN)
VIH
VDD +0.5
VDD +0.25
VSS
VDD
VSS-0.25V
V
SS-0.5V
VIL
6111 drw 22
6111 drw 21
20% tKHKH (MIN)
61.402
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
Advance Information
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
Commercial Temperature Range
18 Mb QDR II SRAM Burst of 4
AC Test Conditions
Parameter
Core Power Supply Voltage
Output Power Supply Voltage
Input High Level
Symbol
Value
1.7-1.9
Unit
V
V
DD
DDQ
IH
IL
V
1.4-1.9
V
V
(VDDQ/2)+ 0.5
(VDDQ/2)- 0.5
V
Input Low Level
V
V
Input Reference Level
Input Rise/Fall Time
VREF
TR/TF
V
DDQ/2
0.3/0.3
DDQ/2
V
ns
Output Timing Reference Level
V
V
6111tbl 11a
NOTE:
1. Parameters are tested with RQ=250Ω
Input Waveform
(VDDQ/2) + 0.5V
Test points
VDDQ/2
V
DDQ/2
(VDDQ/2) - 0.5V
6111 drw 07
Output Waveform
Test points
VDDQ/2
VDDQ/2
6111 drw 08
AC Test Load
VDDQ
/2
DDQ/2
V
Ω
RL = 50
REF
V
OUTPUT
Ω
=50
Z0
Device
Under
Test
Ω
RQ
= 250
ZQ
6111 drw 04
6.42
11
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Commercial Temperature Range
(3,7)
AC Electrical Characteristics (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V,TA = 0 TO 70°C)
250MHz
200MHz
167MHz
Min.
Max
Min.
Max
Min.
Max
Symbol
Parameter
Unit
Notes
Clock Parameters
t
KHKH
KC var
KHKL
KLKH
KHKH
KHKH
KHCH
KC lock
Clock Cycle Time (K,K,C,C)
Clock Phase Jitter (K,K,C,C)
Clock High Time (K,K,C,C)
Clock LOW Time (K,K,C,C)
Clock to clock (K→K,C→C)
Clock to clock (K→K,C→C)
Clock to data clock (K→C,K→C)
DLL lock time (K, C)
4.00
-
8.40
5.00
-
8.40
6.00
-
8.40
ns
ns
t
0.20
0.20
0.20
1,5
8
t
1.60
1.60
1.80
1.80
0.00
1024
30
-
2.00
2.00
2.20
2.20
0.00
1024
30
-
2.40
2.40
2.70
2.70
0.00
1024
30
-
ns
t
-
-
-
ns
8
t
-
-
-
ns
9
t
-
-
-
ns
9
t
1.80
2.30
2.80
ns
t
-
-
-
-
-
-
cycles
ns
2
t
KC reset K static to DLL reset
Output Parameters
t
CHQV
CHQX
CHCQV
CHCQX
CQHQV
CQHQX
CHQZ
CHQX1
C,C HIGH to output valid
C,C HIGH to output hold
C,C HIGH to echo clock valid
C,C HIGH to echo clock hold
CQ,CQ HIGH to output valid
CQ,CQ HIGH to output hold
C HIGH to output High-Z
C HIGH to output Low-Z
-
-0.45
-
0.45
-
-0.45
-
0.45
-
-0.50
-
0.50
ns
ns
ns
ns
ns
ns
ns
ns
3
3
3
3
t
-
0.45
-
-
0.45
-
-
0.50
-
t
t
-0.45
-
-0.45
-
-0.50
-
t
0.30
-
0.35
-
0.40
-
t
-0.30
-
-0.35
-
-0.40
-
t
0.45
-
0.45
-
0.50
-
3,4,5
3,4,5
t
-0.45
-0.45
-0.50
Set-Up Times
t
AVKH
Address valid to K,K rising edge
R,W inputs valid to K,K rising edge
0.50
0.50
-
-
0.60
0.60
-
-
0.70
0.70
-
-
ns
ns
6
tIVKH
Data-in and BWx valid to K, K rising
edge
tDVKH
0.35
-
0.40
-
0.50
-
ns
Hold Times
t
KHAX
KHIX
KHDX
K,K rising edge to address hold
K,K rising edge to R,W inputs hold
0.50
0.50
-
-
0.60
0.60
-
-
0.70
0.70
-
-
ns
ns
6
t
K, K rising edge to data-in and BWx
hold
t
0.35
-
0.40
-
0.50
-
ns
6111 tbl 11
NOTES:
1. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.
2. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.
3. If C,C are tied High, K,K become the references for C,C timing parameters.
4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus contention
because tCHQX1 is a MIN parameter that is worse case at totally different test conditions (0°C, 1.9V) than tCHQZ, which is a MAX parameter
(worst case at 70°C, 1.7V) It is not possible for two SRAMs on the same board to be at such different voltage and temperature.
5. This parameter is guaranteed by device characterization, but not production tested.
6. All address inputs must meet the specified setup and hold times for all latching clock edges.
7. During production testing, the case temperature equals TA.
8. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60% of the cycle time (tKHKH).
9. Clock to clock time (tKHKH) and Clock to clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH).
61.422
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
Advance Information
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
Commercial Temperature Range
18 Mb QDR II SRAM Burst of 4
Timing Waveform of Combined Read and Write Cycles
NOP
7
Write A1
Read A2
4
Write A3
NOP
6
NOP
1
Read A0
3
2
5
K
tKHKL
tKHKH
tKLKH
tKHKH
K
R
tIVKH
tKHIX
tIVKH
tKHIX
W
A3
A1
A2
SA
D
A0
tKHDX
tKHDX
tDVKH
tAVKH tKHAX
tDVKH
D10
D12 D13
D32 D33
D11
Q01
D30 D31
Qx2
Q02
Q03
Q20
Q21
Q22
Q23
Qx3
Q00
Q
tCHQX
tCHQV
tCHQZ
tCQHQV
tKHCH
tCQHQX
tCHQX1
tCHQV
tCHQX
C
tKHKH
tKHKH
tKHCH
tKLKH
tKHKL
.
C
tCHCQV
tCHCQX
CQ
tCHCQV
tCHCQX
CQ
6111 drw09
6.42
13
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Commercial Temperature Range
IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG
This part contains an IEEE standard 1149.1 Compatible TestAc-
cess Port (TAP). The package pads are monitored by the Serial Scan
circuitry when in test mode. This is to support connectivity testing during
manufacturingandsystemdiagnostics. InconformancewithIEEE1149.1,
the SRAM contains aTAPcontroller, Instruction register, Bypass Regis-
ter and ID register. TheTAPcontroller has a standard 16-state machine
that resets internally upon power-up; therefore, the TRST signal is not
required. It is possible to use this device without utilizing the TAP. To
disable theTAPcontroller without interfacing with normal operation of the
SRAM, TCK must be tied to VSS to preclude a mid level input. TMS and
TDI are designed so an undriven input will produce a response identical
to the application of a logic 1, and may be left unconnected, but they may
also be tied to VDD through a resistor. TDO should be left unconnected.
JTAG Block Diagram
JTAG Instruction Coding
IR2 IR1 IR0
Instruction
EXTEST
TDO Output
Notes
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Boundary Scan Register
Identification register
Boundary Scan Register
Do Not Use
IDCODE
2
1
5
4
5
5
A,D
S
SAMPLE-Z
RESERVED
K,K
C,C
SRAM
CORE
Q
SAMPLE/PRELOAD Boundary Scan register
CQ
CQ
RESERVED
RESERVED
BYPASS
Do Not Use
Do Not Use
TDI
BYPASS Reg.
TDO
Bypass Register
3
Identification Reg.
6111tbl 13
NOTES:
Instruction Reg
Control Signal
TAP Controller
.
1. Places Qs in Hi-Z in order to sample all input data regardless of
other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the
serial shift of the external TDI data.
s
TMS
TCK
3. Bypass register is initialized to Vss when BYPASS instruction is
invoked. The Bypass Register also holds serially loaded TDI
when existing the Shift DR states.
6111 drw 18
4. SAMPLE instruction does not place output pins in Hi-Z.
5. This instruction is reserved for future use.
TAP Controller State Diagram
Test Logic Reset
1
0
1
1
1
Run Test Idle
Select DR
0
Select IR
0
0
1
1
1
Capture DR
0
Capture IR
0
Shift DR
1
Shift IR
1
0
0
0
1
Exit 1 DR
0
Exit 1 IR
0
Pause DR
1
Pause IR
1
0
0
0
Exit 2 DR
1
Exit 2 IR
1
0
1
Update DR
0
Update IR
1
6111 drw 17
61.442
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
Advance Information
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
Commercial Temperature Range
18 Mb QDR II SRAM Burst of 4
Scan Register Definition
Part
Instrustion
Register
Bypass
ID
Register
Boundry
Scan
Register
512Kx36
1Mx18
3 bits
3 bits
1 bit
1 bit
32 bits
32 bits
107 bits
107 bits
6111 tbl14
Identification Register Definitions
INSTRUCTION FIELD
ALL DEVICES
DESCRIPTION
PART NUMBER
Revision Number (31:29)
0x0
Revision Number
0x0280
0x0281
512Kx36
1Mx18
QDRII BURST OF 4 71P74604S
71P74804S
Device ID (28:12)
Allows unique identification of SRAM
vendor.
IDT JEDEC ID CODE (11:1)
0x033
1
ID Register Presence Indicator (0)
Indicates the presence of an ID register.
6111 tbl 15
6.42
15
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Commercial Temperature Range
Boundary Scan Exit Order
ORDER
PIN ID
ORDER
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
PIN ID
10D
9E
ORDER
73
PIN ID
2C
3E
2D
2E
1E
2F
1
6R
2
6P
74
3
6N
10C
11D
9C
75
4
7P
76
5
7N
77
6
7R
9D
78
7
8R
11B
11C
9B
79
3F
8
8P
80
1G
1F
9
9R
81
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
11P
10P
10N
9P
10B
11A
Internal
9A
82
3G
2G
1J
83
84
85
2J
10M
11N
9M
9N
8B
86
3K
3J
7C
87
6C
88
2K
1K
2L
3L
1M
1L
3N
3M
1N
2M
3P
8A
89
11L
11M
9L
7A
90
7B
91
6B
92
10L
11K
10K
9J
6A
93
5B
94
5A
95
4A
96
9K
5C
97
10J
11J
11H
10G
9G
4B
98
3A
99
2N
2P
1H
1A
100
101
102
103
104
105
106
107
1P
2B
11F
11G
9F
3R
4R
4P
3B
1C
1B
10F
11E
10E
5P
3D
3C
5N
5R
1D
6111 tbl 16
6111 tbl 17
6111 tbl 18
61.462
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
Advance Information
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
Commercial Temperature Range
18 Mb QDR II SRAM Burst of 4
JTAG DC Operating Conditions
Parameter
Output Power Supply
Symbol
Min
1.4
1.7
1.3
-0.3
-5
Ty p
Max
1.9
Unit
V
Note
V
DDQ
DD
IH
IL
IL
IL
OL
OH
OL
-
1.8
-
Power Supply Voltage
V
1.9
V
Input High Level
V
V
DD+0.3
V
Input Low Level
V
-
0.5
V
TCK Input Leakage Current
TMS, TDI Input Leakage Current
TDO Output Leakage Current
Output High Voltage (IOH = -1mA)
Output Low Voltage (IOL = 1mA)
I
-
+5
µA
µA
µA
V
I
-15
-5
-
+15
+5
I
-
1
1
V
V
DDQ - 0.2
-
VDDQ
V
VSS
-
0.2
V
6111 tbl 19
NOTE:
1. The output impedance of TDO is set to 50 ohms (nominal process) and does not vary with
the external resistor connected to ZQ.
JTAG AC Test Conditions
Parameter
Symbol
Value
1.8
Unit
V
Note
Input High Level
Input Low Level
V
IH
VIL
0
V
Input Rise/Fall Time
TR/TF
1.0/1.0
0.9
ns
V
Input and Output Timing Reference Level
NOTE:
1
6111 tbl 20
1. For SRAM outputs seeAC test load on page 13.
JTAG Input Test Waveform
JTAG AC Test Load
0.9 V
1.8 V
Test points
0.9 V
0.9 V
0 V
6111 drw 23
50Ω
Z0 = 50Ω
TDO
,
6111 drw 24
JTAG Output Test Waveform
Test points
0.9 V
0.9 V
6111 drw 23a
6.42
17
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Commercial Temperature Range
JTAG AC Characteristics
Parameter
Symbol
Min
50
20
20
5
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note
TCK Cycle Time
t
CHCH
CHCL
CLCH
MVCH
CHMX
DVCH
CHDX
SVCH
CHSX
CLQV
-
-
TCK High Pulse Width
TCK Low Pulse Width
TMS Input Setup Time
TMS Input Hold Time
TDI Input Setup Time
TDI Input Hold Time
t
t
-
t
-
t
5
-
t
5
-
t
5
-
SRAM Input Setup Time
SRAM Input Hold Time
Clock Low to Output Valid
t
5
-
t
5
-
t
0
10
6111 tbl21
JTAG Timing Diagram
TCK
tCHCH
t
CHCL
t
CLCH
tMVCH
t
CHMX
TMS
t
DVCH
t
CHDX
TDI/
SRAM
Inputs
tSVCH
t
CHSX
SRAM
Outputs
tCLQV
TDO
6111 drw 19
61.482
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
Advance Information
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
Commercial Temperature Range
18 Mb QDR II SRAM Burst of 4
Package Diagram Outline for 165-Ball Fine Pitch Grid Array
6.42
19
IDT71P74804 (1M x 18-Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Commercial Temperature Range
Ordering Information
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
ipchelp@idt.com
800-345-7015
800-345-7015 or
408-284-8200
fax: 408-284-2775
www.idt.com
“QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “
62.402
IDT71P74804 (1M x 18 x -Bit) 71P74604 (512K x 36-Bit)
18 Mb QDR II SRAM Burst of 4
Commercial Temperature Range
RevisionHistory
REVISION
DATE
PAGES
p. 1-22
p. 1-22
p. 12
DESCRIPTION
0
1
2
07/20/05
12/07/07
09/23/08
ReleasedFinaldatasheet
Removed 71P4204 and 71P4104 speed grades.
Change 250MHz and 200MHz max tKHKH from 6.30 and 7.88 to 8.40ns.
相关型号：
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