71T016SA12BF [IDT]
CABGA-48, Tray;
| 型号： | 71T016SA12BF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | CABGA-48, Tray |
| 文件： | 总9页 (文件大小：293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5V CMOS Static RAM
1 Meg (64K x 16-Bit)
IDT71T016SA
Features
Description
◆
64K x 16 advanced high-speed CMOS Static RAM
TheIDT71T016isa1,048,576-bithigh-speedStaticRAMorganized
as64Kx16.ItisfabricatedusingIDT’shigh-performance,high-reliability
CMOStechnology.Thisstate-of-the-arttechnology,combinedwithinno-
vativecircuitdesigntechniques,providesacost-effectivesolutionforhigh-
speedmemoryneeds.
◆
Equal access and cycle times
— Commercial:10/12/15/20ns
— Industrial:12/15/20ns
One Chip Select plus one Output Enable pin
◆
◆
Bidirectional data inputs and outputs directly
TheIDT71T016has anoutputenablepinwhichoperates as fastas
5ns,withaddressaccesstimesasfastas10ns.Allbidirectionalinputsand
outputsoftheIDT71T016areLVTTL-compatibleandoperationisfroma
single2.5Vsupply.Fullystaticasynchronouscircuitryisused,requiring
noclocks orrefreshforoperation.
LVTTL-compatible
Low power consumption via chip deselect
Upper and Lower Byte Enable Pins
Single 2.5V power supply
◆
◆
◆
◆
Available in 44-pin Plastic SOJ, 44-pin TSOP, and 48-Ball
The IDT71T016 is packaged in a JEDEC standard a 44-pin Plastic
SOJ, 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mm FBGA.
Plastic FBGA packages
Functional Block Diagram
JULY 2008
1
DSC-5326/02
©
2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Pin Configurations
1
2
3
4
5
6
A
B
C
D
E
A
0
A
1
A
2
NC
BLE
OE
I/O8
A3
A4
I/O0
BHE
I/O10
I/O11
I/O12
I/O13
NC
CS
I/O9
A5
A6
I/O
1
I/O2
VSS
NC
NC
A7
I/O
3
VDD
VDD
NC
I/O
4
VSS
F
I/O14
I/O15
NC
A14
A15
I/O
5
I/O6
G
H
A12
A13
I/O7
WE
A8
A9
A10
A11
NC
5326 tbl 02a
FBGA (BF48-1)
Top View
Pin Description
A0
– A15
Address Inputs
Input
Chip Select
Input
Input
Input
Input
Input
I/O
CS
TSOP
Top View
Write Enable
Output Enable
High Byte Enable
Low Byte Enable
Data Input/Output
2.5V Power
WE
OE
BHE
BLE
I/O0 – I/O15
VDD
Power
Gnd
VSS
Ground
5326 tbl 01
Truth Table(1)
CS
H
L
OE
X
L
WE
X
H
H
H
L
BLE
X
L
BHE
X
H
L
I/O
0
-I/O
7
I/O
8
-I/O15
Function
Deselected – Standby
Low Byte Read
High Byte Read
Word Read
High-Z
High-Z
High-Z
DATAOUT
High-Z
DATAOUT
DATAIN
DATAIN
High-Z
High-Z
High-Z
L
L
H
L
DATAOUT
DATAOUT
DATAIN
High-Z
L
L
L
L
X
X
X
H
X
L
L
Word Write
L
L
L
H
L
Low Byte Write
L
L
H
X
H
DATAIN
High-Z
High Byte Write
Outputs Disabled
Outputs Disabled
L
H
X
X
H
L
High-Z
5326 tbl 02
NOTE:
1. H = VIH, L = VIL, X = Don't care.
6.422
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Recommended Operating
Temperature and Supply Voltage
Symbol
Rating
Value
Unit
VDD
Supply Voltage Relative
to VSS
–0.3 to +3.6
V
Grade
Temperature
0°C to +70°C
-40°C to +85°C
VSS
VDD
Commercial
Industrial
0V
0V
See Below
Terminal Voltage Relative
to VSS
–0.3 to VDD+0.3
V
VIN, VOUT
See Below
5326 tbl 04
T
BIAS
Temperature Under Bias
Storage Temperature
Power Dissipation
–55 to +125
–55 to +125
1.25
oC
oC
W
TSTG
Recommended DC Operating
Conditions
P
T
IOUT
DC Output Current
50
mA
Symbol
Parameter
Min.
2.375
0
Typ.
Max.
2.625
0
Unit
V
5326 tbl 03
NOTE:
V
DD
Supply Voltage
2.5
1. StressesgreaterthanthoselistedunderABSOLUTEMAXIMUMRATINGSmaycause
permanentdamagetothedevice.Thisisastressratingonlyandfunctionaloperation
ofthedeviceattheseoranyotherconditionsabovethoseindicatedintheoperational
sections of this specification is not implied. Exposure to absolute maximum rating
conditionsforextendedperiodsmayaffectreliability.
Vss
Ground
0
V
____
V
IH
Input High Voltage
Input Low Voltage
1.7
V
DD+0.3(1)
V
(2)
____
VIL
–0.3
0.7
V
5326 tbl 05
Capacitance
NOTES:
1. VIH (max) = VDD + 1.0V a.c. (pulse width less than tCYC/2) for I < 20 mA, once
per cycle.
2. VIL (min) = -1.0V a.c. (pulse width less than tCYC/2) for I < 20 mA, once per cycle.
(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
6
7
pF
CI/O
V
pF
5326 tbl 06
NOTE:
1. Thisparameterisguaranteedbydevicecharacterization,butnotproductiontested.
DC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
IDT71T016SA
Symbol
Parameter
Input Leakage Current
Test Condition
DD = Max., VIN = VSS to VDD
DD = Max., CS = VIH, VOUT = VSS to VDD
OL = 2.0mA, VDD = Min.
OH = 2.0mA, VDD = Min.
Min.
Max.
5
Unit
µA
µA
V
___
___
___
|ILI|
V
|ILO
|
Output Leakage Current
Output Low Voltage
Output High Voltage
V
5
VOL
I
0.7
___
VOH
I
1.7
V
5326 tbl 07
DC Electrical Characteristics(1,2)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V)
71T016SA10
Com'l
160
71T016SA12
71T016SA15
71T016SA20
Parameter
Symbol
Com'l
150
Ind
Com'l
130
Ind
Com'l
Ind
Unit
Max.
160
130
120
80
120
Dynamic Operating Current
ICC
mA
(3)
CS < VLC, Outputs Open, VDD = Max., f = fMAX
____
____
____
Typ.(4)
90
85
80
Dynamic Standby Power Supply Current
CS > VHC, Outputs Open, VDD = Max., f = fMAX
I
SB
45
10
40
15
45
15
35
15
35
15
30
15
30
15
mA
(3)
Full Standby Power Supply Current (static)
CS > VHC, Outputs Open, VDD = Max., f = 0(3)
ISB
1
mA
NOTES:
5326 tbl 8
1. Allvaluesaremaximumguaranteedvalues.
2. All inputs switch between 0.2V (Low) and VDD – 0.2V (High).
3. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing .
4. Typical values are measured at 2.5V, 25°C and with equal read and write cycles. This parameter is guaranteed by device characterization but is not production
tested.
6.42
3
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels
0V to 2.5V
1.5ns
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
(VDD/2)
(VDD/2)
See Figure 1, 2 and 3
5326 tbl 09
AC Test Loads
+1.25V
50Ω
Z0 = 50Ω
I/O
30pF
5326 drw 03
*Including jig and scope capacitance.
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
Figure 3. Output Capacitive Derating
6.442
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics (VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
71T016SA10(2)
71T016SA12
71T016SA15
71T016SA20
Symbol
Parameter
Min.
Max.
Min. Max.
Min. Max.
Min. Max.
Unit
READ CYCLE
____
____
____
____
t
RC
AA
ACS
Read Cycle Time
10
12
15
20
ns
ns
ns
____
____
____
____
t
Address Access Time
10
12
15
20
____
____
____
____
t
Chip Select Access Time
Chip Select Low to Output in Low-Z
10
12
15
20
(1)
CL Z
____
____
____
____
4
4
5
5
ns
ns
ns
ns
t
____
____
____
____
(1)
Chip Select Hig h to Output in High-Z
Output Enable Low to Output Valid
Output Enable Low to Output in Low-Z
5
6
6
8
tCHZ
____
____
____
____
tOE
5
6
7
8
(1)
(1)
____
____
____
____
0
0
0
0
tOLZ
____
____
____
____
Output Enable High to Output in High-Z
Output Hold from Address Change
Byte Enable Low to Output Valid
Byte Enable Low to Output in Low-Z
5
6
6
8
ns
ns
ns
ns
t
OHZ
OH
BE
t
4
—
4
—
4
—
4
—
____
t
—
5
—
6
—
7
8
(1)
____
____
____
____
0
0
0
0
tBLZ
____
____
____
____
(1)
Byte Enable High to Output in High-Z
5
6
6
8
ns
t
BHZ
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
AW
CW
BW
AS
WR
WP
DW
DH
Write Cycle Time
10
7
7
7
0
0
7
5
0
12
8
8
8
0
0
8
6
0
15
10
10
10
0
20
12
12
12
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Address Valid to End of Write
Chip Select Low to End of Write
Byte Enable Low to End of Write
Address Set-up Time
t
t
t
t
Address Hold from End of Write
Write Pulse Width
0
0
t
10
7
12
9
t
Data Valid to End of Write
Data Hold Time
t
0
0
(1)
OW
____
____
____
____
Write Enable High to Output in Low-Z
Write Enable Low to Output in High-Z
3
3
3
3
ns
t
____
____
____
____
(1)
WHZ
5
6
6
8
ns
t
5326 tbl 10
NOTES:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
2. 00C to +700C temperature range only.
Timing Waveform of Read Cycle No. 1(1,2,3)
NOTES:
1. WE is HIGH for Read Cycle.
2. Deviceiscontinuouslyselected,CSisLOW.
3. OE, BHE, and BLE are LOW.
6.42
5
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 2(1)
NOTES:
1. WE is HIGH for Read Cycle.
2. AddressmustbevalidpriortoorcoincidentwiththelaterofCS,BHE,or BLE transitionLOW;otherwisetAA isthelimitingparameter.
3. Transitionismeasured±200mVfromsteadystate.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuouslyHIGH. Ifduringa WE controlledwrite cycle OE is LOW, tWP mustbe greaterthanorequaltotWHZ+tDW toallowthe I/Odrivers toturnoffanddata tobe placed
onthe bus forthe requiredtDW. IfOE is HIGHduringaWE controlledwrite cycle, this requirementdoes notapplyandthe minimumwrite pulse is as shortas the specifiedtWP.
3. Duringthis period,I/Opins areintheoutputstate,andinputsignals mustnotbeapplied.
4. Ifthe CSLOWorBHE andBLELOWtransitionoccurssimultaneouslywithoraftertheWELOWtransition,theoutputsremaininahigh-impedancestate.
5. Transitionismeasured±200mVfromsteadystate.
6.462
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,4)
Timing Waveform of Write Cycle No. 3 (BHE, BLE Controlled Timing)(1,4)
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuouslyHIGH. Ifduringa WE controlledwrite cycle OE is LOW, tWP mustbe greaterthanorequaltotWHZ+tDW toallowthe I/Odrivers toturnoffanddata tobe placed
onthe bus forthe requiredtDW. IfOE is HIGHduringaWE controlledwrite cycle, this requirementdoes notapplyandthe minimumwrite pulse is as shortas the specifiedtWP.
3. Duringthis period,I/Opins areintheoutputstate,andinputsignals mustnotbeapplied.
4. Ifthe CSLOWorBHE andBLELOWtransitionoccurssimultaneouslywithoraftertheWELOWtransition,theoutputsremaininahigh-impedancestate.
5. Transitionismeasured±200mVfromsteadystate.
6.42
7
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit)
Commercial and Industrial Temperature Ranges
Ordering Information
6.482
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
Datasheet Document History
Rev
0
1
Date
08/23/01
04/16/04
Page
Description
Creatednewdatasheet
Updateddatasheettofullreleaseversion.
UpdatedovershootandundershootspecificationsandtypicalDCelectrical
characteristics.
p. 1-8
p. 3
2
07/14/08
p. 1,2,6,7
Correctedpinlabels outputenable, chipselect, write enable, highandlowbyte
enables tobe OE, CS, WE, BHE, BLE toreflectactive lownature.
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9
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