71V30L55TFG8 [IDT]
Multi-Port SRAM, 1KX8, 55ns, CMOS, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, GREEN, STQFP-64;
| 型号： | 71V30L55TFG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Multi-Port SRAM, 1KX8, 55ns, CMOS, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, GREEN, STQFP-64 静态存储器 内存集成电路 |
| 文件： | 总14页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT71V30S/L
HIGH-SPEED 3.3V
1K X 8 DUAL-PORT
STATIC RAM
Features
◆
◆
High-speed access
On-chip port arbitration logic
◆
◆
◆
◆
◆
Interrupt flags for port-to-port communication
– Commercial: 25/35/55ns (max.)
Low-power operation
– IDT71V30S
— Active: 375mW (typ.)
— Standby: 5mW (typ.)
– IDT71V30L
— Active: 375mW (typ.)
— Standby: 1mW (typ.)
◆
Fully asynchronous operation from either port
Battery backup operation, 2V data retention (L Only)
TTL-compatible, single 3.3V ±0.3V power supply
Industrial temperature range (-40OC to +85OC) is available
for selected speeds
◆
Green parts available, see ordering information
Functional Block Diagram
OE
R
OE
CE
L
CER
L
R/W
R
R/WL
I/O0R-I/O7R
I/O0L- I/O7L
I/O
Control
I/O
Control
(1)
L
(1)
BUSYR
BUSY
A
9L
0L
A
9R
0R
Address
Decoder
MEMORY
ARRAY
Address
Decoder
A
A
10
10
ARBITRATION
and
INTERRUPT
LOGIC
CE
L
L
CE
OE
R/W
R
R
OE
R
R/W
L
(2)
L
(2)
INT
INTR
3741 drw 01
NOTES:
1. IDT71V30: BUSY outputs are non-tristatable push-pulls.
2. INT outputs are non-tristable push-pull output structure.
MARCH 2005
1
DSC 3741/8
©2000IntegratedDeviceTechnology,Inc.
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Description
down feature, controlled by CE, permits the on chip circuitry of each
port to enter a very low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these
devices typically operate on only 375mW of power. Low-power (L)
versions offer battery backup data retention capability, with each Dual-
Port typically consuming 200µW from a 2V battery.
The IDT71V30 is a high-speed 1K x 8 Dual-Port Static RAM. The
IDT71V30 is designed to be used as a stand-alone 8-bit Dual-Port
SRAM.
Both devices provide two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
The IDT71V30 devices are packaged in 64-pin STQFPs.
PinConfigurations(1,2,3)
INDEX
OE
R
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
OE
0L
A
1L
A
A2L
3L
A
4L
A
A5L
6L
A
N/C
A7L
A8L
9L
A
L
48
47
46
0R
A
A
A
A
A
A
A
1R
2R
3R
4R
5R
6R
45
44
43
42
41
40
39
38
37
36
35
34
33
IDT71V30TF
PP64-1(4)
64-Pin STQFP
Top View(5)
N/C
7R
A
8R
A
9R
A
N/C
N/C
N/C
I/O0L
,
7R
I/O
1L
I/O
I/O6R
2L
I/O
3741 drw 03
NOTES:
1. All VCC pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. Package body is approximately 10mm x 10mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate the orientation of the actual part-marking.
6.42
2
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Recommended
DC Operating Conditions
Symbol
Rating
Com'l & Ind
Unit
(2)
Symbol
Parameter
Min.
Typ.
Max.
3.6
0
Unit
V
V
TERM
Terminal Voltage
-0.5 to +4.60
V
with Respect to GND
VCC
Supply Voltage
3.0
3.3
Temperature
Under Bias
-55 to +125
-65 to +150
50
oC
oC
T
BIAS
GND Ground
0
0
V
____
V
IH
Input High Voltage
Input Low Voltage
2.0
V
CC+0.3V
V
Storage
Temperature
TSTG
-0.3(1)
0.8
V
____
VIL
IOUT
DC Output
Current
mA
3741 tbl 02
NOTE:
1. VIL (min.) = -1.5V for pulse width less than 20ns.
3741 tbl 01
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above
those indicated in the operational sections of the specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
Maximum Operating
TemperatureandSupplyVoltage(1,2)
Ambient
2. VTERM must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of VTERM > Vcc + 0.3V.
Grade
Commercial
Industrial
Temperature
0OC to +70OC
-40OC to +85OC
GND
Vcc
0V
3.3V
3.3V
+
+
0.3
0V
0.3
3741 tbl 03
Capacitance(1) (TA = +25OC, f=1.0MHz)
NOTES:
1. This is the parameter TA. This is the "instant on" case temperature.
2. Industrial temperature: for specific speeds, packages and powers,
contact your sales office.
Symbol
Parameter
Conditions(2)
Max.
Unit
C
IN
Input Capacitance
VIN = 3dV
9
pF
Output
Capacitance
VOUT = 3dV
10
pF
COUT
3741 tbl 04
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dv references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
71V30S
71V30L
Symbol
Parameter
Input Leakage
Test Conditions
Min.
Max.
Min.
Max.
Unit
___
___
|ILI|
V
CC = 3.6V,
10
5
5
µA
(1)
Current
VIN = 0V to VCC
___
___
___
___
10
µA
V
|ILO
|
Output Leakage
Current
CE = VIH
,
V
OUT = 0V to VCC
VOL
Output Low Voltage
IOL = 4mA
0.4
0.4
(I/O0-I/O7)
___
___
VOH
Output High Voltage
IOH = -4mA
2.4
2.4
V
3741 tbl 05
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
Supply CurrentVIN > VCC -0.2V or < 0.2V
3
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1,6,7) (VCC = 3.3V ± 0.3V)
71V30X25
71V30X35
71V30X55
Com'l Only
Com'l Only
Com'l Only
Symbol
Parameter
Test Condition
Version
COM'L
Typ.(2)
Max.
Typ.(2)
Max.
Typ.(2)
Max. Unit
mA
ICC
Dynamic Operating Current CEL and CER = VIL,
(Both Ports Active)
S
L
75
75
150
120
75
75
145
115
75
75
135
105
Outputs Disabled
(3)
f = fMAX
___
___
___
___
___
___
___
___
___
___
___
___
IND
S
L
mA
ISB1
ISB2
ISB3
ISB4
Standby Current
(Both Ports - TTL Level
Inputs)
CEL and CER= VIL,
COM'L
IND
S
L
20
20
50
35
20
20
50
35
20
20
50
35
(3)
f = fMAX
___
___
___
___
___
___
___
___
___
___
___
___
S
L
(5)
mA
Standby Current
(One Port - TTL Level
Inputs)
CE"A" = VIL and CE"B" = VIH
Active Port Outputs Disabled,
COM'L
IND
S
L
30
30
105
75
30
30
100
70
30
30
90
60
(3)
f=fMAX
___
___
___
___
___
___
___
___
___
___
___
___
S
L
mA
Full Standby Current (Both
Ports - CMOS Level Inputs) VIN > VCC - 0.2V or
CEL and CER > VCC - 0.2V
COM'L
IND
S
L
1.0
0.2
5.0
3.0
1.0
0.2
5.0
3.0
1.0
0.2
5.0
3.0
VIN < 0.2V, f = 0(4)
___
___
___
___
___
___
___
___
___
___
___
___
S
L
mA
Full Standby Current
(One Port - CMOS
Level Inputs)
CE"A" < 0.2V and
CE"B" > VCC - 0.2V
COM'L
IND
S
L
30
30
90
75
30
30
85
70
30
30
75
60
(5)
VIN > VCC - 0.2V or VIN < 0.2V
Active Port Outputs Disabled
___
___
___
___
___
___
___
___
___
___
___
___
S
L
(3)
f=fMAX
3741 tbl 06
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. VCC = 3.3V, TA = +25°C, and are not production tested. ICCDC = 70mA (Typ.)
3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Refer to chip enable Truth Table I.
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Data Retention Characteristics (L Version Only)
71V30L
Symbol
Parameter
CC for Data Retention
Test Condition
Min.
Typ.(1)
Max.
Unit
V
____
____
VDR
V
2.0
____
____
____
ICCDR
Data Retention Current
Ind.
µA
____
VCC = 2V, CE > VCC -0.2V
Com'l.
100
1500
(3)
CDR
____
____
t
Chip Deselect to Data Retention Time
Operation Recovery Time
VIN > VCC -0.2V or VIN < 0.2V
0
ns
(3)
(2)
RC
____
____
t
R
t
ns
3741 tbl 07
NOTES:
1. VCC = 2V, TA = +25°C, and is not production tested.
2. tRC = Read Cycle Time.
3. This parameter is guaranteed by device characterization but not production tested.
6.42
4
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Test Conditions
Data Retention Waveform
DATA RETENTION MODE
Input Pulse Levels
GND to 3.0V
3ns Max.
1.5V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
CC
V
≥
DR
V
2.0V
3.0V
3.0V
1.5V
t
CDR
tR
Figures 1 and 2
DR
V
CE
3741 tbl 08
IH
V
IH
V
,
3741 drw 04
3.3V
3.3V
590Ω
590Ω
DATA OUT
DATA OUT
435Ω
BUSY
435Ω
INT
30pF
5pF
3741 drw 05
Figure 2. Output Test Load
(For tHZ, tLZ, tWZ and tOW)
Figure 1. AC Output Test Load
* Including scope and jig.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(3,4)
71V30X25
71V30X35
Com'l Only
71V30X55
Com'l Only
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
t
RC
AA
ACE
AOE
OH
LZ
HZ
PU
PD
Read Cycle Time
25
35
55
ns
ns
ns
ns
ns
ns
ns
ns
____
____
____
t
Address Access Time
Chip Enable Access Time
Output Enable Access Time
25
25
35
35
55
55
____
____
____
____
____
____
t
t
12
20
25
____
____
____
t
Output Hold from Address Change
Output Low-Z Time(1,2)
3
3
3
____
____
____
t
0
0
0
Output High-Z Time(1,2)
12
15
30
____
____
____
t
t
Chip Enable to Power Up Time(2)
Chip Disable to Power Down Time(2)
0
0
0
____
____
____
____
____
____
t
50
50
50
ns
3741 tbl 09
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. 'X' in part number indicates power rating (S or L).
4. Industrial temperature: for specific speeds, packages and power contact your sales office.
5
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side(1)
tRC
ADDRESS
tAA
tOH
tOH
DATAOUT
PREVIOUS DATA VALID
DATA VALID
BUSYOUT
3741 drw 06
(2,3)
t
BDD
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in case where the opposite is port is completing a write operation to same the address location. For simultaneous read operations BUSY has
no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
Timing Waveform of Read Cycle No. 2, Either Side(3)
t
ACE
CE
(4)
(2)
tHZ
tAOE
OE
(2)
(1)
t
HZ
t
LZ
VALID DATA
DATAOUT
(1)
(4)
t
LZ
t
PD
t
PU
CC
I
CURRENT
50%
50%
SS
I
3741 drw 07
NOTES:
1. Timing depends on which signal is asserted last, OE or CE.
2. Timing depends on which signal is desserted first, OE or CE.
3. R/W = VIH and the address is valid prior to or coincidental with CE transition LOW.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, and tBDD.
6.42
6
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
OperatingTemperatureandSupplyVoltage(4,5)
71V30X25
71V30X35
Com'l Only
71V30X55
Com'l Only
Com'l Only
Min.
Max.
Min.
Max.
Min.
Max.
Symbol
Parameter
Unit
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
EW
AW
AS
WP
WR
DW
HZ
DH
WZ
OW
Write Cycle Time
25
20
20
0
35
30
30
0
55
40
40
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Chip Enable to End-of-Write
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
t
t
t
20
0
30
0
40
0
t
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time(1,2)
Data Hold Time(3)
t
12
20
20
____
____
____
t
12
15
30
____
____
____
t
0
0
0
(1,2)
____
____
____
t
Write Enable to Output in High-Z
Output Active from End-of-Write(1, 2,3)
15
15
30
____
____
____
t
0
0
0
ns
3741 tbl 10
NOTES:
1. Transition is measured 0mV from Low- or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for tDH must be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over voltage and
temperature, the actual tDH will always be smaller than the actual tOW.
4. 'X' in part number indicates power rating (S or L).
5. Industrial temperatures: for specific speeds, packages and powers contact your sales office.
7
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1,(R/W Controlled Timing)(1,5,8)
t
WC
ADDRESS
OE
(7)
t
HZ
tAW
CE
(2)
WP
(7)
(6)
(3)
t
AS
tWR
t
tHZ
R/W
(7)
tOW
t
WZ
(4)
(4)
OUT
DATA
tDW
tDH
IN
DATA
3741 drw 08
Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)
tWC
ADDRESS
CE
tAW
(3)
(6)
(2)
tAS
t
WR
tEW
R/W
tDW
t
DH
IN
DATA
3741 drw 09
NOTES:
1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W= VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the
bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
6.42
8
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(6,7)
71V30X25
71V30X35
Com'l Only
71V30X55
Com'l Only
Com'l Only
Symbol
BUSY TIMING (M/S=VIH
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
)
____
____
____
____
____
____
____
____
____
____
____
____
t
BAA
BDA
BAC
BDC
WH
WDD
DDD
APS
BDD
20
20
20
20
20
20
30
30
30
ns
ns
ns
ns
ns
ns
ns
ns
BUSY Access Time from Address Match
BUSY Disable Time from Address Not Matched
BUSY Access Time from Chip Enable
BUSY Disable Time from Chip Enable
Write Hold After BUSY(5)
t
t
t
20
20
30
____
____
____
t
20
30
40
(1)
____
____
____
t
Write Pulse to Data Delay
50
60
80
t
Write Data Valid to Read Data Delay(1)
Arbitration Priority Set-up Time(2)
BUSY Disable to Valid Data(3)
35
45
65
____
____
____
____
____
____
t
5
5
5
____
____
____
t
30
30
45
ns
3741 tbl 11
NOTES:
1. Port-to-port delay through SRAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read with BUSY".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
4. To ensure that the Write Cycle is inhibited on Port “B” during contention on Port “A”.
5. To ensure that the Write Cycle is completed on Port “B” after contention on Port “A”.
6. 'X' in part number indicates power rating (S or L).
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Timing Waveform of Write with Port-to-Port Read with BUSY(1,2,3,4)
tWC
ADDR"A"
MATCH
tWP
R/W"A"
tDW
tDH
DATAIN"A"
VALID
(1)
APS
t
ADDR"B"
BUSY "B"
MATCH
tBDD
BDA
t
tWDD
DATAOUT"B"
VALID
t
DDD
3741 drw 10
NOTES:
1. To ensure that the earlier of the two ports wins.
2. CEL = CER = VIL
3. OE = VIL for the reading port.
4. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
9
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Timing Waveform of Write with BUSY(3)
tWP
R/W'A'
tWB
BUSY'B'
(1)
tWH
,
R/W'B'
(2)
NOTES:
3741 drw 11
1. tWH must be met for BUSY.
2. BUSY is asserted on port 'B' blocking R/W'B', until BUSY'B' goes HIGH.
3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port "B" is opposite from port "A".
Timing Waveform of BUSY Arbitration Controlled by CE Timing(1)
ADDR
'A' AND 'B'
ADDRESSES MATCH
CE'B'
(2)
t
APS
CE'A'
tBAC
t
BDC
BUSY'A'
3741 drw 12
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
TimingWaveformof BUSY ArbitrationControlledAddressMatchTiming(1)
t
RC OR tWC
ADDR'A'
ADDR'B'
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
(2)
t
APS
tBAA
tBDA
BUSY'B'
3741 drw 13
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted.
6.42
10
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range(1,2)
71V30X25
71V30X35
71V30X55
Com'l Only
Com'l Only
Com'l Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
____
____
____
____
____
____
t
AS
WR
INS
INR
Address Set-up Time
Write Recovery Time
Interrupt Set Time
0
0
0
ns
ns
ns
t
0
0
0
____
____
____
t
25
25
25
25
45
45
____
____
____
t
Interrupt Reset Time
ns
3741 tbl 12
NOTES:
1. 'X' in part number indicates power rating (S or L).
2. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Timing Waveform of Interrupt Mode(1)
INT Sets
tWC
INTERRUPT ADDRESS (2)
ADDR'A'
(4)
(3)
t
WR
tAS
R/W'A'
INT'B'
(3)
t
INS
3741 drw 14
INT Clears
tRC
ADDR'B'
INTERRUPT CLEAR ADDRESS
(3)
tAS
OE'B'
INT'A'
(3)
tINR
3741 drw 15
NOTES:.
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. See Interrupt Truth Table II.
3. Timing depends on which enable signal (CE or R/W) is asserted last.
4. Timing depends on which enable signal (CE or R/W) is de-asserted first.
11
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Truth Tables
Table I. Non-Contention Read/Write Control(4)
(1)
Left or Right Port
CE
H
H
L
OE
X
X
X
L
R/W
X
D
0-7
Function
Z
Z
Port Disabled and in Power-Down Mode, ISB2 or ISB4
X
CER = CEL =
VIH, Power-Down Mode, ISB1 or ISB3
L
DATAIN
Data on Port Written Into Memory(2)
H
L
DATAOUT Data in Memory Output on Port(3)
High Impedance Outputs
H
L
H
Z
3741 tbl 13
NOTES:
1. A0L – A9L ≠ A0R – A9R.
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
Table II. Interrupt Flag(1,4)
Left Port
Right Port
OE
R/WL
A9L-A0L
R/WR
A
9R-A0R
Function
Set Right INT Flag
Reset Right INT Flag
Set Left INT Flag
Reset Left INT Flag
CEL
OEL
INT
L
CER
R
INTR
(2)
L
L
X
X
L
X
X
X
L
3FF
X
X
X
X
L
L
X
X
L
X
3FF
3FE
X
L
R
(3
)
X
X
X
H
R
(3)
X
X
L
L
X
X
X
L
(2)
X
3FE
H
X
X
L
3741 tbl 14
NOTES:
1. Assumes BUSYL = BUSYR = VIH
2. If BUSYL = VIL, then No Change.
3. If BUSYR = VIL, then No Change.
4. 'H' = HIGH,' L' = LOW,' X' = DON’T CARE
Table III — Address BUSY Arbitration
Inputs
Outputs
A
OL-A9L
(1)
(1)
A
OR-A9R
Function
Normal
Normal
Normal
CE
L
CE
R
BUSY
L
BUSYR
X
H
X
L
X
X
H
L
NO MATCH
MATCH
H
H
H
H
H
MATCH
H
(3)
MATCH
(2)
(2)
Write Inhibit
3741 tbl 15
NOTES:
1. Pins BUSYL and BUSYR are both outputs for IDT71V30. BUSYX outputs on the
IDT71V30 are non-tristatable push-pull.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs
of this port. 'H' if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result.
BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally ignored
when BUSYR outputs are driving LOW regardless of actual logic level on the pin.
6.42
12
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
FunctionalDescription
The IDT71V30 provides two ports with separate control, address
and I/O pins that permit independent access for reads or writes to any
location in memory. The IDT71V30 has an automatic power down
featurecontrolledbyCE.TheCEcontrolson-chippowerdowncircuitry
that permits the respective port to go into a standby mode when not
selected (CE = VIH). When a port is enabled, access to the entire
memory array is permitted.
at3FEor3FFisuser-defined,sinceitisanaddressableSRAMlocation.
Iftheinterruptfunctionisnotused,addresslocations3FEand3FFarenot
usedas mailboxes, andare partofthe randomaccess memory. Refer
toTableIIfortheinterruptoperation.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
SRAM have accessed the same location at the same time. It also
allows one of the two accesses to proceed and signals the other side
that the SRAM is “Busy”. The BUSY pin can then be used to stall the
access until the operation on the other side is completed. If a write
operation has been attempted from the side that receives a BUSY
indication, the write signal is gated internally to prevent the write from
proceeding.
Interrupts
If the user chooses the interrupt function, a memory location (mail
boxormessage center)is assignedtoeachport. The leftportinterrupt
flag (INTL) is asserted when the right port writes to memory location
3FE (HEX), where a write is defined as the CE = R/W = VIL per Truth
TableII.Theleftportclearstheinterruptbyaccessingaddresslocation
3FE access with CER = OER = VIL, R/W is a "don't care". Likewise, the
right port interrupt flag (INTR) is asserted when the left port writes to
memory location 3FF (HEX) and to clear the interrupt flag (INTR), the
rightportmustaccess the memorylocation3FF. The message (8bits)
The use of BUSY logic is not required or desirable for all applica-
tions. Insome cases itmaybe usefultologicallyORthe BUSYoutputs
togetheranduseanyBUSYindicationasaninterruptsourcetoflagthe
eventofanillegalorillogicaloperation.
13
6.42
IDT71V30S/L
High-Speed 1K x 8 Dual-Port Static RAM with Interrupts
Industrial and Commercial Temperature Ranges
Ordering Information
A
IDT
XXXX
A
999
A
A
Device Type Power Speed Package
Process/
Temperature
Range
Blank
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(2)
TF
Green
64-pin STQFP (PP64-1)
25
35
55
Commercial Only
Commercial Only
Commercial Onlyl
Speed in nanoseconds
L
S
Low Power
Standard Power
71V30 8K (1K X 8-Bit) MASTER Dual-Port RAM
3741 drw 16
NOTE:
1. Industrial temperature range is available. For specific speeds, packages and powers contact your sales office.
2. Green parts available. For specific speeds, packages and powers contact your sales office.
DatasheetDocumentHistory
12/9/98:
Initiated datasheet document history
Converted to new format
Cosmetic and typographical corrections
Addedadditionalnotestopinconfigurations
Changeddrawingformat
6/15/99:
8/3/99:
Page 2 Fixed typographical error
9/1/99:
RemovedPreliminary
11/12/99:
1/17/01:
Replaced IDT logo
Pages 1 and 2 Moved all of "Description" to page 2 and adjusted page layouts
Page 3 Increasedstoragetemperatureparameters
ClarifiedTAparameter
Page 4 DCElectricalparameters–changedwordingfrom"open"to"disabled"
Changed±200mVto0mVinnotes
3/14/05:
Page 1 Added green availability to features
Page17Addedgreenindicatortoorderinginformation
Page 1 & 17 Replaced old TM logo with new TM logo
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for Tech Support:
831-754-4613
DualPortHelp@idt.com
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
14
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