71V416YS12YG3 [IDT]
Standard SRAM, 256KX16, 12ns, CMOS, PDSO44;
| 型号： | 71V416YS12YG3 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Standard SRAM, 256KX16, 12ns, CMOS, PDSO44 静态存储器 光电二极管 |
| 文件： | 总9页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS Static RAM
for Automotive Applications
4 Meg (256K x 16-Bit)
IDT71V416YS
IDT71V416YL
Description
Features
◆
TheIDT71V416isa4,194,304-bithigh-speedStaticRAMorganized
as256Kx16.ItisfabricatedusingIDT’shigh-perfomance,high-reliability
CMOStechnology.Thisstate-of-the-arttechnology,combinedwithinno-
vativecircuitdesigntechniques,providesacost-effectivesolutionforhigh-
speedmemoryneedsandautomotiveapplications.
256K x 16 advanced high-speed CMOS Static RAM
◆
JEDEC Center Power / GND pinout for reduced noise.
Equal access and cycle times
◆
– Automotive:12/15/20ns
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
◆
◆
TheIDT71V416has anoutputenablepinwhichoperates as fastas
5ns,withaddressaccesstimesasfastas10ns.Allbidirectionalinputsand
outputsoftheIDT71V416areLVTTL-compatibleandoperationisfroma
single3.3Vsupply.Fullystaticasynchronouscircuitryisused,requiring
noclocks orrefreshforoperation.
The IDT71V416 is packaged in a 44-pin, 400 mil Plastic SOJ and a
44-pin, 400 mil TSOP Type II package and a 48 ball grid array, 9mm x
9mmpackage.
LVTTL-compatible
Low power consumption via chip deselect
Upper and Lower Byte Enable Pins
Single 3.3V power supply
◆
◆
◆
◆
Available in 44-pin, 400 mil plastic SOJ package and a 44-
pin, 400 mil TSOP Type II package and a 48 ball grid array,
9mm x 9mm package.
FunctionalBlockDiagram
Output
Enable
Buffer
OE
Address
Buffers
Row / Column
Decoders
A0 - A17
High
8
8
8
8
Byte
I/O 15
I/O 8
Output
Chip
Select
Buffer
Buffer
CS
High
Byte
Write
Sense
Amps
and
Write
Drivers
4,194,304-bit
Memory
Array
Buffer
16
Write
Enable
Buffer
Low
Byte
8
8
8
8
WE
I/O 7
I/O 0
Output
Buffer
Low
Byte
Write
Buffer
BHE
BLE
Byte
Enable
Buffers
6817 drw 01
DECEMBER 2004
1
©2004 IntegratedDeviceTechnology,Inc.
DSC-6817/00
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM
for Automotive Applications 4 Meg (256K x 16-Bit)
Automotive Temperature Ranges
Pin Configurations - SOJ/TSOP
Pin Configurations - 48 BGA
A0
A1
A2
A3
A4
1
2
44
A17
A16
1
2
3
4
5
6
43
42
41
40
39
38
37
A
B
C
D
E
A0
A1
A2
NC
BLE
OE
3
A15
OE
4
I/O0
I/O1
VSS
VDD
I/O6
I/O7
NC
A3
A5
A4
A6
I/O8
I/O9
BHE
I/O2
I/O3
I/O4
I/O5
NC
CS
BHE
5
6
BLE
CS
I/O10
I/O11
I/O12
I/O13
WE
I/O 0
I/O 1
I/O 2
I/O 3
7
I/O 15
I/O 14
I/O 13
I/O 12
8
A17
NC
A14
A12
A7
VDD
VSS
9
36
35
34
33
32
31
30
29
28
27
26
25
24
23
10
11
12
13
14
15
16
17
18
19
20
21
22
SO44-1
SO44-2
A16
A15
A13
DD
V
VSS
VSS
I/O 4
I/O 5
I/O 6
I/O 7
WE
A5
VDD
F
I/O14
I/O15
I/O 11
I/O 10
I/O 9
G
H
I/O 8
NC*
A
8
A
9
A
10
A
11
NC
A14
A13
A12
6817 tbl 11
A6
PinDescriptions
A7
A8
A11
A10
A0 - A17
Address Inputs
Input
Input
Input
Input
Input
Input
I/O
A9
Chip Select
Write Enable
Output Enable
CS
WE
6817 drw 02
OE
*Pin 28 can either be a NC or connected to Vss
High Byte Enable
Low Byte Enable
Data Input/Output
3.3V Power
BHE
BLE
Top View
I/O0 - I/O15
VDD
Pwr
VSS
Ground
Gnd
6817 tbl 01
Truth Table(1)
I/O0-I/O7
High-Z
I/O8-I/O15
CS
H
L
OE
X
L
WE
X
H
H
H
L
BLE
X
L
BHE
X
H
L
Function
High-Z
High-Z
Deselected - Standby
Low Byte Read
High Byte Read
Word Read
DATAOUT
High-Z
L
L
H
L
DATAOUT
DATAOUT
DATAIN
High-Z
L
L
L
DATAOUT
DATAIN
DATAIN
High-Z
L
X
X
X
H
X
L
L
Word Write
L
L
L
H
L
Low Byte Write
High Byte Write
Outputs Disabled
Outputs Disabled
L
L
H
X
H
DATAIN
High-Z
L
H
X
X
H
High-Z
L
High-Z
High-Z
NOTE:
1. H = VIH, L = VIL, X = Don't care.
6817 tbl 03
6.422
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM
for Automotive Applications 4 Meg (256K x 16-Bit)
Automotive Temperature Ranges
AbsoluteMaximumRatings(1)
RecommendedOperating
TemperatureandSupply
Voltage
Symbol
Rating
Value
Unit
V
Supply Voltage Relative to
VSS
VDD
-0.5 to +4.6
-0.5 to VDD+0.5
Grade
Temperature
-40°C to +125°C
-40°C to +105°C
-40°C to +85°C
0°C to +70°C
VSS
0V
0V
0V
0V
VDD
Terminal Voltage Relative to
VSS
V
Automotive Grade 1
Automotive Grade 2
Automotive Grade 3
Automotive Grade 4
See Below
See Below
See Below
VIN, VOUT
TBIAS
TJ
Temperature Under Bias
Junction Temperature Range
Storage Temperature
Power Dissipation
-55 to +125
-40 to +150
-65 to +150
1
oC
oC
oC
W
See Below
TSTG
PT
6817 tbl 05
RecommendedDCOperating
Conditions
IOUT
DC Output Current
50
mA
6817 tbl 04
NOTE:
Symbol
Parameter
Supply Voltage
Ground
Min.
3.0
0
Typ.
3.3
0
Max.
Unit
V
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
VDD
3.6
0
VSS
V
(1)
____
VDD+0.3
0.8
VIH
VIL
Input High Voltage
Input Low Voltage
2.0
V
(1)
____
-0.3
V
SOJ/TSOPCapacitance
(TA = +25°C, f = 1.0MHz)
6817 tbl 06
NOTE:
1. Refer to maximum overshoot/undershoot diagram below. The measured
voltage at device pin must not exceed half sinusoidal wave with 2V peak and
half period of 2ns.
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
7
8
pF
CI/O
pF
MaximumOvershoot/Undershoot
6817 tbl 02
+2V
48BGACapacitance
V
IH
2ns
(TA = +25°C, f = 1.0MHz)
Symbol
CIN
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
VIN = 3dV
VOUT = 3dV
Max. Unit
2ns
IL
V
6
7
pF
-2V
6817 drw 12
CI/O
pF
6817 tbl 02b
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
6.42
3
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM
for Automotive Applications 4 Meg (256K x 16-Bit)
Automotive Temperature Ranges
DC Electrical Characteristics
(VDD = Min. to Max., Automotive Temperature Ranges)
Automotive
Temperature
Grade
IDT71V416
Symbol
Parameter
Input Leakage Current
Test Conditions
Min.
Max.
Unit
___
___
___
___
___
1 and 2
3 and 4
1 and 2
3 and 4
5
1
5
1
|ILI|
VDD = Max., VIN = VSS to VDD
µA
|ILO|
Output Leakage Current
VDD = Max., CS = VIH, VOUT = VSS to VDD
µA
V
VOL
VOH
Output Low Voltage
Output High Voltage
IOL = 8mA, VDD = Min.
IOH = -4mA, VDD = Min.
0.4
___
2.4
V
6817 tbl 07
DC Electrical Characteristics(1, 2, 3)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V, Automotive Temperature Ranges)
71V416S/L12
71V416S/L15
Automotive Grade
71V416S/L20
Automotive Grade
Symbol
Parameter
Automotive Grade
Unit
1
2
3 and 4
1
2
3 and 4
1
2
3 and 4
S
L
Max.
Max.
130
120
120
110
110
100
125
115
115
105
105
95
120
110
110
100
100
90
Dynamic Operating Current
CS < VLC, Outputs Open, VDD = Max., f = fMAX
CC
I
mA
mA
(3)
Ty p . (4)
85
85
85
80
80
80
80
80
80
S
L
S
L
Max.
Max.
Max.
65
50
20
10
65
50
20
10
65
45
20
10
55
45
20
10
55
45
20
10
50
40
20
10
50
40
20
10
50
40
20
10
50
40
20
10
Dynamic Standby Power Supply Current
CS > VHC, Outputs Open, VDD = Max., f = fMAX
SB
I
(3)
Full Standby Power Supply Current (static)
CS > VHC, Outputs Open, VDD = Max., f = 0
SB1
I
mA
(3)
IDT71V416S/71MVax4. 16L
6817 tbl 8
NOTES:
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and VDD -0.2V (High).
3. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
4. Typical values are measured at 3.3V, 25oC and with equal read and write cycles. This parameter is guaranteed by device characterization but is not production tested.
3.3V
AC Test Loads
+1.5V
320
50
OUT
DATA
I/O
Z = 50
0
5pF*
350
30pF
6817 drw 03
6817 drw 04
Figure 1. AC Test Load
*Including jig and scope capacitance.
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
7
6
5
4
3
tAA, tACS
(Typical, ns)
AC Test Conditions
Input Pulse Levels
GND to 3.0V
1.5ns
2
1
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
1.5V
1.5V
180
8 20 40 60 80 100 120 140 160
CAPACITANCE (pF)
200
6817 drw 05
Figures 1,2 and 3
Figure 3. Output Capacitive Derating
6817 tbl 09
6.442
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM
for Automotive Applications 4 Meg (256K x 16-Bit)
Automotive Temperature Ranges
AC Electrical Characteristics
(VDD = Min. to Max., Automotive Temperature Ranges)
71V416S/L12
71V416S/L15
71V416S/L20
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
tRC
Read Cycle Time
12
15
20
ns
ns
ns
ns
____
____
____
tAA
tACS
Address Access Time
12
15
20
____
____
____
Chip Select Access Time
Chip Select Low to Output in Low-Z
12
15
20
____
____
____
(1,2)
4
4
4
tCLZ
____
____
____
(1,2)
Chip Select High to Output in High-Z
Output Enable Low to Output Valid
Output Enable Low to Output in Low-Z
6
7
8
ns
ns
ns
tCHZ
____
____
____
tOE
6
7
8
____
____
____
(1,2)
0
0
0
tOLZ
____
____
____
(1,2)
Output Enable High to Output in High-Z
Output Hold from Address Change
Byte Enable Low to Output Valid
Byte Enable Low to Output in Low-Z
6
7
8
ns
ns
ns
ns
tOHZ
tOH
tBE
4
—
4
—
4
—
____
—
6
—
7
8
____
____
____
(1,2)
0
0
0
tBLZ
____
____
____
(1,2)
Byte Enable High to Output in High-Z
Chip Select Low to Power Up
6
7
8
ns
ns
ns
tBHZ
____
____
____
(3)
0
0
0
tPU
____
____
____
(3)
Chip Select High to Power Down
12
15
20
tPD
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
tWC
tAW
tCW
tBW
tAS
Write Cycle Time
12
8
8
8
0
0
8
6
0
15
10
10
10
0
20
10
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End of Write
Chip Select Low to End of Write
Byte Enable Low to End of Write
Address Set-up Time
tWR
tWP
tDW
tDH
Address Hold from End of Write
Write Pulse Width
0
0
10
7
10
8
Data Valid to End of Write
Data Hold Time
0
0
____
____
____
(1,2)
Write Enable High to Output in Low-Z
3
3
3
tOW
____
____
____
(1,2)
Write Enable Low to Output in High-Z
7
7
8
ns
tWHZ
6817 tbl 10
NOTES:
1. At any given temperature and voltage condition, tCHZ is less than tCLZ, tOHZ is less than tOLZ, and tWHZ is less than tOW for any given device.
2. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
3. This parameter is guaranteed by design and not production tested.
Timing Waveform of Read Cycle No. 1(1,2,3)
t
RC
ADDRESS
t
AA
t
OH
t
OH
DATAO U T VALID
6 81 7 d 06
DATAOUT
NOTES:
PREVIOUS DATAOUT VALID
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. OE, BHE, and BLE are LOW.
6.42
5
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM
for Automotive Applications 4 Meg (256K x 16-Bit)
Automotive Temperature Ranges
Timing Waveform of Read Cycle No. 2(1)
t
RC
ADDRESS
OE
t
AA
t
OH
(3)
t
OHZ
t
OE
(3)
t
OLZ
CS
(2)
t
ACS
(3)
(3)
(3)
t
CHZ
t
CLZ
BLE
,
BHE
(2)
t
BE
(3)
t
BHZ
t
BLZ
DATAOUT
DATAOUT VALID
t
PD
t
PU
I
CC
V
DD
Supply
Current
I
SB
6817 drw 07
NOTES:
1. WE is HIGH for Read Cycle.
2. Address must be valid prior to or coincident with the later of CS, BHE, or BLE transition LOW; otherwise tAA is the limiting parameter.
3. Transition is measured ±200mV from steady state.
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1,2,4)
t
WC
ADDRESS
CS
t
AW
(2)
(5)
(5)
t
CW
t
CHZ
t
BW
BHE
,
BLE
WE
t
WR
t
BHZ
t
WP
t
AS
(5)
t
WHZ
(5)
OW
t
(3)
DATAOUT
DATAIN
PREVIOUS DATA VALID
DATA VALID
t
DH
DW
t
DATAIN VALID
6817 drw 08
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. OE is continuously HIGH. If during a WE controlled write cycle OE is LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is as
short as the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
5. Transition is measured ±200mV from steady state.
6.462
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM
for Automotive Applications 4 Meg (256K x 16-Bit)
Automotive Temperature Ranges
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1,3)
t
WC
ADDRESS
CS
t
AW
(2)
t
AS
t
CW
t
BW
BHE, BLE
WE
t
WP
t
WR
DATAOUT
DATAIN
t
DATAIN VALID
DH
t
DW
6817 d09
Timing Waveform of Write Cycle No. 3
(BHE, BLE Controlled Timing)(1,3)
t
WC
ADDRESS
CS
t
AW
(2)
t
CW
t
AS
t
BW
BHE, BLE
t
WP
t
WR
WE
DATAOUT
t
DATAIN VALID
DH
t
DW
DATAIN
6817 d10
NOTES:
1. A write occurs during the overlap of a LOW CS, LOW BHE or BLE, and a LOW WE.
2. During this period, I/O pins are in the output state, and input signals must not be applied.
3. If the CS LOW or BHE and BLE LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high-impedance state.
6.42
7
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM
for Automotive Applications 4 Meg (256K x 16-Bit)
Automotive Temperature Ranges
OrderingInformation
IDT
71V416
X
X
XX
XXX
X
X
Device
Type
Power
Speed
Package
Process/
Temperature
Range
1
2
3
4
Automotive Grade 1 (-40°C to +125°C)
Automotive Grade 2 (-40°C to +105°C)
Automotive Grade 3 (-40°C to +85°C)
Automotive Grade 4 (0°C to +70°C)
G
Restricted hazardous substance device
Y
PH
BE
44-pin, 400-mil SOJ (SO44-1)
44-pin TSOP Type II (SO44-2)
48 Ball Grid Array
12
15
20
Speed in nanoseconds
S
L
Standard Power
Low Power
Y
Y die stepping
6817 drw 11a
6.482
IDT71V416YS, IDT71V416YL 3.3V CMOS Static RAM
for Automotive Applications 4 Meg (256K x 16-Bit)
Automotive Temperature Ranges
DatasheetDocumentHistory
Rev
Date
Page
Description
0
12/17/04
p. 1-8
ReleasedAutomotivedatasheet
CORPORATE HEADQUARTERS
2975StenderWay
Santa Clara, CA 95054
for SALES:
for Tech Support:
sramhelp@idt.com
800-544-7726
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
9
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