71V424L12YG [IDT]
3.3V CMOS Static RAM;
| 型号： | 71V424L12YG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3V CMOS Static RAM |
| 文件： | 总9页 (文件大小：72K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT71V424S
IDT71V424L
3.3V CMOS Static RAM
4 Meg (512K x 8-Bit)
Features
Description
◆
512K x 8 advanced high-speed CMOS Static RAM
JEDEC Center Power / GND pinout for reduced noise
Equal access and cycle times
TheIDT71V424isa4,194,304-bithigh-speedStaticRAMorganized
as512Kx8.Itisfabricatedusinghigh-perfomance,high-reliabilityCMOS
technology.Thisstate-of-the-arttechnology,combinedwithinnovative
circuitdesigntechniques,providesacost-effectivesolutionforhigh-speed
memoryneeds.
◆
◆
— CommercialandIndustrial:10/12/15ns
Single 3.3V power supply
One Chip Select plus one Output Enable pin
Bidirectional data inputs and outputs directly
TTL-compatible
Low power consumption via chip deselect
Available in 36-pin, 400 mil plastic SOJ package and
44-pin, 400 mil TSOP.
◆
◆
◆
TheIDT71V424hasanoutputenablepinwhichoperatesasfastas
5ns,withaddressaccesstimesasfastas10ns.Allbidirectionalinputsand
outputs of the IDT71V424 are TTL-compatible and operation is from a
single3.3Vsupply.Fullystaticasynchronouscircuitryisused,requiring
no clocks or refresh for operation.
◆
◆
TheIDT71V424ispackagedina36-pin,400milPlasticSOJand44-
pin, 400milTSOP.
FunctionalBlockDiagram
A0
•
•
•
•
4,194,304-BIT
MEMORY ARRAY
ADDRESS
DECODER
•
•
A18
8
8
I/O0 - I/O7
I/O CONTROL
8
WE
OE
CS
CONTROL
LOGIC
3622 drw 01
SEPTEMBER 2013
1
©2013IntegratedDeviceTechnology,Inc.
DSC-3622/10
IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
PinConfiguration
PinConfiguration
NC
NC
NC
NC
A0
A1
1
2
44
43
A0
A1
A2
A3
A4
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
A18
A17
A16
A15
OE
3
NC
42
41
A18
A17
4
A2
A3
A4
5
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A16
A15
6
I/O 7
I/O 6
I/O 0
I/O 1
7
8
CS
OE
SO36-1
VDD
V
V
SS
DD
I/00
I/01
9
I/07
I/06
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
I/O 2
I/O 3
WE
I/O 5
I/O 4
A14
A13
A12
A11
A10
NC
SO44-2
V
V
DD
SS
V
V
SS
DD
A5
A6
A7
A8
A9
I/02
I/03
I/05
I/04
A14
WE
A5
A6
A13
A12
A7
A8
A9
NC
NC
A11
A10
NC
3622 drw 02
SOJ
Top View
NC
NC
3622 drw 11
TSOP
Top View
PinDescription
Capacitance
(TA = +25°C, f = 1.0MHz, SOJ package)
A
0
– A18
Address Inputs
Input
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
Chip Select
Input
Input
Input
I/O
CS
C
IN
V
7
8
pF
Write Enable
Output Enable
Data Input/Output
3.3V Power
Ground
WE
OE
C
I/O
V
pF
3622 tbl 03
I/O0 - I/O7
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
V
V
DD
SS
Power
Gnd
3622 tbl 02
Truth Table(1,2)
CS
OE
WE
I/O
Function
L
L
H
DATAOUT Read Data
DATAIN Write Data
High-Z Output Disabled
L
X
L
L
H
X
H
H
X
High-Z Deselected - Standby (ISB
)
(3)
X
X
High-Z Deselected - Standby (ISB1)
V
HC
3622 tbl 01
NOTES:
1. H = VIH, L = VIL, x = Don't care.
2. VLC = 0.2V, VHC = VDD -0.2V.
3. Other inputs ≥VHC or ≤VLC.
6.242
IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
AbsoluteMaximumRatings(1)
RecommendedOperating
TemperatureandSupplyVoltage
Symbol
Rating
Value
Unit
Grade
Commercial
Industrial
Temperature
0°C to +70°C
–40°C to +85°C
V
SS
VDD
VDD
Supply Voltage Relative to
-0.5 to +4.6
V
0V
0V
See Below
See Below
VSS
Terminal Voltage Relative
to VSS
-0.5 to VDD+0.5
V
VIN, VOUT
3622 tbl 05
T
T
P
BIAS
STG
T
Temperature Under Bias
Storage Temperature
Power Dissipation
-55 to +125
oC
oC
W
RecommendedDCOperating
Conditions
-55 to +125
1
Symbol
Parameter
Min.
Typ.
Max.
3.6
Unit
V
I
OUT
DC Output Current
50
mA
V
DD
SS
IH
IL
Supply Voltage
3.0
3.3
3622 tbl 04
NOTE:
V
Ground
0
0
0
V
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
____
V
Input High Voltage
Input Low Voltage
2.0
V
DD+0.3(1)
0.8
V
-0.3(2)
V
____
V
3622 tbl 06
NOTES:
1. VIH (max.) = VDD+2V for pulse width less than 5ns, once per cycle.
2. VIL (min.) = –2V for pulse width less than 5ns, once per cycle.
DC Electrical Characteristics
(VDD = Min. to Max., Commercial and Industrial Temperature Ranges)
IDT71V424
Symbol
|ILI
|ILO
Parameter
Input Leakage Current
Test Condition
DD = Max., VIN = VSS to VDD
Min.
Max. Unit
___
|
V
V
5
5
µA
µA
V
___
___
|
Output Leakage Current
Output Low Voltage
Output High Voltage
DD = Max., CS = VIH, VOUT = VSS to VDD
VOL
I
I
OL = 8mA, VDD = Min.
OH = -4mA, VDD = Min.
0.4
___
VOH
2.4
V
3622 tbl 07
DC Electrical Characteristics(1, 2, 3)
(VDD = Min. to Max., VLC = 0.2V, VHC = VDD – 0.2V)
71V424S/L 10
Com'l. Ind.
71V424S/L 12
71V424S/L 15
Unit
Symbol
Parameter
Dynamic Operating Current
Com'l.
Ind.
170
155
55
Com'l.
Ind.
160
145
50
S
L
S
L
S
L
180
165
60
180
165
60
170
155
55
160
145
50
mA
mA
mA
mA
mA
ICC
(4)
CS < VLC, Outputs Open, VDD = Max., f = fMAX
Dynamic Standby Power Supply Current
ISB
CS > VHC, Outputs Open, VDD = Max., f = fMAX(4)
55
55
50
50
45
45
20
20
20
20
20
20
Full Standby Power Supply Current (static)
ISB1
CS > VHC, Outputs Open, VDD = Max., f = 0(4)
10
10
10
10
10
10
mA
3622 tbl 08
NOTES:
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and VDD - 0.2V (High).
3. Power specifications are preliminary.
4. fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
6.42
3
IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
1.5ns
1.5V
1.5V
See Figure 1, 2 and 3
3622 tbl 09
AC Test Loads
3.3V
+1.5V
50Ω
320Ω
I/O
Z0 = 50Ω
OUT
DATA
30pF
5pF*
350Ω
3622 drw 03
3622 drw 04
*Including jig and scope capacitance.
Figure 1. AC Test Load
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
7
6
•
ΔtAA,
t
ACS
5
4
3
(Typical, ns)
•
•
2
1
•
•
•
•
180
8 20 40 60 80 100 120 140 160
CAPACITANCE (pF)
200
3622 drw 05
Figure 3. Output Capacitive Derating
6.42
IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VCC = 3.3V ± 10%, Commercial and Industrial Temperature Ranges)
71V424S/L10
71V424S/L12
71V424S/L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
____
____
____
t
RC
AA
ACS
Read Cycle Time
10
12
15
ns
ns
ns
ns
____
____
____
t
Address Access Time
Chip Select Access Time
Chip Select to Output in Low-Z
10
12
15
____
____
____
t
10
12
15
____
____
____
(1)
CLZ
4
4
4
t
____
____
____
(1)
Chip Deselect to Output in High-Z
Output Enable to Output Valid
5
6
7
ns
ns
ns
ns
ns
ns
ns
t
CHZ
____
____
____
tOE
5
6
7
(1)
(1)
____
____
____
Output Enable to Output in Low-Z
Output Disable to Output in High-Z
Output Hold from Address Change
Chip Select to Power Up Time
Chip Deselect to Power Down Time
0
0
0
tOLZ
____
____
____
5
6
7
t
OHZ
____
____
____
tOH
4
4
4
____
____
____
(1)
PU
0
0
0
t
____
____
____
(1)
PD
10
12
15
t
WRITE CYCLE
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
WC
AW
CW
AS
WP
WR
DW
DH
Write Cycle Time
10
8
12
8
15
10
10
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
Address Valid to End of Write
Chip Select to End of Write
Address Set-up Time
Write Pulse Width
t
8
8
t
0
0
t
8
8
10
0
t
Write Recovery Time
Data Valid to End of Write
Data Hold Time
0
0
t
6
6
7
t
0
0
0
____
____
____
(1)
OW
Output Active from End of Write
3
3
3
t
(1)
WHZ
____
____
____
Write Enable to Output in High-Z
6
7
7
ns
t
3622 tbl 10
NOTE:
1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
6.42
5
IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle No. 1(1)
tRC
ADDRESS
OE
t
AA
tOE
(5)
tOLZ
CS
(3)
tACS
(5)
(5)
tOHZ
tCLZ
(5)
tCHZ
HIGH IMPEDANCE
DATAOUT
DATAOUT VALID
t
PD
t
PU
I
I
CC
SB
V
CC SUPPLY
CURRENT
3622 drw 06
Timing Waveform of Read Cycle No. 2(1, 2, 4)
t
RC
ADDRESS
DATAOUT
tAA
t
OH
tOH
PREVIOUS DATAOUT VALID
DATAOUT VALID
3622 drw 07
NOTES:
1. WE is HIGH for Read Cycle.
2. Device is continuously selected, CS is LOW.
3. Address must be valid prior to or coincident with the later of CS transition LOW; otherwise tAA is the limiting parameter.
4. OE is LOW.
5. Transition is measured ±200mV from steady state.
6.642
IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (WE Controlled Timing)(1, 2, 4)
t
WC
ADDRESS
t
AW
CS
t
WR
(2)
tAS
t
WP
WE
(5)
tCHZ
(5)
(5)
t
WHZ
tOW
HIGH IMPEDANCE
DATAOUT
DATAIN
(3)
(3)
tDH
t
DW
DATAIN VALID
3622 drw 08
Timing Waveform of Write Cycle No. 2 (CS Controlled Timing)(1, 4)
tWC
ADDRESS
tAW
CS
tAS
tCW
tWR
WE
tDW
tDH
DATAIN
DATAIN VALID
3622 drw 09
NOTES:
1. A write occurs during the overlap of a LOW CS and a LOW WE.
2. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and
data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse
is the specified tWP.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the CS LOW transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS must be active during the tCW
write period.
5. Transition is measured ±200mV from steady state.
6.42
7
IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
OrderingInformation
71V424
X
XX
XXX
X
X
X
Device
Type
Power Speed Package
Process/
Temperature
Range
Blank Tube or Tray
8
Tape and Reel
Commercial (0°C to +70°C)
Industrial (–40°C to +85°C)
Blank
I
G
Green
Y
PH
36-pin 400 mil SOJ (SO36-1)
44-pin TSOP Type II (SO44-2)
10
12
15
Speed in nanoseconds
S
L
Standard Power
Low Power
3622 drw 10
6.842
IDT71V424S, IDT71V424L, 3.3V CMOS Static RAM
4 Meg (512K x 8-bit)
Commercial and Industrial Temperature Ranges
DatasheetDocumentHistory
8/13/99
Updatedtonewformat
Pg. 2
Pg. 7
RemovedSO44-1fromTSOPpinout
RevisedfootnotesonWriteCycleNo. 1diagram
RemovedfootnotefortWR onWriteCycleNo. 2diagram
Pg. 9
Pg. 1–9
Pg. 8
Pg. 8
Pg. 3
AddedDatasheetDocumentHistory
AddedIndustrialtemperaturerangeofferings
Addeddierevisionoptiontoorderinginformation
Updatednote, L10speedgradecommercialtemperatureonlyandupdateddiesteppingfromYFtoY.
Increased ISB for all "L" and S15 speeds by 10mA and increased for S12 speed by 5mA (refer to
PCN# SR-0402-02).
8/31/99
11/22/02
07/31/03
07/28/04
Pg. 8
Pg. 1, 8
Added"Restrictedhazardoussubstancedevice"totheorderinginformation.
Added Y and V step part numbers to front page and ordering information. Updated the ordering
informationbyremovingthe“IDT”notation.
09/20/08
05/12/09
06/11/09
09/26/13:
Pg. 3,5,8
Pg.1,8
Pg.1-9
Pg.1
Add Industrial grade for 10ns Low Power.
RemovedVS,VLfromdatasheetandorderinginformation.
Removedthe/YS&/YLfromthedevicenamefortheentiredatasheet.
RemovedIDT'sreferencetofabrication.
Pg.8
UpdatedorderinginformationbyaddingT&R,updatedRestrictedHazardousSubstanceDevice
wording to Green and removed the Die Stepping Revision, the”Y” designator.
for Tech Support:
sramhelp@idt.com
408-284-4532
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or
408-284-8200
fax: 408-284-2775
www.idt.com
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
6.42
9
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