71V65803Z150BQGI [IDT]
3.3V Synchronous ZBT SRAMs;型号: | 71V65803Z150BQGI |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | 3.3V Synchronous ZBT SRAMs 静态存储器 |
文件: | 总26页 (文件大小:368K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
256K x 36, 512K x 18
3.3V Synchronous ZBT™ SRAMs
ZBT™ Feature
IDT71V65603/Z
IDT71V65803/Z
3.3V I/O, Burst Counter
Pipelined Outputs
AddressandcontrolsignalsareappliedtotheSRAMduringoneclock
cycle,andtwocycleslatertheassociateddatacycleoccurs,beitreadorwrite.
TheIDT71V65603/5803containdataI/O,addressandcontrolsignal
registers.Outputenableistheonlyasynchronoussignalandcanbeused
todisabletheoutputsatanygiventime.
A Clock Enable (CEN) pin allows operation of the IDT71V65603/5803
tobesuspendedaslongasnecessary.Allsynchronousinputsareignored
when(CEN)ishighandtheinternaldeviceregisterswillholdtheirprevious
values.
Therearethreechipenablepins(CE1, CE2, CE2)thatallowtheuser
to deselect the device when desired. If any one of these three are not
asserted when ADV/LD is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will be
completed. The data bus will tri-state two cycles after chip is deselected
or a write is initiated.
TheIDT71V65603/5803haveanon-chipburstcounter.Intheburst
mode, the IDT71V65603/5803 can provide four cycles of data for a
single address presented to the SRAM. The order of the burst
sequence is defined by the LBO input pin. The LBO pin selects
between linear and interleaved burst sequence. The ADV/LD signal is
used to load a new external address (ADV/LD = LOW) or increment
the internal burst counter (ADV/LD = HIGH).
Features
◆
256K x 36, 512K x 18 memory configurations
◆
Supports high performance system speed - 150MHz
(3.8ns Clock-to-Data Access)
◆
ZBTTM Feature - No dead cycles between write and read cycles
◆
Internally synchronized output buffer enable eliminates the
need to control OE
Single R/W (READ/WRITE) control pin
Positive clock-edge triggered address, data, and control signal
◆
◆
registers for fully pipelined applications
4-word burst capability (interleaved or linear)
Individual byte write (BW1 - BW4) control (May tie active)
Three chip enables for simple depth expansion
3.3V power supply (±5%)
3.3V I/O Supply (VDDQ)
Power down controlled by ZZ input
Packaged in a JEDEC standard 100-pin plastic thin quad
◆
◆
◆
◆
◆
◆
◆
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array(fBGA).
Description
The IDT71V65603/5803 are 3.3V high-speed 9,437,184-bit
(9Megabit)synchronousSRAMS.Theyaredesignedtoeliminatedeadbus
cycleswhenturningthebusaroundbetweenreadsandwrites, orwritesand
reads. Thus, they have been given the name ZBTTM, or Zero Bus Turn-
around.
The IDT71V65603/5803 SRAM utilize IDT's latest high-performance
CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and 165 fine pitch ball grid array (fBGA) .
Pin Description Summary
A
0-A18
Address Inputs
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Chip Enables
CE1
, CE
2
, CE
2
Output Enable
OE
R/W
Read/Write Signal
Clock Enable
CEN
Individual Byte Write Selects
Clock
BW
1
, BW
2
, BW
3
, BW
4
CLK
ADV/LD
LBO
Advance burst address / Load new address
Linear / Interleaved Burst Order
Sleep Mode
Synchronous
Static
ZZ
Asynchronous
Synchronous
Static
I/O
0
-I/O31, I/OP1-I/OP4
Data Input / Output
Core Power, I/O Power
Ground
V
V
DD, VDDQ
SS
Supply
Supply
Static
5304 tbl 01
ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.
OCTOBER 2008
1
©2008 Integrated Device Technology, Inc.
DSC-5304/08
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Definitions(1)
Symbol
Pin Function
I/O
Active
Description
A
0-A18
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination of the
rising edge of CLK, ADV/LD low, CEN low, and true chip enables.
ADV/LD
Advance / Load
I
N/A
ADV/LD is a synchronous input that is used to load the internal registers with new address
and control when it is sampled low at the rising edge of clock with the chip selected. When
ADV/LD is low with the chip deselected, any burst in progress is terminated. When ADV/LD
is sampled high then the internal burst counter is advanced for any burst that was in
progress. The external addresses are ignored when ADV/LD is sampled high.
R/W
Read / Write
Clock Enable
I
I
N/A
R/W signal is a synchronous input that identifies whether the current load cycle initiated is a
Read or Write access to the memory array. The data bus activity for the current cycle takes
place two clock cycles later.
LOW
Synchronous Clock Enable Input. When CEN is sampled high, all other synchronous
inputs, including clock are ignored and outputs remain unchanged. The effect of CEN
sampled high on the device outputs is as if the low to high clock transition did not occur.
For normal operation, CEN must be sampled low at rising edge of clock.
CEN
Individual Byte
Write Enables
I
I
LOW
LOW
Synchronous byte write enables. Each 9-bit byte has its own active low byte write enable.
BW
1
-BW
4
On load write cycles (When R/W and ADV/LD are sampled low) the appropriate byte write
signal (BW1-BW4) must be valid. The byte write signal must also be valid on each cycle of
a burst write. Byte Write signals are ignored when R/W is sampled high. The appropriate
byte(s) of data are written into the device two cycles later. BW -BW can all be tied low if
always doing write to the entire 36-bit word.
1
4
Chip Enables
Synchronous active low chip enable. CE and CE
1
2
are used with CE
2
2 to enable the
CE1
, CE
2
IDT71V65603/5803. (CE
1
or CE
2
sampled high or CE sampled low) and ADV/LD low at the
rising edge of clock, initiates a deselect cycle. The ZBTTM has a two cycle deselect, i.e.,
the data bus will tri-state two clock cycles after deselect is initiated.
CE
2
Chip Enable
Clock
I
I
HIGH Synchronous active high chip enable. CE
2
is used with CE
1
and CE2 to enable the chip.
CE2 has inverted polarity but otherwise identical to CE
1
and CE2.
CLK
N/A
N/A
This is the clock input to the IDT71V65603/5803. Except for OE, all timing references for the
device are made with respect to the rising edge of CLK.
I/O0-I/O31
Data Input/Output
Linear Burst Order
I/O
I
Synchronous data input/output (I/O) pins. Both the data input path and data output path are
registered and triggered by the rising edge of CLK.
I/OP1-I/OP4
LOW
Burst order selection input. When LBO is high the Interleaved burst sequence is selected.
When LBO is low the Linear burst sequence is selected. LBO is a static input and it must
not change during device operation.
LBO
Output Enable
Sleep Mode
I
I
LOW
N/A
Asynchronous output enable. OE must be low to read data from the 71V65603/5803. When
OE is high the I/O pins are in a high-impedance state. OE does not need to be actively
controlled for read and write cycles. In normal operation, OE can be tied low.
OE
ZZ
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
71V65603/5803 to its lowest power consumption level. Data retention is guaranteed in
Sleep Mode.
V
DD
DDQ
SS
Power Supply
Power Supply
Ground
N/A
N/A
N/A
N/A
N/A
N/A
3.3V core power supply.
3.3V I/O Supply.
V
V
Ground.
5304tbl 02
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
6.242
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Functional Block Diagram
512x18 BIT
LBO
MEMORY ARRAY
Address
Address A [0:18]
D
D
Q
Q
CE1, CE2, CE2
R/W
CEN
Control
ADV/LD
BW x
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
D
Output Register
Q
Clock
Gate
O E
5304 drw 01
,
Data I/O [0:15],
I/O P[1:2]
6.42
3
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Functional Block Diagram
512x18 BIT
LBO
MEMORY ARRAY
Address
Address A [0:18]
D
D
Q
Q
CE1, CE2, CE2
R/W
CEN
Control
ADV/LD
BW x
DI
DO
D
Q
Control Logic
Clk
Mux
Sel
D
Output Register
Q
Clock
Gate
O E
5304 drw 01
,
Data I/O [0:15],
I/O P[1:2]
Recommended DC Operating
Conditions
Symbol
Parameter
Core Supply Voltage
I/O Supply Voltage
Supply Voltage
Min.
3.135
3.135
0
Typ.
Max.
3.465
3.465
0
Unit
V
V
DD
DDQ
SS
3.3
V
3.3
V
V
0
V
____
V
IH
IH
IL
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
2.0
V
DD+0.3
V
____
____
V
2.0
V
DDQ+0.3
0.8
V
V
-0.3(1)
V
5304 tbl 04
NOTES:
1. VIL (min.) = –1.0V for pulse width less than tCYC/2, once per cycle.
6.442
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Recommended Operating
Temperature and Supply Voltage
Grade
Ambient
V
SS
V
DD
VDDQ
Temperature(1)
Commercial
Industrial
0° C to +70° C
-40°C to +85°C
0V
0V
3.3V±5%
3.3V±5%
3.3V±5%
3.3V±5%
5304 tbl 05
NOTES:
1. During production testing, the case temperature equals the ambient temperature.
Pin Configuration - 256K x 36
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
1
80
I/OP3
I/O16
I/O17
I/OP2
I/O15
I/O14
2
79
3
78
4
77
VDDQ
VDDQ
5
VSS
76
75
74
73
VSS
6
I/O18
I/O19
I/O20
I/O21
I/O13
I/O12
I/O11
I/O10
7
8
9
72
71
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
VSS
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDQ
VDDQ
I/O22
I/O9
I/O8
I/O23
(1)
VDD
V
SS
(1)
V
DD
DD
VDD
(1)
V
VDD
VSS
ZZ
I/O
I/O
I/O24
I/O25
7
6
VDDQ
V
V
DDQ
SS
VSS
I/O26
I/O27
I/O28
I/O29
I/O
I/O
I/O
I/O
5
4
3
2
VSS
VSS
VDDQ
VDDQ
I/O30
I/O31
I/OP4
I/O
I/O
1
0
I/OP1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
5304 drw 02
,
Top View
100 TQFP
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is ≥ VIH.
2. Pin 84 is reserved for a future 16M.
3. DNU=Do not use. Pins 38, 39, 42 and 43 are reserved for respective JTAG pins: TMS, TDI, TDO and TCK. The current die
revision allows these pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
6.42
5
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Pin Configuration - 512K x 18
Commercial &
Symbol
Rating
Unit
Industrial
(2)
V
V
V
V
TE RM
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
1
80
NC
NC
NC
DDQ
A
NC
NC
10
2
79
78
77
(3,6)
(4,6)
(5,6)
TE RM
TE RM
TE RM
Terminal Voltage with
Respect to GND
-0.5 to VDD
-0.5 to VDD +0.5
-0.5 to VDDQ +0.5
-0 to +70
V
V
3
4
V
V
VDDQ
5
SS
76
75
74
73
VSS
6
NC
NC
NC
I/OP1
I/O
Terminal Voltage with
Respect to GND
7
8
I/O8
7
9
I/O9
72
71
I/O
6
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
SS
VSS
Terminal Voltage with
Respect to GND
V
70
69
68
67
66
65
64
63
62
61
60
59
VDDQ
VDDQ
I/O10
I/O11
I/O
I/O
5
4
(1)
oC
V
DD
V
V
SS
Commercial
Operating Temperature
(1)
VDD
DD
A(7)
(1)
V
DD
VDD
T
VSS
ZZ
I/O
I/O
I/O12
I/O13
3
Industrial
Operating Temperature
-40 to +85
oC
oC
2
VDDQ
V
V
DDQ
SS
VSS
Temperature
Under Bias
-55 to +125
TBIAS
I/O14
I/O15
I/OP2
NC
I/O
I/O
NC
NC
1
0
58
57
56
55
Storage
Temperature
-55 to +125
oC
TSTG
VSS
VSS
54
53
V
DDQ
NC
NC
NC
VDDQ
NC
NC
NC
52
51
P
T
Power Dissipation
DC Output Current
2.0
50
W
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
,
IOUT
mA
5304 drw 02a
5304 tbl 06
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. VDD terminals only.
3. VDDQ terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary; however,
the voltage on any input or I/O pin cannot exceed VDDQ during power supply ramp
up.
Top View
100 TQFP
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the
input voltage is ≥ VIH.
2. Pin 84 is reserved for a future 16M.
3. DNU=Do not use. Pins 38, 39, 42 and 43 are reserved for respective JTAG
pins: TMS, TDI, TDO and TCK. The current die revision allows these pins to be
left unconnected, tied LOW (VSS), or tied HIGH (VDD).
7. During production testing, the case temperature equals TA.
100 TQFP Capacitance(1)
165 fBGA Capacitance(1)
(TA = +25° C, f = 1.0MHz)
(TA = +25° C, f = 1.0MHz)
Parameter(1 )
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
Symbol
Parameter(1)
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
Symbol
CIN
V
5
7
pF
CIN
V
TBD
TBD
pF
CI/O
V
pF
CI/O
V
pF
5304 tbl 07
5304 tbl 07b
119 BGA Capacitance(1)
(TA = +25° C, f = 1.0MHz)
Symbol
Parameter(1 )
Input Capacitance
I/O Capacitance
Conditions
IN = 3dV
OUT = 3dV
Max. Unit
CIN
V
7
7
pF
CI/O
V
pF
5304 tbl 07a
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
6.642
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration - 256K X 36, 119 BGA
1
2
3
4
5
6
7
(2)
NC
DDQ
6
4
8
16
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
A
A
2
3
2
9
NC
NC
CE
NC
NC
2
CE
ADV/LD
7
DD
12
15
A
A
V
A
16
I/O
P3
I/O
SS
SS
SS
SS
SS
SS
P2
I/O
15
I/O
V
V
V
NC
V
V
V
17
I/O
18
I/O
13
I/O
14
I/O
1
CE
DDQ
20
19
I/O
12
I/O
DDQ
10
V
V
OE
21
I/O
11
I/O
G
H
J
I/O
A17
I/O
BW
2
3
BW
22
I/O
23
I/O
SS
SS
V
9
I/O
8
I/O
V
V
V
R/W
DDQ
V
DD
DD
V
DD
V
DDQ
7
DD(1)
SS
DD(1)
V
V
V
24
I/O
26
I/O
SS
6
I/O
K
L
CLK
NC
V
I/O
25
I/O
27
I/O
4
I/O
5
I/O
4
BW
BW1
DDQ
28
SS
SS
SS
SS
SS
SS
3
DDQ
V
V
I/O
V
V
V
V
V
V
I/O
M
N
P
R
T
CEN
29
I/O
30
I/O
1
2
I/O
1
I/O
A
A
0
I/O
31
I/O
P4
0
P1
I/O
I/O
NC
5
DD
VDD(1)
13
NC
A
V
A
A
LBO
10
11
14
A
NC
NC
DNU
A
NC
DNU
ZZ
(3)
(3)
(3)
(3)
(3)
DDQ
V
DDQ
V
DNU
DNU
DNU
U
,
5304 drw 13A
Top View
Pin Configuration - 512K X 18, 119 BGA
1
2
3
4
5
6
7
DDQ
6
4
8
16
A
DDQ
V
A
B
C
D
E
F
V
A
A
A
A
A
A
NC(2)
3
2
9
CE2
NC
NC
NC
NC
NC
2
CE
ADV/LD
7
DD
V
13
17
A
A
A
8
I/O
SS
SS
SS
SS
SS
SS
SS
P1
I/O
NC
V
V
V
NC
V
V
V
V
9
I/O
7
I/O
NC
DDQ
1
CE
NC
6
I/O
DDQ
V
V
NC
OE
10
5
I/O
G
H
J
NC
I/O
NC
NC
A18
BW
2
11
I/O
SS
V
SS
4
I/O
V
V
V
NC
R/W
DD(1)
SS
DD(1)
DDQ
V
DD
12
DD
V
DD
DDQ
V
V
V
V
SS
3
I/O
K
L
NC
I/O
V
CLK
NC
NC
13
I/O
SS
SS
2
NC
V
I/O
NC
NC
BW
1
DDQ
V
14
I/O
SS
SS
SS
DDQ
V
M
N
P
R
T
V
V
V
V
V
V
CEN
1
15
SS
SS
1
0
I/O
NC
NC
A
I/O
NC
NC
0
P2
I/O
A
I/O
5
DD
V
12
A
NC
NC
DDQ
A
V
DD(1)
NC
LBO
10
15
A
14
11
A
A
NC
A
ZZ
(3)
(3)
(3)
(3)
(3)
DNU
DNU
DNU
DNU
DNU
DDQ
V
U
V
5304 drw 13B
Top View
NOTES:
1. J3, J5, and R5 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. A4 is reserved for future 16M.
3. DNU = Do not use. Pin U2, U3, U4, U5 and U6 are reserved for respective JTAG pins: TMS, TDI, TCK, TDO and TRST. The current die revision allows these pins to
be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
6.42
7
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Pin Configuration - 256K X 36, 165 fBGA
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
NC(2)
NC
A
7
6
ADV/LD
OE
A
17
A
A
8
9
NC
CE
1
BW
3
BW
2
CE
2
CEN
R/W
A
CE
2
CLK
NC(2)
NC(2)
I/OP2
I/O14
I/O12
I/O10
BW4
BW1
I/OP3
I/O17
I/O19
I/O21
I/O23
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC
I/O16
I/O18
I/O20
I/O22
V
V
V
V
V
V
V
V
I/O15
I/O13
I/O11
G
H
J
I/O
9
I/O8
V
DD(1)
V
DD(1)
I/O24
I/O26
I/O28
I/O30
NC
NC
NC
NC
ZZ
I/O25
I/O27
I/O29
I/O31
I/OP4
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
DDQ
DDQ
DDQ
DDQ
DDQ
I/O
I/O
I/O
7
I/O
I/O
I/O
I/O
6
K
L
V
V
V
V
V
V
V
V
5
3
4
2
0
M
N
P
R
I/O
1
DNU(3)
DNU(3)
DNU(3)
NC
V
DD(1)
NC
I/OP1
NC
NC(2)
NC(2)
A
A
5
4
A
2
3
A
1
DNU(3)
DNU(3)
A
10
11
A
13
12
A
A
14
15
A
A
0
A
A
A
16
LBO
5304 tbl 25a
Pin Configuration - 512K X 18, 165 fBGA
1
NC(2)
NC
NC
NC
NC
NC
NC
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
A
7
6
NC
ADV/LD
OE
A
18
A
A
8
9
A10
CE
1
BW
2
CE
2
CEN
R/W
A
CE
2
NC
CLK
NC(2)
NC(2)
I/OP1
BW1
NC
I/O
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
V
V
V
V
V
V
V
V
V
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
SS
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
V
V
V
V
V
V
SS
DD
DD
DD
DD
DD
DD
DD
DD
DD
SS
V
DDQ
DDQ
DDQ
DDQ
DDQ
NC
NC
NC
NC
NC
NC
8
V
V
V
V
V
V
V
V
I/O
I/O
I/O
I/O
7
6
5
4
I/O
9
I/O10
I/O11
G
H
J
V
DD(1)
I/O12
I/O13
I/O14
I/O15
I/OP2
NC
V
DD(1)
NC
NC
ZZ
NC
V
DDQ
DDQ
DDQ
DDQ
DDQ
V
DDQ
DDQ
DDQ
DDQ
DDQ
I/O
I/O
I/O
3
NC
NC
NC
NC
NC
NC
K
L
NC
V
V
V
V
V
V
V
V
2
NC
1
M
N
P
R
NC
I/O0
NC
DNU(3)
DNU(3)
DNU(3)
NC
V
DD(1)
NC
NC(2)
NC(2)
A
A
5
4
A
2
3
A
1
DNU(3)
DNU(3)
A
11
A
14
13
A
A
15
16
A
A
0
A
12
A
A
17
LBO
5304 tbl25b
NOTES:
1. H1, H2, and N7 do not have to be directly connected to VDD as long as the input voltage is ≥ VIH.
2. B9, B11, A1, R2 and P2 is reserved for future 18M, 36M, 72M, 144M and 288M, respectively.
3. DNU=Do not use. Pins P5, R5, P7 and R7 are reserved for respective JTAG pins: TDI, TMS, TDO and TCK on future revisions. The current die revision allows these
pins to be left unconnected, tied LOW (VSS), or tied HIGH (VDD).
6.842
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Synchronous Truth Table(1)
R/W
Chip(5)
ADV/LD
ADDRESS
USED
PREVIOUS CYCLE
CURRENT CYCLE
I/O
CEN
BWx
Enable
(2 cycles later)
L
L
L
L
H
X
Select
Select
X
L
L
Valid
X
External
External
Internal
X
X
LOAD WRITE
LOAD READ
D(7)
Q(7)
D(7)
H
Valid
LOAD WRITE /
BURST WRITE
BURST WRITE
(Advance burst counter)(2)
L
X
X
H
X
Internal
LOAD READ /
BURST READ
BURST READ
Q(7)
(Advance burst counter)(2)
L
L
X
X
X
Deselect
L
H
X
X
X
X
X
X
X
X
DESELECT or STOP(3)
NOOP
HiZ
HiZ
X
X
DESELECT / NOOP
X
H
SUSPEND(4)
Previous Value
5304 tbl 08
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. When ADV/LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of the burst
cycle (Read or Write) is determined by the status of the R/W signal when the first address is loaded at the beginning of the burst cycle.
3. Deselect cycle is initiated when either (CE1, or CE2 is sampled high or CE2 is sampled low) and ADV/LD is sampled low at rising edge of clock. The data bus will tri-state
two cycles after deselect is initiated.
4. When CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/Os remains
unchanged.
5. To select the chip requires CE1 = L, CE2 = L, CE2 = H on these chip enables. Chip is deselected if any one of the chip enables is false.
6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.
Partial Truth Table for Writes(1)
(3)
(3 )
OPERATION
R/W
H
L
BW
X
1
BW
X
2
BW
3
BW4
READ
X
X
WRITE ALL BYTES
L
L
L
H
H
L
L
(2)
WRITE BYTE 1 (I/O[0:7], I/OP1
)
L
L
H
L
H
H
H
L
(2)
WRITE BYTE 2 (I/O[8:15], I/OP2
)
L
H
H
H
H
(2,3)
WRITE BYTE 3 (I/O[16:23], I/OP3
)
L
H
H
H
(2,3)
WRITE BYTE 4 (I/O[24:31], I/OP4
)
L
H
H
NO WRITE
L
H
5304 tbl 09
NOTES:
1. L = VIL, H = VIH, X = Don’t Care.
2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.
6.42
9
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Interleaved Burst Sequence Table (LBO=VDD)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
A0
0
A1
A0
First Address
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
0
1
Second Address
Third Address
1
0
1
0
0
1
0
1
Fourth Address(1)
1
0
1
0
5304 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Linear Burst Sequence Table (LBO=VSS)
Sequence 1
Sequence 2
Sequence 3
Sequence 4
A1
A0
0
A1
A0
1
A1
1
A0
0
A1
1
A0
First Address
0
0
1
1
0
1
1
0
1
Second Address
Third Address
1
0
1
1
0
0
0
1
0
0
0
1
Fourth Address(1)
1
0
0
1
1
0
5304 tbl 11
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Functional Timing Diagram(1)
CYCLE
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
n+37
CLOCK
(2)
ADDRESS
A29
C29
A30
C30
A31
C31
A32
C32
A33
C33
A34
C34
A35
C35
A36
C36
A37
C37
(A0 - A17)
(2)
CONTROL
(R/W, ADV/LD, BWx)
(2)
DATA
D/Q27
D/Q28
D/Q29
D/Q30
D/Q32
D/Q33
D/Q34
D/Q35
D/Q31
I/O [0:31], I/O P[1:4]
5304 drw 03
,
NOTES:
1. This assumes CEN, CE1, CE2, CE2 are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data delay
from the rising edge of clock.
61.402
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load, Burst,
Deselect and NOOP Cycles(2)
CE(1)
Cycle
Address
R/W
ADV/LD
I/O
Comments
Load read
Burst read
Load read
CEN
BWx
X
X
X
X
X
X
X
X
L
OE
X
X
L
n
A
0
H
X
H
X
X
H
X
X
L
L
H
L
L
L
X
n+1
X
X
L
L
X
n+2
A
1
L
Q0
n+3
X
X
L
H
X
L
L
L
Q0+1 Deselect or STOP
n+4
H
L
L
L
Q1
NOOP
n+5
A
2
L
X
X
L
Z
Z
Load read
n+6
X
X
H
L
X
H
L
L
Burst read
n+7
L
Q
2
Deselect or STOP
n+8
A
3
L
L
L
Q2+1 Load write
n+9
X
X
L
H
L
X
L
L
L
X
X
X
X
X
X
X
L
Z
Burst write
Load write
n+10
n+11
n+12
n+13
n+14
n+15
n+16
n+17
n+18
n+19
A
4
L
L
D3
X
X
X
X
L
L
H
X
L
L
X
X
L
D3+1 Deselect or STOP
H
L
L
D4
NOOP
A
5
6
7
L
Z
Z
Load write
Load read
Load write
Burst write
Load read
A
A
H
L
L
L
L
X
L
L
L
L
D5
X
X
H
X
L
H
L
X
L
L
L
Q
6
A
8
9
L
X
X
L
X
X
L
D7
X
H
L
X
L
L
D7+1 Burst read
A
L
Q
8
Load write
5304tbl 12
NOTES:
1. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
2. H = High; L = Low; X = Don’t Care; Z = High Impedance.
Read Operation(1)
CE(2)
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
BWx
X
OE
X
n
A
0
H
X
X
L
X
X
L
X
X
L
L
X
X
Address and Control meet setup
Clock Setup Valid
n+1
n+2
X
X
X
X
X
X
L
Q
0
Contents of Address A0 Read Out
5304 tbl 13
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
11
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Burst Read Operation(1)
CE(2)
L
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
L
BWx
X
OE
X
X
L
n
A
0
H
X
X
X
X
H
X
X
H
L
X
X
Address and Control meet setup
Clock Setup Valid, Advance Counter
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
X
H
H
H
H
L
X
L
X
X
X
X
X
L
X
Q0
Address A0 Read Out, Inc. Count
X
L
X
L
Q
0+1
0+2
0+3
Address A0+1 Read Out, Inc. Count
Address A0+2 Read Out, Inc. Count
X
L
X
L
Q
Q
A
1
L
L
X
L
Address A0+3 Read Out, Load A1
X
X
H
H
L
X
L
X
L
Q0
Address A
Address A
0
1
Read Out, Inc. Count
Read Out, Inc. Count
X
L
X
L
Q
1
A
2
L
L
X
L
Q1+1
Address A1+1 Read Out, Load A2
5304 tbl 14
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance..
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation(1)
CE(2)
Cycle
Address
R/W
ADV/LD
I/O
X
Comments
CEN
BWx
OE
X
n
A
0
L
L
X
X
L
X
X
L
L
L
L
X
X
Address and Control meet setup
Clock Setup Valid
n+1
n+2
X
X
X
X
X
X
X
D0
Write to Address A0
5304 tbl 15
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Burst Write Operation(1)
CE(2)
L
Cycle
Address
R/W
ADV/LD
I/O
X
Comments
CEN
L
BWx
OE
X
n
A
0
L
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
Address and Control meet setup
Clock Setup Valid, Inc. Count
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
X
H
H
H
H
L
X
L
X
X
X
X
X
X
L
X
D0
Address A0 Write, Inc. Count
X
L
X
D0+1
Address A0+1 Write, Inc. Count
Address A0+2 Write, Inc. Count
X
L
X
D
0+2
0+3
A
X
X
1
L
L
X
D
Address A0+3 Write, Load A1
X
X
L
H
H
L
X
L
X
D0
Address A
Address A
0
1
Write, Inc. Count
Write, Inc. Count
X
L
X
D1
A
2
L
L
X
D1+1
Address A1+1 Write, Load A2
5304 tbl 16
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
61.422
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Clock Enable Used(1)
CE(2)
Cycle
Address
R/W
ADV/LD
I/O
Comments
CEN
BWx
OE
X
X
X
L
n
A
0
H
X
H
X
X
H
H
H
L
X
L
X
X
L
L
L
L
L
X
X
X
X
Address and Control meet setup
Clock n+1 Ignored
Clock Valid
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
H
L
X
A
1
L
X
X
X
X
H
H
L
X
Q
Q
Q
0
Clock Ignored, Data Q
0
0
is on the bus.
is on the bus.
X
X
L
0
0
Clock Ignored, Data Q
A
2
3
4
L
X
L
Address A
Address A
0
1
Read out (bus trans.)
Read out (bus trans.)
A
A
L
L
X
L
Q1
L
L
X
L
Q2
Address A2 Read out (bus trans.)
5304 tbl 17
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
Write Operation with Clock Enable Used(1)
CE(2)
Cycle
Address
R/W
ADV/LD
I/O
X
Comments
CEN
BWx
OE
n
A
0
L
X
L
X
X
L
L
L
L
X
L
X
X
L
L
L
L
L
L
X
Address and Control meet setup.
Clock n+1 Ignored.
Clock Valid.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
X
X
H
L
X
X
X
A
1
L
L
X
X
X
X
X
H
H
L
X
X
X
Clock Ignored.
X
X
X
X
Clock Ignored.
A
2
3
4
L
L
X
D0
Write Data D
Write Data D
Write Data D
0
A
A
L
L
L
X
D1
1
L
L
L
X
D2
2
5304 tbl 18
NOTES:
1. H = High; L = Low; X = Don’t Care; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
6.42
13
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Read Operation with Chip Enable Used(1)
I/O(3)
CE(2)
Cycle
Address
R/W
ADV/LD
Comments
CEN
BWx
OE
n
X
X
X
X
H
X
H
X
X
H
X
X
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
?
?
Z
Z
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
H
Deselected.
A
0
L
Address and Control meet setup
Deselected or STOP.
X
H
A
1
L
Q0
Address A
Deselected or STOP.
Address A Read out. Deselected.
0 Read out. Load A1.
X
X
H
X
L
Z
H
Q
Z
Z
1
1
A
2
L
X
X
L
Address and control meet setup.
Deselected or STOP.
X
X
H
H
Q
2
Address A2 Read out. Deselected.
5304 tbl 19
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
Write Operation with Chip Enable Used(1)
I/O(3)
CE(2)
Cycle
Address
R/W
ADV/LD
Comments
CEN
BWx
OE
n
X
X
X
X
L
L
L
L
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
?
?
Z
Z
Deselected.
Deselected.
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
H
A
0
L
Address and Control meet setup
Deselected or STOP.
X
X
L
H
X
L
A
1
L
D0
Address D
Deselected or STOP.
Address D Write in. Deselected.
0 Write in. Load A1.
X
X
X
X
L
H
X
X
L
Z
H
D
Z
Z
1
1
A
2
L
Address and control meet setup.
Deselected or STOP.
X
X
X
X
H
X
X
H
D2
Address D2 Write in. Deselected.
5304 tbl 20
NOTES:
1. H = High; L = Low; X = Don’t Care; ? = Don’t Know; Z = High Impedance.
2. CE = L is defined as CE1 = L, CE2 = L and CE2 = H. CE = H is defined as CE1 = H, CE2 = H or CE2 = L.
61.442
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (VDD = 3.3V +/-5%)
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
___
|ILI|
Input Leakage Current
V
DD = Max., VIN = 0V to VDD
5
µA
LBO Input Leakage Current(1)
Output Leakage Current
Output Low Voltage
___
___
___
|ILI
|ILO
VO
|
V
V
DD = Max., VIN = 0V to VDD
30
5
µA
µA
V
|
OUT = 0V to VDDQ, Device Deselected
L
IOL = +8mA, VDD = Min.
0.4
___
V
OH
Output High Voltage
IOH = -8mA, VDD = Min.
2.4
V
NOTE:
5304 tbl 21
1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to Vss if not actively driven.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range(1) (VDD = 3.3V +/-5%)
150MHz
133MHz
100MHz
Com'l
Unit
Symbol
Parameter
Test Conditions
Com'l
Ind
Com'l
Ind
Ind
I
DD
Device Selected, Outputs Open,
Operating Power
Supply Current
mA
ADV/LD = X, VDD = Max.,
325
40
345
300
40
320
250
40
270
(2)
V
IN > VIH or < VIL, f = fMAX
ISB1
Device Deselected, Outputs Open,
DD = Max., VIN > VHD or < VLD
f = 0(2,3)
CMOS Standby Power
Supply Current
mA
mA
mA
V
,
60
140
60
60
130
60
60
120
60
Device Deselected, Outputs Open,
ISB2
Clock Running Power
Supply Current
V
DD = Max., VIN > VHD or < VLD,
120
40
110
40
100
40
(2.3)
f = fMAX
ISB3
Device Selected, Outputs Open,
Idle Power
Supply Current
CEN > VIH, VDD = Max.,
(2,3)
V
IN > VHD or < VLD, f = fMAX
Device Selected, Outputs Open
Full Sleep Mode
Supply Current
IZZ
CEN ≤ VIL, VDD = Max., ZZ ≥ VHD
40
60
40
60
40
60
mA
V
IN ≥ VHD or ≤ V
LD, f = fMax(2, 3)
5304 tbl 22
NOTES:
1. All values are maximum guaranteed values.
2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC; f=0 means no input lines are changing.
3. For I/Os VHD = VDDQ – 0.2V, VLD = 0.2V. For other inputs VHD = VDD – 0.2V, VLD = 0.2V.
AC Test Load
AC Test Conditions
V
DDQ/2
(VDDQ = 3.3V)
50Ω
I/O
Z0 = 50Ω
Input Pulse Levels
0 to 3V
2ns
,
5304 drw 04
6
5
4
Input Rise/Fall Times
Figure 1. AC Test Load
Input Timing Reference Levels
Output Timing Reference Levels
AC Test Load
1.5V
1.5V
•
3
ΔtCD
See Figure 1
(Typical, ns)
2
•
5304 tbl 23
•
1
•
•
20 30 50
80 100
Capacitance (pF)
200
5304 drw 05
,
Figure 2. Lumped Capacitive Load, Typical Derating
6.42
15
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(VDD = 3.3V +/-5%, Commercial and Industrial Temperature Ranges)
150MHz(6)
133MHz
100MHz
Max.
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Unit
____
____
____
t
CYC
Clock Cycle Time
6.7
7.5
10
ns
MHz
ns
____
____
____
(1)
Clock Frequency
150
133
100
tF
(2)
CH
____
____
____
Clock High Pulse Width
Clock Low Pulse Width
2.0
2.0
2.2
2.2
3.2
3.2
t
____
____
____
(2)
CL
ns
t
Output Parameters
____
____
____
t
CD
Clock High to Valid Data
Clock High to Data Change
Clock High to Output Active
3.8.
4.2
5
ns
ns
ns
____
____
____
tCDC
1.5
1.5
1.5
1.5
1.5
1.5
____
____
____
(3, 4,5)
CLZ
t
(3, 4,5)
Clock High to Data High-Z
1.5
3
1.5
3
1.5
3.3
ns
ns
ns
ns
t
CHZ
____
____
____
tOE
Output Enable Access Time
3.8
4.2
5
____
____
____
(3,4)
(3,4)
Output Enable Low to Data Active
Output Enable High to Data High-Z
0
0
0
t
OLZ
____
____
____
3.8
4.2
5
t
OHZ
Set Up Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
SE
SA
SD
SW
SADV
SC
SB
Clock Enable Setup Time
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.7
1.7
1.7
1.7
1.7
1.7
1.7
2.0
2.0
2.0
2.0
2.0
2.0
2.0
ns
ns
ns
ns
ns
ns
ns
t
Address Setup Time
t
Data In Setup Time
t
Read/Write (R/W) Setup Time
Advance/Load (ADV/LD) Setup Time
Chip Enable/Select Setup Time
Byte Write Enable (BWx) Setup Time
t
t
t
Hold Times
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
____
t
HE
HA
HD
HW
HADV
HC
HB
Clock Enable Hold Time
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
t
Address Hold Time
t
Data In Hold Time
t
Read/Write (R/W) Hold Time
Advance/Load (ADV/LD) Hold Time
Chip Enable/Select Hold Time
Byte Write Enable (BWx) Hold Time
t
t
t
5304 tbl 24
NOTES:
1. tF = 1/tCYC.
2. Measured as HIGH above 0.6VDDQ and LOW below 0.4VDDQ.
3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that tCHZ (device turn-off) is about 1ns faster than tCLZ (device turn-on) at a given temperature and voltage. The
specs as shown do not imply bus contention because tCLZ is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than tCHZ, which is a
Max. parameter (worse case at 70 deg. C, 3.135V).
6. Commercial temperature range only.
61.462
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of Read Cycle(1,2,3,4)
,
6.42
17
tCYC
CLK
t
CH
tCL
t
SE
t
HE
CEN
tSADV
t
HADV
ADV/LD
R/W
t
SW
tHW
t
SA
tHA
A2
A1
ADDRESS
t
t
SC
t
HC
HB
CE1, CE2(2)
SB
t
BW1 - BW4
OE
(CEN high, eliminates
current L-H clock edge)
(Burst Wraps around
to initial state)
t
SD
tSD
t
HD
t
HD
DATAIN
D(A1)
D(A2)
D(A2+3
)
D(A2)
D(A2+1
)
D(A2+2
)
Pipeline
Write
Burst Pipeline Write
5304 drw 07
Pipeline
Write
NOTES:
1. D (A1) represents the first input to the external address A1. D (A2) represents the first input to the external address A2; D (A2+1) represents the next input data in the burst sequence of
the base address A2, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the LBO input.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/LD LOW.
4. R/W is don't care when the SRAM is bursting (ADV/LD sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/W signal when new address
and control are loaded into the SRAM.
5. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two
cycles before the actual data is presented to the SRAM.
tCYC
CLK
tCH
tCL
t
SE
tHE
CEN
tSADV
tHADV
ADV/LD
tSW
t
HW
R/W
t
t
SA
t
HA
A
2
A5
A
3
A4
A
8
A9
A1
A6
A7
ADDRESS
SC
tHC
(2)
CE1, CE2
t
SB
tHB
BW1
- BW
4
OE
tSD tHD
D(A5)
D(A4)
D(A2)
DATAIN
Write
Write
t
tCLZ
CDC
t
CHZ
t
CD
Q(A6)
Q(A3)
Q(A7)
Q(A1)
DATAOUT
Read
Read
Read
5304 drw 08
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two
cycles before the actual data is presented to the SRAM.
tCYC
CLK
tCH
tCL
tSE
tHE
CEN
tSADV
tHADV
ADV/LD
tSW
tHW
R/W
tSA
tHA
A
2
A
4
A5
A
1
A3
ADDRESS
tSC
tHC
(2)
CE1, CE2
tSB
tHB
B(A2)
BW1 - BW4
OE
tSD tHD
D(A2)
DATAIN
tCHZ
tCDC
tCD
Q(A1)
Q(A3)
Q(A1)
DATAOUT
tCLZ
5304 drw 09
NOTES:
1. Q (A1) represents the first output from the external address A1. D (A2) represents the input data to the SRAM corresponding to address A2.
2. CE2 timing transitions are identical but inverted to the CE1 and CE2 signals. For example, when CE1 and CE2 are LOW on this waveform, CE2 is HIGH.
3. CEN when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The part will behave as if the L-H clock transition did not
occur. All internal registers in the SRAM will retain their previous state.
4. Individual Byte Write signals (BWx) must be valid on all write and burst-write cycles. A write cycle is initiated when R/W signal is sampled LOW. The byte write information comes in two
cycles before the actual data is presented to the SRAM.
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of CS Operation(1,2,3,4)
,
6.42
21
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
100-Pin Plastic Thin Quad Flatpack (TQFP) Package Diagram Outline
62.422
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
119 Ball Grid Array(BGA) Package Diagram Outline
6.42
23
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
165 Fine Pitch Ball Grid Array (fBGA) Package Diagram Outline
62.442
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Timing Waveform of OE Operation(1)
OE
t
OE
tOHZ
tOLZ
DATAOUT
Valid
,
5304 drw 11
NOTE:
1. A read operation is assumed to be in progress.
Ordering Information
6.42
25
IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT™ Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs
Commercial and Industrial Temperature Ranges
Datasheet Document History
12/31/99
03/04/00
04/20/00
Created new datasheet from obsolete devices IDT71V656 and IDT71V658
Pg. 1,14,15 Removed 166MHz speed grade offering; Added 150MHz speed grade offering
Pg. 5,6
Pg. 5,6
Pg. 7
Added JTAG test pins to TQFP pin configuration; removed footnote
Add clarification note to Recommended Operating temperature and Absolute Max Ratings tables
Add note to BGA pin Configuration; correct typo within pinout
Insert TQFP Package Diagram Outline
Pg. 21
05/23/00
07/28/00
Add new package offering, 13 x 15mm 165 fBGA
Correction in BG 119 Package Diagram Outline
Add industrial temperature
Pg. 23
Pg. 2
Correction VDDQ 3.3V I/O supply
Pg. 5-8
Pg. 7
Remove JTAG offerings, refer to IDT71V656xx and IDT71V658xx device errata sheet
Correct pin B2
Pg. 8
Change pin B1 to NC
Pg. 23
Pg. 8
Pg. 15
Pg. 16
Update BG119 Package Diagram Outline
11/04/00
10/16/01
12/04/02
Add note to pin N5 on BQ165 pinout, reserved for JTAG TRST
Add Izz parameter to DC Electrical Characteristics
Changed sub-header to include Commercial and Industrial Temperature Ranges. Corrected the TCH
from 22ns to 2.2ns and TSADV from 20ns to 2.0ns.
Changed datasheet from Prelininary to final release.
Added I temp to 150MHz.
Pg. 1-25
Pg. 15
Pg. 16
Corrected typo from 22 to 2.2.
12/19/02
09/30/04
Pg. 1,2,5,6, Removed JTAG functionality for current die revision.
7,8
Pg. 7
Pg. 5,6
Pg. 7
Corrected pin configuration on the x36, 119BGA. Switched pins I/O0 and I/OP1.
Updated temperature TA note.
Updated pin configuration for the 119BGA-reordered I/O signals on P7,N6,L6, K7,H6, G7, F6, E7, D6
(512K x18).
Pg. 25
Pg. 25
Pg. 25
Added "restricted hazardous substance device" to ordering information.
Added Z generation die step to data sheet ordering information.
Updated the ordering information by removing the "IDT" notation.
02/21/07
10/16/08
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for SALES:
for Tech Support:
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408-284-4532
800-345-7015 or 408-284-8200
fax:408-284-2775
www.idt.com
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
62.462
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