72201L10J8_技术文档

CMOSSyncFIFO^™

64 x 9, 256 x 9, 512 x 9,

1,024 x 9, 2,048 x 9,

4,096 x 9 and 8,192 x 9

IDT72421,IDT72201

IDT72211,IDT72221

IDT72231,IDT72241

IDT72251

FEATURES:

DESCRIPTION:

•

64 x 9-bit organization (IDT72421)

The IDT72421/72201/72211/72221/72231/72241/72251 SyncFIFO™

256 x 9-bit organization (IDT72201)

512 x 9-bit organization (IDT72211)

1,024 x 9-bit organization (IDT72221)

2,048 x 9-bit organization (IDT72231)

4,096 x 9-bit organization (IDT72241)

8,192 x 9-bit organization (IDT72251)

10 ns read/write cycle time

Read and Write Clocks can be independent

Dual-Ported zero fall-through time architecture

Empty and Full Flags signal FIFO status

Programmable Almost-Empty and Almost-Full flags can be set

to any depth

are very high-speed, low-power First-In, First-Out (FIFO) memories with

clockedreadandwrite controls. These devices have a 64, 256, 512, 1,024,

2,048,4,096,and8,192x9-bitmemoryarray,respectively. TheseFIFOsare

applicableforawidevarietyofdatabufferingneedssuchasgraphics,localarea

networksandinterprocessorcommunication.

TheseFIFOshave9-bitinputandoutputports.Theinputportiscontrolled

bya free-runningclock(WCLK), andtwowrite enable pins (WEN1, WEN2).

DataiswrittenintotheSynchronousFIFOoneveryrisingclockedgewhenthe

writeenablepinsareasserted.Theoutputportiscontrolledbyanotherclock

pin (RCLK) and two read enable pins (REN1, REN2). The Read Clock can

betiedtotheWriteClockforsingleclockoperationorthetwoclocks canrun

asynchronous ofoneanotherfordual-clockoperation.Anoutputenablepin

(OE)is providedonthe readportforthree-state controlofthe output.

The Synchronous FIFOs have twofixedflags, Empty(EF)andFull(FF).

Two programmable flags, Almost-Empty (PAE) and Almost-Full (PAF), are

provided for improved system control. The programmable flags default to

Empty+7andFull-7forPAE andPAF,respectively.Theprogrammableflag

offsetloadingiscontrolledbyasimplestatemachineandisinitiatedbyasserting

•

Programmable Almost-Empty and Almost-Full flags default to

Empty+7, and Full-7, respectively

•

Output enable puts output data bus in high-impedance state

Advanced submicron CMOS technology

Available in the 32-pin plastic leaded chip carrier (PLCC) and

32-pin Thin Quad Flat Pack (TQFP)

•

For through-hole product please see the IDT72420/72200/72210/ the load pin (LD).

72220/72230/72240 data sheet

These FIFOs are fabricated using IDT’s high-speed submicron CMOS

technology.

•

Industrial temperature range (–40°C to +85°C) is available

Green parts available, see ordering information

FUNCTIONAL BLOCK DIAGRAM

D0 - D8

WCLK

WEN1

WEN2

LD

OFFSET REGISTER

INPUT REGISTER

EF

FLAG

LOGIC

WRITE CONTROL

LOGIC

PAE

PAF

FF

RAM ARRAY

64 x 9, 256 x 9,

512 x 9, 1,024 x 9,

2,048 x 9, 4,096 x 9,

8,192 x 9

WRITE POINTER

READ POINTER

READ CONTROL

LOGIC

OUTPUT REGISTER

RESET LOGIC

RCLK

REN1

REN2

RS

2655 drw01

OE

Q0 - Q8

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OCTOBER 2008

1

DSC-2655/5

©

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PINCONFIGURATION

INDEX

4

3

2

32 31 30

1

29 28 27 26 25

32 31 30

D1

29

28

27

26

25

24

23

22

21

RS

5

1

2

3

4

D

1

24

23

22

21

20

19

18

17

D

0

WEN1

WCLK

WEN2/LD

6

D0

WCLK

PAF

PAE

7

PAF

WEN2/LD

8

PAE

GND

VCC

9

VCC

GND

REN1

RCLK

REN2

OE

5

Q8

10

11

12

13

REN1

Q7

6

7

8

Q7

RCLK

Q6

REN2

Q5

9

10 11 12 13 14 15 16

14 15 16 17 18 19 20

2655 drw 02

2655 drw02a

TQFP (PR32-1, order code: PF)

TOP VIEW

PLCC (J32-1, order code: J)

TOP VIEW

PINDESCRIPTIONS

Symbol

D0-D8

RS

Name

I/O

Description

DataInputs

I

Datainputs fora9-bitbus.

Reset

When RS is set LOW, internal read and write pointers are set to the first location of the RAM array,FF and PAF

go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up.

WCLK

WriteClock

I

DataiswrittenintotheFIFOonaLOW-to-HIGHtransitionofWCLKwhentheWriteEnable(s)areasserted.

WEN1

WriteEnable1

Ifthe FIFOis configuredtohave programmable flags, WEN1 is the onlywrite enable pin. WhenWEN1 is LOW,

data is writtenintothe FIFOoneveryLOW-to-HIGHtransitionWCLK. Ifthe FIFOis configuredtohave twowrite

enables, WEN1 mustbeLOWandWEN2mustbeHIGHtowritedataintotheFIFO.Datawillnotbewritteninto

the FIFOifthe FF is LOW.

WEN2/ WriteEnable2/

I

The FIFO is configured at reset to have either two write enables or programmable flags. If WEN2/LD is HIGH

atreset,this pinoperates as asecondwriteenable. IfWEN2/LD is LOWatreset,this pinoperates as acontrol

toloadandreadtheprogrammableflagoffsets.IftheFIFOis configuredtohavetwowriteenables,WEN1 must

be LOWandWEN2mustbe HIGHtowrite data intothe FIFO. Data willnotbe writtenintothe FIFOifthe FF is

LOW. Ifthe FIFOis configuredtohave programmable flags, WEN2/LD is heldLOWtowrite orreadthe

programmableflagoffsets.

LD

Load

Q0-Q8

RCLK

REN1

DataOutputs

ReadClock

O Dataoutputsfora9-bitbus.

I

Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN1 and REN2 are asserted.

When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.

Data will not be read from the FIFO if the EF is LOW.

Read Enable 1

REN2

OE

Read Enable 2

OutputEnable

EmptyFlag

I

When REN1 and REN2 are LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.

Data will not be read from the FIFO if the EF is LOW.

WhenOE is LOW, the data outputbus is active. IfOE is HIGH, the outputdata bus willbe ina high-impedance

state.

EF

O When EF is LOW, the FIFOis emptyandfurtherdata reads fromthe outputare inhibited. WhenEF is HIGH, the

FIFO is not empty. EF is synchronized to RCLK.

PAE

PAF

FF

Programmable

Almost-EmptyFlag

O When PAE isLOW,theFIFOisalmost-emptybasedontheoffsetprogrammedintotheFIFO.Thedefault

offsetatresetis Empty+7. PAE is synchronizedtoRCLK.

O WhenPAFisLOW,theFIFOisalmost-fullbasedontheoffsetprogrammedintotheFIFO.Thedefaultoffset

at reset is Full-7. PAF is synchronized to WCLK.

O WhenFF is LOW, the FIFOis fullandfurtherdata writes intothe inputare inhibited. WhenFF is HIGH, the FIFO

isnotfull.FF issynchronizedtoWCLK.

Programmable

Almost-FullFlag

Full Flag

VCC

Power

One +5 volt power supply pin.

One 0 volt ground pin.

GND

Ground

©

OCTOBER22,2008

2

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

ABSOLUTEMAXIMUMRATINGS

RECOMMENDEDOPERATING

CONDITIONS

Symbol

Rating

Com'l & Ind'l

Unit

V

Symbol

Parameter

Min. Typ. Max.

Unit

V^TERM

TerminalVoltagewith

RespecttoGND

StorageTemperature

–0.5to+7.0

V^CC

SupplyVoltage

4.5

5.0

5.5

V

T^STG

–55to +125

–50 to +50

°C

Commercial/Industrial

SupplyVoltage

GND

V^IH

0

2.0

0

—

0

—

V

InputHighVoltage

Commercial/Industrial

InputLowVoltage

Commercial/Industrial

OperatingTemperature

Commercial

I^OUT

DCOutputCurrent

mA

NOTE:

V^IL

TA

—

0

—

0.8

+70

+85

V

°C

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of the specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

OperatingTemperature

Industrial

–40

DCELECTRICALCHARACTERISTICS

(Commercial: VCC = 5V ± 10%, T

A

= 0

°

C to +70

°

C; Industrial: VCC = 5V ± 10%, T

A

= –40

°

C to +85

°

C)

IDT72421

IDT72201

IDT72211

IDT72221

IDT72231

IDT72241

IDT72251

Com'l and Ind'l⁽¹⁾

tCLK = 10, 15, 25 ns

Com'l and Ind'l⁽¹⁾

tCLK = 10, 15, 25 ns

Symbol

Parameter

Min.

–1

Typ.

—

Max.

1

Min.

Typ.

—

Max.

(2)

ILI

Input Leakage Current (Any Input)

OutputLeakageCurrent

–1

–10

2.4

—

1

10

—

0.4

50

5

(3)

ILO

–10

2.4

—

10

—

0.4

35

5

VOH

VOL

Output Logic “1” Voltage, IOH = –2mA

OutputLogic“0”Voltage,IOL=8mA

Active Power Supply Current

StandbyCurrent

(4,5,6)

ICC1

—

(4,7)

ICC2

—

NOTES:

1. Industrial temperature range product for the 15ns and 25ns speed grades are available as standard product.

2. Measurements with 0.4 ≤ VIN ≤ VCC.

3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.

4. Tested with outputs open (IOUT = 0).

5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.

6. Typical ICC1 = 1.7 + 0.7*fS + 0.02*CL*fS (in mA).

These equations are valid under the following conditions:

VCC = 5V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF).

7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.

©

OCTOBER22,2008

3

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

ACELECTRICALCHARACTERISTICS

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)

Commercial

IDT72421L10

IDT72201L10

IDT72211L10

IDT72221L10

IDT72231L10

IDT72241L10

IDT72251L10

Com'l & Ind'l⁽¹⁾

IDT72421L25

IDT72201L25

IDT72211L25

IDT72221L25

IDT72231L25

IDT72241L25

IDT72251L25

IDT72421L15

IDT72201L15

IDT72211L15

IDT72221L15

IDT72231L15

IDT72241L15

IDT72251L15

Symbol

fS

Parameter

Clock Cycle Frequency

Min.

—

Max.

Min.

—

Max.

Min.

—

Max.

40

Unit

MHz

100

6.5

—

10

—

6

66.7

10

—

15

—

8

tA

DataAccessTime

ClockCycleTime

ClockHighTime

2

10

4.5

3

2

15

6

2

25

10

6

15

—

25

—

13

15

—

ns

tCLK

tCLKH

tCLKL

tDS

ClockLowTime

6

DataSetupTime

4

tDH

DataHoldTime

0.5

3

1

tENS

tENH

tRS

EnableSetupTime

EnableHoldTime

ResetPulseWidth⁽²⁾

ResetSetupTime

Reset Recovery Time

ResettoFlagandOutputTime

4

6

0.5

10

8

1

15

10

—

0

15

—

0

tRSS

tRSR

tRSF

tOLZ

tOE

8

—

0

(3)

OutputEnabletoOutputinLow-Z

OutputEnabletoOutputValid

3

(3)

tOHZ

tWFF

tREF

tPAF

tPAE

tSKEW1

OutputEnabletoOutputinHigh-Z

WriteClocktoFullFlag

3

6

3

8

3

—

5

6.5

—

6

10

—

10

ReadClocktoEmptyFlag

WriteClocktoProgrammableAlmost-FullFlag

ReadClocktoProgrammableAlmost-EmptyFlag

SkewtimebetweenReadClock& WriteClockfor

Empty Flag & Full Flag

t^SKEW2

SkewtimebetweenReadClock&WriteClockfor

Almost-EmptyFlag&ProgrammableAlmost-FullFlag

14

—

15

—

18

—

ns

NOTES:

1. Industrial temperature range product for the 15ns and 25ns speed grades are available as standard product.

2. Pulse widths less than minimum values are not allowed.

3. Values guaranteed by design, not currently tested.

5V

ACTESTCONDITIONS

In Pulse Levels

GND to 3.0V

3ns

1.5V

See Figure 1

1.1K

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

D.U.T.

30pF*

680Ω

CAPACITANCE(Ta = +25°C, f = 1.0MHz)

Symbol

Parameter

InputCapacitance

OutputCapacitance

Conditions

VIN = 0V

Max. Unit

2655 drw 03

(2)

CIN

10

pF

(1,2)

COUT

NOTES:

VOUT = 0V

or equivalent circuit

Figure 1. Output Load

*includesjigandscopecapacitances

1. With output deselected (OE ≥ VIH).

2. Characterized values, not currently tested.

©

OCTOBER22,2008

4

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

OUTPUTENABLE(OE)

SIGNALDESCRIPTIONS

WhenOutputEnable (OE)is enabled(LOW), the paralleloutputbuffers

receivedatafromtheoutputregister. WhenOutputEnable(OE)is disabled

(HIGH),theQoutputdatabusisinahigh-impedancestate.

INPUTS:

DATA IN (D0 - D8)

Datainputsfor9-bitwidedata.

WRITE ENABLE 2/LOAD (WEN2/LD)

This is a dual-purpose pin. The FIFO is configured at Reset to have

programmableflagsortohavetwowriteenables,whichallowsdepthexpansion.

IfWriteEnable2/Load(WEN2/LD)issetHIGHatReset(RS=LOW),thispin

operates as a second write enable pin.

If the FIFO is configured to have two write enables, when Write Enable

(WEN1)is LOWandWrite Enable 2/Load(WEN2/LD)is HIGH, data canbe

loadedintotheinputregisterandRAMarrayontheLOW-to-HIGHtransition

ofeveryWriteClock(WCLK). DataisstoredintheRAMarraysequentiallyand

independentlyofanyongoingreadoperation.

CONTROLS:

RESET (RS)

ResetisaccomplishedwhenevertheReset(RS)inputistakentoaLOW

state. During reset, both internal read and write pointers are set to the first

location. Aresetisrequiredafterpower-upbeforeawriteoperationcantake

place. TheFullFlag(FF)andProgrammableAlmost-Fullflag(PAF)willbereset

toHIGHaftertRSF. TheEmptyFlag(EF)andProgrammableAlmost-Empty

flag(PAE)willberesettoLOWaftertRSF. Duringreset,theoutputregisteris

initializedtoallzerosandtheoffsetregistersareinitializedtotheirdefaultvalues.

In this configuration, when Write Enable (WEN1) is HIGH and/or Write

Enable2/Load(WEN2/LD)isLOW,theinputregisterholdsthepreviousdata

and no new data is allowed to be loaded into the register.

WRITE CLOCK (WCLK)

Topreventdataoverflow,theFullFlag(FF)willgoLOW,inhibitingfurther

writeoperations. Uponthecompletionofavalidreadcycle,theFullFlag(FF)

willgoHIGHaftertWFF,allowingavalidwritetobegin. WriteEnable1(WEN1)

and Write Enable 2/Load (WEN2/LD) are ignored when the FIFO is full.

TheFIFOisconfiguredtohaveprogrammableflagswhentheWriteEnable

2/Load(WEN2/LD)is setLOWatReset(RS=LOW). TheIDT72421/72201/

72211/72221/72231/72241/72251devicescontainfour8-bitoffsetregisters

whichcanbeloadedwithdataontheinputs,orreadontheoutputs. SeeFigure

3fordetailsofthesizeoftheregistersandthedefaultvalues.

IftheFIFOisconfiguredtohaveprogrammableflagswhentheWriteEnable

1(WEN1)andWriteEnable2/Load(WEN2/LD)aresetLOW,dataontheinputs

DiswrittenintotheEmpty(LeastSignificantBit)OffsetregisteronthefirstLOW-

to-HIGHtransitionoftheWriteClock(WCLK). DataiswrittenintotheEmpty(Most

SignificantBit)OffsetregisteronthesecondLOW-to-HIGHtransitionoftheWrite

Clock(WCLK),intotheFull(LeastSignificantBit)Offsetregisteronthethird

transition,andintotheFull(MostSignificantBit)Offsetregisteronthefourth

transition. ThefifthtransitionoftheWriteClock(WCLK)againwritestotheEmpty

(LeastSignificantBit)Offsetregister.

AwritecycleisinitiatedontheLOW-to-HIGHtransitionoftheWriteClock

(WCLK). DatasetupandholdtimesmustbemetinrespecttotheLOW-to-HIGH

transition of WCLK. The Full Flag (FF) and Programmable Almost-Full flag

(PAF)aresynchronizedwithrespecttotheLOW-to-HIGHtransitionofWCLK.

The Write andReadClocks canbe asynchronous orcoincident.

WRITE ENABLE 1 (WEN1)

IftheFIFOisconfiguredforprogrammableflags,WriteEnable1(WEN1)

istheonlyenablecontrolpin. Inthisconfiguration,whenWriteEnable1(WEN1)

isLOW,datacanbeloadedintotheinputregisterandRAMarrayontheLOW-

to-HIGHtransitionofeveryWriteClock(WCLK). DataisstoredintheRAMarray

sequentiallyandindependentlyofanyongoingreadoperation.

Inthisconfiguration,whenWriteEnable1(WEN1)isHIGH,theinputregister

holdsthepreviousdataandnonewdataisallowedtobeloadedintotheregister.

IftheFIFOisconfiguredtohavetwowriteenables,whichallowsfordepth

expansion,therearetwoenablecontrolpins. SeeWriteEnable2paragraph

belowforoperationinthisconfiguration.

Topreventdataoverflow,theFullFlag(FF)willgoLOW,inhibitingfurther

writeoperations. Uponthecompletionofavalidreadcycle,theFullFlag(FF)

willgoHIGHaftertWFF,allowingavalidwritetobegin. WriteEnable1(WEN1)

is ignored when the FIFO is full.

However,writingalloffsetregistersdoesnothavetooccuratonetime. One

ortwooffsetregisterscanbewrittenandthenbybringingtheWriteEnable2/

Load (WEN2/LD) pin HIGH, the FIFO is returned to normal read/write

operation. WhentheWriteEnable2/Load(WEN2/LD)pinissetLOW,theWrite

Enable1(WEN1)isLOW,thenextoffsetregisterinsequenceiswritten.

READ CLOCK (RCLK)

DatacanbereadontheoutputsontheLOW-to-HIGHtransitionoftheRead

Clock(RCLK). TheEmptyFlag(EF)andProgrammableAlmost-Emptyflag

(PAE)aresynchronizedwithrespecttotheLOW-to-HIGHtransitionofRCLK.

The Write andReadClocks canbe asynchronous orcoincident.

LD

0

WEN1

0

WCLK

Selection

EmptyOffset(LSB)

Empty Offset (MSB)

Full Offset (LSB)

Full Offset (MSB)

READ ENABLES (REN1, REN2)

WhenbothReadEnables(REN1,REN2)areLOW,dataisreadfromthe

RAMarraytotheoutputregisterontheLOW-to-HIGHtransitionoftheRead

Clock (RCLK).

WheneitherReadEnable(REN1,REN2)isHIGH,theoutputregisterholds

the previous data and no new data is allowed to be loaded into the register.

Whenallthe data has beenreadfromthe FIFO, the EmptyFlag(EF)will

goLOW,inhibitingfurtherreadoperations. Onceavalidwriteoperationhas

beenaccomplished, the EmptyFlag(EF)willgoHIGHaftertREF anda valid

readcanbegin. TheReadEnables(REN1,REN2)areignoredwhentheFIFO

isempty.

0

1

0

1

No Operation

Write Into FIFO

No Operation

1

NOTE:

1. For the purposes of this table, WEN2 = VIH.

2. The same selection sequence applies to reading from the registers. REN1 and REN2

are enabled and read is performed on the LOW-to-HIGH transition of RCLK.

Figure 2. Write Offset Register

©

OCTOBER22,2008

5

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

Thecontentsoftheoffsetregisterscanbereadontheoutputlineswhenthe

A read and write should not be performed simultaneously to the offset

WriteEnable2/Load(WEN2/LD)pinissetLOWandbothReadEnables(REN1, registers.

REN2)aresetLOW. DatacanbereadontheLOW-to-HIGHtransitionofthe

Read Clock (RCLK).

IDT72421 - 64 x 9-BIT

IDT72201 - 256 x 9-BIT

8

6 5

0

8

7

0

Empty Offset (LSB) Reg.

Default Value 007H

6 5

7

Full Offset (LSB) Reg.

Default Value 007H

Full Offset (LSB) Reg.

Default Value 007H

IDT72211 - 512 x 9-BIT

IDT72221 - 1,024 x 9-BIT

8

7

0

8

7

0

Empty Offset (LSB) Reg.

Default Value 007H

Empty Offset (LSB)

Default Value 007H

1

8

(MSB)

00

0

7

Full Offset (LSB) Reg.

Default Value 007H

Full Offset (LSB)

Default Value 007H

8

1

0

1

(MSB)

00

(MSB)

0

IDT72231 - 2,048 x 9-BIT

IDT72241 - 4,096 x 9-BIT

IDT72251 8,192 x 9-BIT

8

7

0

8

7

0

8

7

0

Empty Offset (LSB) Reg.

Default Value 007H

Empty Offset (LSB)

Default Value 007H

2

0

3

4

(MSB)

000

0000

00000

7

Full Offset (LSB)

Full Offset (LSB) Reg.

Default Value 007H

2

3

4

(MSB)

000

0000

00000

2655 drw 05

Figure 3. Offset Register Location and Default Values

©

OCTOBER22,2008

6

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

(1,024-m)writesfortheIDT72221,(2,048-m)writesfortheIDT72231,(4,096-

m)writesfortheIDT72241,and(8,192-m)writesfortheIDT72251. Theoffset

“m”isdefinedintheFulloffsetregisters.

IfthereisnoFulloffsetspecified,theProgrammableAlmost-Fullflag(PAF)

will go LOW at Full-7 words.

OUTPUTS:

FULL FLAG (FF)

TheFullFlag(FF)willgoLOW,inhibitingfurtherwriteoperation,whenthe

device is full. If no reads are performed after Reset (RS), the Full Flag (FF)

willgoLOWafter64writesfortheIDT72421,256writesfortheIDT72201,512

writes for the IDT72211, 1,024 writes for the IDT72221, 2,048 writes for the

IDT72231,4,096writesfortheIDT72241,and8,192writesfortheIDT72251.

The Full Flag (FF) is synchronized with respect to the LOW-to-HIGH

transitionoftheWriteClock(WCLK).

TheProgrammableAlmost-Fullflag(PAF)issynchronizedwithrespectto

theLOW-to-HIGHtransitionoftheWriteClock(WCLK).

PROGRAMMABLEALMOST-EMPTYFLAG(PAE)

TheProgrammableAlmost-Emptyflag(PAE)willgoLOWwhentheread

pointeris"n+1"locationslessthanthewritepointer. Theoffset"n"isdefined

in the Empty Offset registers. If no reads are performed after Reset the

Programmable Almost-Empty flag (PAE) will go HIGH after "n+1" for the

IDT72421/72201/72211/72221/72231/72241/72251.

IfthereisnoEmptyoffsetspecified,theProgrammableAlmost-Emptyflag

(PAE)willgoLOWatEmpty+7words.

EMPTY FLAG (EF)

TheEmptyFlag(EF)willgoLOW,inhibitingfurtherreadoperations,when

thereadpointerisequaltothewritepointer,indicatingthedeviceisempty.

The Empty Flag (EF) is synchronized with respect to the LOW-to-HIGH

transitionoftheReadClock(RCLK).

TheProgrammableAlmost-Emptyflag(PAE)issynchronizedwithrespect

totheLOW-to-HIGHtransitionoftheReadClock(RCLK).

PROGRAMMABLE ALMOST-FULL FLAG (PAF)

The Programmable Almost-Full flag (PAF) will go LOW when the FIFO

reachesthealmost-fullcondition.IfnoreadsareperformedafterReset(RS),

theProgrammableAlmost-Fullflag(PAF)willgoLOWafter(64-m)writesforthe

IDT72421,(256-m)writesfortheIDT72201,(512-m)writesfortheIDT72211,

DATA OUTPUTS (Q0 - Q8)

Dataoutputsfora9-bitwidedata.

TABLE 1 — STATUS FLAGS

NUMBER OF WORDS IN FIFO

IDT72421

0

1 to n ⁽¹⁾

IDT72201

0

1 to n ⁽¹⁾

IDT72211

0

1 to n ⁽¹⁾

FF

H

L

PAF

H

PAE

L

EF

L

H

L

H

(n+1)to(64-(m+1))

(64-m)⁽²⁾to63

64

(n+1)to(256-(m+1))

(n+1)to(512-(m+1))

H

(2)

(256-m) to255

(512-m) to511

L

H

256

512

L

H

NUMBER OF WORDS IN FIFO

IDT72221

IDT72231

IDT72241

IDT72251

FF

PAF

PAE

EF

0

H

L

1ton⁽¹⁾

H

L

H

(n+1)to(1,024-(m+1))

(n+1)to(2,048-(m+1))

(n+1)to(4,096-(m+1))

(n+1)to(8,192-(m+1))

H

(2)

(1,024-m) to1,023

(2,048-m) to2,047

(4,096-m)⁽²⁾to4,095

4,096

(8,192-m)⁽²⁾to8,191

8,192

H

L

H

1,024

2,048

NOTES:

1. n = Empty Offset (n = 7 default value)

2. m = Full Offset (m = 7 default value)

©

OCTOBER22,2008

7

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

tRS

RS

REN1, REN2

WEN1

tRSS

tRSR

WEN2/LD⁽¹⁾

EF, PAE

tRSF

FF, PAF

tRSF

OE = 1⁽²⁾

Q0 - Q8

2655 drw 06

OE = 0

NOTES:

1. Holding WEN2/LD HIGH during reset will make the pin act as a second write enable pin. Holding WEN2/LD LOW during reset will make the pin act as a load enable for the programmable

flag offset registers.

2. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.

3. The clocks (RCLK, WCLK) can be free-running during reset.

Figure 4. Reset Timing

tCLK

tCLKH

tCLKL

WCLK

tDH

tDS

D0 - D8

DATA IN VALID

t

ENH

t

ENS

NO OPERATION

WEN1

t

tENS

WEN2/

(If Applicable)

t

WFF

tWFF

FF

(1)

tSKEW1

RCLK

REN1,

2655 drw 07

REN2

NOTE:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the current clock cycle. If the time between the rising edge of RCLK

and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.

Figure 5. Write Cycle Timing

©

OCTOBER22,2008

8

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

tCLK

tCLKH

tCLKL

RCLK

tENS

tENH

REN1,

REN2

NO OPERATION

tREF

EF

tA

VALID DATA

Q0 - Q8

tOLZ

tOHZ

tOE

OE

(1)

SKEW1

t

WCLK

WEN1

2655 drw 08

WEN2

NOTE:

1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between the rising edge of RCLK

and the rising edge of WCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.

Figure 6. Read Cycle Timing

WCLK

tDS

D0 - D8

D1

D2

D3

D0 (First Valid Write)

tENS

WEN1

WEN2

(If Applicable)

(1)

tFRL

tSKEW1

RCLK

tREF

EF

tENS

REN1,

REN2

tA

Q0 - Q8

D0

D1

tOLZ

tOE

OE

NOTE:

2655 drw 09

1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1

When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1

The Latency Timings apply only at the Empty Boundary (EF = LOW).

Figure 7. First Data Word Latency Timing

©

OCTOBER22,2008

9

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

NO WRITE

WCLK

tSKEW1

tDS

tSKEW1

D0 - D8

t

WFF

t

WFF

t

WFF

FF

(1)

t

ENH

tENS

t

ENS

WEN1

tENH

t

ENS

tENS

WEN2

(If Applicable)

RCLK

tENH

tENS

REN1,

REN2

tA

OE

LOW

tA

Q0

- Q8

DATA READ

NEXT DATA READ

DATA IN OUTPUT REGISTER

2655 drw 10

NOTE:

1. Only one of the two write enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.

Figure 8. Full Flag Timing

WCLK

tDS

D0 - D8

DATA WRITE 1

DATA WRITE 2

tENS

tENH

WEN1

tENS

tENH

WEN2

(If Applicable)

(1)

FRL

(1)

FFL

t

tSKEW1

RCLK

tREF

EF

REN1,

REN2

OE LOW

tA

Q0

- Q8

DATA READ

DATA IN OUTPUT REGISTER

2655 drw 11

NOTE:

1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1

When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK+ tSKEW1

The Latency Timings apply only at the Empty Boundary (EF = LOW).

Figure 9. Empty Flag Timing

©

OCTOBER22,2008

10

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

tCLKH

tCLKL

(4)

WCLK

t

ENH

t

ENS

WEN1

t

ENS

t

WEN2

(If Applicable)

t

PAF

Full - (m+1) words in FIFO⁽¹⁾

(2)

Full - m words in FIFO

(3)

SKEW2

t

PAF

RCLK

tENH

tENS

REN1,

2655 drw 12

REN2

NOTES:

1. m = PAF offset .

2. 64-m words in FIFO for IDT72421, 256-m words for IDT72201, 512-m words for IDT72211, 1,024-m words for IDT72221, 2,048-m words for IDT72231, 4,096-m words for IDT72241,

and 8,192-m words for IDT72251.

3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK and

the rising edge of WCLK is less than tSKEW2, then PAF may not change state until the next WCLK rising edge.

4. If a write is performed on this rising edge of the Write Clock, there will be Full - (m-1) words in the FIFO when PAF goes LOW.

Figure 10. Programmable Full Flag Timing

tCLKH

tCLKL

WCLK

t

ENS

t

ENH

WEN1

t

WEN2

(If Applicable)

n words in FIFO ⁽¹⁾

n+1 words in FIFO

PAE

(2)

tSKEW2

t

PAE

tPAE

(3)

RCLK

tENS

tENH

REN1,

2655 drw 13

REN2

NOTES:

1. n = PAE offset.

2. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to change during that clock cycle. If the time between the rising edge of WCLK and

the rising edge of RCLK is less than tSKEW2, then PAE may not change state until the next RCLK rising edge.

3. If a read is performed on this rising edge of the Read Clock, there will be Empty + (n-1) words in the FIFO when PAE goes LOW.

Figure 11. Programmable Empty Flag Timing

©

OCTOBER22,2008

11

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

tCLK

tCLKH

tCLKL

WCLK

tENH

tENS

LD

tENS

WEN1

tDS

tDH

D0 - D7

PAE OFFSET

(LSB)

PAE OFFSET

(MSB)

PAF OFFSET

(LSB)

PAF OFFSET

(MSB)

2655 drw 14

Figure 12. Write Offset Registers Timing

tCLK

tCLKH

tCLKL

RCLK

tENS

tENH

LD

tENS

REN1,

REN2

tA

EMPTY OFFSET

(LSB)

EMPTY OFFSET

(MSB)

FULL OFFSET

(LSB)

DATA IN OUTPUT REGISTER

Q0 - Q7

FULL OFFSET

(MSB)

2655 drw15

Figure 13. Read Offset Registers Timing

©

OCTOBER22,2008

12

IDT72421/72201/72211/72221/72231/72241/72251 CMOS SyncFIFO™

64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

configuration,theWriteEnable2/Load(WEN2/LD)pinissetLOWatResetso

thatthepinoperatesasacontroltoloadandreadtheprogrammableflagoffsets.

OPERATINGCONFIGURATIONS

SINGLE DEVICE CONFIGURATION

AsingleIDT72421/72201/72211/72221/72231/72241/72251maybeused

when the application requirements are for 64/256/512/1,024/2,048/4,096/

8,192wordsorless.WhentheseFIFOsareinaSingleDeviceConfiguration,

theReadEnable2(REN2)controlinputcanbegrounded(seeFigure14). In

thisconfiguration,theWriteEnable2/Load(WEN2/LD)pinissetLOWatReset

sothatthe pinoperates as a controltoloadandreadthe programmable flag

offsets.

DEPTH EXPANSION - The IDT72421/72201/72211/72221/72231/72241/

72251canbeadaptedtoapplicationswhentherequirementsareforgreater

than 64/256/512/1,024/2,048/4,096/8,192 words. The existence of two

enable pins on the read and write port allow depth expansion. The Write

Enable 2/Load pin is used as a second write enable in a depth expansion

configurationthustheProgrammableflagsaresettothedefaultvalues. Depth

expansionis possiblebyusingoneenableinputforsystemcontrolwhilethe

otherenableinputiscontrolledbyexpansionlogictodirecttheflowofdata. A

typicalapplicationwouldhavetheexpansionlogicalternatedataaccessfrom

onedevicetothenextinasequentialmanner. Thesedevices operateinthe

DepthExpansionconfigurationwhenthefollowingconditionsaremet:

1. The WEN2/ LD pin is held HIGH during Reset so that this pin operates a

secondWriteEnable.

WIDTH EXPANSION CONFIGURATION

Wordwidthmaybeincreasedsimplybyconnectingthecorrespondinginput

controlssignalsofmultipledevices. Acompositeflagshouldbecreatedforeach

oftheendpointstatusflags(EFandFF). Thepartialstatusflags(AEandAF)

canbedetectedfromanyonedevice. Figure15demonstratesa18-bitword

width by using two IDT72421/72201/72211/72221/72231/72241/72251s.

AnywordwidthcanbeattainedbyaddingadditionalIDT72421/72201/72211/

72221/72231/72241/72251s.

2. Externallogicis usedtocontrolthe flowofdata.

Please see the Application Note "DEPTH EXPANSION OF IDT'S SYN-

CHRONOUSFIFOsUSINGTHERINGCOUNTERAPPROACH"fordetails

ofthisconfiguration.

When these FIFOs are in a Width Expansion Configuration, the Read

Enable 2 (REN2) control input can be grounded (see Figure 15). In this

RESET (RS)

WRITE CLOCK (WCLK)

WRITE ENABLE 1 (WEN1)

READ CLOCK (RCLK)

IDT

READ ENABLE 1 (REN1)

OUTPUT ENABLE (OE)

72421

72201

72211

72221

72231

72241

72251

WRITE ENABLE 2/LOAD (WEN2/LD)

DATA IN (D

0

- D8)

DATA OUT (Q

EMPTY FLAG (EF)

PROGRAMMABLE ALMOST-EMPTY (PAE)

0 - Q8)

FULL FLAG (FF)

PROGRAMMABLE ALMOST-FULL (PAF)

2655 drw 16

READ ENABLE 2 (REN2)

Figure 14. Block Diagram of Single 64 x 9, 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 Synchronous FIFO

RESET (RS)

DATA IN (D)

18

9

READ CLOCK (RCLK)

WRITE CLOCK (WCLK)

READ ENABLE (REN)

OUTPUT ENABLE (OE)

PROGRAMMABLE (PAE)

WRITE ENABLE1 (WEN1)

IDT

72421

72201

72211

72221

72231

72241

72251

72421

72201

72211

72221

72231

72241

72251

WRITE ENABLE2/LOAD (WEN2/LD)

FULL FLAG (FF) #1

FULL FLAG (FF) #2

EMPTY FLAG (EF) #1

EMPTY FLAG (EF) #2

9

PROGRAMMABLE (PAF)

18

9

DATA OUT (Q)

2655 drw 17

READ ENABLE 2 (REN2)

Figure 15. Block Diagram of 64 x 18, 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18

Synchronous FIFO Used in a Width Expansion Configuration

©

OCTOBER22,2008

13

ORDERING INFORMATION

XXXXX

X

XX

X

Device Type Power Speed Package

Process/

Temperature

Range

BLANK Commercial (0°C to +70°C)

I⁽¹⁾

Industrial (-40° to +85°C)

G⁽²⁾

Green

J

PF

Plastic Leaded Chip Carrier (PLCC, J32-1)

Thin Quad Flat Pack (TQFP, PR32-1)

Commercial Only

Commercial & Industrial

10

15

25

Clock Cycle Time (tCLK

Speed in Nanoseconds

)

Low Power

L

64 x 9 ⎯ SyncFIFO

72421

72201

72211

72221

72231

72241

72251

256 x 9 ⎯ SyncFIFO

512 x 9 ⎯ SyncFIFO

1,024 x 9 ⎯ SyncFIFO

2,048 x 9 ⎯ SyncFIFO

4,096 x 9 ⎯ SyncFIFO

8,192 x 9 ⎯ SyncFIFO

2655 drw18

NOTES:

1. Industrial temperature range product for the 15ns and 25ns speed grades are available as standard product.

2. Green parts are available. For specific speeds and packages contact your sales office.

DATASHEETDOCUMENTHISTORY

10/03/2000

05/01/2001

02/08/2006

10/22/2008

pgs. 2, 3, 4 and 14.

pgs. 1, 2, 3, 4 and 14.

pgs. 1 and 14.

pg. 14.

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

for Tech Support:

408-360-1753

email:FIFOhelp@idt.com

800-345-7015 or 408-284-8200

fax: 408-284-2775

www.idt.com

14


型号：	72201L10J8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	PLCC-32, Reel
文件：	总14页 (文件大小：126K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

72201L10J8 [IDT]

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