72291L25PFG [IDT]
FIFO;
| 型号： | 72291L25PFG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO 先进先出芯片 |
| 文件： | 总26页 (文件大小：418K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS SuperSync FIFO™
65,536 x 9
131,072 x 9
IDT72281
IDT72291
• Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-
pin Slim Thin Quad Flat Pack (STQFP)
• High-performance submicron CMOS technology
• Industrial temperature range (-40°C to +85°C) is available
FEATURES:
• Choose among the following memory organizations:
IDT72281
IDT72291
65,536 x 9
131,072 x 9
• Pin-compatible with the IDT72261LA/72271LA SuperSync FIFOs
• 10ns read/write cycle time (6.5ns access time)
• Fixed, low first word data latency time
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable
settings
• Retransmit operation with fixed, low first word data
latency time
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of two preselected offsets
• Program partial flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First
Word Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
DESCRIPTION:
TheIDT72281/72291areexceptionallydeep,highspeed,CMOSFirst-In-
First-Out(FIFO)memorieswithclockedreadandwritecontrols. TheseFIFOs
offernumerousimprovementsoverpreviousSuperSyncFIFOs,includingthe
following:
• Thelimitationofthefrequencyofoneclockinputwithrespecttotheotherhas
been removed. The Frequency Select pin (FS) has been removed, thus
it is no longer necessary to select which of the two clock inputs, RCLK or
WCLK, is running at the higher frequency.
• The period required by the retransmit operation is now fixed and short.
• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan
emptyFIFOtothetimeitcanberead,isnowfixedandshort. (Thevariable
clock cycle counting delay associated with the latency period found on
previousSuperSyncdeviceshasbeeneliminatedonthisSuperSyncfamily.)
SuperSyncFIFOsareparticularlyappropriatefornetwork,video,telecom-
munications,datacommunicationsandotherapplicationsthatneedtobuffer
largeamountsofdata.
• Independent Read and Write clocks (permit reading and writing
simultaneously)
FUNCTIONALBLOCKDIAGRAM
D0 -D8
WEN
WCLK
LD
SEN
OFFSET REGISTER
INPUT REGISTER
FF/IR
PAF
EF/OR
PAE
FLAG
LOGIC
WRITE CONTROL
LOGIC
HF
FWFT/SI
RAM ARRAY
65,536 x 9
131,072 x 9
WRITE POINTER
READ POINTER
READ
CONTROL
LOGIC
RT
OUTPUT REGISTER
MRS
PRS
RESET
LOGIC
RCLK
REN
Q0 -Q8
4675 drw01
OE
IDT, IDTlogoareregisteredtrademarksofIntegratedDeviceTechnology, Inc. TheSuperSyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
MARCH 2013
1
©
2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4675/5
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
operation,whichconsistsofactivatingRENandenablingarisingRCLKedge,
willshiftthewordfrominternalmemorytothedataoutputlines.
DESCRIPTION(CONTINUED)
InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectlyto
thedataoutputlinesafter threetransitionsoftheRCLKsignal.ARENdoesnot
havetobeassertedforaccessingthefirstword.However,subsequentwords
writtentotheFIFOdorequireaLOWonRENforaccess. ThestateoftheFWFT/
SIinputduringMasterResetdeterminesthetimingmodeinuse.
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFOcan
provide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs
inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding
data inputs of the next). No external logic is required.
TheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable
(WEN)input. DataiswrittenintotheFIFOoneveryrisingedgeofWCLKwhen
WENisasserted.TheoutputportiscontrolledbyaReadClock(RCLK)input
andReadEnable(REN)input. DataisreadfromtheFIFOoneveryrisingedge
ofRCLKwhenRENisasserted. AnOutputEnable(OE)inputisprovidedfor
three-statecontroloftheoutputs.
ThefrequenciesofboththeRCLKandtheWCLKsignalsmayvaryfrom0
tofMAXwithcompleteindependence. Therearenorestrictionsonthefrequency
oftheoneclockinputwithrespecttotheother.
TheseFIFOshavefiveflagpins,EF/OR(EmptyFlagorOutputReady),FF/
IR(FullFlagorInputReady),HF(Half-fullFlag),PAE(ProgrammableAlmost-
Emptyflag)andPAF(ProgrammableAlmost-Fullflag). TheEFandFFfunctions
areselectedinIDTStandardmode. TheIRandORfunctionsareselectedin
Therearetwopossibletimingmodesofoperationwiththesedevices:IDT
Standard mode and First Word Fall Through (FWFT) mode.
InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear
onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread
PINCONFIGURATIONS
PIN 1
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
WEN
SEN
DC(1)
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
DNC(3)
DNC(3)
GND
DNC(3)
DNC(3)
2
3
VCC
4
VCC
5
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
GND(2)
D8
6
VCC
DNC(3)
DNC(3)
DNC(3)
GND
DNC(3)
DNC(3)
Q8
7
8
9
10
11
12
13
14
15
16
Q7
Q6
D7
GND
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
4675 drw 02
TQFP (PN64-1, ORDER CODE: PF)
STQFP (PP64-1, ORDER CODE: TF)
TOP VIEW
NOTES:
1. DC = Don’t Care. Must be tied to GND or VCC, cannot be left open.
2. This pin may either be tied to GND or left open.
3. DNC = Do Not Connect.
2
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
StandardmodeorFWFTmode. TheLDpinselectseitherapartialflagdefault
settingof127withparallelprogrammingorapartialflagdefaultsettingof1,023
withserialprogramming. Theflagsareupdatedaccordingtothetimingmode
anddefaultoffsetsselected.
DESCRIPTION(CONTINUED)
FWFTmode. HF,PAEandPAFarealwaysavailableforuse,irrespectiveof
timingmode.
The Partial Reset (PRS) also sets the read and write pointers to the first
locationofthememory. However,thetimingmode,partialflagprogramming
method,anddefaultorprogrammedoffsetsettingsexistingbeforePartialReset
remainunchanged.Theflagsareupdatedaccordingtothetimingmodeand
offsets in effect. PRS is useful for resetting a device in mid-operation, when
reprogrammingpartialflagswouldbeundesirable.
TheRetransmitfunctionallowsdatatoberereadfromtheFIFOmorethan
once. ALOWontheRTinputduringarisingRCLKedgeinitiatesaretransmit
operationbysettingthereadpointertothefirstlocationofthememoryarray.
If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill
automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply
currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
The IDT72281/72291 are fabricated using high speed submicron CMOS
technology.
PAEandPAFcanbeprogrammedindependentlytoswitchatanypointin
memory. (SeeTableIandTableII.) Programmableoffsetsdeterminetheflag
switchingthresholdandcanbeloadedbytwomethods:parallelorserial. Two
defaultoffsetsettingsarealsoprovided,sothatPAEcanbesettoswitchat127
or1,023locationsfromtheemptyboundaryandthePAFthresholdcanbeset
at127or1,023locationsfromthefullboundary. Thesechoicesaremadewith
the LD pin during Master Reset.
For serialprogramming,SENtogetherwithLDoneachrisingedgeofWCLK,
are used to load the offset registers via the Serial Input (SI). For parallel
programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused
toloadtheoffsetregistersviaDn. RENtogetherwithLDoneachrisingedge
ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether
serialorparalleloffsetloadinghasbeenselected.
DuringMasterReset(MRS)thefollowingeventsoccur:Thereadandwrite
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
PARTIAL RESET (PRS) MASTER RESET (MRS)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
DATA OUT (Q0 - Qn)
DATA IN (D0 - Dn)
IDT
72281
72291
RETRANSMIT (RT)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
FULL FLAG/INPUT READY (FF/IR)
HALF-FULL FLAG (HF)
PROGRAMMABLE ALMOST-FULL (PAF)
4675 drw 03
Figure 1. Block Diagram of Single 65,536 x 9 and 131,072 x 9 Synchronous FIFO
3
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTION
Symbol
D0–D8
MRS
Name
I/O
Description
DataInputs
I
I
Datainputsfora9-bitbus.
MasterReset
PartialReset
Retransmit
MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During
Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, one of two program-
mableflagdefaultsettings,andserialorparallelprogrammingoftheoffsetsettings.
PRS
RT
I
I
PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During
Partial Reset, the existing mode (IDT or FWFT), programming method (serial or parallel), and
programmableflagsettingsareallretained.
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to
LOW (OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, program
ming method, existing timing mode or programmable flag settings. RT is useful to reread data from
the first physical location of the FIFO.
FWFT/SI
WCLK
FirstWordFall
Through/Serial In
I
I
During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset,
thispinfunctionsasaserialinputforloadingoffsetregisters
WriteClock
When enabled by WEN, the rising edge of WCLK writes data into the FIFO and offsets into the
programmable registers for parallel programming, and when enabled by SEN, the rising edge of
WCLKwritesonebitofdataintotheprogrammableregisterforserialprogramming.
WEN
RCLK
WriteEnable
ReadClock
I
I
WENenablesWCLKforwritingdataintotheFIFOmemoryandoffsetregisters.
When enabled by REN, the rising edge of RCLK reads data from the FIFO memory and offsets from
theprogrammableregisters.
REN
OE
SEN
LD
Read Enable
OutputEnable
SerialEnable
Load
I
I
I
I
REN enablesRCLKforreadingdatafromtheFIFOmemoryandoffsetregisters.
OEcontrolstheoutputimpedanceofQn.
SENenablesserialloadingofprogrammableflagoffsets.
During Master Reset, LD selects one of two partial flag default offsets (127 or 1,023 and determines
the flag offset programming method, serial or parallel. After Master Reset, this pin enables writing to
andreadingfromtheoffsetregisters.
DC
Don't Care
I
This pin must be tied to either VCC or GND and must not toggle after Master Reset.
FF/IR
Full Flag/
Input Ready
O
In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO
memory is full. In the FWFT mode, the IRfunction is selected. IR indicates whether or not there is
spaceavailableforwritingtotheFIFOmemory.
EF/OR
PAF
EmptyFlag/
OutputReady
O
O
O
In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO
memory is empty. In FWFT mode, the OR function is selected. OR indicates whether or not there
isvaliddataavailableattheoutputs.
Programmable
Almost-FullFlag
PAF goes LOW if the number of words in the FIFO memory is more than total word capacity of the
FIFOminusthefulloffsetvaluem, whichisstoredintheFullOffsetregister. Therearetwopossible
default values for m: 127 or 1,023.
PAE
Programmable
Almost-EmptyFlag
PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in
the Empty Offset register. There are two possible default values for n: 127 or 1,023. Other values
for n can be programmed into the device.
HF
Q0–Q8
VCC
Half-FullFlag
DataOutputs
Power
O
O
HF indicateswhethertheFIFOmemoryismoreorlessthanhalf-full.
Dataoutputsfora9-bus
+5 Volt power supply pins.
GND
Ground
Groundpins.
4
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ABSOLUTEMAXIMUMRATINGS
RECOMMENDEDDCOPERATING
CONDITIONS
Symbol
Rating
Commercial
Unit
VTERM
TerminalVoltage
–0.5 to +7
V
Symbol
Parameter
Min.
Typ.
Max.
Unit
with respect to GND
VCC
Supply Voltage(Com’l & Ind’l)
Supply Voltage(Com’l & Ind’l)
4.5
5.0
5.5
V
TSTG
IOUT
Storage
Temperature
–55to+125
–50to+50
°C
GND
VIH
0
0
0
V
InputHighVoltage
(Com’l & Ind’l)
DCOutputCurrent
mA
2.0
—
—
V
NOTE:
(1)
VIL
InputLowVoltage
(Com’’ & Ind’l)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
—
0
—
—
0.8
70
V
TA
OperatingTemperature
Commercial
°C
TA
OperatingTemperature
Industrial
-40
—
85
°C
NOTE
1. 1.5V undershoots are allowed for 10ns once per cycle.
DCELECTRICALCHARACTERISTICS
(Commercial: VCC = 5V 10%, TA = 0°C to +70°C; Industrial: VCC = 5V 10%, TA = -40° to +85°C)
IDT72281
IDT72291
Commercial & Industrial(1)
tCLK = 10, 15, 20 ns
Symbol
Parameter
Min.
Max.
Unit
(2)
ILI
InputLeakageCurrent
OutputLeakageCurrent
–1
1
μA
μA
V
(3)
ILO
–10
2.4
—
10
—
VOH
VOL
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
0.4
V
(4,5,6)
ICC1
Active Power Supply Current
StandbyCurrent
—
—
80
20
mA
mA
(4,7)
ICC2
NOTES:
1. Industrial temperature range product for 15ns and 20ns speed grade are available as a standard device.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 20 + 1.8*fS + 0.02*CL*fS (in mA) with VCC = 5V, tA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching
at fS/2, CL = capacitive load (in pF).
7. All Inputs = VCC – 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
VIN = 0V
10
pF
Capacitance
(1,2)
COUT
Output
VOUT = 0V
10
pF
Capacitance
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
5
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ACELECTRICALCHARACTERISTICS(1)
(Commercial: VCC = 5V 10%, TA = 0°C to +70°C; Industrial: VCC = 5V 10%, TA = -40°C to +85°C)
Commercial
Commercial & Industrial(2)
IDT72281L10
IDT72291L10
IDT72281L15
IDT72291L15
IDT72281L20
IDT72291L20
Symbol
Parameter
Clock Cycle Frequency
Min.
Max.
Min.
Max.
Min.
Max.
Unit
fS
—
2
100
—
2
66.7
—
2
50
MHz
tA
DataAccessTime
6.5
—
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
6
10
—
—
—
—
—
—
—
—
—
—
—
—
15
—
—
—
8
12
—
—
—
—
—
—
—
—
—
—
—
—
20
—
—
—
10
10
12
12
12
12
22
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time
10
4.5
4.5
3
15
6
20
8
Clock High Time
Clock Low Time
6
8
DataSetupTime
4
5
tDH
DataHoldTime
0
1
1
tENS
tENH
tLDS
tLDH
tRS
EnableSetupTime
3
4
5
EnableHoldTime
0
1
1
LoadSetupTime
3
4
5
LoadHoldTime
ResetPulseWidth(3)
0
1
1
10
10
10
—
0
15
15
15
—
0
20
20
20
—
0
tRSS
tRSR
tRSF
tFWFT
tRTS
tOLZ
tOE
ResetSetupTime
ResetRecoveryTime
ResettoFlagandOutputTime
ModeSelectTime
RetransmitSetupTime
OutputEnabletoOutputinLowZ(4)
OutputEnabletoOutputValid
OutputEnabletoOutputinHighZ(4)
Write Clock to FF or IR
Read Clock to EF or OR
Write Clock to PAF
3
4
5
0
0
0
2
3
3
tOHZ
tWFF
tREF
tPAF
tPAE
tHF
2
6
3
8
3
—
—
—
—
—
5
6.5
6.5
6.5
6.5
16
—
—
—
—
—
—
—
—
6
10
10
10
10
20
—
—
—
—
—
—
—
—
10
20
60
Read Clock to PAE
Clock to HF
tSKEW1
tSKEW2
tSKEW3
Skew time between RCLK and WCLK for FF/IR
Skew time between RCLK and WCLK for PAE and PAF
Skew time between RCLK and WCLK for EF/OR
12
60
15
60
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for 15ns and 20ns speed grade are available as a standard device.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
5V
1.1K
D.U.T.
ACTESTCONDITIONS
30pF*
680Ω
InputPulseLevels
GND to 3.0V
3ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
OutputLoad
4675 drw 04
1.5V
* Includes jig and scope capacitances.
1.5V
SeeFigure2
Figure 2. Output Load
6
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
When configured in IDT Standard mode, the EF and FF outputs are
double register-buffered outputs.
FUNCTIONALDESCRIPTION
Relevant timing diagrams for IDT Standard mode can be found in Figure
7, 8 and 11.
TIMING MODES: IDT STANDARD VS FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72281/72291 support two different timing modes of operation:
IDT Standard mode or First Word Fall Through (FWFT) mode. The selec-
tion of which mode will operate is determined during Master Reset, by the
state of the FWFT/SI input.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 2. To write data into to the FIFO, WEN must be
LOW. Data presented to the DATA IN lines will be clocked into the FIFO on
subsequent transitions of WCLK. After the first write is performed, the Output
Ready (OR) flag will go LOW. Subsequent writes will continue to fill up the
FIFO. PAE will go HIGH after n + 2 words have been loaded into the FIFO,
where n is the empty offset value. The default setting for this value is stated
in the footnote of Table 2. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the 32,770th
word for the IDT72281 and 65,538th word for the IDT72291, respectively
was written into the FIFO. Continuing to write data into the FIFO will cause
the PAF to go LOW. Again, if no reads are performed, the PAF will go LOW
after (65,537-m) writes for the IDT72281 and (131,073-m) writes for the
IDT72291, where m is the full offset value. The default setting for this value
is stated in the footnote of Table 2.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (EF) to indicate whether or
not there are any words present in the FIFO. It also uses the Full Flag
function (FF) to indicate whether or not the FIFO has any free space for
writing. In IDT Standard mode, every word read from the FIFO, including
the first, must be requested using the Read Enable (REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will
be selected. This mode uses Output Ready (OR) to indicate whether or not
there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to
indicate whether or not the FIFO has any free space for writing. In the
FWFT mode, the first word written to an empty FIFO goes directly to Qn
after three RCLK rising edges, REN = LOW is not necessary. Subsequent
words must be accessed using the Read Enable (REN) and RCLK.
Various signals, both input and output signals operate differently depend-
ing on which timing mode is in effect.
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting
further write operations. If no reads are performed after a reset, IR will go
HIGH after D writes to the FIFO. D = 65,537 writes for the IDT72281 and
131,073 writes for the IDT72291, respectively. Note that the additional word
in FWFT mode is due to the capacity of the memory plus output register.
If the FIFO is full, the first read operation will cause the IR flag to go LOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 2. If further read operations occur, without
write operations, the PAE will go LOW when there are n + 1 words in the
FIFO, where n is the empty offset value. Continuing read operations will
cause the FIFO to become empty. When the last word has been read from
the FIFO, OR will go HIGH inhibiting further read operations. REN is ig-
nored when the FIFO is empty.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manner outlined in Table 1. To write data into to the FIFO, Write Enable
(WEN) must be LOW. Data presented to the DATA IN lines will be clocked
into the FIFO on subsequent transitions of the Write Clock (WCLK). After the
first write is performed, the Empty Flag (EF) will go HIGH. Subsequent
writes will continue to fill up the FIFO. The Programmable Almost-Empty flag
(PAE) will go HIGH after n + 1 words have been loaded into the FIFO,
where n is the empty offset value. The default setting for this value is stated
in the footnote of Table 1. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (HF) would toggle to LOW
once the 32,769th word for IDT72281 and 65,537th word for IDT72291
respectively was written into the FIFO. Continuing to write data into the
FIFO will cause the Programmable Almost-Full flag (PAF) to go LOW.
Again, if no reads are performed, the PAF will go LOW after (65,536-m)
writes for the IDT72281 and (131,072-m) writes for the IDT72291. The
offset “m” is the full offset value. The default setting for this value is stated in
the footnote of Table 1. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further write
operations. If no reads are performed after a reset, FF will go LOW after D
writes to the FIFO. D = 65,536 writes for the IDT72281 and 131,072 for the
IDT72291, respectively.
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and HF to go HIGH at the
conditions described in Table 1. If further read operations occur, without
write operations, PAE will go LOW when there are n words in the FIFO,
where n is the empty offset value. Continuing read operations will cause the
FIFO to become empty. When the last word has been read from the FIFO,
the EF will go LOW inhibiting further read operations. REN is ignored when
the FIFO is empty.
When configured in FWFT mode, the OR flag output is triple register-
buffered, and the IR flag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 9, 10
and 12.
PROGRAMMING FLAG OFFSETS
Full and Empty Flag offset values are user programmable. The IDT72281/
72291 has internal registers for these offsets. Default settings are stated in
the footnotes of Table 1 and Table 2. Offset values can be programmed into
the FIFO in one of two ways; serial or parallel loading method. The selec-
tion of the loading method is done using the LD (Load) pin. During Master
Reset, the state of the LD input determines whether serial or parallel flag
offset programming is enabled. A HIGH on LD during Master Reset selects
serial loading of offset values and in addition, sets a default PAE offset value
of 3FFH (a threshold 1,023 words from the empty boundary), and a default
PAF offset value of 3FFH (a threshold 1,023 words from the full boundary).
A LOW on LD during Master Reset selects parallel loading of offset values,
and in addition, sets a default PAE offset value of 07FH (a threshold 127
words from the empty boundary), and a default PAF offset value of 07FH (a
threshold 127 words from the full boundary). See Figure 3, Offset Register
Location and Default Values.
7
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE
IDT72281
IDT72291
FF
H
H
H
H
H
L
PAF HF PAE EF
0
0
H
H
H
H
L
H
H
H
L
L
L
L
H
H
H
H
H
1 to n(1)
1 to n(1)
Number of
Words in
FIFO
(n + 1) to 32,768
32,769 to (65,536–(m+1))
(n + 1) to 65,536
65,537 to (131,072–(m+1))
H
H
H
H
(65,536
–
m)(2) to65,535
65,536
(131,072
–
m)(2) to131,071
L
131,072
L
L
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
TABLE 2 — STATUS FLAGS FOR FWFT MODE
IDT72281
IDT72291
0
1 to n+ 1(1)
FF
L
PAF HF PAE EF
0
H
H
H
H
L
H
H
H
L
L
L
H
L
L
L
L
L
1 to n+ 1(1)
L
Number of
Words in
FIFO
(n + 2) to 32,769
32,770 to (65,537–(m+1))(2)
(n + 2) to 65,537
65,538 to (131,073–(m+1))(2)
L
H
H
H
H
L
(65,537
–
m)(2) to65,536
65,537
(131,073
–
m)(2) to131,072
L
L
131,073
H
L
L
NOTES:
1. n = Empty Offset, Default Values: n = 127 when parallel offset loading is selected or n = 1,023 when serial offset loading is selected.
2. m = Full Offset, Default Values: m = 127 when parallel offset loading is selected or m = 1,023 when serial offset loading is selected.
8
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72281 (65,536 x 9 ⎯ BIT)
IDT72291 (131,072 x 9 ⎯ BIT)
8
8
8
7
7
0
0
0
8
8
7
7
0
0
EMPTY OFFSET (LSB) REGISTER
EMPTY OFFSET (LSB) REGISTER
DEFAULT VALUE
7FH if LD is LOW at Master Reset
FFH if LD is HIGH at Master Reset
DEFAULT VALUE
7FH if LD is LOW at Master Reset
FFH if LD is HIGH at Master Reset
EMPTY OFFSET (MSB) REGISTER
EMPTY OFFSET (MID-BYTE) REGISTER
DEFAULT VALUE
00H if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
DEFAULT VALUE
00H if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
7
8
1
0
EMPTY OFFSET
(MSB) REGISTER
FULL OFFSET (LSB) REGISTER
DEFAULT
0H
DEFAULT VALUE
7FH if LD is LOW at Master Reset
FFH if LD is HIGH at Master Reset
8
8
7
7
0
FULL OFFSET (LSB) REGISTER
8
7
0
FULL OFFSET (MSB) REGISTER
DEFAULT VALUE
7FH if LD is LOW at Master Reset
FFH if LD is HIGH at Master Reset
DEFAULT VALUE
00H if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
0
FULL OFFSET (MID-BYTE) REGISTER
DEFAULT VALUE
00H if LD is LOW at Master Reset
03H if LD is HIGH at Master Reset
8
1
0
FULL OFFSET
(MSB) REGISTER
DEFAULT
0H
4675 drw06
Figure 3. Offset Register Location and Default Values
WCLK
RCLK
X
LD WEN REN SEN
IDT72281
IDT72291
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Parallel write to registers:
Empty Offset (LSB)
0
0
0
0
1
1
1
0
1
1
1
0
Empty Offset (Mid-Byte)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Full Offset (Mid-Byte)
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (Mid-Byte)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (Mid-Byte)
Full Offset (MSB)
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
X
Serial shift into registers:
32 bits for the IDT72281
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
Serial shift into registers:
34 bits for the IDT72291
1 bit for each rising WCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
X
X
X
No Operation
No Operation
Write Memory
X
1
1
0
1
1
X
X
Write Memory
X
X
1
1
X
1
0
1
X
X
Read Memory
No Operation
Read Memory
X
No Operation
4675 drw07
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 4. Programmable Flag Offset Programming Sequence
9
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ter. See Figure 15, Parallel Loading of Programmable Flag Registers for
the IDT72291, for the timing diagram for this mode.
SERIAL PROGRAMMING MODE
If Serial Programming mode has been selected, as described above,
then programming of PAE and PAF values can be achieved by using a
combination of the LD, SEN, WCLK and SI input pins. Programming PAE
and PAF proceeds as follows: when LD and SEN are set LOW, data on the
SI input are written, one bit for each WCLK rising edge, starting with the
Empty Offset LSB and ending with the Full Offset MSB. A total of 32 bits for
the IDT72281 and 34 bits for the IDT72291. See Figure 13, Serial Loading
of Programmable Flag Registers, for the timing diagram for this mode.
Using the serial method, individual registers cannot be programmed se-
lectively. PAE and PAF can show a valid status only after the complete set
of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered.
When LD is LOW and SEN is HIGH, no serial write to the registers can
occur.
The act of writing offsets in parallel employs a dedicated write offset
register pointer. The act of reading offsets employs a dedicated read offset
register pointer. The two pointers operate independently; however, a read
and a write should not be performed simultaneously to the offset registers. A
Master Reset initializes both pointers to the Empty Offset (LSB) register. A
Partial Reset has no effect on the position of these pointers.
Write operations to the FIFO are allowed before and during the parallel
programming sequence. In this case, the programming of all offset registers
does not have to occur at one time. One, two or more offset registers can be
written and then by bringing LD HIGH, write operations can be redirected
to the FIFO memory. When LD is set LOW again, and WEN is LOW, the
next offset register in sequence is written to. As an alternative to holding
WEN LOW and toggling LD, parallel programming can also be interrupted
by setting LD LOW and toggling WEN.
Note that the status of a partial flag (PAE or PAF) output is invalid during
the programming process. From the time parallel programming has begun,
a partial flag output will not be valid until the appropriate offset word has
been written to the register(s) pertaining to that flag. Measuring from the
rising WCLK edge that achieves the above criteria; PAF will be valid after
two more rising WCLK edges plus tPAF, PAE will be valid after the next two
rising RCLK edges plus tPAE plus tSKEW2.
The act of reading the offset registers employs a dedicated read offset
register pointer. The contents of the offset registers can be read on the Q0-
Qn pins when LD is set LOW and REN is set LOW. For the IDT72281, data
are read via Qn from the Empty Offset LSB Register on the first LOW-to-
HIGH transition of RCLK. Upon the second LOW-to-HIGH transition of RCLK,
data are read from the Empty Offset MSB Register. Upon the third LOW-to-
HIGH transition of RCLK, data are read from the Full Offset LSB Register.
Upon the fourth LOW-to-HIGH transition of RCLK, data are read from the
Full Offset MSB Register. The fifth transition of RCLK reads, once again,
from the Empty Offset LSB Register. See Figure 16, Parallel Read of Pro-
grammable Flag Registers for the IDT72281, for the timing diagram for this
mode.
For the IDT72291, data is read via Qn from the Empty Offset LSB Regis-
ter on the first LOW-to-HIGH transition of RCLK. Upon the second LOW-to-
HIGH transition of RCLK, data are read from the Empty Offset Mid-Byte
Register. Upon the third LOW-to-HIGH transition of RCLK, data are read
from the Empty Offset MSB Register. Upon the fourth LOW-to-HIGH transi-
tion of RCLK, data are read from the Full Offset LSB Register. Upon the fifth
LOW-to-HIGH transition of RCLK, data are read from the Full Offset Mid-
Byte Register. Upon the sixth LOW-to-HIGH transition of RCLK, data are
read from the Full Offset MSB Register. The seventh transition of RCLK
reads, once again, from the Empty Offset LSB Register. See Figure 17,
Parallel Read of Programmable Flag Registers for the IDT72291, for the
timing diagram for this mode.
It is permissible to interrupt the offset register read sequence with reads
or writes to the FIFO. The interruption is accomplished by deasserting
REN, LD, or both together. When REN and LD are restored to a LOW
level, reading of the offset registers continues where it left off. It should be
noted, and care should be taken from the fact that when a parallel read of
the flag offsets is performed, the data word that was present on the output
lines Qn will be overwritten.
Write operations to the FIFO are allowed before and during the serial
programming sequence. In this case, the programming of all offset bits does
not have to occur at once. A select number of bits can be written to the SI
input and then, by bringing LD and SEN HIGH, data can be written to FIFO
memory via Dn by toggling WEN. When WEN is brought HIGH with LD and
SEN restored to a LOW, the next offset bit in sequence is written to the
registers via SI. If an interruption of serial programming is desired, it is
sufficient either to set LD LOW and deactivate SEN or to set SEN LOW and
deactivate LD. Once LD and SEN are both restored to a LOW level, serial
offset programming continues.
From the time serial programming has begun, neither partial flag will be
valid until the full set of bits required to fill all the offset registers has been
written. Measuring from the rising WCLK edge that achieves the above
criteria; PAF will be valid after two more rising WCLK edges plus tPAF, PAE
will be valid after the next two rising RCLK edges plus tPAE plus tSKEW2.
It is not possible to read the flag offset values in a serial mode.
PARALLEL MODE
If Parallel Programming mode has been selected, as described above,
then programming of PAE and PAF values can be achieved by using a
combination of the LD, WCLK , WEN and Dn input pins. For the IDT72281,
programming PAE and PAF proceeds as follows: when LD and WEN are
set LOW, data on the inputs Dn are written into the Empty Offset LSB
Register on the first LOW-to-HIGH transition of WCLK. Upon the second
LOW-to-HIGH transition of WCLK, data are written into the Empty Offset
MSB Register. Upon the third LOW-to-HIGH transition of WCLK, data are
written into the Full Offset LSB Register. Upon the fourth LOW-to-HIGH
transition of WCLK, data are written into the Full Offset MSB Register. The
fifth transition of WCLK writes, once again, to the Empty Offset LSB Register.
See Figure 14, Parallel Loading of Programmable Flag Registers for the
IDT72281, for the timing diagram for this mode.
For the IDT72291, programming PAE and PAF proceeds as follows:
when LD and WEN are set LOW, data on the inputs Dn are written into the
Empty Offset LSB Register on the first LOW-to-HIGH transition of WCLK.
Upon the second LOW-to-HIGH transition of WCLK, data are written into the
Empty Offset Mid-Byte Register. Upon the third LOW-to-HIGH transition of
WCLK, data are written into the Empty Offset MSB Register. Upon the fourth
LOW-to-HIGH transition of WCLK, data are written into the Full Offset LSB
Register. Upon the fifth LOW-to-HIGH transition of WCLK, data are written
into the Full Offset Mid-Byte Register. Upon the sixth LOW-to-HIGH transi-
tion of WCLK, data are written into the Full Offset MSB Register. The sev-
enth transition of WCLK writes, once again, into the Empty Offset LSB Regis-
Parallel reading of the offset registers is always permitted regardless of
which timing mode (IDT Standard or FWFT modes) has been selected.
10
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Retransmit setup requires a LOW on REN to enable the rising edge of
RCLK. See Figure 11, Retransmit Timing (IDT Standard Mode), for the
relevant timing diagram.
If FWFT mode is selected, the FIFO will mark the beginning of the
Retransmit setup by setting OR HIGH. During this period, the internal read
pointer is set to the first location of the RAM array.
RETRANSMIT OPERATION
The Retransmit operation allows data that has already been read to be
accessed again. There are two stages: first, a setup procedure that resets
the read pointer to the first location of memory, then the actual retransmit,
which consists of reading out the memory contents, starting at the begin-
ning of memory.
When OR goes LOW, Retransmit setup is complete; at the same time,
the contents of the first location appear on the outputs. Since FWFT mode
is selected, the first word appears on the outputs, no LOW on REN is
necessary. Reading all subsequent words requires a LOW on REN to
enable the rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT
Mode), for the relevant timing diagram.
For either IDT Standard mode or FWFT mode, updating of the PAE,
HF and PAF flags begin with the rising edge of RCLK that RT is setup.
PAE is synchronized to RCLK, thus on the second rising edge of RCLK
after RT is setup, the PAE flag will be updated. HF is asynchronous, thus
the rising edge of RCLK that RT is setup will update HF. PAF is synchro-
nized to WCLK, thus the second rising edge of WCLK that occurs tSKEW
after the rising edge of RCLK that RT is setup will update PAF. RT is
synchronized to RCLK.
Retransmit setup is initiated by holding RT LOW during a rising RCLK
edge. REN and WEN must be HIGH before bringing RT LOW. At least
one word, but no more than D– 2 words should have been written into
the FIFO between Reset (Master or Partial) and the time of Retransmit
setup. D = 65,536 for the IDT72281 and D = 131,072 for the IDT72291
in IDT Standard mode. In FWFT mode, D = 65,537 for the IDT72281
and D = 131,073 for the IDT72291.
If IDT Standard mode is selected, the FIFO will mark the beginning of
the Retransmit setup by setting EF LOW. The change in level will only be
noticeable if EF was HIGH before setup. During this period, the internal
read pointer is initialized to the first location of the RAM array.
When EF goes HIGH, Retransmit setup is complete and read opera-
tions may begin starting with the first location in memory. Since IDT Stan-
dard mode is selected, every word read including the first word following
11
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
the read pointer to the first location of memory, then the actual retransmit,
which consists of reading out the memory contents, starting at the beginning
of the memory.
SIGNAL DESCRIPTION
INPUTS:
Retransmit setup is initiated by holding RT LOW during a rising RCLK
edge. REN and WEN must be HIGH before bringing RT LOW.
If IDT Standard mode is selected, the FIFO will mark the beginning of the
Retransmit setup by setting EF LOW. The change in level will only be
noticeable if EF was HIGH before setup. During this period, the internal
read pointer is initialized to the first location of the RAM array.
When EF goes HIGH, Retransmit setup is complete and read operations
may begin starting with the first location in memory. Since IDT Standard
mode is selected, every word read including the first word following Re-
transmit setup requires a LOW on REN to enable the rising edge of RCLK.
See Figure 11, Retransmit Timing (IDT Standard Mode), for the relevant
timing diagram.
If FWFT mode is selected, the FIFO will mark the beginning of the Re-
transmit setup by setting OR HIGH. During this period, the internal read
pointer is set to the first location of the RAM array.
When OR goes LOW, Retransmit setup is complete; at the same time, the
contents of the first location appear on the outputs. Since FWFT mode is
selected, the first word appears on the outputs, no LOW on REN is neces-
sary. Reading all subsequent words requires a LOW on REN to enable the
rising edge of RCLK. See Figure 12, Retransmit Timing (FWFT Mode), for
the relevant timing diagram.
DATA IN (D0 - D8)
Data inputs for 9-bit wide data.
CONTROLS:
MASTER RESET (MRS)
A Master Reset is accomplished whenever the MRS input is taken to a
LOW state. This operation sets the internal read and write pointers to the first
location of the RAM array. PAE will go LOW, PAF will go HIGH, and HF
will go HIGH.
If FWFT is LOW during Master Reset then the IDT Standard mode,
along with EF and FF are selected. EF will go LOW and FF will go HIGH. If
FWFT is HIGH, then the First Word Fall Through mode (FWFT), along with
IR and OR, are selected. OR will go HIGH and IR will go LOW.
If LD is LOW during Master Reset, then PAE is assigned a threshold 127
words from the empty boundary and PAF is assigned a threshold 127
words from the full boundary; 127 words corresponds to an offset value of
07FH. Following Master Reset, parallel loading of the offsets is permitted,
but not serial loading.
If LD is HIGH during Master Reset, then PAE is assigned a threshold
1,023 words from the empty boundary and PAF is assigned a threshold
1,023 words from the full boundary; 1,023 words corresponds to an offset
value of 3FFH. Following Master Reset, serial loading of the offsets is
permitted, but not parallel loading.
Parallel reading of the registers is always permitted. (See section de-
scribing the LD pin for further details.)
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dual purpose pin. During Master Reset, the state of the FWFT/
SI input determines whether the device will operate in IDT Standard mode
or First Word Fall Through (FWFT) mode.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (EF) to indicate whether
or not there are any words present in the FIFO memory. It also uses the
Full Flag function (FF) to indicate whether or not the FIFO memory has any
free space for writing. In IDT Standard mode, every word read from the
FIFO, including the first, must be requested using the Read Enable (REN)
and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will
be selected. This mode uses Output Ready (OR) to indicate whether or not
there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to
indicate whether or not the FIFO memory has any free space for writing. In
the FWFT mode, the first word written to an empty FIFO goes directly to Qn
after three RCLK rising edges, REN = LOW is not necessary. Subsequent
words must be accessed using the Read Enable (REN) and RCLK.
After Master Reset, FWFT/SI acts as a serial input for loading PAE and
PAF offsets into the programmable registers. The serial input function can
only be used when the serial loading method has been selected during
Master Reset. Serial programming using the FWFT/SI pin functions the
same way in both IDT Standard and FWFT modes.
During a Master Reset, the output register is initialized to all zeroes. A
Master Reset is required after power up, before a write operation can take
place. MRS is asynchronous.
See Figure 5, Master Reset Timing, for the relevant timing diagram.
PARTIAL RESET (PRS)
A Partial Reset is accomplished whenever the PRS input is taken to a
LOW state. As in the case of the Master Reset, the internal read and write
pointers are set to the first location of the RAM array, PAE goes LOW, PAF
goes HIGH, and HF goes HIGH.
Whichever mode is active at the time of Partial Reset, IDT Standard mode
or First Word Fall Through, that mode will remain selected. If the IDT
Standard mode is active, then FF will go HIGH and EF will go LOW. If the
First Word Fall Through mode is active, then OR will go HIGH, and IR will
go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. The programming method (parallel or serial) currently active
at the time of Partial Reset is also retained. The output register is initialized
to all zeroes. PRS is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation, when reprogramming partial flag offset settings may not be con-
venient.
WRITE CLOCK (WCLK)
A write cycle is initiated on the rising edge of the WCLK input. Data setup
and hold times must be met with respect to the LOW-to-HIGH transition of the
WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle, the
FF/IR, PAF and HF flags will not be updated. (Note that WCLK is only
capable of updating HF flag to LOW.) The Write and Read Clocks can
either be independent or coincident.
See Figure 6, Partial Reset Timing, for the relevant timing diagram.
RETRANSMIT (RT)
The Retransmit operation allows data that has already been read to be
accessed again. There are two stages: first, a setup procedure that resets
12
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
WRITE ENABLE (WEN)
When the WEN input is LOW, data may be loaded into the FIFO RAM
OUTPUT ENABLE (OE)
When Output Enable is enabled (LOW), the parallel output buffers re-
array on the rising edge of every WCLK cycle if the device is not full. Data ceive data from the output register. When OE is HIGH, the output data bus
is stored in the RAM array sequentially and independently of any ongoing (Qn) goes into a high impedance state.
read operation.
When WEN is HIGH, no new data is written in the RAM array on each LOAD (LD)
WCLK cycle.
This is a dual purpose pin. During Master Reset, the state of the LD
To prevent data overflow in the IDT Standard mode, FF will go LOW, input determines one of two default offset values (127 or 1,023) for the PAE
inhibiting further write operations. Upon the completion of a valid read and PAF flags, along with the method by which these offset registers can be
cycle, FF will go HIGH allowing a write to occur. The FF is updated by two programmed, parallel or serial. After Master Reset, LD enables write op-
WCLK cycles + tSKEW after the RCLK cycle.
erations to and read operations from the offset registers. Only the offset
To prevent data overflow in the FWFT mode, IR will go HIGH, inhibiting loading method currently selected can be used to write to the registers.
further write operations. Upon the completion of a valid read cycle, IR will Offset registers can be read only in parallel. A LOW on LD during Master
go LOW allowing a write to occur. The IR flag is updated by two WCLK Reset selects a default PAE offset value of 07FH (a threshold 127 words
cycles + tSKEW after the valid RCLK cycle.
WEN is ignored when the FIFO is full in either FWFT or IDT Standard 127 words from the full boundary), and parallel loading of other offset
from the empty boundary), a default PAF offset value of 07FH (a threshold
mode.
READ CLOCK (RCLK)
values. A HIGH on LD during Master Reset selects a default PAE offset
value of 3FFH (a threshold 1,023 words from the empty boundary), a
default PAF offset value of 3FFH (a threshold 1,023 words from the full
A read cycle is initiated on the rising edge of the RCLK input. Data can boundary), and serial loading of other offset values.
be read on the outputs, on the rising edge of the RCLK input. It is permis-
After Master Reset, the LD pin is used to activate the programming
sible to stop the RCLK. Note that while RCLK is idle, the EF/OR, PAE and process of the flag offset values PAE and PAF. Pulling LD LOW will begin a
HF flags will not be updated. (Note that RCLK is only capable of updating the serial loading or parallel load or read of these offset values. See Figure 4,
HF flag to HIGH.) The Write and Read Clocks can be independent or Programmable Flag Offset Programming Sequence.
coincident.
OUTPUTS:
READ ENABLE (REN)
FULL FLAG (FF/IR)
When Read Enable is LOW, data is loaded from the RAM array into the
output register on the rising edge of every RCLK cycle if the device is not
empty.
This is a dual purpose pin. In IDT Standard mode, the Full Flag (FF)
function is selected. When the FIFO is full, FF will go LOW, inhibiting further
write operations. When FF is HIGH, the FIFO is not full. If no reads are
performed after a reset (either MRS or PRS), FF will go LOW after D writes
When the REN input is HIGH, the output register holds the previous data
and no new data is loaded into the output register. The data outputs Q0-Qn
to the FIFO (D = 65,536 for the IDT72281 and 131,072 for the IDT72291).
maintain the previous data value.
See Figure 7, Write Cycle and Full Flag Timing (IDT Standard Mode), for
the relevant timing information.
In the IDT Standard mode, every word accessed at Qn, including the first
word written to an empty FIFO, must be requested using REN. When the last
In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW
word has been read from the FIFO, the Empty Flag (EF) will go LOW,
when memory space is available for writing in data. When there is no
inhibiting further read operations. REN is ignored when the FIFO is empty.
longer any free space left, IR goes HIGH, inhibiting further write operations.
Once a write is performed, EF will go HIGH allowing a read to occur. The EF
If no reads are performed after a reset (either MRS or PRS), IR will go
flag is updated by two RCLK cycles + tSKEW after the valid WCLK cycle.
HIGH after D writes to the FIFO (D = 65,537 for the IDT72281 and 131,073
In the FWFT mode, the first word written to an empty FIFO automatically
for the IDT72291) See Figure 9, Write Timing (FWFT Mode), for the
relevant timing information.
goes to the outputs Qn, on the third valid LOW to HIGH transition of RCLK +
tSKEW after the first write. REN does not need to be asserted LOW. In
The IR status not only measures the contents of the FIFO memory, but
order to access all other words, a read must be executed using REN. The
also counts the presence of a word in the output register. Thus, in FWFT
mode, the total number of writes necessary to deassert IR is one greater
than needed to assert FF in IDT Standard mode.
RCLK LOW to HIGH transition after the last word has been read from the
FIFO, Output Ready (OR) will go HIGH with a true read (RCLK with REN
= LOW), inhibiting further read operations. REN is ignored when the FIFO
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR
is empty.
are double register-buffered outputs.
SERIAL ENABLE (SEN)
EMPTY FLAG (EF/OR)
The SEN input is an enable used only for serial programming of the
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag
offset registers. The serial programming method must be selected during
(EF) function is selected. When the FIFO is empty, EF will go LOW,
Master Reset. SEN is always used in conjunction with LD. When these
lines are both LOW, data at the SI input can be loaded into the program
register one bit for each LOW-to-HIGH transition of WCLK. (See Figure 4.)
inhibiting further read operations. When EF is HIGH, the FIFO is not empty.
See Figure 8, Read Cycle, Empty Flag and First Word Latency Timing
(IDT Standard Mode), for the relevant timing information.
In FWFT mode, the Output Ready (OR) function is selected. OR goes
LOW at the same time that the first word written to an empty FIFO appears
When SEN is HIGH, the programmable registers retains the previous
settings and no offsets are loaded. SEN functions the same way in both IDT
Standard and FWFT modes.
13
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
valid on the outputs. OR stays LOW after the RCLK LOW to HIGH transition LOW when there are n words or less in the FIFO. The offset “n” is the
that shifts the last word from the FIFO memory to the outputs. OR goes empty offset value. The default setting for this value is stated in the footnote
HIGH only with a true read (RCLK with REN = LOW). The previous data of Table 1.
stays at the outputs, indicating the last word was read. Further data reads
are inhibited until OR goes LOW again. See Figure 10, Read Timing in the FIFO. The default setting for this value is stated in the footnote of
(FWFT Mode), for the relevant timing information.
In FWFT mode, the PAE will go LOW when there are n+1 words or less
Table 2.
See Figure 19, Programmable Almost-Empty Flag Timing (IDT Stan-
EF/OR is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode, EF is a double register-buffered output. In FWFT dard and FWFT Mode), for the relevant timing information.
mode, OR is a triple register-buffered output.
PAE is synchronous and updated on the rising edge of RCLK.
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
HALF-FULL FLAG (HF)
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
This output indicates a half-full FIFO. The rising WCLK edge that fills the
reaches the almost-full condition. In IDT Standard mode, if no reads are FIFO beyond half-full sets HF LOW. The flag remains LOW until the differ-
performed after reset (MRS), PAF will go LOW after (D – m) words are ence between the write and read pointers becomes less than or equal to
written to the FIFO. The PAF will go LOW after (65,536–m) writes for the half of the total depth of the device; the rising RCLK edge that accomplishes
IDT72281 and (131,072–m) writes for the IDT72291. The offset “m” is the this condition sets HF HIGH.
full offset value. The default setting for this value is stated in the footnote of
Table 1.
In FWFT mode, the PAF will go LOW after (65,537–m) writes for the for the IDT72281 and 131,072 for the IDT72291.
IDT72281 and (131,073–m) writes for the IDT72291, where m is the full
In IDT Standard mode, if no reads are performed after reset (MRS or
PRS), HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 65,536
In FWFT mode, if no reads are performed after reset (MRS or PRS), HF
offset value. The default setting for this value is stated in the footnote of will go LOW after [(D-1)/2]+ 2 writes to the FIFO, where D = 65,537 for the
Table 2.
See Figure 18, Programmable Almost-Full Flag Timing (IDT Standard
and FWFT Mode), for the relevant timing information.
IDT72281 and 131,073 for the IDT72291.
See Figure 20, Half-Full Flag Timing (IDT Standard and FWFT Modes),
for the relevant timing information. Because HF is updated by both RCLK
and WCLK, it is considered asynchronous.
PAF is synchronous and updated on the rising edge of WCLK.
PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)
DATA OUTPUTS (Q0-Q8)
The Programmable Almost-Empty flag (PAE) will go LOW when the FIFO
reaches the almost-empty condition. In IDT Standard mode, PAE will go
(Q0 - Q8) are data outputs for 9-bit wide data.
14
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tRS
MRS
REN
tRSR
tRSS
tRSS
tRSR
WEN
FWFT/SI
LD
t
RSR
t
FWFT
tRSS
tRSR
tRSS
RT
tRSS
SEN
t
RSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
EF/OR
FF/IR
t
RSF
t
RSF
PAE
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
4675 drw 08
Figure 5. Master Reset Timing
15
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tRS
PRS
REN
tRSS
tRSR
tRSS
tRSR
WEN
RT
tRSS
tRSS
SEN
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
t
RSF
EF/OR
t
RSF
FF/IR
PAE
t
RSF
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
4675 drw 09
Figure 6. Partial Reset Timing
16
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
t
CLK
t
CLKH
tCLKL
NO WRITE
NO WRITE
2
1
WCLK
1
2
(1)
SKEW1
t
SKEW1(1)
t
t
DS
tDH
t
DS
tDH
D
X
DX+1
D0 - Dn
t
WFF
t
WFF
t
WFF
tWFF
WEN
RCLK
t
ENS
tENH
t
ENS
tENH
REN
t
A
t
A
Q0 - Qn
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
4675 drw 10
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus tWFF). If the time between the
rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH.
Figure 7. Write Cycle and Full Flag Timing (IDT Standard Mode)
tCLK
tCLKH
tCLKL
1
2
RCLK
REN
EF
tENH
tENS
tENS
tENH
t
ENH
tENS
NO OPERATION
NO OPERATION
REF
tREF
t
tREF
tA
tA
tA
D0
Q0
- Qn
LAST WORD
D1
LAST WORD
tOLZ
t
OLZ
tOHZ
tOE
OE
t
SKEW3(1)
WCLK
tENH
tENH
tENS
tENS
WEN
tDS
tDH
tDHS
tDS
D0
- Dn
D0
D1
4675 drw 11
NOTES:
1. tSKEW3 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW3, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
Figure 8. Read Cycle, Empty Flag and First Data Word Latency Timing (IDT Standard Mode)
17
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
18
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
19
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
1
2
RCLK
t
ENS
t
ENH
t
ENS
tENH
tRTS
REN
t
A
t
A
t
A
(3)
(3)
Q0 - Qn
Wx
Wx+1
W
1
W
2
t
SKEW2
1
2
WCLK
WEN
RT
tRTS
t
ENS
tENH
(5)
tREF
tREF
EF
PAE
HF
t
PAE
tHF
t
PAF
PAF
4675 drw 14
NOTES:
1. Retransmit setup is complete after EF returns HIGH, only then can a read operation begin.
2. OE = LOW.
3. W1 = first word written to the FIFO after Master Reset, W2 = second word written to the FIFO after Master Reset.
4. No more than D – 2 may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, FF will be HIGH throughout the Retransmit setup
procedure. D = 65,536 for the IDT72281 and 131,072 for the IDT72291.
5. EF goes HIGH at 60 ns + 1 RCLK cycle + tREF.
Figure 11. Retransmit Timing (IDT Standard Mode)
20
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
3
1
2
4
RCLK
t
ENH
t
ENH
t
ENS
t
ENH
tRTS
REN
- Q
t
A
t
A
(4)
Q0
n
Wx
Wx+1
W2
W
1
W3
t
SKEW2
1
2
WCLK
tRTS
WEN
t
ENS
tENH
RT
OR
(5)
tREF
tREF
t
PAE
PAE
tHF
HF
t
PAF
PAF
4675 drw 15
NOTES:
1. Retransmit setup is complete after OR returns LOW.
2. No more than D – 2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup
procedure. D = 65,537 for the IDT72281 and 131,073 for the IDT72291.
3. OE = LOW.
4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.
5. OR goes LOW at 60 ns + 2 RCLK cycles + tREF.
Figure 12. Retransmit Timing (FWFT Mode)
WCLK
tENH
tENS
tENH
SEN
LD
tLDH
tLDS
tLDH
tDH
tDS
(1)
(1)
BIT 0
BIT 0
BIT X
BIT X
SI
4675 drw16
FULL OFFSET
EMPTY OFFSET
NOTE:
1. X = 15 for the IDT72281 and X = 16 for the IDT72291.
Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
21
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
t
CLK
t
CLKH
t
CLKL
WCLK
LD
t
LDS
t
LDH
t
t
LDH
ENH
t
ENS
t
t
ENH
DH
WEN
t
DH
t
DS
D0 - D7
PAE OFFSET
(LSB)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MSB)
4675 drw 17
Figure 14. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) for the IDT72281
t
CLK
t
CLKH
tCLKL
WCLK
LD
t
LDS
t
LDH
t
LDH
t
ENS
t
t
ENH
DH
t
ENH
WEN
t
DH
t
DS
D0 - D7
PAF OFFSET
(MSB)
PAE OFFSET
(LSB)
PAE OFFSET
(MID-BYTE)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MID-BYTE)
4675 drw 18
Figure 15. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes) for the IDT72291
t
CLK
t
CLKH
t
CLKL
RCLK
t
LDS
t
LDH
t
LDH
LD
t
ENS
tENH
t
ENH
REN
t
A
t
A
PAE OFFSET
(LSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MSB)
DATA IN OUTPUT
REGISTER
PAE OFFSET
(MSB)
Q0 - Q7
4675 drw 19
NOTE:
1. OE = LOW.
Figure 16. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for the IDT72281
t
CLK
t
CLKH
t
CLKL
RCLK
t
t
LDS
tLDH
t
LDH
LD
t
ENH
ENS
tENH
REN
t
A
t
A
PAE OFFSET
(LSB)
PAE OFFSET
(MID-BYTE)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MID-BYTE)
PAF OFFSET
(MSB)
DATA IN OUTPUT REGISTER
Q0 - Q7
4675 drw 20
NOTE:
1. OE = LOW.
Figure 17. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for the IDT72291
22
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
t
CLKH
t
CLKL
1
2
WCLK
WEN
PAF
2
1
t
ENS
tENH
t
PAF
tPAF
D - m words in FIFO(2)
D - (m+1) words in FIFO(2)
D-(m+1) words
in FIFO(2)
(3)
tSKEW2
RCLK
t
ENH
t
ENS
4675 drw 21
REN
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
In IDT Standard mode: D = 65,536 for the IDT72281 and 131,072 for the IDT72291.
In FWFT mode: D = 65,537 for the IDT72281 and 131,073 for the IDT72291.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAF). If the time between
the rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
Figure 18. Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
t
CLKH
t
CLKL
WCLK
t
ENH
t
ENS
WEN
PAE
n words in FIFO (2)
n+1 words in FIFO (3)
,
n words in FIFO (2)
n+1 words in FIFO (3)
,
n+1 words in FIFO (2)
n+2 words in FIFO (3)
,
(4)
t
SKEW2
1
t
PAE
tPAE
2
1
2
RCLK
t
ENS
tENH
4675 drw 22
REN
NOTES:
1. n = PAE offset.
2. For IDT Standard mode.
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAE). If the time between
the rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
Figure 19. Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
HF
tHF
D/2 + 1 words in FIFO(1)
D-1
2
,
D/2 words in FIFO(1)
D-1
2
,
D/2 words in FIFO(1)
D-1
2
,
[
+ 2
words in FIFO(2)
]
[
+ 1
]
words in FIFO(2)
[
+ 1
words in FIFO(2)
]
tHF
RCLK
tENS
REN
4675 drw 23
NOTES:
1. For IDT Standard mode: D = maximum FIFO depth. D = 65,536 for the IDT72281 and 131,072 for the IDT72291.
2. For FWFT mode: D = maximum FIFO depth. D = 65,537 for the IDT72281 and 131,073 for the IDT72291.
Figure 20. Half-Full Flag Timing (IDT Standard and FWFT Modes)
23
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
by one cycle between FIFOs. In IDT Standard mode, such problems can be
avoided by creating composite flags, that is, ANDing EF of every FIFO, and
separatelyANDingFFofeveryFIFO.InFWFTmode,compositeflagscanbe
createdbyORingORofeveryFIFO,andseparatelyORingIRofeveryFIFO.
Figure 23 demonstrates a width expansion using two IDT72281/72291
devices.D0-D8fromeachdeviceforma18-bitwideinputbusandQ0-Q8from
eachdeviceforma18-bitwideoutputbus.Anywordwidthcanbeattainedby
addingadditionalIDT72281/72291devices.
OPTIONALCONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signalsofmultipledevices.Statusflagscanbedetectedfromanyonedevice.
TheexceptionsaretheEFandFFfunctionsinIDTStandardmodeandtheIR
andORfunctionsinFWFTmode.BecauseofvariationsinskewbetweenRCLK
and WCLK, it is possible for EF/FF deassertion and IR/OR assertion to vary
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
Dm+1 - Dn
m + n
m
n
D0 - Dm
DATA IN
READ CLOCK (RCLK)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
IDT
IDT
72281
72291
PROGRAMMABLE (PAE)
72281
72291
FULL FLAG/INPUT READY (FF/IR)
#1
(1)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
(1)
GATE
FULL FLAG/INPUT READY (FF/IR) #2
GATE
EMPTY FLAG/OUTPUT READY (EF/OR) #2
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
m + n
n
Qm+1 - Qn
FIFO
#1
FIFO
#2
DATA OUT
m
4675 drw 24
Q0 - Qm
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 21. Block Diagram of 65,536 x 18 and 131,072 x 18 Width Expansion
24
IDT72281/72291
CMOS SuperSync FIFO™ 65,536 x 9 and 131,072 x 9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
FWFT/SI
•
TRANSFER CLOCK
FWFT/SI
FWFT/SI
READ CLOCK
READ ENABLE
WRITE CLOCK
WRITE ENABLE
WCLK
WEN
IR
RCLK
WCLK
•
RCLK
OR
WEN
REN
IDT
72281
72291
IDT
72281
72291
INPUT READY
OUTPUT READY
OUTPUT ENABLE
REN
OR
OE
Qn
IR
OE
GND
n
DATA OUT
n
n
DATA IN
Dn
Qn
Dn
4675 drw 25
Figure 22. Block Diagram of 131,072 x 9 and 262,144 x 9 Depth Expansion
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
TheIDT72281caneasilybeadaptedtoapplicationsrequiringdepthsgreater
than 65,536 and 131,072 for the IDT72291 with a 9-bit bus width. In FWFT
mode, the FIFOs can be connected in series (the data outputs of one FIFO
connectedtothedatainputsofthenext)withnoexternallogicnecessary.The
resultingconfigurationprovidesatotaldepthequivalenttothesumofthedepths
associatedwitheachsingleFIFO.Figure24showsadepthexpansionusing
twoIDT72281/72291devices.
CareshouldbetakentoselectFWFTmodeduringMasterResetforallFIFOs
in the depth expansion configuration. The first word written to an empty
configurationwillpassfromoneFIFOtothenext("rippledown")untilitfinally
appears at the outputs of the last FIFO in the chain–no read operation is
necessarybuttheRCLKofeachFIFOmustbefree-running.Eachtimethedata
word appears at the outputs of one FIFO, that device's OR line goes LOW,
enabling a write to the next FIFO in line.
specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
clock,fortheORflag.
The"rippledown"delayisonlynoticeableforthefirstwordwrittentoanempty
depthexpansionconfiguration.Therewillbenodelayevidentforsubsequent
wordswrittentotheconfiguration.
The first free location created by reading from a full depth expansion
configurationwill"bubbleup"fromthelastFIFOtothepreviousoneuntilitfinally
movesintothefirstFIFOofthechain.Eachtimeafreelocationiscreatedinone
FIFOofthechain,thatFIFO'sIRlinegoesLOW,enablingtheprecedingFIFO
to write a word to fill it.
Forafullexpansionconfiguration,theamountoftimeittakesforIRofthefirst
FIFOinthechaintogoLOWafterawordhasbeenreadfromthelastFIFOis
the sum of the delays for each individual FIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
Foranemptyexpansionconfiguration,theamountoftimeittakesforORof
thelastFIFOinthechaintogoLOW(i.e.validdatatoappearonthelastFIFO's
outputs)afterawordhasbeenwrittentothefirstFIFOisthesumofthedelays
for each individual FIFO:
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period.NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer
clock,fortheIRflag.
TheTransferClocklineshouldbetiedtoeitherWCLKorRCLK,whichever
isfaster.Boththeseactionsresultindatamoving,asquicklyaspossible,tothe
endofthechainandfreelocationstothebeginningofthechain.
(N – 1)*(4*transfer clock) + 3*TRCLK
whereNisthenumberofFIFOsintheexpansionandTRCLKistheRCLKperiod.
Note that extra cycles should be added for the possibility that the tSKEW3
25
ORDERINGINFORMATION
XXXXX
X
XX
X
X
X
X
Process /
Temperature
Range
Device Type
Power Speed
Package
Tube or Tray
Tape and Reel
BLANK
8
BLANK Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
I(1)
Green
G
PF
TF
Thin Plastic Quad Flatpack (TQFP, PN64-1)
Slim Thin Quad Flatpack (STQFP, PP64-1)
10
15
20
Commercial Only
Clock Cycle Time (tCLK
)
Com'l & Ind'l
Com'l & Ind'l
Speed in Nanoseconds
Low Power
L
72281
72291
65,536 x 9 SuperSyncFIFO
131,072 x 9 SuperSyncFIFO
4675 drw26
NOTE:
1. Industrial temperature range product for 15ns and 20ns speed grade are available as a standard device.
DATASHEETDOCUMENTHISTORY
04/24/2001
01/13/2009
03/20/2013
pgs. 1, 5, 6 and 26.
pg. 26.
pg. 3, 8, 14 and 26.
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