723614L20PF8 [IDT]
TQFP-120, Reel;
| 型号： | 723614L20PF8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | TQFP-120, Reel |
| 文件： | 总32页 (文件大小：308K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS SyncBiFIFOTM WITH
BUS-MATCHING AND BYTE SWAPPING
64 x 36 x 2
IDT723614
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor interface control logic
• EFA, FFA, AEA, and AFA flags synchronized by CLKA
• EFB, FFB, AEB, and AFB flags synchronized by CLKB
• Passive parity checking on each port
• Parity generation can be selected for each port
• Supports clock frequencies up to 67 MHz
• Fast access times of 10 ns
• Available in 132-pin plastic quad flat package (PQF) or space-
saving 120-pin thin quad flat package (TQFP)
• Industrial temperature range (–40°C to +85°C) is available
• Green parts available, see ordering information
FEATURES:
• Free-running CLKA and CLKB can be asynchronous or
coincident (simultaneous reading and writing of data on a
single clock edge is permitted)
• Two independent clocked FIFOs (64 x 36 storage capacity each)
buffering data in opposite directions
• Mailbox bypass Register for each FIFO
• Dynamic Port B bus sizing of 36 bits (long word), 18 bits (word),
and 9 bits (byte)
• Selection of Big- or Little-Endian format for word and byte bus
sizes
• Three modes of byte-order swapping on port B
FUNCTIONALBLOCKDIAGRAM
CLKA
CSA
W/RA
ENA
Port-A
Control
Logic
MBF1
MBA
PEFB
Parity
Gen/Check
Mail 1
Register
PGB
RAM
ARRAY
36
64 x 36
RST
Device
Control
ODD/
EVEN
Read
Pointer
Write
Pointer
EFB
AEB
FFA
AFA
Status Flag
Logic
FIFO1
36
FS0
FS1
Programmable Flag
Offset Register
B
0-B35
A
0
- A35
FIFO2
FFB
AFB
EFA
AEA
Status Flag
Logic
Write
Pointer
Read
Pointer
36
RAM
ARRAY
64 x 36
PGA
Mail 2
Register
Parity
Gen/Check
PEFA
MBF2
CLKB
CSB
W/RB
ENB
Port-B
Control
Logic
BE
SIZ0
SIZ1
SW0
SW1
3146 drw01
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. SyncBIFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
JANUARY 2009
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
DSC-3146/3
©
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
withachoiceofbig-orlittle-endianconfigurations.Threemodesofbyte-order
swappingarepossiblewithanybussizeselection.Communicationbetween
eachportcanbypasstheFIFOsviatwo36-bitmailboxregisters. Eachmailbox
registerhasaflagtosignalwhennewmailhasbeenstored.Parityischecked
passively on each port and may be ignored if not desired. Parity generation
canbeselectedfordatareadfromeachport.Twoormoredevicescanbeused
inparalleltocreatewiderdatapaths.
DESCRIPTION:
TheIDT723614isamonolithic,high-speed,low-powerCMOSbidirectional
clockedFIFOmemory.Itsupportsclockfrequenciesupto67MHzandhasread
accesstimesasfastas10ns.Twoindependent64x36dual-portSRAMFIFOs
on board the chip buffer data in opposite directions. Each FIFO has flags to
indicateemptyandfullconditionsandtwoprogrammableflags(Almost-Fulland
Almost-Empty)toindicatewhenaselectednumberofwordsisstoredinmemory.
FIFOdataonportBcanbeinputandoutputin36-bit,18-bit,and9-bitformats
PINCONFIGURATIONS
GND
AEA
EFA
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND
AEB
EFB
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
A
A
A
0
1
2
B
B
B
0
1
2
GND
GND
A
A
A
A
3
4
5
6
B
B
B
B
V
B
B
B
3
4
5
6
CC
7
8
V
CC
A
A
A
7
8
9
9
GND
GND
A
10
11
B
B
V
B
B
B
10
11
CC
12
13
14
A
V
CC
98
A
12
13
14
97
A
96
A
GND
95
GND
94
A
A
A
A
A
A
15
16
17
18
19
20
B
B
B
B
B
B
15
16
17
18
19
20
93
92
91
90
89
88
GND
GND
87
A21
A22
A23
B21
B22
B23
86
85
84
3146 drw02
NOTES:
1. Electrical pin 1 in center of beveled edge.
2. Uses Yamaichi socket IC51-1324-828.
PQFP (PQ132-1, ORDER CODE: PQF)
TOP VIEW
JANUARY14,2009
2
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
ThisdeviceisaclockedFIFO,whichmeanseachportemploysasynchro-
nousinterface.AlldatatransfersthroughaportaregatedtotheLOW-to-HIGH
transitionofacontinuous(free-running)portclockbyenablesignals.Theclocks
for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectionalinterfacebetweenmicroprocessorsand/orbusescontrolledbya
synchronousinterface.
The Full Flag (FFA, FFB) and Almost-Full flag (AFA, AFB) of a FIFO are
two-stagesynchronizedtotheportclockthatwritesdatatoitsarray. TheEmpty
Flag(EFA,EFB)andAlmost-Empty(AEA,AEB)flagofaFIFOaretwostage
synchronizedtotheportclockthatreadsdatafromitsarray.
The IDT723614 is characterized for operation from 0°C to 70°C.
PINCONFIGURATIONS(CONTINUED)
A
A
A
23
22
21
1
B
22
21
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
2
B
3
GND
GND
4
B
B
B
B
B
B
B
B
B
B
B
20
19
18
17
16
15
14
13
12
11
10
A
A
A
A
A
A
A
A
A
A
A
20
19
18
17
16
15
14
13
12
11
10
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GND
GND
B
B
B
V
B
B
B
B
9
8
7
CC
6
5
4
3
A
A
A
9
8
7
VCC
A
A
A
A
6
5
4
3
GND
GND
B2
B1
B0
A
A
A
2
1
0
EFB
AEB
AFB
EFA
AEA
3146 drw03
NOTE:
1. Pin 1 identifier in corner.
TQFP (PN120-1, ORDER CODE: PF)
TOP VIEW
COMMERCIALANDINDUSTRIAL
JANUARY14,2009
3
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
PIN DESCRIPTION
Symbol
A0-A35
AEA
Name
I/O
I/O
O
Description
PortAData
36-bitbidirectionaldataportforsideA.
ProgrammableAlmost-EmptyflagsynchronizedtoCLKA.ItisLOWwhenthenumberof36-bit
PortAAlmost-Empty
Flag
(PortA) words in FIFO2 is less than or equal to the value in the offset register, X.
Programmable Almost-EmptyflagsynchronizedtoCLKB. Itis LOWwhenthe numberof36-bit
(PortB) words in FIFO1 is less than or equal to the value in the offset register, X.
ProgrammableAlmost-FullflagsynchronizedtoCLKA.ItisLOWwhenthenumberof36-bitempty
(PortA) locations inFIFO1is less thanorequaltothe value inthe offsetregister, X.
ProgrammableAlmost-FullflagsynchronizedtoCLKB.ItisLOWwhenthenumberof36-bitempty
(PortB) locations inFIFO2is less thanorequaltothe value inthe offsetregister, X.
AEB
AFA
AFB
PortBAlmost-Empty
Flag
O
PortAAlmost-Full
Flag
O
PortBAlmost-Full
Flag
O
B0-B35
Port B Data
I/O
I
36-bitbidirectionaldataportforsideB.
BE
Big-endianselect
Selects the bytes on portBusedduringbyte orworddata transfer. ALOWonBE selects the most
mostsignificantbytesonB0-B35foruse,andaHIGHselectstheleastsignificantbytes.
CLKA
CLKB
Port A Clock
PortBClock
I
I
CLKA is a continuous clock that synchronizes all data transfers through port A and can be
asynchronous or coincident to CLKB. EFA, FFA, AFA, and AEA are synchronized to the
LOW-to-HIGHtransitionofCLKA.
CLKB is a continuous clock that synchronizes all data transfers through port B and can be
asynchronous orcoincidenttoCLKA. PortBbyte swappinganddata portsizingoperations are
alsosynchronoustotheLOW-to-HIGHtransitionofCLKB.EFB,FFB,AFB,andAEBaresynchro-
nizedtotheLOW-to-HIGHtransitionofCLKB.
CSA
CSB
EFA
PortAChipSelect
PortBChipSelect
PortAEmptyFlag
I
I
CSAmustbe LOWtoenable a LOW-to-HIGHtransitionofCLKAtoreadorwrite data onportA.
The A0-A35 outputs are in the high-impedance state when CSA is HIGH.
CSBmustbe LOWtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onportB.
The B0-B35 outputs are in the high-impedance state when CSB is HIGH.
O
EFAis synchronizedtothe LOW-to-HIGHtransitionofCLKA. WhenEFAis LOW,FIFO2is
(PortA) empty, and reads from its memory are disabled. Data can be read from FIFO2 to the output
register when EFA is HIGH. EFA is forced LOW when the device is reset and is set HIGH by
thesecondLOW-to-HIGHtransitionofCLKAafterdataisloadedintoemptyFIFO2memory.
EFB
PortBEmptyFlag
(PortB)
O
EFBis synchronizedtothe LOW-to-HIGHtransitionofCLKB. WhenEFBis LOW,the FIFO1is
empty, andreads fromits memoryare disabled. Data canbe readfromFIFO1tothe output
register when EFB is HIGH. EFB is forced LOW when the device is reset and is set HIGH by the
secondLOW-to-HIGHtransitionofCLKBafterdataisloadedintoemptyFIFO1memory.
ENA
ENB
FFA
Port A Enable
Port B Enable
Port A Full Flag
I
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
FFAis synchronizedtothe LOW-to-HIGHtransitionofCLKA. WhenFFAis LOW, FIFO1is full,
O
(PortA) and writes to its memory are disabled. FFA is forced LOW when the device is reset and is set
HIGHbythesecondLOW-to-HIGHtransitionofCLKAafterreset.
FFB
Port B Full Flag
O
FFBis synchronizedtothe LOW-to-HIGHtransitionofCLKB. WhenFFBis LOW, FIFO2is full,
(PortB) and writes to its memory are disabled. FFB is forced LOW when the device is reset and is set
HIGHbythesecondLOW-to-HIGHtransitionofCLKBafterreset.
FS1, FS0 Flag-OffsetSelects
I
I
The LOW-to-HIGHtransitionofRST latches the values ofFS0andFS1, whichselects one of
fourpresetvalues fortheAlmost-FullflagandAlmost-Emptyflagoffset.
MBA
Port A Mailbox
Select
A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the
A0-A35outputs are active, a HIGHlevelonMBAselects data fromthe mail2registerforoutput,
andaLOWlevelselectsFIFO2outputregisterdataforoutput.
MBF1
Mail1RegisterFlag
O
O
MBF1is setLOWbyaLOW-to-HIGHtransitionofCLKAthatwrites datatothemail1register.
Writes to the mail1 register are inhibited while MBF1 is set LOW. MBF1 is set HIGH by a LOW-to-
HIGH transition of CLKB when a port B read is selected and both SIZ1 and SIZ0 are HIGH.
MBF1 is set HIGH when the device is reset.
MBF2is setLOWbyaLOW-to-HIGHtransitionofCLKBthatwrites datatothemail2register.
Writes to the mail2 register are inhibited while MBF2 is set LOW. MBF2 is set HIGH by a LOW-to-
HIGH transition of CLKA when a port A read is selected and MBA is HIGH. MBF2 is set HIGH
when the device is reset.
MBF2
Mail2RegisterFlag
JANUARY14,2009
4
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
PIN DESCRIPTION (CONTINUED)
Symbol
Name
I/O
Description
ODD/
EVEN
Odd/EvenParity
Select
I
Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when
ODD/EVEN is LOW. ODD/EVENalsoselects the type ofparitygeneratedforeachportifparity
generation is enabled for a read operation.
PEFA
Port A Parity Error
Flag
O
When any byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes are organized as
(PortA) A0-A8,A9-A17,A18-A26,andA27-A35,withthe mostsignificantbitofeachbyte servingas the
paritybit.The type ofparitycheckedis determinedbythe state ofthe ODD/EVENinput.
The parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate
parityifparitygenerationis selectedbyPGA. Therefore, ifa mail2readparitygenerationis setup
by having W/RA LOW, MBA HIGH, and PGA HIGH, the PEFA flag is forced HIGH regardless of the
A0-A35inputs.
PEFB
Port B Parity Error
Flag
O
When any valid byte applied to terminals B0-B35 fails parity, PEFB is LOW. Bytes are organized
(PortB) as B0-B8, B9-B17, B18-B26, B27-B35 with the most significant bit of each byte serving as the parity
bit. A byte is valid when it is used by the bus size selected for Port B. The type of parity checked is
determined by the state of the ODD/EVEN input.
The parity trees used to check the B0-B35 inputs are shared by the mail 1 register to generate parity if
parity generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by
having W/RB LOW, SIZ1 and SIZ0 HIGH, and PGB HIGH, the PEFB flag is forced HIGH regardless
ofthestateoftheB0-B35inputs.
PGA
PGB
RST
Port A Parity
Generation
I
I
I
Parity is generated for data reads from port A when PGA is HIGH. The type of parity generated is
selectedbythe state ofthe ODD/EVENinput. Bytes are organizedas A0-A8, A9-A17, A18-A26,
andA27-A35.Thegeneratedparitybits areoutputinthemostsignificantbitofeachbyte.
Port B Parity
Generation
Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is
selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26,
andB27-B35. The generatedparitybits are outputinthe mostsignificantbitofeachbyte.
Reset
To resetthedevice,fourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsof
CLKBmustoccurwhile RST is LOW. This sets the AFA, AFB, MBF1, and MBF2 flags HIGH and
the EFA,EFB,AEA,AEB,FFA,andFFBflags LOW. The LOW-to-HIGHtransitionofRSTlatches
thestatusoftheFS1andFS0inputstoselectAlmost-FullandAlmost-Emptyflagoffsets.
SIZ0, SIZ1 PortBBus Size
Selects
I
A LOW-to-HIGH transition of CLKB latches the states of SIZ0, SIZ1, and BE, and the following
(PortB) LOW-to-HIGH transition of CLKB implements the latched states as a port B bus size. Port B bus sizes
can be long word, word, or byte. A high on both SIZ0 and SIZ1 accesses the mailbox registers for
a port B 36-bit write or read.
SW0, SW1 Port B byte Swap
Select
I
At the beginning of each long word transfer, one of four modes of byte-order swapping is selected by
(Port B) SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-
order swapping is possible with any bus-size selection.
W/RA
W/RB
PortAWrite/Read
Select
I
A HIGH selects a write operationanda LOWselects a readoperationonfora LOW-to-HIGHportA
transitionofCLKA. TheA0-A35outputs areinthehigh-impedancestatewhenW/RAis HIGH.
A HIGH selects a write operationanda LOWselects a readoperationonfora LOW-to-HIGHportB
B transitionofCLKB. The B0-B35outputs are inthe high-impedance state whenW/RBis HIGH.
PortBWrite/Read
Select
I
COMMERCIALANDINDUSTRIAL
5
JANUARY14,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
ABSOLUTEMAXIMUMRATINGSOVEROPERATINGFREE-AIRTEMPERATURE
RANGE(UNLESSOTHERWISENOTED)(1)
Symbol
Rating
Commercial
–0.5to7
Unit
V
VCC
SupplyVoltageRange
(2)
VI
InputVoltageRange
–0.5 to VCC+0.5
–0.5 to VCC+0.5
±20
V
VO(2)
OutputVoltageRange
V
IIK
Input Clamp Current, (VI < 0 or VI > VCC)
Output Clamp Current, (VO < 0 or VO > VCC)
Continuous OutputCurrent, (VO =0toVCC)
ContinuousCurrentThroughVCC orGND
StorageTemperatureRange
mA
mA
mA
mA
°C
IOK
IOUT
ICC
±50
±50
±500
TSTG
–65to150
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device
at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDEDOPERATING
CONDITIONS
Symbol
VCC
VIH
Parameter
Min. Max. Unit
SupplyVoltage
4.5
2
5.5
–
V
V
HIGH Level Input Voltage
LOW-LevelInputVoltage
HIGH-LevelOutputCurrent
LOW-LevelOutputCurrent
OperatingFree-airTemperature
VIL
–
0.8
–4
8
V
IOH
–
mA
mA
°C
IOL
–
TA
0
70
ELECTRICALCHARACTERISTICSOVERRECOMMENDEDOPERATING
FREE-AIR TEMPERATURE RANGE (UNLESS OTHERWISE NOTED)
Parameter
Test Conditions
Min.
Typ.(1)
Max.
Unit
V
VOH
VOL
II
VCC = 4.5V,
VCC = 4.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VCC = 5.5 V,
VI = 0,
IOH = –4 mA
IOL = 8 mA
VI = VCC or 0
VO = VCC or 0
IO = 0 mA,
f = 1 MHz
2.4
0.5
±50
±50
1
V
µA
µA
mA
pF
IOZ
(2)
ICC
VI = VCC or GND
CIN
4
8
COUT
VO = 0,
f = 1 MHZ
pF
NOTES:
1 . All typical values are at VCC = 5 V, TA = 25°C.
2. For additional ICC information, see the following page.
JANUARY14,2009
6
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
400
350
V
CC = 5.5V
f
= 1/2 f
data
T = 25° C
s
A
V
V
CC = 5V
C = 0 pF
L
300
CC = 4.5V
250
200
150
100
50
0
0
10
20
30
40
50
60
70
80
3146 drw04
fs ⎯ Clock Frequency ⎯ MHz
Figure 1. Typical Characteristics: Supply Current vs Clock Frequency
CALCULATINGPOWERDISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT723614 with CLKA and CLKB set
to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to
normalize the graph to a zero-capacitance load. Once the capacitive lead per data-output channel is known, the power dissipation can be calculated with
the equation below.
WithICC(f) takenfromFigure 1, the maximumpowerdissipation(PT)ofthe IDT723614canbe calculatedby:
2
PT = VCC x ICC(f) + Σ(CL x VOH x fo)
where:
CL
fo
VOH
=
=
=
output capacitance load
switching frequency of an output
output high level voltage
When no reads or writes are occurring on the IDT723614, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fs is
calculated by:
PT=VCC x fS x 0.290 mA/MHz
COMMERCIALANDINDUSTRIAL
7
JANUARY14,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C; Industrial; VCC = 5.0V 10%,TA = 40°C to +85°C)
Commercial
Com'l & Ind'l(1)
IDT723614L20
IDT723614L15
Symbol
fS
Parameter
Min.
–
Max.
Min.
–
Max.
50
–
Unit
MHz
ns
Clock Frequency, CLKA or CLKB
66.7
–
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time, CLKA or CLKB
15
6
20
8
Pulse Duration, CLKA and CLKB HIGH
PulseDuration,CLKAandCLKBLOW
SetupTime, A0-A35before CLKA↑andB0-B35before CLKB↑
–
–
ns
6
–
8
–
ns
4
–
5
–
ns
tENS
Setup Time, CSA, W/RA, ENA and MBA before CLKA↑; CSB, W/RB and ENB
beforeCLKB↑
5
–
5
–
ns
tSZS
tSWS
tPGS
Setup Time, SIZ0, SIZ1, and BE before CLKB↑
4
5
4
–
–
–
5
7
5
–
–
–
ns
ns
ns
SetupTime,SW0andSW1beforeCLKB↑
SetupTime, ODD/EVENandPGAbefore CLKA↑;ODD/EVENandPGBbefore
(2)
CLKB↑
(3)
tRSTS
tFSS
tDH
SetupTime,RSTLOWbeforeCLKA↑orCLKB↑
5
5
1
1
–
–
–
–
6
6
1
1
–
–
–
–
ns
ns
ns
ns
Setup Time, FS0 and FS1 before RST HIGH
HoldTime,A0-A35afterCLKA↑andB0-B35afterCLKB↑
tENH
Hold Time, CSA, W/RA, ENA and MBA after CLKA↑; CSB, W/RB, and ENB
afterCLKB↑
tSZH
tSWH
tPGH
Hold Time, SIZ0, SIZ1, and BE after CLKB↑
2
0
0
–
–
–
2
0
0
–
–
–
ns
ns
ns
HoldTime,SW0andSW1afterCLKB↑
HoldTime,ODD/EVENandPGAafterCLKA↑;ODD/EVENandPGBafter
(2)
CLKB↑
(3)
tRSTH
tFSH
HoldTime, RSTLOWafterCLKA↑orCLKB↑
5
4
–
–
–
–
6
4
–
–
–
–
ns
ns
ns
ns
Hold Time, FS0 and FS1 after RST HIGH
tSKEW1(4) Skew Time, between CLKA↑ and CLKB↑ for EFA, EFB, FFA, and FFB
tSKEW2(4) Skew Time, between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and AFB
NOTES:
8
8
14
16
1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Only applies for a clock edge that does a FIFO read.
3. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
4. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
JANUARY14,2009
8
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF
SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30PF
(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C; Industrial; VCC = 5.0V 10%,TA = 40°C to +85°C)
Commercial
Com'l & Ind'l(1)
IDT723614L20
IDT723614L15
Symbol
tA
Parameter
Min.
2
Max.
Min.
2
Max.
12
Unit
ns
Access Time,CLKA↑toA0-A35andCLKB↑toB0-B35
Propagation Delay Time, CLKA↑ to FFA and CLKB↑ to FFB
PropagationDelayTime, CLKA↑toEFAandCLKB↑ toEFB
PropagationDelayTime, CLKA↑toAEAandCLKB↑ toAEB
PropagationDelayTime, CLKA↑toAFAandCLKB↑toAFB
10
10
10
10
10
9
tWFF
tREF
tPAE
tPAF
tPMF
2
2
12
ns
2
2
12
ns
2
2
12
ns
2
2
12
ns
Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH and CLKB↑ to
MBF2 LOW or MBF1 HIGH
1
1
12
ns
tPMR
PropagationDelayTime, CLKA↑toB0-B35(2) andCLKB↑ toA0-A35(3)
3
2
1
3
3
2
11
11
11
10
11
11
3
2
1
3
3
2
13
12
ns
ns
ns
ns
ns
ns
tPPE(4) Propagationdelaytime,CLKB↑toPEFB
tMDV
tPDPE
tPOPE
Propagation Delay Time, MBA to A0-A35 valid and SIZ1, SIZ0 to B0-B35 valid
Propagation Delay Time, A0-A35 valid to PEFA valid; B0-B35 valid to PEFB valid
Propagation Delay Time, ODD/EVEN to PEFAand PEFB
11. 5
11
12
(5)
tPOPB Propagation Delay Time, ODD/EVEN to parity bits (A8, A17, A26, A35) and
12
(B8, B17, B26, B35)
tPEPE
Propagation Delay Time, CSA, ENA, W/RA, MBA, or PGA to PEFA; CSB, ENB,
W/RB, SIZ1, SIZ0, or PGB to PEFB
1
3
11
12
1
3
12
13
ns
ns
(5)
tPEPB
Propagation Delay Time, CSA, ENA, W/RA, MBA, or PGA to parity bits (A8, A17,
A26, A35); CSB, ENB, W/RB, SIZ1, SIZ0, or PGB to parity bits (B8, B17, B26, B35)
tRSF
tEN
Propagation Delay Time, RST to (MBF1, MBF2) HIGH
1
2
15
10
1
2
20
12
ns
ns
Enable Time, CSAandW/RALOWtoA0-A35active andCSBLOWandW/RB
HIGHtoB0-B35active
tDIS
Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance and CSB HIGH or
W/RBLOWtoB0-B35athigh-impedance
1
8
1
9
ns
NOTES:
1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Writing data to the mail1 register when the B0-B35 outputs are active and SIZ1, SIZ0 are HIGH.
3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
4. Only applies when a new port B bus size is implemented by the rising CLKB edge.
5. Only applies when reading data from a mail register.
COMMERCIALANDINDUSTRIAL
JANUARY14,2009
9
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
B, EFBis setLOWwhenthefourthbyteorsecondwordofthelastlongword
is read.
SIGNALDESCRIPTIONS
The read pointer of a FIFO is incremented each time a new word is
clocked to the output register. The state machine that controls an Empty
Flag monitors a write-pointer and read-pointer comparator that indicates
whentheFIFOSRAMstatusisempty,empty+1,orempty+2. Awordwritten
to a FIFO can be read to the FIFO output register in a minimum of three
cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag is
LOW if a word in memory is the next data to be sent to the FIFO output
register and two cycles of the port clock that reads data from the FIFO have
notelapsedsincethetimethewordwaswritten. TheEmptyFlagoftheFIFO
is set HIGH by the second LOW-to-HIGH transition of the synchronizing
clock, and the new data word can be read to the FIFO output register in the
following cycle.
RESET
The IDT723614 is reset by taking the Reset (RST) input LOW for at least
four port A clock (CLKA) and four port B clock (CLKB) LOW-to-HIGH
transitions. The Reset input can switch asynchronously to the clocks. A
device resetinitializes the internalreadandwrite pointers ofeachFIFOand
forces the Full Flags (FFA, FFB) LOW, the Empty Flags (EFA, EFB) LOW,
the Almost-Empty flags (AEA, AEB) LOW and the Almost-Full flags (AFA,
AFB) HIGH. A reset also forces the Mailbox Flags (MBF1, MBF2) HIGH.
After a reset, FFA is set HIGH after two LOW-to-HIGH transitions of CLKA
and FFB is set HIGH after two LOW-to-HIGH transitions of CLKB. The
device must be reset after power up before data is written to its memory.
A LOW-to-HIGH transition on the RST input loads the Almost-Full and
Almost-EmptyOffsetregister(X)withthevaluesselectedbytheFlagSelect
(FS0, FS1) inputs. The values that can be loaded into the registers are
shown in Table 1.
A LOW-to-HIGH transition on an Empty Flag synchronizing clock begins
thefirstsynchronizationcycleofawriteiftheclocktransitionoccursattimetSKEW1
orgreaterafterthewrite. Otherwise,thesubsequentclockcyclecanbethefirst
synchronization cycle (see Figure 14 and 15).
FIFO WRITE/READ OPERATION
FULL FLAG (FFA, FFB)
The state of port A data A0-A35 outputs is controlled by the port A Chip
Select(CSA)andtheportAWrite/Readselect(W/RA). TheA0-A35outputs
areinthehigh-impedancestatewheneitherCSAorW/RAis HIGH.TheA0-
A35 outputs are active when both CSA and W/RA are LOW. Data is loaded
into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA
when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is LOW, and FFA
is HIGH. Datais readfromFIFO2totheA0-A35outputs byaLOW-to-HIGH
transition of CLKA when CSA is LOW, W/RA is LOW, ENA is HIGH, MBA
is LOW, and EFA is HIGH (see Table 2).
The portBcontrolsignals are identicaltothose ofportA. The state ofthe
port B data (B0-B35) outputs is controlled by the port B Chip Select (CSB)
andtheportBWrite/Readselect(W/RB). TheB0-B35outputsareinthehigh-
impedancestatewheneitherCSBorW/RBisHIGH. TheB0-B35outputsare
activewhenbothCSBandW/RBareLOW.DataisloadedintoFIFO2fromthe
B0-B35inputson aLOW-to-HIGHtransitionofCLKBwhenCSBisLOW,W/RB
is HIGH, ENB is HIGH, EFB is HIGH, and either SIZ0 or SIZ1 is LOW. Data
isreadfromFIFO1totheB0-B35outputsbyaLOW-to-HIGHtransitionofCLKB
whenCSBisLOW,W/RBisLOW,ENBisHIGH, EFBisHIGH,andeitherSIZ0
or SIZ1 is LOW (see Table 3).
The Full Flag of a FIFO is synchronized to the port clock that writes data
to its array. When the Full Flag is HIGH, a memory location is free in the
SRAMtoreceive newdata. Nomemorylocations are free whenthe fullflag
is LOW and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, the write pointer is incremented.
The state machine that controls a Full Flag monitors a write-pointer and
read-pointer comparator that indicates when the FIFO SRAM status is full,
full-1, or full-2. From the time a word is read from a FIFO, the previous
memory location is ready to be written in a minimum of three cycles of the
FullFlagsynchronizingclock. Therefore, a FullFlagis LOWifless thantwo
cycles of the Full Flag synchronizing clock have elapsed since the next
memorywritelocationhas beenread. ThesecondLOW-to-HIGHtransition
ontheFullFlagsynchronizationclockafterthereadsetstheFullFlagHIGHand
thedatacanbewritteninthefollowingclockcycle.
A LOW-to-HIGH transition on a Full Flag synchronizing clock begins the
first synchronization cycle of a read if the clock transition occurs at time
tSKEW1 orgreateraftertheread. Otherwise,thesubsequentclockcyclecan
be the first synchronization cycle (see Figure 16 and 17).
The setup and hold time constraints to the port clocks for the port Chip
Selects (CSA, CSB) and Write/Read selects (W/RA, W/RB) are only for
enabling write and read operations and are not related to high-impedance
control of the data outputs. If a port enable is LOW during a clock cycle, the
port Chip Select and Write/Read select can change states during the setup
and hold time window of the cycle.
ALMOST-EMPTY FLAGS (AEA, AEB)
The Almost-Empty flag of a FIFO is synchronized to the port clock that
reads datafromits array. Thestatemachinethatcontrols anAlmost-Empty
flag monitors a write-pointer and a read-pointer comparator that indicates
when the FIFO SRAM status is almost-empty, almost-empty+1, or almost-
empty+2. The almost-emptystate is definedbythe value ofthe Almost-Full
and Almost-Empty Offset register (X). This register is loaded with one of
four preset values during a device reset (see Reset above). An Almost-
Empty flag is LOW when the FIFO contains X or less long words in memory
and is HIGH when the FIFO contains (X+1) or more long words.
Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing
clock are required after a FIFO write for the Almost-Empty flag to reflect the
new level of fill. Therefore, the Almost-Empty flag of a FIFO containing
(X+1) or more long words remains LOW if two cycles of the synchronizing
clock have not elapsed since the write that filled the memory to the (X+1)
level. An Almost-Empty flag is set HIGH by the second LOW-to-HIGH
transition of the synchronizing clock after the FIFO write that fills memory
to the (X+1) level. A LOW-to-HIGH transition of an Almost-Empty flag
synchronizingclockbegins the firstsynchronizationcycle ifitoccurs attime
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through two flip-flop stages.
This is done to improve flag reliability by reducing the probability of
metastable events on the output when CLKA and CLKB operate asynchro-
nouslytooneanother.EFA,AEA,FFA,andAFAaresynchronizedtoCLKA.
EFB, AEB, FFB, and AFB are synchronized to CLKB. Tables 4 and 5 show
the relationship of each port flag to FIFO1 and FIFO2.
EMPTY FLAGS (EFA, EFB)
TheEmptyFlagofaFIFOissynchronizedtotheportclockthatreadsdata
fromitsarray. WhentheEmptyFlagisHIGH,newdatacanbereadtotheFIFO
outputregister. WhentheEmptyFlagisLOW,theFIFOisemptyandattempted
FIFOreadsareignored.WhenreadingFIFO1withabyteorwordsizeonport
JANUARY14,2009
10
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
tSKEW2 or greater after the write that fills the FIFO to (X+1) long words. offill. Therefore,theAlmost-FullflagofaFIFOcontaining[64-(X+1)]orless
Otherwise, the subsequent synchronizing clock cycle can be the first words remains LOW if two cycles of the synchronizing clock have not
synchronization cycle (see Figure 18 and 19).
elapsed since the read that reduced the number of long words in memory
to [64-(X+1)]. An Almost-Full flag is set HIGH by the second LOW-to-HIGH
transition of the synchronizing clock after the FIFO read that reduces the
ALMOST FULL FLAGS (AFA, AFB)
TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwrites number of long words in memory to [64-(X+1)]. A LOW-to-HIGH transition
data to its array. The state machine that controls an Almost-Full flag of an Almost-Full flag synchronizing clock begins the first synchronization
monitors a write-pointer and read-pointer comparator that indicates when cycleifitoccursattimetSKEW2orgreaterafterthereadthatreducesthenumber
the FIFO SRAM status is almost full, almost full-1, or almost full-2. The oflongwordsinmemoryto[64-(X+1)]. Otherwise,thesubsequentsynchro-
almost-fullstateisdefinedbythevalueoftheAlmost-FullandAlmost-Empty nizingclockcyclecanbethefirstsynchronizationcycle(seeFigure20and21).
Offset register (X). This register is loaded with one of four preset values
during a device reset (see Reset above). An Almost-Full flag is LOW when MAILBOX REGISTERS
the FIFO contains (64-X) or more long words in memory and is HIGH when
the FIFO contains [64-(X+1)] or less long words.
Each FIFO has a 36-bit bypass register to pass command and control
information between port A and port B without putting it in queue. The
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclock Mailbox-Select (MBA, MBB) inputs choose between a mail register and a
arerequiredafteraFIFOreadfortheAlmost-Fullflagtoreflectthenewlevel FIFOforaportdatatransferoperation. ALOW-to-HIGHtransitiononCLKA
writes A0-A35 data to the mail1 register when a port A write is selected by
CSA,W/RA,andENAwithMBAHIGH. ALOW-to-HIGHtransitiononCLKB
writes B0-B35 data to the mail2 register when a port B write is selected by
TABLE 1 — FLAG PROGRAMMING
CSB, W/RB, andENBwithbothSIZ1andSIZ0HIGH. Writingdata toa mail
register sets the corresponding flag (MBF1 or MBF2) LOW. Attempted
writes to a mail register are ignored while the mail flag is LOW.
ALMOST-FULL AND
ALMOST-EMPTY FLAG
OFFSET REGISTER (X)
FS1
FS0
RST
When the port A data outputs (A0-A35) are active, the data on the bus
comesfromtheFIFO2outputregisterwhenMBAisLOWandfromthemail2
register when MBA is HIGH. When the port B data outputs (B0-B35) are
active, the data on the bus comes from the FIFO1 output register when
eitherone orbothSIZ1andSIZ0are LOWandfromthe mail2registerwhen
both SIZ1 and SIZ0 are HIGH. The Mail1 Register Flag (MBF1) is set HIGH
H
H
L
L
H
L
H
L
↑
↑
↑
↑
16
12
8
4
TABLE 2 — PORT-A ENABLE FUNCTION TABLE
CSA
H
L
W/RA
ENA
MBA
CLKA
A0-A35Outputs
InHigh-ImpedanceState
InHigh-ImpedanceState
InHigh-ImpedanceState
InHigh-ImpedanceState
Active,FIFO2OutputRegister
Active,FIFO2OutputRegister
Active,Mail2Register
Port Functions
X
X
X
X
None
None
H
L
X
X
L
H
H
L
↑
FIFO1Write
Mail1Write
L
H
H
H
↑
L
L
L
L
X
None
L
L
H
L
↑
FIFO2Read
None
L
L
L
H
X
L
L
H
H
↑
Active,Mail2Register
Mail2 Read (Set MBF2 HIGH)
TABLE 3 — PORT-B ENABLE FUNCTION TABLE
CSB
H
L
W/RB
ENB
SIZ1, SIZ0
CLKB
B0-B35Outputs
InHigh-ImpedanceState
InHigh-ImpedanceState
InHigh-ImpedanceState
InHigh-ImpedanceState
Active,FIFO1OutputRegister
Active,FIFO1OutputRegister
Active,Mail1Register
Port Functions
X
X
X
X
None
None
H
L
X
X
L
H
H
One,bothLOW
Both HIGH
One,bothLOW
One,bothLOW
Both HIGH
Both HIGH
↑
FIFO2Write
Mail2Write
L
H
H
↑
L
L
L
X
None
L
L
H
↑
FIFO1read
None
L
L
L
X
L
L
H
↑
Active,Mail1Register
Mail1 Read (Set MBF1 HIGH)
COMMERCIALANDINDUSTRIAL
JANUARY14,2009
11
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
byarising CLKBedgewhenaportBreadisselectedbyCSB,W/RB,andENB subsequentFIFO1readswiththesamebus-sizeimplementationoutputtherest
withbothSIZ1andSIZ0HIGH.TheMail2RegisterFlag(MBF2)is setHIGH ofthe longwordtothe FIFO1outputregisterinthe ordershownbyFigure 2.
byaLOW-to-HIGHtransitiononCLKAwhenportAreadisselectedbyCSA,
EachFIFO1readwithanewbus-sizeimplementationautomaticallyunloads
W/RA,andENAandMBAisHIGH.Thedatainthemailregisterremainsintact datafromtheFIFO1RAMtoitsoutputregisterandauxiliaryregisters.Therefore,
afteritis readandchanges onlywhennewdata is writtentothe register.
implementinganewportBbussizeandperformingaFIFO1readbeforeallbytes
orwordsstoredintheauxiliaryregistershavebeenreadresultsinalossofthe
unread long word data.
When reading data from FIFO1 in byte or word format, the unused B0-
B35 outputs remain inactive but static, with the unused FIFO1 output
register bits holding the last data value to decrease power consumption.
TABLE 4 — FIFO1 FLAG OPERATION
Synchronized
Synchronized
Number of 36-Bit
Words in the FIFO1(1)
to CLKB
to CLKA
BUS-MATCHING FIFO2 WRITES
EFB
AEB
AFA
H
FFA
Data is written to the FIFO2 RAM in 36-bit long word increments. FIFO2
writes, with a long-word bus size, immediately store each long word in
FIFO2 RAM. Data written to FIFO2 with a byte or word bus size stores the
initial bytes or words inauxiliaryregisters. The CLKBrisingedge thatwrites
the fourth byte or the second word of long word to FIFO2 also stores the
entire long word in FIFO2 RAM. The bytes are arranged in the manner
shown in Figure 2.
0
1 to X
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
(X+1)to[64-(X+1)]
(64-X)to63
64
H
L
L
Each FIFO2 write with a new bus-size implementation resets the state
machine thatcontrols the data flowfromthe auxiliaryregisters tothe FIFO2
RAM. Therefore, implementing a new bus size and performing a FIFO2
write before bytes or words stored in the auxiliary registers have been
loaded to FIFO2 RAM results in a loss of data.
TABLE 5 — FIFO2 FLAG OPERATION
Synchronized
Synchronized
Number of 36-Bit
Words in the FIFO2(1)
to CLKA
to CLKB
PORT-B MAIL REGISTER ACCESS
EFA
AEA
AFB
H
FFB
In addition to selecting port-B bus sizes for FIFO reads and writes, the
port B bus Size select (SIZ0, SIZ1) inputs also access the mail registers.
WhenbothSIZ0andSIZ1areHIGH,themail1registerisaccessedforaport
B long word read and the mail2 register is accessed for a port B long word
write. The mail register is accessed immediately and any bus-sizing
operation that may be underway is unaffected by the mail register access.
After the mail register access is complete, the previous FIFO access can
resume in the next CLKB cycle. The logic diagram in Figure 3 shows the
previous bus-size selection is preserved when the mail registers are
accessedfromportB.AportBbussizeisimplementedoneachrisingCLKB
edgeaccordingtothestates ofSIZ0_Q,SIZ1_Q,andBE_Q.
0
1 to X
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
H
(X+1)to[64-(X+1)]
(64-X)to63
64
H
L
L
NOTE:
1. X is the value in the Almost-Empty flag and Almost-Full flag Offset register.
DYNAMIC BUS SIZING
The port B bus can be configured in a 36-bit long word, 18-bit word, or 9-
bitbyteformatfordatareadfromFIFO1orwrittentoFIFO2.Word-andbyte-
size bus selections can utilize the most significant bytes of the bus (Big-
Endian) or least significant bytes of the bus (Little-Endian). Port B bus size
can be changed dynamically and synchronous to CLKB to communicate
with peripherals of various bus widths.
The levels applied to the port B bus Size select (SIZ0, SIZ1) inputs and
the Big-Endian select (BE) input are stored on each CLKB LOW-to-HIGH
transition. The stored port B bus size selection is implemented by the next
rising edge on CLKB according to Figure 2.
BYTE SWAPPING
The byte-order arrangement of data read from FIFO1 or data written to
FIFO2canbe changedsynchronous tothe risingedge ofCLKB. Byte-order
swapping is not available for mail register data. Four modes of byte-order
swapping(includingnoswap)canbedonewithanydataportsizeselection.
The order of the bytes are rearranged within the long word, but the bit order
within the bytes remains constant.
Byte arrangement is chosen by the port B Swap select (SW0, SW1)
inputs on a CLKB rising edge that reads a new long word from FIFO1 or
writes a new long word to FIFO2. The byte order chosen on the first byte or
first word of a new long word read from FIFO1 or written to FIFO2 is
maintained until the entire long word is transferred, regardless of the SW0
and SW1 states during subsequent writes or reads. Figure 4 is an example
ofthebyte-orderswappingavailableforlongwords.Performingabyteswap
and bus size simultaneously for a FIFO1 read first rearranges the bytes as
shown in Figure 4, then outputs the bytes as shown in Figure 2. Simulta-
neousbus-sizingandbyte-swappingoperationsforFIFO2writes,firstloads
thedataaccordingtoFigure2,thenswapsthebytesasshowninFigure4when
the long word is loaded to FIFO2 RAM.
Only 36-bit long-word data is written to or read from the two FIFO
memories on the IDT723614. Bus-matching operations are done after data
is read from the FIFO1 RAM and before data is written to the FIFO2 RAM.
Port B bus sizing does not apply to mail register operations.
BUS-MATCHING FIFO1 READS
Datais readfromtheFIFO1RAMin36-bitlongwordincrements.Ifalong
wordbus size is implemented, the entire longwordimmediatelyshifts tothe
FIFO1 output register. If byte or word size is implemented on port B, only
the firstone ortwobytes appearonthe selectedportionofthe FIFO1output
register,withtherestofthelongwordstoredinauxiliaryregisters.Inthiscase,
JANUARY14,2009
12
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
A35⎯A27 A26⎯A18
A17⎯A9
A8⎯A0
Write to FIFO1/
Read From FIFO2
BYTE ORDER ON PORT A:
D
A
B
C
B35⎯B27
B26⎯B18 B17⎯B9
B8⎯B0
Read from FIFO1/
Write to FIFO2
BE SIZ1 SIZ0
D
A
B
C
X
L
L
(a) LONG WORD SIZE
B8⎯B0
B8⎯B0
B35⎯B27 B26⎯B18 B17⎯B9
BE
SIZ1 SIZ0
1st: Read from FIFO1/
Write to FIFO2
B
A
L
L
H
B35⎯B27 B26⎯B18 B17⎯B9
2nd: Read from FIFO1/
Write to FIFO2
C
D
(b) WORD SIZE
⎯ BIG-ENDIAN
B8⎯B0
B17⎯B9
B35⎯B27 B26⎯B18
BE
SIZ1
L
SIZ0
H
1st: Read from FIFO1/
Write to FIFO2
C
D
H
B8⎯B0
B35⎯B27 B26⎯B18 B17⎯B9
2nd: Read from FIFO1/
Write to FIFO2
A
B
(c) WORD SIZE
⎯ LITTLE-ENDIAN
B26⎯B18 B17⎯B9
B26⎯B18 B17⎯B9
B8⎯B0
B8⎯B0
B35⎯B27
BE
SIZ1 SIZ0
1st: Read from FIFO1/
Write to FIFO2
A
L
H
L
B35⎯B27
2nd: Read from FIFO1/
Write to FIFO2
B
B26⎯B18 B17⎯B9
B26⎯B18 B17⎯B9
B8⎯B0
B8⎯B0
B35⎯B27
3rd: Read from FIFO1/
Write to FIFO2
C
B35⎯B27
4th: Read from FIFO1/
Write to FIFO2
D
(d) BYTE SIZE
⎯
BIG-ENDIAN
B17⎯B9
B8⎯B0
B35⎯B27 B26⎯B18
BE SIZ1 SIZ0
1st: Read from FIFO1/
Write to FIFO2
D
H
H
L
B26⎯B18
B35⎯B27
B17⎯B9
B17⎯B9
B17⎯B9
B8⎯B0
2nd: Read from FIFO1/
Write to FIFO2
C
B8⎯B0
B26⎯B18
B26⎯B18
B35⎯B27
B35⎯B27
3rd: Read from FIFO1/
Write to FIFO2
B
B8⎯B0
4th: Read from FIFO1/
Write to FIFO2
A
3146 fig 01
(d) BYTE SIZE
⎯ LITTLE-ENDIAN
Figure 2. Dynamic Bus Sizing
COMMERCIALANDINDUSTRIAL
JANUARY14,2009
13
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
PARITYGENERATION
PARITY CHECKING
A HIGH level on the port A Parity Generate select (PGA) or port B Parity
Generateselect(PGB)enablestheIDT723614togenerateparitybitsforport
reads froma FIFOormailboxregister. PortAbytes are arrangedas A0-A8,
A9-A17,A18-26,andA27-A35,withthemostsignificantbitofeachbyteused
astheparitybit. PortBbytesarearrangedasB0-B8,B9-B17,B18-B26,and
B27-B35,withthemostsignificantbitofeachbyteusedastheparitybit. Awrite
toa FIFOormailregisterstores the levels appliedtoallnine inputs ofa byte
regardlessofthestateoftheParityGenerateselect(PGA,PGB)inputs. When
dataisreadfromaportwithparitygenerationselected,thelowereightbitsof
eachbyteareusedtogenerateaparitybitaccordingtothelevelontheODD/
EVENselect. Thegeneratedparitybitsaresubstitutedforthelevelsoriginally
writtentothemostsignificantbitsofeachbyteasthewordisreadtothedata
outputs.
Parity bits for FIFO data are generated after the data is read from SRAM
and before the data is written to the output register. Therefore, the port A
ParityGenerateselect(PGA)andOdd/Evenparityselect(ODD/EVEN)have
setupandholdtimeconstraintstotheportAClock(CLKA)andtheportBParity
Generateselect(PGB)andODD/EVENhavesetupandhold-timeconstraints
totheportBClock(CLKB). Thesetimingconstraintsonlyapplyforarisingclock
edge used to read a new long word to the FIFO output register.
Thecircuitusedtogenerateparityforthemail1dataissharedbytheportB
bus(B0-B35)tocheckparityandthecircuitusedtogenerateparityforthemail2
data is shared by the port A bus (A0-A35) to check parity. The shared parity
treesofaportareusedtogenerateparitybitsforthedatainamailregisterwhen
theportChipSelect(CSA,CSB)isLOW,Enable(ENA,ENB)isHIGH,Write/
Readselect(W/RA,W/RB)inputisLOW,the Mailregisterisselected(MBAis
HIGH for port A; both SIZ0 and SIZ1 are HIGH for port B), and port Parity
Generateselect(PGA,PGB)isHIGH. Generatingparityformailregisterdata
doesnotchangethecontentsoftheregister.
The port A inputs (A0-A35) and port B inputs (B0-B35) each have four
paritytreestochecktheparityofincoming(oroutgoing)data. Aparityfailure
on one or more bytes of the port A data bus is reported by a LOW level on
the port Parity Error Flag (PEFA). A parity failure on one or more bytes of
the port B data input that are valid for the bus-size implementation is
reportedbyaLOWlevelontheportBParityErrorFlag(PEFB). OddorEven
parity checking can be selected, and the Parity Error Flags can be ignored
if this feature is not desired.
Parity status is checked on each input bus according to the level of the
Odd/Even parity (ODD/EVEN) select input. A parity error on one or more
valid bytes of a port is reported by a LOW level on the corresponding port
Parity Error Flag (PEFA, PEFB) output. Port A bytes are arranged as A0-
A8, A9-A17, A18-A26, and A27-A35. Port B bytes are arranged as B0-B8,
B9-B17, B18-B26, andB27-B35, andits validbytes are those usedina port
Bbus-sizeimplementation. WhenOdd/Evenparityis selected, aportParity
Error Flag (PEFA, PEFB) is LOW if any byte on the port has an odd/even
numberofLOWlevelsappliedtothebits.
ThefourparitytreesusedtochecktheA0-A35inputsaresharedbythemail2
register when parity generation is selected for port A reads (PGA = HIGH).
WhenaportAreadfromthemail2registerwithparitygenerationisselectedwith
CSALOW, ENAHIGH, W/RALOW, MBAHIGH, andPGAHIGH, the portA
ParityErrorFlag(PEFA)is heldHIGHregardless ofthelevels appliedtothe
A0-A35inputs. Likewise,theparitytreesusedtochecktheB0-B35inputsare
sharedbythemail1registerwhenparitygenerationisselectedforportBreads
(PGB = HIGH). WhenaportBreadfromthemail1registerwithparitygeneration
isselectedwithCSBLOW,ENB HIGH,W/RBLOW,bothSIZ0andSIZ1HIGH,
andPGBHIGH,theportBParityErrorFlag(PEFB)isheldHIGHregardless
ofthelevelsappliedtotheB0-B35inputs.
CLKB
MUX
G1
SIZ0 Q
SIZ1 Q
BE Q
1
•
D
Q
•
SIZ0
SIZ1
BE
•
•
1
•
3146 fig02
Figure 3. Logic Diagrams for SIZ0, SIZ1, and BE Register
JANUARY14,2009
14
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
A35⎯A27
A26⎯A18
A17⎯A9
A8⎯A0
B
A
C
D
SW1 SW0
L
L
A
B
C
D
B35⎯B27
B26⎯B18
B17⎯B9
B8⎯B0
(a) NO SWAP
A35⎯A27
A26⎯A18
A17⎯A9
A8⎯A0
SW1 SW0
A
B
C
D
L
H
A
D
C
B
B35⎯B27
B26⎯B18
B17⎯B9
B8⎯B0
(b) BYTE SWAP
A35⎯A27
A26⎯A18
A17⎯A9
A8⎯A0
SW1 SW0
B
A
C
D
H
L
D
B
C
A
B35⎯B27
B26⎯B18
B17⎯B9
B8⎯B0
(c) WORD SWAP
A35⎯A27
A26⎯A18
A17⎯A9
A8⎯A0
SW1 SW0
A
B
C
D
H
H
B
A
D
C
B35⎯B27
B26⎯B18
B17⎯B9
B8⎯B0
3146 fig03
(d) BYTE-WORD SWAP
Figure 4. Byte Swapping (Long Word Size Example)
COMMERCIALANDINDUSTRIAL
JANUARY14,2009
15
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
CLKA
CLKB
tRSTH
t
FSS
t
RSTS
t
FSH
RST
FS1,FS0
FFA
0,1
t
WFF
t
t
WFF
REF
EFA
t
WFF
t
WFF
FFB
EFB
t
REF
t
RSF
MBF1,
MBF2
t
PAE
AEA
AFA
t
PAF
t
PAE
AEB
AFB
t
PAF
3146 drw05
Figure 5. Device Reset Loading the X Register with the Value of Eight
JANUARY14,2009
16
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
tCLK
tCLKH
tCLKL
CLKA
FFA
CSA
HIGH
t
ENS
tENH
t
ENS
t
ENH
ENH
W/RA
t
ENS
t
MBA
tENS
tENS
tENH
tENH
tENS
tENH
ENA
tDS
tDH
(1)
W2(1)
No Operation
A0 - A35
W1
ODD/
EVEN
tPDPE
tPDPE
Valid
Valid
PEFA
3146 drw06
NOTE:
1. Written to FIFO1.
Figure 6. Port-A Write Cycle Timing for FIFO1
CLKB
FFB
CSB
HIGH
t
ENS
ENS
t
W/RB
t
ENH
t
t
ENS
tENS
tENH
ENB
SWS
t
SWH
SW1,
SW0
t
SZH
t
SZS
BE
t
SZS
t
SZH
SIZ1,
SIZ0
(0,0)
(0,0)
DS
(1)
NOT (1,1)
tDH
t
B0-B35
ODD/
EVEN
t
PPE
tPDPE
PEFB
VALID
3146 drw 07
VALID
NOTE:
1. SIZ0 = HIGH and SIZ1 = HIGH writes data to the mail2 register
DATA SWAP TABLE FOR LONG-WORD WRITES TO FIFO2
SWAP MODE
DATA WRITTEN TO FIFO2
DATA READ FROM FIFO2
SW1
L
SW0
L
B35-27
B26-18
B17-B9
B8-B0
D
A35-27
A26-A18
A17-A9
A8-A0
D
A
D
C
B
C
D
C
B
A
A
A
A
B
B
B
C
C
C
L
H
A
D
H
L
B
D
H
H
B
A
D
C
A
B
C
D
COMMERCIALANDINDUSTRIAL
JANUARY14,2009
Figure 7. Port-B Long-Word Write Cycle Timing for FIFO2
17
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
CLKB
FFB
CSB
HIGH
tENH
tENS
tENS
W/RB
tENH
tENS
tENH
tENS
ENB
SW1, SW0
BE
t
SWS
tSWH
t
SZS
t
t
SZH
SZH
t
t
SZH
SZH
t
SZS
t
SZS
t
SZS
SIZ1, SIZ0
NOT (1,1) (1)
(0, 1)
(0, 1)
tDH
tDS
Little-
Endian
B0-B17
tDH
tDS
Big-
Endian
B18-B35
ODD/EVEN
tPDPE
t
PPE
VALID
PEFB
VALID
3146 drw08
NOTES:
1. SIZ0 = HIGH and SIZ1 = HIGH writes data to the mail2 register.
2. PEFB indicates parity error for the following bytes: B35-B27 and B26-B18 for Big-Endian bus, and B17-B9 and B8-B0 for Little-Endian bus.
DATA SWAP TABLE FOR WORD WRITES TO FIFO2
DATA WRITTEN TO FIFO2
SWAP
WRITE
NO.
DATA READ FROM FIFO2
MODE
BIG-ENDIAN
LITTLE-ENDIAN
B17-B9 B8-B0
SW1
SW0
B35-27
B26-18
A35-27
A26-A18
A17-A9
A8-A0
L
L
1
2
1
2
1
2
1
A
C
D
B
C
A
B
B
D
C
A
D
B
A
C
D
A
B
C
D
D
D
D
A
B
D
A
C
D
B
A
C
B
D
C
L
H
L
A
A
A
B
B
B
C
C
C
H
H
H
2
D
C
B
A
Figure 8. Port-B Word Write Cycle Timing for FIFO2
JANUARY14,2009
18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
CLKB
FFB
CSB
HIGH
tENS
tENH
tENS
tENH
W/RB
tENS
tENH
tSZH
tENS
tENH
ENB
tSWS
tSZS
SW1,
SW0
tSZS
tSZS
tSZH
tSZH
BE
tSZH
tDH
tSZS
tDS
SIZ1,
SIZ0
(1,0)
(1,0)
(1,0)
(1,0)
Not (1,1)(1)
Little-
Endian
B0-
B8
tDS
tDH
Big- B27-
Endian B35
ODD/EVEN
tPPE
tPDPE
tPDPE
tPDPE
Valid
Valid
Valid
PEFB
3146 drw09
Valid
NOTES:
1.
SIZ0 = HIGH and SIZ1 = HIGH writes data to the mail2 register.
2. PEFB indicates parity error for the following bytes: B35—B27 for Big-Endian bus and B17—B9 for Little-Endian bus.
DATA SWAP TABLE FOR BYTE WRITES TO FIFO2
DATA WRITTEN TO FIFO2
SWAP
MODE
WRITE
NO.
DATA READ FROM FIFO2
BIG-ENDIAN
B35-27
LITTLE-ENDIAN
B8-B0
SW1
SW0
A35-27
A26-A18
A17-A9
A8-A0
1
2
3
4
A
B
C
D
D
C
B
A
L
L
A
B
C
D
1
2
3
4
D
C
B
A
A
B
C
D
A
A
B
B
C
C
D
D
L
H
L
1
2
3
4
C
D
A
B
B
A
D
C
H
H
1
2
3
4
B
A
D
C
C
D
A
B
H
A
B
C
D
Figure 9. Port-B Byte Write Cycle Timing for FIFO2
COMMERCIALANDINDUSTRIAL
JANUARY14,2009
19
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
CLKB
EFB
CSB
HIGH
W/RB
tENS
tENH
tENS
tENH
ENB
No Operation
tSWS
tSWH
SW1,
SW0
t
SZH
t
SZS
BE
t
SZH
t
SZS
NOT (1,1)(1)
(0,0)
SIZ1,
SIZ0
NOT (1,1)(1)
(0,0)
tPGS
t
PGH
PGB,
ODD/
EVEN
tDIS
t
A
tA
tEN
Previous Data
W1(2)
W2(2)
B0-B35
3146 drw10
NOTES:
1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35.
2. Data read from FIFO1.
DATA SWAP TABLE FOR FIFO LONG-WORD READS FROM FIFO1
DATA WRITTEN TO FIFO1
SWAP MODE
DATA READ FROM FIFO1
A35-27
A26-A18
A17-A9
A8-A0
D
SW1
SW0
L
B35-27
B26-18
B17-B9
B8-B0
D
A
A
A
B
B
B
C
C
C
L
L
A
D
C
B
C
D
C
B
A
D
H
A
D
H
L
B
A
B
C
D
H
H
B
A
D
C
Figure 10. Port-B Long-Word Read Cycle Timing for FIFO1
JANUARY14,2009
20
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
CLKB
EFB
CSB
HIGH
W/RB
tENS
tSWS
tENH
tSWH
ENB
No Operation
SW1,
SW0
tSZH
tSZH
tSZS
BE
tSZS
SIZ1,
SIZ0
NOT (1,1)(1)
NOT (1,1)(1)
(0,1)
(0,1)
tPGS
tPGH
tA
PGB,
ODD/
EVEN
tEN
tA
tA
tDIS
tDIS
Little-
Previous Data
tA
Read 1
Read 1
Read 2
Read 2
Endian(2)
B0-B17
Big-
Endian(2)
B18-B35
Previous Data
3146 drw11
NOTES:
1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35.
2. Unused word B0-B17 or B18-B35 holds last FIFO1 output register data for word-size reads.
DATA SWAP TABLE FOR WORD READS FROM FIFO1
DATA READ FROM FIFO1
DATA WRITTEN TO FIFO1
SWAP MODE
READ
NO.
BIG-ENDIAN
B35-B27 B26-B18
LITTLE-ENDIAN
A35-A27
A26-A18
A17-A9
A8-A0
D
SW1
SW0
L
B17-B9
B8-B0
1
2
A
C
B
D
C
A
D
B
A
A
A
A
B
B
B
B
C
C
C
C
L
L
1
2
D
B
C
A
B
D
A
C
D
H
1
2
C
A
D
B
A
C
B
D
D
H
H
L
1
2
B
D
A
C
D
B
C
A
D
H
Figure 11. Port-B Word Read Cycle Timing for FIFO1
COMMERCIALANDINDUSTRIAL
JANUARY14,2009
21
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
CLKB
EFB
CSB
HIGH
W/RB
tENS
tENH
ENB
No Operation
tSWS
tSWH
SW1,
SW0
t
SZS
t
t
SZH
SZH
BE
t
SZS
SIZ1,
SIZ0
(1)
(1,0)
Not (1,1)
(1,0)
(1,0)
(1,0)
(1)
(1)
(1)
Not (1,1)
PGH
Not (1,1)
PGS
Not (1,1)
t
t
PGB,
ODD/
EVEN
t
DIS
DIS
tEN
tA
tA
t
A
tA
Previous Data
Read 1
Read 2
Read 3
Read 4
Read 4
B0-B8
t
tA
tA
tA
tA
Previous Data
Read 1
Read 2
Read 3
B27-B35
3146 drw12
NOTES:
1. SIZ0 = HIGH and SIZ1 = HIGH selects the mail1 register for output on B0-B35.
2. Unused bytes hold last FIFO1 output register data for byte-size reads.
DATA SWAP TABLE FOR BYTE READS FROM FIFO1
DATA READ FROM FIFO 1
DATA WRITTEN TO FIFO 1
SWAP MODE
READ
NO.
BIG-
ENDIAN
LITTLE-
ENDIAN
A35-A27
A26-A18
A17-A9
A8-A0
SW1
SW0
B35-B27
B8-B0
1
2
3
4
A
B
C
D
D
C
B
A
A
B
C
D
L
L
L
1
2
3
4
D
C
B
A
A
B
C
D
A
A
A
B
B
B
C
C
C
D
D
D
H
L
1
2
3
4
C
D
A
B
B
A
D
C
H
H
1
2
3
4
B
A
D
C
C
D
A
B
H
Figure 12. Port-B Byte Read Cycle Timing for FIFO1
JANUARY14,2009
22
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
tCLK
tCLKH
tCLKL
CLKA
EFA
CSA
HIGH
W/RA
MBA
ENA
t
ENH
t
ENH
tENH
t
ENS
tENS
tENS
No Operation
Word 2(1)
t
MDV
tDIS
tEN
tA
tA
(1)
A0 - A35
Word 1
Previous Data
tPGH
tPGH
tPGS
tPGS
PGA,
ODD/
EVEN
3146 drw13
NOTE:
1. Read from FIFO2.
Figure 13. Port-A Read Cycle Timing for FIFO2
t
CLKtCLKL
t
CLKH
CLKA
CSA
LOW
HIGH
WRA
t
ENH
ENH
t
ENS
MBA
tENS
t
ENA
FFA
HIGH
tDS
tDH
W1
A0 - A35
t
CLKHCLKtCLKL
(1)
SKEW1
t
t
1
2
CLKB
t
REF
t
REF
EFB
CSB
FIFO1 Empty
LOW
LOW
LOW
W/RB
SIZ1,
SIZ0
tENS
tENH
ENB
tA
B0 -B35
W1
3146 drw14
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA
edge and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
2. Port-B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port-B size is word or byte, EFB is set LOW by the last word or byte read from FIFO1,
respectively.
Figure 14. EFB Flag Timing and First Data Read when FIFO1 is Empty
COMMERCIALANDINDUSTRIAL
23
JANUARY14,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
tCLK
tCLKH
tCLKL
CLKB
CSB
LOW
HIGH
W/RB
tENS
tENS
tENH
tENH
SIZ1,
SIZ0
ENB
FFB
HIGH
tDS
tDH
W1
B0 - B35
tCLKtCLKL
(1)
tSKEW1
tCLKH
1
2
CLKA
tREF
tREF
EFA
CSA
FIFO2 Empty
LOW
LOW
LOW
W/RA
MBA
tENS
tENH
ENA
tA
A0 -A35
W1
3146 drw15
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB
edge and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
2. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte tSKEW1 is referenced to the rising CLKB edge that writes the
last word or byte of the long word, respectively.
Figure 15. EFA Flag Timing and First Data Read when FIFO2 is Empty
JANUARY14,2009
24
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
tCLK
tCLKH
tCLKL
CLKB
CSB
LOW
LOW
LOW
W/RB
SIZ1,
SIZ0
tENH
tENS
ENB
EFB
HIGH
tA
Previous Word in FIFO1 Output Register
Next Word From FIFO1
B0 - B35
(1)
SKEW1
tCLK
t
tCLKH
tCLKL
1
2
CLKA
t
WFF
t
WFF
FFA
CSA
FIFO1 Full
LOW
HIGH
WRA
tENS
tENH
MBA
tENS
tENH
ENA
tDS
tDH
A0 - A35
To FIFO1
3146 drw16
NOTES:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and
rising CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown.
2. Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW1 is referenced from the rising CLKB edge that reads the last
word or byte of the long word, respectively.
Figure 16. FFA Flag Timing and First Available Write when FIFO1 is Full.
COMMERCIALANDINDUSTRIAL
25
JANUARY14,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
tCLK
tCLKL
tCLKH
CLKA
CSA
LOW
LOW
LOW
W/RA
MBA
tENS
tENH
ENA
EFA
HIGH
tA
Previous Word in FIFO2 Output Register
Next Word From FIFO2
A0 - A35
(1)
SKEW1
t
tCLK
tCLKH
tCLKL
1
2
CLKB
t
WFF
t
WFF
FFB
CSB
FIFO2 Full
LOW
HIGH
W/RB
tENH
tENS
SIZ1,
SIZ0
tENS
tENH
ENB
tDS
tDH
B0 - B35
To FIFO2
3146 drw17
NOTES:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA
edge and rising CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown.
2. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, FFB is set LOW by the last word or byte write of the long
word, respectively.
Figure 17. FFB Flag Timing and First Available Write when FIFO2 is Full
CLKA
tENS
tENH
ENA
(1)
tSKEW2
1
2
CLKB
t
PAE
(X+1) Long Words in FIFO1
ENH
t
PAE
AEB
X Long Word in FIFO1
t
tENS
ENB
3146 drw18
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA
edge and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, MBB = LOW).
3. Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, AEB is set LOW by the last word or byte read of the long
word, respectively.
Figure 18. Timing for AEB when FIFO1 is Almost-Empty
JANUARY14,2009
26
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
CLKB
tENS
tENH
ENB
tSKEW2(1)
1
2
CLKA
AEA
t
PAE
t
PAE
(X+1) Long Words in FIFO2
X Long Words in FIFO2
tENH
tENS
ENA
3146 drw19
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising
CLKB edge and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (CSB = LOW, W/RB = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW).
3. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW2 is referenced from the rising CLKB edge that
writes the last word or byte of the long word, respectively.
Figure 19. Timing for AEA when FIFO2 is Almost-Empty
(1)
SKEW2
t
1
2
CLKA
ENA
tENS
tENH
t
PAF
tPAF
(64-X) Long Words in FIFO1
AFA
CLKB
ENB
[64-(X+1)] Long Words in FIFO1
tENS
tENH
3146 drw20
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising
CLKA edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = LOW, MBB = LOW).
3. Port B size of long word is selected for FIFO1 read by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, tSKEW2 is referenced from the last word or byte read of
the long word, respectively.
Figure 20. Timing for AFA when FIFO1 is Almost-Full
(1)
SKEW2
t
1
2
CLKB
ENB
tENS
tENH
t
PAF
t
PAF
(64-X) Long Words in FIFO2
AFB
CLKA
ENA
[64-(X+1)] Long Words in FIFO2
tENS
tENH
3146 drw21
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising
CLKB edge and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (CSB = LOW, W/RB = HIGH, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW).
3. Port B size of long word is selected for FIFO2 write by SIZ1 = LOW, SIZ0 = LOW. If port B size is word or byte, AFB is set LOW by the last word or byte read of
the long word, respectively.
Figure 21. Timing for AFB when FIFO2 is Almost-Full
COMMERCIALANDINDUSTRIAL
27
JANUARY14,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
CLKA
tENS
tENH
CSA
W/RA
MBA
ENA
A0 - A35
CLKB
tDH
t
DS
W1
t
PMF
t
PMF
MBF1
CSB
W/RB
SIZ1,
SIZ0
tENH
tENS
ENB
t
PMR
tEN
tDIS
t
MDV
W1 (Remains valid in Mail1 Register after read)
B0 - B35
3146 drw22
FIFO1 Output Register
NOTE:
1. Port B Parity Generation off (PGB = LOW).
Figure 22. Timing for Mail1 Register and MBF1 Flag
JANUARY14,2009
28
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
CLKB
tENH
tENS
CSB
W/RB
t
SZH
t
SZS
SIZ1,
SIZ0
ENB
B0 - B35
CLKA
tDH
t
DS
W1
t
PMF
t
PMF
MBF2
CSA
W/RA
MBA
ENA
tENH
tENS
t
PMR
tEN
tDIS
t
MDV
W1 (Remains valid in Mail2 Register after read)
A0 - A35
3146 drw23
FIFO2 Output Register
NOTE:
1. Port-A Parity Generation off (PGA = LOW).
Figure 23. Timing for Mail2 Register and MBF2 Flag
ODD/
EVEN
W/RA
MBA
PGA
t
PEPE
tPOPE
tPOPE
t
PEPE
PEFA
Valid
Valid
Valid
Valid
3146 drw24
Figure 24. ODD/EVEN. W/RA, MBA, and PGA to PEFA Timing
COMMERCIALANDINDUSTRIAL
JANUARY14,2009
29
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
ODD/
EVEN
W/RB
SIZ1,
SIZ0
PGB
t
PEPE
t
PEPE
tPOPE
tPOPE
PEFB
Valid
Valid
Valid
Valid
3146 drw25
Figure 25. ODD/EVEN. W/RB, SIZ1, SIZ0, and PGB to PEFB Timing
ODD/
EVEN
CSA LOW
W/RA
MBA
PGA
t
PEPB
t
MDV
tEN
t
POPB
tPEPB
Generated Parity
A8, A17,
A26, A35
Generated Parity
Mail2 Data
3146 drw26
Mail2
Data
NOTE:
1. ENA is HIGH.
Figure 26. Parity Generation Timing when Reading from the Mail2 Register
ODD/
EVEN
CSB LOW
W/RB
SIZ1,
SIZ0
PGB
t
PEPB
MDV
tEN
t
tPOPB
tPEPB
B8, B17,
B26, B35
Generated Parity
Generated Parity
Mail1 Data
Mail1
Data
3146 drw27
NOTE:
1. ENB is HIGH.
Figure 27. Parity Generation Timing when Reading from the Mail1 Register
JANUARY14,2009
30
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT723614CMOSSYNCBIFIFO™WITHBUS-MATCHING
AND BYTE SWAPPING 64 x 36 x 2
5 V
1.1 kΩ
From Output
Under Test
30 pF (1)
680Ω
LOAD CIRCUIT
3 V
3 V
Timing
Input
1.5 V
High-Level
1.5 V
Input
1.5 V
1.5 V
GND
GND
t
S
th
tW
3 V
3 V
Data,
Enable
Input
1.5 V
1.5 V
Low-Level
Input
1.5 V
GND
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Enable
1.5 V
1.5 V
tPZL
GND
≈3 V
tPLZ
3 V
Input
1.5 V
1.5 V
1.5 V
Low-Level
Output
GND
V
OL
tPD
t
PZH
tPD
V
V
OH
OH
In-Phase
Output
1.5 V
1.5 V
High-Level
Output
1.5 V
V
t
PHZ
OL
≈OV
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3146 drw28
NOTE:
1. Includes probe and jig capacitance.
Figure 28. Load Circuit and Voltage Waveforms
COMMERCIALANDINDUSTRIAL
JANUARY14,2009
31
ORDERING INFORMATION
X
XX
X
X
XXXXXX
X
Device Type Power
Speed
Package
Process/
Temperature
Range
Commercial (0°C to +70°C)
Industrial (40°C to +85°C)
BLANK
I(1)
Green
G
Thin Quad Flat Pack (TQFP, PN120-1)
Plastic Quad Flat Pack (PQFP, PQ132-1)
PF
PQF
Commercial Only
Com'l & Ind'l
Clock Cycle Time (t CLK
)
15
20
Speed in Nanoseconds
Low Power
L
64 x 36 x 2 SyncBiFIFO™
723614
3146 drw29
NOTES:
1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Green parts are available. For specific speeds and packages contact your sales office.
DATASHEETDOCUMENTHISTORY
03/05/2002
06/06/2005
01/14/2009
pgs. 1, 8, 9 and 32.
pgs. 1, 2, 3 and 32.
pg. 32.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, Ca 95138
for SALES:
for TECH SUPPORT:
408-360-1753
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
FIFOhelp@idt.com
32
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