723616L20PFG8_技术文档

CMOS TRIPLE BUS SyncFIFO™

WITH BUS-MATCHING AND

BYTE SWAPPING 64 x 36 x 2

IDT723616

• Width can be easily expanded by adding FIFOs

• Auto power down minimizes power dissipation

• Available in a space-saving 128-pin Thin Quad Flatpack (TQFP)

• High performance sub-micron CMOS technology

• Industrial temperature range (–40^oC to +85^oC) is available

• Green parts available, see ordering information

FEATURES:

• Two independent FIFOs (64 X 36 storage capacity each) buffer

data between bidirectional 36-bit port A and two unidirectional

18/9-bit ports (Port B transmits, Port C receives)

• Clock frequencies up to 67 MHz (10 ns access time)

Free-running clock lines for each port: CLKA, CLKB and CLKC,

may be asynchronous or coincident (simultaneous reading and

writing of data is permitted)

DESCRIPTION:

•

IDT Standard timing

TheIDT723616isamonolithic,high-speed,low-power,CMOSTripleBus

SyncFIFO™ (clocked) memory which supports clock frequencies up to 67

MHzandhas readaccess times as fastas 10ns. Twoindependent64x36

dual-portSRAMFIFOsonboardeachchipbufferdatabetweenabidirectional

36-bitbus(PortA)andtwounidirectional18-bitbuses(PortBtransmitsdata,

PortCreceives data.)FIFOdata canbe readoutofports Bandwritteninto

portCusingeither18-bitor9-bitformats.

• Empty flag functions: EFA (synchronized by CLKA) and EFB

(synchronized by CLKB)

• Full flag functions: FFA (synchronized by CLKA) and FFC

(synchronized by CLKC)

• Programmable Almost-Empty and Almost-Full flags; each has

four default offsets (4, 8, 12 and 16)

• Bus sizing of 18-bits (word) and 9-bits (byte) for ports B and C

• Byte order swapping on ports B and C

• Passive parity checking on ports A and C

• Parity generation can be selected for ports A and B

• Master Reset clears data and configures FIFO

Reset(RST)initializesthereadandwritepointerstothefirstlocationofthe

memoryarrayandselectsoneoffourpossibledefaultflagoffsetsettings:4,8,

12 or 16.

EachFIFOhasflagstoindicateemptyandfullconditionsandtwoprogram-

mable flags (Almost-Full and Almost-Empty) to indicate when a selected

FUNCTIONALBLOCKDIAGRAM

CLKA

PGB

Port-A

CSA

Control

W/RA

ENA

Logic

RAM

ARRAY

18

B0 - B17

Parity

check

64 x 36

PEFA

Port-B

Control

Logic

CLKB

RENB

Write

Pointer

Read

Pointer

36

FFA

AFA

Status Flag

Logic

EFB

AEB

FIFO 1

FIFO 2

SWB0

SWB1

SWC0

SWC1

SIZ0

Common

Port

Programmable Flag

Offset Registers

Control

Logic

FS0

FS1

- A35

(B and C)

A

0

SIZ1

EFA

AEA

Status Flag

Logic

FFC

AFC

Read

Pointer

Write

Pointer

36

FIFO2,

FIFO1

Reset/

Control

Logic

Parity

RST

PEFC

Check

ODD/EVEN

RAM

ARRAY

18

C0 - C17

64 x 36

CLKC

Port-C

Control

Logic

WENC

PGA

3520 drw01

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.SyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.

FEBRUARY 2009

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

1

©

DSC-3107/3

IDT723616CMOSTRIPLEBUSSyncFIFO

BUS-MATCHINGANDBYTESWAPPING64x36x2

™WITH

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

This device is a clocked FIFO, which means each port employs a

synchronousinterface.AlldatatransfersthroughaportaregatedtotheLOW-

to-HIGHtransitionofacontinuous(free-running)portclockbyenablesignals.

The clocks for each port are independent of one another and can be

asynchronous or coincident. The enables for each port are arranged to

provide a simple bidirectional interface between microprocessors and/or

buses controlledbyasynchronous interface.

DESCRIPTION(CONTINUED)

numberofwordsisstoredinmemory.DataonPortBcanbeaccessedin18-

bitand9-bitformats.FIFODataonPortCcanbeinputin18-bitand9-bitformats.

Byte-orderswappingonportsBandCispossiblewithanybussizeselection.

ParityischeckedpassivelyonportsAandCandmaybeignoredifnotdesired.

Parity generation can be selected for data read from ports A and B. Two or

more devices can be used in parallel to create wider or deeper FIFO

configurations.

PIN CONFIGURATION

INDEX

1

2

3

4

5

6

7

NC

B8

B7

B6

Vcc

A26

A25

A24

A23

A22

A21

102

101

100

99

B5

98

B4

97

B3

96

8

9

GND

B2

94

GND

A20

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

GND

A9

A8

A7

Vcc

A6

A5

A4

A3

GND

A2

A1

95

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

B1

93

B0

92

C17

91

C16

90

C15

89

C14

88

C13

87

C12

86

C11

85

C10

84

GND

C9

C8

C7

Vcc

C6

C5

C4

C3

83

82

81

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

GND

C2

C1

C0

EFB

AEB

AFC

FFC

A0

EFA

AEA

AFA

FFA

CSA

ENA

RENB

WENC

3520 drw02

TQFP (PK128-1, ORDER CODE: PF)

TOP VIEW

NOTE:

1. NC - No internal connection.

2

IDT723616CMOSTRIPLEBUSSyncFIFO

BUS-MATCHINGANDBYTESWAPPING64x36x2

™

WITH

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

ThisFIFOemploysIDTStandardModetiming;thatistosay,thefirstword totheportclockthatreadsdatafromitsarray. Fourdefaultoffsetsettingsare

writtentoanemptyFIFOisdepositedintothememoryarray.Areadoperation alsoprovided.TheAEAandAEBthresholdcanbesetat4,8,12or16locations

isrequiredtoaccessthatword(alongwithallotherwordsresidinginmemory). fromtheemptyboundaryandtheAFAandAFCthresholdcanbesetat4,8,

Each FIFO has an Empty Flag (EFA and EFB) and a Full Flag (FFA and 12or16locationsfromthefullboundary.Allthesechoicesaremadeusingthe

FFC). EF indicates whether or not the FIFO memory is empty. FF shows FS0 and FS1 inputs during Reset.

whetherthe memoryis fullornot.

EachFIFOhasaprogrammableAlmost-Emptyflag(AEAandAEB)anda awidthexpansionrequiresnoadditional,externalcomponents.

If, atanytime, the FIFOis notactivelyperforminga function, the chipwill

TwoormoreFIFOsmaybeusedinparalleltocreatewiderdatapaths.Such

programmableAlmost-Fullflag(AFAandAFC).AEAandAEBindicatewhen

aselectednumberofwordswrittentoFIFOmemoryachieveapredetermined automatically power down. During the power down state, supply current

"almost-emptystate".AFAandAFCindicatewhenaselectednumberofwords consumption (ICC) is at a minimum. Initiating any operation (by activating

writtentothememoryachieveapredetermined"almost-fullstate".

FFA,FFC,AFAandAFCaretwo-stagesynchronizedtotheportclockthat

writesdataintoitsarray.EFA,EFB,AEA,andAEBaretwo-stagesynchronized arefabricatedusingIDT’shighspeed,submicronCMOStechnology.

controlinputs)willimmediatelytakethedeviceoutofthePowerDownstate.

The IDT723616 are characterized for operation from 0°C to 70°C. They

3

IDT723616CMOSTRIPLEBUSSyncFIFO

BUS-MATCHINGANDBYTESWAPPING64x36x2

™WITH

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PINDESCRIPTION

Symbol

A0-A35

AEA

Name

I/O

O

Description

PortAData

36-bitbidirectionaldataportforsideA.

PortAAlmost-Empty

Flag

ProgrammableAlmost-EmptyflagsynchronizedtoCLKA.ItisLOWwhenthenumberof 36-bit

words in FIFO2 is less than or equal to the value in the offset register, X.

AEB

AFA

AFC

PortBAlmost-Empty

Flag

O

Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of 36-bit

words in FIFO1 is less than or equal to the value in the offset register, X.

PortAAlmost-Full

Flag

ProgrammableAlmost-FullflagsynchronizedtoCLKA.ItisLOWwhenthenumberof36-bitempty

locations inFIFO1is less thanorequaltothe value inthe offsetregister, X.

PortCAlmost-Full

Flag

ProgrammableAlmost-FullflagsynchronizedtoCLKC.ItisLOWwhenthenumberof

36-bitemptylocations inFIFO2is less thanorequaltothe value inthe offsetregister, X.

B0-B17

C0-C17

CLKA

PortBData.

Port-CData

PortAClock

O

I

18-bitoutputdataportforsideB.

18-bitinputdataportforsideC.

I

CLKA is a continuous clock that synchronizes all data transfers through port A and can be

asynchronous or coincident to CLKB and CLKC. EFA, FFA, AFA, and AEA are synchronized

totheLOW-to-HIGHtransitionofCLKA.

CLKB

CLKC

PortBClock

Port-CClock

I

CLKB is a continuous clock that synchronizes all data read from port B and can be asynchronous

or coincident to CLKA and CLKC. Port B byte swapping and data port sizing operations are also

synchronous totheLOW-to-HIGHtransitionofCLKB.EFBandAEBaresynchronizedtothe

LOW-to-HIGHtransitionofCLKB.

CLKCis a continuous clockthatsynchronizes alldata writtentoportCandcanbe asynchronous

orcoincidenttoCLKAandCLKC. FFC and AFC are synchronizedtothe LOW-to-HIGHtransition

ofCLKC.

CSA

EFA

PortAChipSelect

PortAEmptyFlag

I

CSA mustbe LOWtoenable a LOW-to-HIGHtransitionofCLKAtoreadorwrite data onportA.

The A0-A35 outputs are in the high-impedance state whenCSA is HIGH.

EFAissynchronizedtotheLOW-to-HIGHtransitionofCLKA.WhenEFAis LOW,FIFO2is empty,

andreads fromits memoryare disabled. Data canbe readfromFIFO2tothe outputregister

when EFA is HIGH. EFA is forced LOW when the device is reset and is set HIGH by the second

LOW-to-HIGHtransitionofCLKAafterdataisloadedintoemptyFIFO2memory.

O

EFB

PortBEmptyFlag

O

EFBis synchronizedtotheLOW-to-HIGHtransitionofCLKB.WhenEFBis LOW,theFIFO1is

empty, andreads fromits memoryare disabled. Data canbe readfromFIFO1tothe output

register when EFB is HIGH. EFB is forced LOW when the device is reset and is set HIGH by the

secondLOW-to-HIGHtransitionofCLKBafterdataisloadedintoemptyFIFO1memory.

ENA

Port A Enable

I

ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.

FFA

Port A Full Flag

O

FFA is synchronizedtothe LOW-to-HIGHtransitionofCLKA. WhenFFA is LOW, FIFO1is full,

and writes to its memory are disabled. FFA is forced LOW when the device is reset and is set

HIGHbythesecondLOW-to-HIGHtransitionofCLKAafterreset.

FFC

Port C Full Flag

O

FFC is synchronized to the LOW-to-HIGH transition of CLKC. WhenFFC is LOW, FIFO2is full,

and writes to its memory are disabled. FFC is forced LOW when the device is reset and is set

HIGHbythesecondLOW-to-HIGHtransitionofCLKCafterreset.

FS1, FS0 Flag-OffsetSelects

I

The LOW-to-HIGH transition of RST latches the values of FS0 and FS1, which selects oneoffour

presetvaluesfortheAlmost-FullflagandAlmost-Emptyflagoffset.

ODD/

Odd/EvenParity

Select

Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when

ODD/EVEN is LOW.ODD/EVEN alsoselects thetypeofparitygeneratedforeachportifparity

generation is enabled for a read operation.

EVEN

PEFA

Port A Parity Error

Flag

O

When any byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes are organized as

A0-A8, A9-A17, A18-A26, andA27-A35, withthe mostsignificantbitofeachbyte servingas

theparitybit.ThetypeofparitycheckedisdeterminedbythestateoftheODD/EVENinput.

The parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate

parityifparitygenerationis selectedbyPGA.Therefore,ifa mail2 read parity generation is

setup by having W/RA LOW, and PGA HIGH, the PEFA flag is forced HIGH regardless of the

A0-A35inputs.

4

IDT723616CMOSTRIPLEBUSSyncFIFO

BUS-MATCHINGANDBYTESWAPPING64x36x2

™WITH

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PINDESCRIPTION(CONTINUED)

Symbol

Name

I/O

Description

PEFC

Port C Parity Error

Flag

O

When any valid byte applied to terminals B0-B17 fails parity, PEFC is LOW. Bytes are organized

as B0-B8 and B9-B17 with the most significant bit of each byte serving as the parity bit. A byte

is valid when it is used by the bus size selected for Port C. The type of parity checked is

determined by the state of the ODD/ EVEN input.

The parity trees used to check the B0-B17 inputs are shared by the mail 1 register to generate parity if

parity generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by

having WENC LOW, SIZ1 and SIZ0 HIGH, and PGB HIGH, the PEFC flag is forced HIGH

regardless of the state of the B0-B17 inputs.

PGA

PGB

Port A Parity

Generation

I

Parity is generated for data reads from port A when PGA is HIGH. The type of parity generated

is selectedbythe state ofthe ODD/EVEN input. Bytes are organizedas A0-A8, A9-A17, A18-A26,

andA27-A35.Thegeneratedparitybits areoutputinthemostsignificantbitofeachbyte.

Port B Parity

Generation

Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated

is selectedbythe state ofthe ODD/EVEN input.Bytes are organizedas B0-B8 and B9-B17. The

generatedparitybitsareoutputinthemostsignificantbitofeachbyte.

RENB

Port B Read Enable

Reset

I

RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read data on port B.

RST

To resetthedevice,fourLOW-to-HIGHtransitionsofCLKA,fourLOW-to-HIGHtransitionsofCLKB,

andfourLOW-to-HIGHtransitions ofCLKCmustoccurwhileRSTis LOW.This sets theAFA and

AFCflags HIGHandthe EFA,EFB,AEA,AEB,FFA,andFFCflags LOW.TheLOW-to-HIGH

transitionofRSTlatchesthestatusoftheFS1andFS0inputstoselectAlmost-FullandAlmost-

Emptyflagoffsets.

SIZ0, SIZ1 BusSizeSelect

(Ports B and C)

I

The levels on these inputs determine the bus size for ports B and C . These levels must be

stable before Master Reset and must remain static for the duration of FIFO operation. Either

a word or a byte size may be selected for both ports B and C together; the ports cannot be

configuredindependently.

SWB0

SWB1

Port B Byte Swap

Port C Byte Swap

The levels on these inputs select one of four modes of byte-order swapping for Port B. These levels

must be stable before Master Reset and must remain static for the duration of FIFO operation. The

four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order swapping is

possiblewithanybussizeselection.

SWC0

The levels on these inputs select one of four modes of byte-order swapping for Port C. These levels

must be stable before Master Reset and must remain static for the duration of FIFO operation. The

four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order swapping is

possiblewithanybussizeselection.

W/RA

PortAWrite/Read

Select

I

A HIGHselects a write operationanda LOWselects a readoperationonportAfora LOW-to-HIGH

transitionofCLKA.TheA0-A35outputs areinthehigh-impedancestatewhenW/RAis HIGH.

AHIGHselects aPortCwriteoperationforaLOW-to-HIGHtransitionofCLKC.

WENC

PortCWriteEnable

5

IDT723616CMOSTRIPLEBUSSyncFIFO

BUS-MATCHINGANDBYTESWAPPING64x36x2

™

WITH

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

ABSOLUTEMAXIMUMRATINGSOVEROPERATINGFREE-AIRTEMPERATURE

RANGE(UNLESSOTHERWISENOTED)⁽¹⁾

Symbol

Rating

Commercial

–0.5to7

–0.5toVCC+0.5

±20

Unit

V

VCC

SupplyVoltageRange

(2)

VI

InputVoltageRange

V

VO⁽²⁾

OutputVoltageRange

V

IIK

Input Clamp Current, (VI < 0 or VI > VCC)

mA

° C

IOK

Output Clamp Current, (VO < 0 or VO > VCC)

Continuous OutputCurrent, (VO =0toVCC)

ContinuousCurrentThroughVCC orGND

StorageTemperatureRange

±50

IOUT

ICC, IGND

TSTG

±50

±500

–65to150

NOTES:

1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of

the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions

for extended periods may affect device reliability.

2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

Symbol

VCC

VIH

Parameter

SupplyVoltage

Min.

4.5

2

Max.

5.5

—

0.8

–4

Unit

V

HIGH Level Input Voltage

LOW-LevelInputVoltage

HIGH-LevelOutputCurrent

LOW-LevelOutputCurrent

OperatingFree-airTemperature

V

VIL

—

0

V

IOH

mA

° C

IOL

8

TA

70

ELECTRICALCHARACTERISTICSOVERRECOMMENDEDOPERATINGFREE-AIR

TEMPERATURERANGE(UNLESSOTHERWISENOTED)

IDT723616

Commercial & Industrial⁽¹⁾

tA = 15, 20 ns

Parameter

Test Conditions

Min.

2.4

—

Typ.⁽¹⁾

—

4

Max.

—

Unit

V

VOH

VOL

II

VCC = 4.5V, IOH = –4 mA

VCC = 4.5 V, IOL = 8 mA

VCC = 5.5 V, VI = VCC or 0

VCC = 5.5 V, VO = VCC or 0

0.5

±50

1

V

—

µ A

mA

pF

IOZ

—

(3)

ICC

VCC = 5.5 V, IO = 0 mA, VI = VCC or GND

VI = 0, f = 1 MHz

—

CIN

—

COUT

VO = 0, f = 1 MHz

—

8

—

pF

NOTES:

1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.

2. All typical values are at VCC = 5V, TA = 25°C.

3 For additional ICC information, see following page.

6

IDT723616CMOSTRIPLEBUSSyncFIFO

BUS-MATCHINGANDBYTESWAPPING64x36x2

™WITH

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

400

VCC = 5.5V

350

= 1/2

f data

f

s

T

= 25° C

A

VCC = 5V

C

L

= 0 pF

300

VCC = 4.5V

250

200

150

100

50

0

10

20

30

40

50

60

70

80

3520 drw04

fs

⎯ Clock Frequency ⎯ MHz

Figure 1. Typical Characteristics: Supply Current vs Clock Frequency

CALCULATING POWER DISSIPATION

The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT723616 with CLKA and CLKB set to

fs.Alldatainputsanddataoutputschangestateduringeachclockcycletoconsumethehighestsupplycurrent.Dataoutputsweredisconnectedtonormalize

thegraphtoazero-capacitanceload.Oncethecapacitiveleadperdata-outputchannelisknown,thepowerdissipationcanbecalculatedwiththeequation

below.

With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of the IDT723616 can be calculated by:

2

PT = VCC x ICC(f) + Σ(CL x VOH x fo)

where:

CL

fo

VOH

=

outputcapacitanceload

switchingfrequencyofanoutput

outputhighlevelvoltage

When no reads or writes are occurring on the IDT723616, the power dissipated by a single clock (CLKA or CLKB) input running at frequency

fS is calculatedby:

PT=VCC x fS x 0.290 mA/MHz

7

IDT723616CMOSTRIPLEBUSSyncFIFO

BUS-MATCHINGANDBYTESWAPPING64x36x2

™

WITH

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY

VOLTAGE AND OPERATING FREE-AIR TEMPERATURE

(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C; Industrial; VCC = 5.0V 10%,TA = 40°C to +85°C)

Commercial

Com’l & Ind’l⁽¹⁾

IDT723616L20

IDT723616L15

Symbol

fS

Parameter

Clock Frequency, CLKA, CLKB, or CLKC

Min.

–

Max.

Min.

–

Max.

50

–

Unit

MHz

ns

66.7

–

tCLK

tCLKH

tCLKL

tDS

Clock Cycle Time, CLKA, CLKB, or CLKC

15

6

20

8

Pulse Duration, CLKA, CLKB, and CLKC

–

ns

Pulse Duration, CLKA, CLKB, and CLKC

6

–

8

–

ns

Setup Time, A0-A35 before CLKA↑ and C0-C17 before CLKC↑

4

–

5

–

ns

tENS

SetupTime, CSA, W/RA, andENAbefore CLKA↑;RENBbefore CLKB↑;

WENCbeforeCLKC↑

5

–

5

–

ns

tSZS

tSWS

tPGS

Setup Time, SIZ0 and SIZ1 before CLKB↑ and CLKC↑

4

5

4

–

5

7

5

–

ns

SetupTime,SWB0andSWB1beforeCLKB↑,SWCOandSWC1,beforeCLKC↑

SetupTime, ODD/EVEN andPGAbefore CLKA↑;ODD/EVENandPGBbefore

(2)

CLKB↑

(3)

tRSTS

tFSS

tDH

SetupTime,RST LOWbeforeCLKA↑,CLKB↑,orCLKC↑

5

1

–

6

1

–

ns

Setup Time, FS0 and FS1 before RST HIGH

HoldTime, A0-A35afterCLKA↑andC0-C17afterCLKC↑

tENH

HoldTime,CSA,W/RA,andENAafterCLKA↑;RENBafterCLKB↑;WENB

afterCLKC↑

tSZH

tSWH

tPGH

Hold Time, SIZ0 and SIZ1 after CLKB↑ and CLKC↑

2

0

–

2

0

–

ns

HoldTime,SWB0andSWB1afterCLKB↑,SWC0andSWC1afterCLKC↑

HoldTime,ODD/EVEN andPGAafterCLKA↑;ODD/EVENandPGBafter

(2)

CLKB↑

(2)

tRSTH

tFSH

tSKEW1⁽⁴⁾

HoldTime, RSTLOWafterCLKA↑,CLKB↑ orCLKC↑

5

4

8

–

6

4

8

–

ns

Hold Time, FS0 and FS1 after RST HIGH

Skew Time, between CLKA↑ and CLKB↑ for EFB and FFA; between CLKC↑

and CLKA↑ for EFA and FFC

tSKEW2⁽⁴⁾

SkewTime, betweenCLKA↑andCLKB↑ forAEB andAFA;betweenCLKC↑

and CLKA↑ for AEA and AFC

14

–

16

–

ns

NOTES:

1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.

2. Only applies for a clock edge that does a FIFO read.

3. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

4. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationships among CLKA cycle, CLKB cycle and CLKC.

8

IDT723616CMOSTRIPLEBUSSyncFIFO

BUS-MATCHINGANDBYTESWAPPING64x36x2

™

WITH

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

SWITCHINGCHARACTERISTICSOVERRECOMMENDEDRANGESOFSUPPLY

VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30PF

(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C; Industrial; VCC = 5.0V 10%,TA = 40°C to +85°C)

Commercial

Com’l & Ind’l⁽¹⁾

IDT723616L20

IDT723616L15

Symbol

tA

Parameter

Min.

2

Max.

10

Min.

2

Max.

12

Unit

ns

Access Time,CLKA↑toA0-A35andCLKB↑toB0-B17

Propagation Delay Time, CLKA↑ to FFA and CLKC↑ to FFC

PropagationDelayTime, CLKA↑toEFA andCLKB↑to EFB

PropagationDelayTime, CLKA↑toAEA andCLKB↑toAEB

Propagation Delay Time, CLKA↑ to AFA and CLKC↑ to AFC

Propagationdelaytime,CLKB↑toPEFB

tWFF

tREF

2

10

2

12

ns

2

10

2

12

ns

tPAE

2

10

2

12

ns

tPAF

tPPE⁽²⁾

2

10

2

12

ns

2

10

2

12

ns

tPDPE

Propagation Delay Time, A0-A35 valid to PEFA valid; C0-C17 valid to PEFC

valid

2

10

2

11

ns

tPOPE

tPEPE

tEN

Propagation Delay Time, ODD/EVEN to PEFA and PEFC

PropagationDelayTime, W/RAorPGAtoPEFA

2

1

2

10

2

1

2

12

ns

Enable Time, CSA and W/RA LOW to A0-A35 active and RENB HIGH to B0-B17

active

tDIS

Disable Time, CSA orW/RAHIGHtoA0-A35athigh-impedance andRENBLOW

toB0-B17athigh-impedance

1

8

1

9

ns

NOTE:

1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.

2. Only applies when a new port B bus size is implemented by the rising CLKB edge.

9

IDT723616CMOSTRIPLEBUSSyncFIFO

BUS-MATCHINGANDBYTESWAPPING64x36x2

™WITH

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

FIFO WRITE/READ OPERATION

SIGNALDESCRIPTIONS

The state of Port A data A0-A35 outputs is controlled by the Port A chip

select(CSA)andthePortAwrite/readselect(W/RA).TheA0-A35outputsare

inthehigh-impedancestatewheneitherCSAorW/RAisHIGH.TheA0-A35

outputs are active whenbothCSAandW/RAare LOW. Data is loadedinto

FIFO1fromtheA0-A35inputs onaLOW-to-HIGHtransitionofCLKAwhen

CSA is LOW, W/RA is HIGH, ENA is HIGH, and FFA is HIGH. Data is read

fromFIFO2totheA0-A35outputsbyaLOW-to-HIGHtransitionofCLKAwhen

CSAis LOW, W/RAis LOW, ENAis HIGH, andEFAis HIGH(see Table 2).

ThestateofthePortBdata(B0-B17)outputs is controlledbyPortBread

select(RENB). The B0-B17outputs are inthe high-impedance state when

REN is LOW. The B0-B17 outputs are active when REN IS HIGH. Data is

read from FIFO1 to the B0-B17 outputs by a LOW-to-HIGH transition of

CLKB when RENB is HIGH, EFB is HIGH, and either SIZ0 or SIZ1 is LOW

(see Table 3).

RESET

The IDT723616 is reset by taking the reset (RST) input LOW for at least

four Port A clock (CLKA), four Port B clock (CLKB) and four Port C clock

(CLKC) LOW-to-HIGH transitions. The reset input can switch asynchro-

nously to the clocks. A device reset initializes the internal read and write

pointers ofeachFIFOandforces the fullflags (FFA, FFC)LOW, the empty

flags (EFA, EFB) LOW, the Almost-Empty flags (AEA, AEB) LOW and the

Almost-Full flags (AFA, AFC) HIGH. After a reset, FFA is set HIGH after

two LOW-to-HIGH transitions of CLKA and FFC is set HIGH after two

LOW-to-HIGH transitions of CLKC. The device must be reset after power

up before data is written to its memory.

A LOW-to-HIGH transition on the RST input loads the Almost-Full and

Almost-Empty Offset register (X) with the values selected by the flag-

select (FS0, FS1) inputs. The values that can be loaded into the registers

are shown in Table 1.

Data is loaded into FIFO2 from the C0-C17 inputs on a LOW-to-HIGH

transition of CLKC when WENC is HIGH, FFC is HIGH, and either SIZ0 or

SIZ1 is LOW (see Table 4).

ThesetupandholdtimeconstraintstothePortClocksforthePortAchipselect

(CSA) and write/read selects (W/RA, RENB, WENC) are only for enabling

writeandreadoperationsandarenotrelatedtohigh-impedancecontrolofthe

dataoutputs.IfaportenableisLOWduringaclockcycle,thePortChipselect

(forPortA)andwrite/readselect(forallports)canchangestatesduringthe

setupandholdtime windowofthe cycle.

TABLE 1 — FLAG PROGRAMMING

ALMOST-FULL AND

FS1

FS0

RST

ALMOST-EMPTY FLAG

OFFSET REGISTER (X)

H

L

H

L

H

L

↑

16

12

8

4

TABLE 2 — PORT-A ENABLE FUNCTION TABLE

CSA

W/RA

ENA

CLKA

A0-A35Outputs

Port Functions

None

H

X

↑

InHigh-ImpedanceState

Active,FIFO2OutputRegister

L

H

L

None

L

H

FIFO1Write

None

L

X

↑

L

H

FIFO2Read

TABLE 3 — PORT-B ENABLE FUNCTION TABLE

RENB

SIZ1, SIZ0

CLKB

B0-B17Outputs

Port Functions

L

X

InHigh-ImpedanceState

Active,FIFO1OutputRegister

None

(1)

H

OneortheotherLOW

↑

FIFO1read

NOTE:

1. At no time during the operation of the FIFO is it permissible to apply a LOW logic level simultaneously to both SIZ0 and SIZ1, nor is it permissible to apply a HIGH logic level

simultaneously to both these inputs. These state combinations are reserved.

TABLE 4 — PORT-C ENABLE FUNCTION TABLE

WENC

SIZ1, SIZ0

CLKC

C0-C17Inputs

Port Functions

None

L

X

InHigh-ImpedanceState

(1)

H

OneortheotherLOW

↑

FIFO2 write

NOTE:

1. At no time during the operation of the FIFO is it permissible to apply a LOW logic level simultaneously to both SIZ0 and SIZ1, nor is it permissible to apply a HIGH logic level

simultaneously to both these inputs. These state combinations are reserved.

10

IDT723616CMOSTRIPLEBUSSyncFIFO

BUS-MATCHINGANDBYTESWAPPING64x36x2

™WITH

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

SYNCHRONIZED FIFO FLAGS

EachFIFOissynchronizedtoitsPortClockthroughtwoflip-flopstages.This

is done to improve flag reliability by reducing the probability of metastable

location is ready to be written in a minimum of three cycles of the full flag

synchronizingclock.Therefore,afullflagisLOWiflessthantwocyclesofthe

fullflagsynchronizingclockhaveelapsedsincethenextmemorywritelocation

eventsontheoutputwhenCLKAoperatesasynchronouslyrelativetoCLKB hasbeenread.ThesecondLOW-to-HIGHtransitiononthefullflagsynchro-

orCLKC.EFA,AEA,FFA,andAFAaresynchronizedtoCLKA.EFBandAEB

aresynchronizedtoCLKB.FFCandAFCaresynchronizedtoCLKC.Tables

5 and 6 show the relationship of each port flag to FIFO1 and FIFO2.

nizationclockafterthereadsetsthefullflagHIGHandthedatacanbewritten

inthefollowingclockcycle.

ALOW-to-HIGHtransitiononafullflagsynchronizingclockbeginsthefirst

synchronizationcycleofareadiftheclocktransitionoccursattimetSKEW1or

greateraftertheread.Otherwise,thesubsequentclockcyclecanbethefirst

synchronization cycle (see Figure 14 and 15).

EMPTY FLAGS (EFA, EFB)

The empty flag of a FIFO is synchronized to the Port Clock that reads

data from its array. When the empty flag is HIGH, new data can be read

to the FIFO output register. When the empty flag is LOW, the FIFO is

empty and attempted FIFO reads are ignored. When reading FIFO1 with

ALMOST-EMPTY FLAGS (AEA, AEB)

TheAlmost-EmptyflagofaFIFOissynchronizedtothePortClockthatreads

a byte or word size on Port B, EFB is set LOW when the fourth byte or data from its array. The state machine that controls an Almost-Empty flag

second word of the last long word is read.

The read pointer of a FIFO is incremented each time a new word is

monitorsawrite-pointerandaread-pointercomparatorthatindicateswhen

theFIFOSRAMstatusisalmost-empty,almost-empty+1,oralmost-empty+2.

clocked to the output register. The state machine that controls an empty Thealmost-emptystateisdefinedbythevalueoftheAlmost-FullandAlmost-

flagmonitorsawrite-pointerandread-pointercomparatorthatindicateswhen EmptyOffsetregister(X).Thisregisterisloadedwithoneoffourpresetvalues

theFIFOSRAMstatusisempty,empty+1,orempty+2.AwordwrittentoaFIFO duringadevicereset(seeResetabove).AnAlmost-EmptyflagisLOWwhen

canbereadtotheFIFOoutputregisterinaminimumofthreecyclesoftheempty theFIFOcontainsXorlesslongwordsinmemoryandisHIGHwhentheFIFO

flagsynchronizingclock.Therefore,anemptyflagisLOWifawordinmemory contains (X+1) or more long words.

isthenextdatatobesenttotheFIFOoutputregisterandtwocyclesofthePort

ClockthatreadsdatafromtheFIFOhavenotelapsedsincethetimetheword

TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizingclock

arerequiredafteraFIFOwritefortheAlmost-Emptyflagtoreflectthenewlevel

waswritten.TheemptyflagoftheFIFOissetHIGHbythesecondLOW-to- offill.Therefore,theAlmost-EmptyflagofaFIFOcontaining(X+1)ormore

HIGHtransitionofthesynchronizingclock,andthenewdatawordcanberead longwords remains LOWiftwocycles ofthe synchronizingclockhave not

totheFIFOoutputregisterinthefollowingcycle.

ALOW-to-HIGHtransitiononanemptyflagsynchronizingclockbeginsthe

elapsedsincethewritethatfilledthememorytothe(X+1)level.AnAlmost-

Empty flag is set HIGH by the second LOW-to-HIGH transition of the

firstsynchronizationcycleofawriteiftheclocktransitionoccursattimetSKEW1 synchronizingclockaftertheFIFOwritethatfillsmemorytothe(X+1)level.

orgreaterafterthewrite.Otherwise,thesubsequentclockcyclecanbethe

first synchronization cycle (see Figure 12 and 13).

ALOW-to-HIGHtransitionofanAlmost-Emptyflagsynchronizingclockbegins

thefirstsynchronizationcycleifitoccursattimetSKEW2orgreaterafterthe

write that fills the FIFO to (X+1) long words. Otherwise, the subsequent

synchronizingclockcyclecanbethefirstsynchronizationcycle(seeFigure

FULL FLAG (FFA, FFC)

ThefullflagofaFIFOissynchronizedtothePortClockthatwritesdatato 16 and 17).

its array. Whenthe fullflagis HIGH, a memorylocationis free inthe SRAM

toreceivenewdata.NomemorylocationsarefreewhenthefullflagisLOW ALMOST-FULL FLAGS (AFA, AFC)

andattemptedwrites tothe FIFOare ignored.

TheAlmost-FullflagofaFIFOissynchronizedtothePortClockthatwrites

Each time a word is written to a FIFO, the write pointer is incremented. datatoitsarray.ThestatemachinethatcontrolsanAlmost-Fullflagmonitors

The state machine that controls a full flag monitors a write-pointer and a write-pointer and read-pointer comparator that indicates when the FIFO

read-pointercomparatorthatindicateswhentheFIFOSRAMstatusisfull,full- SRAMstatusisalmost-full,almost-full-1,oralmost-full-2.Thealmost-fullstate

1,orfull-2.Fromthe time a wordis readfroma FIFO,the previous memory isdefinedbythevalueoftheAlmost-FullandAlmost-EmptyOffsetregister(X).

TABLE 6 — FIFO2 FLAG OPERATION

TABLE 5 — FIFO1 FLAG OPERATION

Synchronized

to CLKA

Synchronized

to CLKC

Synchronized

to CLKB

Synchronized

to CLKA

Number of 36-Bit

Words in the FIFO2⁽¹

Number of 36-Bit

Words in the FIFO1⁽¹⁾

EFA

L

AEA

AFC

H

FFC

EFB

L

AEB

AFA

H

FFA

0

1 to X

L

H

L

0

1 to X

L

H

L

H

(X+1)to[64–(X+1)]

(64–X)to63

64

H

(X+1)to[64–(X+1)]

(64–X)to63

64

H

L

H

L

H

L

H

L

NOTE:

1. X is the value in the Almost-Empty flag and Almost-Full flag Offset register.

11

IDT723616CMOSTRIPLEBUSSyncFIFO

BUS-MATCHINGANDBYTESWAPPING64x36x2

™

WITH

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

Thisregisterisloadedwithoneoffourpresetvaluesduringadevicereset(see dataportsizeselection.Theorderofthebytesarerearrangedwithinthelong

Resetabove).AnAlmost-FullflagisLOWwhentheFIFOcontains(64-X)or word,butthebitorderwithinthebytes remains constant.

morelongwordsinmemoryandisHIGHwhentheFIFOcontains[64-(X+1)]

or less long words.

TheswapconfigurationcanbeselectedindependentlyforportsBandC.

ThePortBSwapSelectinputs(SWB0andSWB1)areusedtochoosethebyte

TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclock arrangementforPortB.ThePortCSwapSelectinputs(SWC0andSWC1)

arerequiredafteraFIFOreadfortheAlmost-Fullflagtoreflectthenewlevel areusedtochoosethebytearrangementforPortC.Thelevelsappliedtothe

offill.Therefore,theAlmost-FullflagofaFIFOcontaining[64-(X+1)]orless swapselectmustbestaticthroughoutFIFOoperation.Theselevelscanonly

wordsremainsLOWiftwocyclesofthesynchronizingclockhavenotelapsed be changed when the FIFO is idle (no read or write activity) just preceding

sincethereadthatreducedthenumberoflongwordsinmemoryto[64-(X+1)]. Master Reset operation. Figures 3 and 4 are examples of the byte-order

AnAlmost-FullflagissetHIGHbythesecondLOW-to-HIGHtransitionofthe swappingoperationsavailablefor18-bitwords.Performingabyteswapand

synchronizingclockaftertheFIFOreadthatreducesthenumberoflongwords bussizesimultaneouslyforaFIFO1readfirstrearrangesthebytesasshown

in memory to [64-(X+1)]. A LOW-to-HIGH transition of an Almost-Full flag inFigure 3, thenoutputs the bytes as showninFigure 2. Simultaneous bus

synchronizingclockbeginsthefirstsynchronizationcycleifitoccursattime sizing and byte swapping operations for FIFO2 writes first loads the data

tSKEW2 or greater after the read that reduces the number of long words in accordingtoFigure 2, thenswaps the bytes as showninFigure 4whenthe

memoryto[64-(X+1)].Otherwise,thesubsequentsynchronizingclockcycle long word is loaded to FIFO2 RAM.

can be the first synchronization cycle (see Figure 18 and 19).

PARITY CHECKING

BUS SIZING

The Port A inputs (A0-A35) have four parity trees to check the parity of

Both ports B and C, taken together, may be configured for either an 18- incoming(oroutgoing)data;thePortBinputs(B0-B17)havetwoparitytrees

bit word or a 9-bit byte format, thus determining the word width of the data tochecktheparityofoutgoingdata;PortCinputs (C0-C17)havetwoparity

read from FIFO1 or written to FIFO2. Whichever bus size is selected treestochecktheparityofincomingdata.Aparityfailureononeormorebytes

appliestobothportsBandC.Itisnotpossibletoconfigurethebuswidthofports ofthePortAdatabus is reportedbyaLOWlevelontheportparityerrorflag

B and C independently.

(PEFA).Aparityfailureononeormorebytes ofthePortCdatabus thatare

Thelevelsappliedtothebussizeselect(SIZ0,SIZ1)inputsmustbestatic validforthebus sizeimplementationis reportedbyaLOWlevelonthePort

throughoutFIFOoperation.TheselevelscanonlybechangedwhentheFIFO Cparityerrorflag(PEFC).Oddorevenparitycheckingcanbeselected,and

isidle(noreadorwriteactivity)justprecedingMasterResetoperation.The the parityerrorflags canbe ignoredifthis feature is notdesired.

bussizeasselectedusingSIZ0andSIZ1isimplementedaccordingtoFigure

2. Note thatneithera HIGHnora LOWlogiclevelshouldbe appliedtoboth EVEN parity select input. A parity error on one or more valid bytes of a port

SIZ0andSIZ1atthe same time;these states are reserved.

ParitystatusischeckedoneachinputbusaccordingtotheleveloftheODD/

isreportedbyaLOWlevelonthecorrespondingportparityerrorflag(PEFA,

Only36-bitlong-worddataiswrittentoorreadfromthetwoFIFOmemories PEFC)output.PortAbytes are arrangedas A0-A8,A9-A17,A18-A26,and

ontheIDT723616.Bus-matchingoperationsaredoneafterdataisreadfrom A27-A35.PortCbytesarearrangedasC0-C8andC9-C17,anditsvalidbytes

the FIFO1 RAM and before data is written to the FIFO2 RAM.

arethoseusedinaPortCbussizeimplementation.WhenODD/EVENparity

is selected, a port parity error flag (PEFA, PEFC) is LOW if any byte on the

porthas anODD/EVENnumberofLOWlevels appliedtothe bits.

BUS-MATCHING FIFO1 READS

Data is read from the FIFO1 RAM in 36-bit long word increments. Since

Port B can only have a byte or word size, only the first one or two bytes PARITYGENERATION

appear on the selected portion of the FIFO1 output register, with the rest

A HIGH level on the Port A parity generate select (PGA) or Port B parity

of the long word stored in auxiliary registers. In this case, subsequent generateselect(PGB)enablestheIDT723616togenerateparitybitsforport

FIFO1 reads with the same bus size implementation output the rest of the reads from a FIFO. Port A bytes are arranged as A0-A8, A9-A17, A18-26,

long word to the FIFO1 output register in the order shown by Figure 2.

andA27-A35,withthemostsignificantbitofeachbyteusedastheparitybit.

When reading data from FIFO1 in byte format, the unused B0-B17 PortBbytesarearrangedasB0-B8andB9-B17,withthemostsignificantbit

outputs remain inactive but static, with the unused FIFO1 output register ofeachbyteusedastheparitybit.AwritetoaFIFOstoresthelevelsapplied

bits holding the last data value to decrease power consumption.

toallnineinputsofabyteregardlessofthestateoftheparitygenerateselect

(PGA, PGB) inputs. When data is read from a port with parity generation

selected, the lower eight bits of each byte are used to generate a parity bit

BUS-MATCHING FIFO2 WRITES

Data is written to the FIFO2 RAM in 36-bit long word increments. Data accordingtothelevelontheODD/EVENselect.Thegeneratedparitybitsare

can be written to FIFO2 with a byte or word bus size. This action stores the substitutedforthelevelsoriginallywrittentothemostsignificantbitsofeachbyte

initial bytes or words in auxiliary registers. The CLKC rising edge that as the word is read to the data outputs.

writes the fourthbyte orthe secondwordoflongwordtoFIFO2alsostores

Paritybits forFIFOdata are generatedafterthe data is readfromSRAM

the entire long word in FIFO2 RAM. The bytes are arranged in the manner andbeforethedataiswrittentotheoutputregister.Therefore,thePortAparity

shown in Figure 2.

generateselect(PGA)andODD/EVENparityselect(ODD/EVEN)havesetup

and hold time constraints to the Port A clock (CLKA) and the Port B parity

generateselect(PGB)andODD/EVENhavesetupandhold-timeconstraints

BYTE SWAPPING

The byte-order arrangement of data read from FIFO1 or data written to tothePortBclock(CLKB).Thesetimingconstraintsonlyapplyforarisingclock

FIFO2 can be changed synchronous to the rising edge of CLKB. Four edge used to read a new long word to the FIFO output register.

modes of byte-order swapping (including no swap) can be done with any

12

IDT723616CMOSTRIPLEBUSSyncFIFO

BUS-MATCHINGANDBYTESWAPPING64x36x2

™

WITH

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

A35⎯A27 A26⎯A18

A17⎯A9

A8⎯A0

Write to FIFO1/

Read From FIFO2

BYTE ORDER ON PORT A:

D

A

B

C

B17⎯B9

B8⎯B0

C8⎯C0

C17⎯C9

1st: Read

from FIFO1

1st: Write

to FIFO2

SIZ1 SIZ0

B

A

C

D

L

H

B17⎯B9

B8⎯B0

C8⎯C0

C17⎯C9

2nd: Write

to FIFO2

2nd: Read

from FIFO1

A

B

C

D

WORD SIZE

C8⎯C0

C17⎯C9

B17⎯B9

B8⎯B0

SIZ1 SIZ0

1st: Write

to FIFO2

1st: Read

D

A

from FIFO1

H

L

C8⎯C0

B17⎯B9

2nd: Write

to FIFO2

2nd: Read

from FIFO1

C

B

C8⎯C0

B8⎯B0

C17⎯C9

B17⎯B9

3rd: Write

to FIFO2

3rd: Read

from FIFO1

B

C

C8⎯C0

B17⎯B9

4th: Read

from FIFO1

4th: Write

to FIFO2

A

D

3520 fig01

BYTE SIZE

NOTE:

1. At no time during the operation of the FIFO is it permissible to apply a LOW logic level simultaneously to both SIZ0 and SIZ1, nor is it permissible to apply a HIGH logic level

simultaneously to both these inputs. These state combinations are reserved.

Figure 2. Bus Sizing

13

IDT723616CMOSTRIPLEBUSSyncFIFO

BUS-MATCHINGANDBYTESWAPPING64x36x2

™WITH

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

Byte order on Port A:

A26⎯A18

A17⎯A9

A35⎯A27

A8⎯A0

Write to FIFO1

B

A

C

D

B17⎯B9

B8⎯B0

SWB1 SWB0

L

B

A

1st: Read from FIFO1

2nd: Read from FIFO1

C

D

NO SWAP

B17⎯B9

B8⎯B0

SWB1 SWB0

L

H

D

C

1st: Read from FIFO1

2nd: Read from FIFO1

B

A

BYTE SWAP

B17⎯B9

B8⎯B0

SWB1 SWB0

1st: Read from FIFO1

2nd: Read from FIFO1

D

H

L

C

A

B

WORD SWAP

B17⎯B9

B8⎯B0

SWB1 SWB0

1st: Read from FIFO1

2nd: Read from FIFO1

A

H

B

D

C

BYTE-WORD SWAP

3520 fig01a

Figure 3. Port B Byte Swapping (Word Size Example)

14

IDT723616CMOSTRIPLEBUSSyncFIFO

BUS-MATCHINGANDBYTESWAPPING64x36x2

™

WITH

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

A26⎯A18

A17⎯A9

A8⎯A0

A35⎯A27

BYTE ORDER ON PORT A:

Read from FIFO2

B

A

C

D

C17⎯C9

C8⎯C0

SWC1 SWC0

D

C

1st: Write to FIFO2

2nd: Write to FIFO2

L

A

B

NO SWAP

C17⎯C9

C8⎯C0

SWC1 SWC0

A

B

1st: Write to FIFO2

2nd: Write to FIFO2

L

H

D

C

BYTE SWAP

C17⎯C9

C8⎯C0

SWC1 SWC0

A

1st: Write to FIFO2

2nd: Write to FIFO2

B

H

L

C

D

WORD SWAP

C17⎯B9

C8⎯B0

SWC1 SWC0

1st: Write to FIFO2

C

D

H

2nd: Write to FIFO2

A

B

3520 fig01b

BYTE-WORD SWAP

Figure 4. Port C Byte Swapping (Word Size Example)

15

IDT723616CMOSTRIPLEBUSSyncFIFO

BUS-MATCHINGANDBYTESWAPPING64x36x2

™WITH

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

CLKA

CLKB

CLKC

}

tRSTH

t

FSH

t

RSTS

t

FSS

}

RST

FS1,FS0

0,1

t

WFF

t

WFF

FFA

t

REF

EFA

FFB

t

WFF

t

WFF

t

REF

EFB

AEA

AFA

AEB

t

PAE

t

PAF

t

PAE

t

PAF

AFC

3520 drw05

Figure 5. Device Reset Loading the X Register with the Value of Eight

tCLK

tCLKH

tCLKL

CLKA

FFA

CSA

HIGH

t

ENS

t

ENH

tENS

t

ENH

W/RA

tENS

tENH

tENS

tENH

tENS

tENH

ENA

tDH

tDS

(1)

W2⁽¹⁾

No Operation

A0 - A35

W1

ODD/

EVEN

tPDPE

Valid

PEFA

3520 drw06

NOTE:

1. Written to FIFO1.

Figure 6. Port-A Write Cycle Timing for FIFO1

16

IDT723616CMOSTRIPLEBUSSyncFIFO

BUS-MATCHINGANDBYTESWAPPING64x36x2

™WITH

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

CLKC

FFC HIGH

tENH

tENS

WENC

tDH

tDS

C0-C17

ODD/EVEN

tPDPE

PEFC

VALID

3520 drw07

NOTE:

1. PEFC indicates parity error for the following bytes: C17-C9 and C8-C0.

DATA SWAP TABLE FOR WORD WRITES TO FIFO2

SWAP

WRITE

MODE

NO.

DATA WRITTEN TO FIFO2

DATA READ FROM FIFO2

SWC1

SWC0

C17-C9

C8-C0

A35-27

A26-A18

A17-A9

A8-A0

L

1

2

C

A

D

B

A

B

C

D

L

H

L

1

2

B

D

A

C

A

B

C

D

1

2

A

C

B

D

H

1

2

D

B

C

A

Figure 7. Port-C Word Write Cycle Timing for FIFO2

17

IDT723616CMOSTRIPLEBUSSyncFIFO

BUS-MATCHINGANDBYTESWAPPING64x36x2

™WITH

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

CLKC

FFC

HIGH

tENS

tENH

tENS

tENH

WENC

tDS

tDH

C0-C8

ODD/EVEN

PEFC

t

PPE

tPDPE

t

PDPE

t

PDPE

Valid

3520 drw08

Valid

NOTE:

1. PEFC indicates parity error for the following byte: C8—C0.

DATA SWAP TABLE FOR BYTE WRITES TO FIFO2

SWAP

WRITE

MODE

NO.

DATA WRITTEN TO FIFO2

DATA READ FROM FIFO2

A17-A9

SWC1

SWC0

C8-C0

A35-27

A26-A18

A8-A0

1

D

L

2

3

4

C

B

A

B

C

D

1

2

3

4

A

B

C

D

L

H

L

B

D

1

2

3

4

B

A

D

C

1

2

3

4

C

D

A

B

H

Figure 8. Port-C Byte Write Cycle Timing for FIFO2

18

IDT723616CMOSTRIPLEBUSSyncFIFO

BUS-MATCHINGANDBYTESWAPPING64x36x2

™WITH

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

CLKB

EFB HIGH

tENH

tENS

RENB

tPGS

tPGH

PGB,

ODD/

EVEN

tEN

tDIS

tA

Previous Data

B0-B17

3520drw09

DATA SWAP TABLE FOR WORD READS FROM FIFO1

SWAP MODE

SWB0

DATA WRITTEN TO FIFO1

READ

NO.

DATA READ FROM FIFO1

SWB1

A35-A27

A26-A18

A17-A9

A8-A0

D

B17-B9

B8-B0

1

2

A

C

B

D

L

H

L

A

B

C

1

2

D

B

C

A

D

1

2

C

A

D

B

H

D

1

2

B

D

A

C

H

D

Figure 9. Port-B Word Read Cycle Timing for FIFO1

19

IDT723616CMOSTRIPLEBUSSyncFIFO

BUS-MATCHINGANDBYTESWAPPING64x36x2

™WITH

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

CLKB

EFB

HIGH

tENS

tENH

RENB

tPGS

tPGH

t

SZS

tSZH

PGB,

ODD/

EVEN

tDIS

tEN

tA

B0-B8

Previous Data

3520 drw10

NOTE:

1. Unused bytes hold last FIFO1 output register data for byte-size reads.

DATA SWAP TABLE FOR BYTE READS FROM FIFO1

DATA READ

FROM FIFO 1

SWAP MODE

DATA WRITTEN TO FIFO 1

A26-A18

READ

NO.

SWB1

SWB0

A35-A27

A17-A9

A8-A0

B17-B9

1

2

3

4

A

B

C

D

L

A

B

C

D

1

2

3

4

D

C

B

A

H

L

A

C

1

2

3

4

C

D

A

B

H

1

2

3

4

B

A

D

C

H

Figure 10. Port-B Byte Read Cycle Timing for FIFO1

20

IDT723616CMOSTRIPLEBUSSyncFIFO

BUS-MATCHINGANDBYTESWAPPING64x36x2

™WITH

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

tCLK

tCLKH

tCLKL

CLKA

EFA HIGH

CSA

W/RA

tENS

tENH

tENS

tENH

ENA

No Operation

tEN

tA

t

DIS

tA

A0 - A35

Word 1⁽¹⁾

Word 2 ⁽¹⁾

Previous Data

tPGS

tPGH

PGA,

ODD/

EVEN

3520 drw11

NOTE:

1. Read from FIFO2.

Figure 11. Port-A Read Cycle Timing for FIFO2

t

CLK

t

CLKL

t

CLKH

CLKA

CSA LOW

WRA HIGH

tENS

tENH

ENA

FFA

HIGH

tDS

tDH

A0 - A35

W1

t

CLK

(1)

SKEW1

t

CLKH

t

CLKL

1

2

CLKB

t

REF

t

REF

FIFO1 Empty

EFB

tENS

tENH

RENB

tDIS

tEN

tA

B0 -B17

Previous Data

3520 drw12

NOTES:

1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge

and rising CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.

2. Port-B size is word or byte; EFB is set LOW by the last word or byte read from FIFO1, respectively. (The word-size case is shown.)

Figure 12. EFB Flag Timing and First Data Read when FIFO1 is Empty

21

IDT723616CMOSTRIPLEBUSSyncFIFO

BUS-MATCHINGANDBYTESWAPPING64x36x2

™WITH

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

t

^CLKtCLKL

t

CLKH

CLKC

tENS

tENH

WENC

FFC

HIGH

tDH

tDS

tDH

t

DS

Write 1

Write 2

C0 - C17

t

CLK

(1)

SKEW1

tCLKH

t

tCLKL

CLKA

1

2

t

REF

t

REF

EFA

CSA

FIFO2 Empty

LOW

W/RA

tENS

tENH

ENA

tA

A0 -A35

W1

3520 drw13

NOTES:

1. tSKEW1 is the minimum time between a rising CLKC edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKC

edge and rising CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.

2. Port-C size is word or byte; tSKEW1 is referenced to the rising CLKC edge that writes the last word or byte of the long word, respectively. (The word-size case is shown.)

Figure 13. EFA Flag Timing and First Data Read when FIFO2 is Empty

tCLK

tCLKL

tCLKH

CLKB

RENB

tENH

tENS

EFB

HIGH

tDIS

tA

t

EN

B0 - B17

(1)

Previous Word in

FIFO1 Output Register

tSKEW1

tCLK

tCLKH

tCLKL

CLKA

1

2

t

WFF

tWFF

FFA

FIFO1 Full

CSA LOW

WRA HIGH

tENS

tENH

ENA

tDS

tDH

A0 - A35

To FIFO1

3520 drw14

NOTES:

1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB

edge and rising CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown.

2. Port-B size is word or byte; tSKEW1 is referenced from the rising CLKB edge that reads the last word or byte of the long word, respectively. (The word-size case is shown.)

Figure 14. FFA Flag Timing and First Available Write when FIFO1 is Full

22

IDT723616CMOSTRIPLEBUSSyncFIFO

BUS-MATCHINGANDBYTESWAPPING64x36x2

™

WITH

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

tCLK

tCLKH

tCLKL

CLKA

CSA

LOW

W/RA

tENH

tENS

ENA

EFA

HIGH

tA

Previous Word in FIFO2 Output Register

Next Word From FIFO2

A0 - A35

(1)

tSKEW1

t

^CLKtCLKL

tCLKH

CLKC

FFC

1

2

t

WFF

ENH

t

WFF

FIFO2 Full

t

tENS

WENC

C0 - C17

tDS

tDH

tDS

3520 drw15

To FIFO2

NOTES:

1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge

and rising CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown.

2. Port-C size is word or byte; FFC is set LOW by the last word or byte write of the long word, respectively. (The word-size case is shown.)

Figure 15. FFC Flag Timing and First Available Write when FIFO2 is Full

CLKA

tENS

tENH

ENA

(1)

tSKEW2

1

2

CLKB

t

PAE

(X+1) Long Words in FIFO1

ENS ENH

t

PAE

X Long Word in FIFO1

AEB

t

RENB

3520 drw16

NOTES:

1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA

edge and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.

2. FIFO1 Write (CSA = LOW, W/RA = HIGH).

3. Port-B size is word or byte; AEB is set LOW by the last word or byte read of the long word, respectively.

Figure 16. Timing for AEB when FIFO1 is Almost-Empty

CLKC

tENS

tENH

WENC

(1)

t

SKEW2

1

2

CLKA

t

PAE

t

PAE

AEA

X Long Words in FIFO2

^{(X+1) Long Words in FIFO}t²ENH

t

ENS

ENA

3520 drw17

NOTES:

1. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKC edge

and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.

2. FIFO2 read (CSA = LOW, W/RA = LOW).

3. Port-C size is word or byte; tSKEW2 is referenced from the rising CLKC edge that writes the last word or byte of the long word, respectively.

Figure 17. Timing for AEA when FIFO2 is Almost-Empty

23

IDT723616CMOSTRIPLEBUSSyncFIFO

BUS-MATCHINGANDBYTESWAPPING64x36x2

™WITH

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

(1)

tSKEW2

CLKA

1

2

tENH

tPAF

tENS

ENA

tPAF

(64-X) Long Words in FIFO1

tENH

AFA

[64-(X+1)] Long Words in FIFO1

CLKB

tENS

RENB

3520 drw18

NOTES:

1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA

edge and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKB cycle later than shown.

2. FIFO1 Write (CSA = LOW, W/RA = HIGH).

3. Port-B size is word or byte; tSKEW2 is referenced from the last word or byte read of the long word, respectively.

Figure 18. Timing for AFA when FIFO1 is Almost-Full

(1)

tSKEW2

1

2

CLKC

tENH

tPAF

tENS

WENC

tPAF

(64-X) Long Words in FIFO2

tENH

AFC [64-(X+1)] Long Words in FIFO2

CLKA

ENA

tENS

3520drw19

NOTES:

1. tSKEW2 is the minimum time between a rising CLKC edge and a rising CLKA edge for AFC to transition HIGH in the next CLKC cycle. If the time between the rising

CLKC edge and rising CLKA edge is less than tSKEW2, then AFC may transition HIGH one CLKA cycle later than shown.

2. Port-C size is word or byte; AFC is set LOW by the last word or byte read of the long word, respectively.

Figure 19. Timing for AFC when FIFO2 is Almost-Full

ODD/

EVEN

W/RA

PGA

tPOPE

t

PEPE

tPEPE

PEFA

Valid

3520 drw20

Figure 20. ODD/EVEN, W/RA and PGA to PEFA Timing

ODD/

EVEN

tPOPE

PEFC

Valid

3520 drw21

Figure 21. ODD/EVEN to PEFC Timing

24

IDT723616CMOSTRIPLEBUSSyncFIFO

BUS-MATCHINGANDBYTESWAPPING64x36x2

™

WITH

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PARAMETER MEASUREMENT INFORMATION

5 V

1.1 kΩ

From Output

Under Test

30 pF ⁽¹⁾

680Ω

LOAD CIRCUIT

3 V

Timing

Input

1.5 V

High-Level

1.5 V

Input

1.5 V

GND

t

S

th

tW

3 V

Data,

Enable

Input

1.5 V

Low-Level

Input

1.5 V

GND

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATIONS

3 V

Output

Enable

1.5 V

t

PZL

GND

tPLZ

3 V

≈3 V

Input

1.5 V

Low-Level

Output

GND

V

OL

tPD

t

PZH

tPD

V

OH

In-Phase

Output

1.5 V

High-Level

Output

t

PHZ

V

≈OV

OL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

3520 drw22

NOTE:

1. Includes probe and jig capacitance.

Figure 22. Load Circuit and Voltage Waveforms

25

ORDERINGINFORMATION

X

XX

X

XXXXXX

Device Type Power Speed Package

Process/

Temperature

Range

BLANK

I⁽¹⁾

Commercial (0°C to +70°C)

Industrial (40°C to +85°C)

G⁽²⁾

Green

Thin Quad Flat Pack (TQFP, PK128-1)

PF

15

20

Commercial Only

Com'l & Ind'l

Clock Cycle Time (tCLK)

Speed in Nanoseconds

L

Low Power

723616

4 x 36 x 2⎯Triple Bus SyncFIFO

3520 drw23

NOTES:

1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.

2. Green parts available. For specific speeds and packages contact your sales office.

DATASHEETDOCUMENTHISTORY

03/05/2002

02/04/2009

pgs. 1, 6, 8, 9 and 26.

pgs. 1, and 26.

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

for Tech Support:

408-360-1753

email:FIFOhelp@idt.com

800-345-7015 or 408-284-8200

fax: 408-284-2775

www.idt.com

26


型号：	723616L20PFG8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Bi-Directional FIFO, 128X36, 12ns, Synchronous, CMOS, PQFP128 先进先出芯片
文件：	总26页 (文件大小：203K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

723616L20PFG8 [IDT]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E