723631L20PFG [IDT]
FIFO, 512X36, 13ns, Synchronous, CMOS, PQFP120, TQFP-120;
| 型号： | 723631L20PFG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 512X36, 13ns, Synchronous, CMOS, PQFP120, TQFP-120 时钟 先进先出芯片 内存集成电路 |
| 文件： | 总21页 (文件大小：216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS SyncFIFO™
512 x 36
IDT723631
IDT723641
IDT723651
1,024 x 36
2,048 x 36
• Output Ready (OR) and Almost-Empty (AE) flags synchronized
by CLKB
• Available in 132-pin plastic quad flat package (PQFP) or space-
saving 120-pin thin quad flat package (TQFP)
• Industrial temperature range (–40°C to +85°C) is available
• Green parts available, see ordering information
FEATURES:
• Storage capacity:
IDT723631 - 512 x 36
IDT723641 - 1,024 x 36
IDT723651 - 2,048 x 36
• Supports clock frequencies up to 67 MHz
• Fast access times of 11ns
DESCRIPTION:
• Free-running CLKA and CLKB can be asynchronous or coinci-
dent (permits simultaneous reading and writing of data on a
single clock edge)
• Clocked FIFO buffering data from Port A to Port B
• Synchronous read retransmit capability
• Mailbox register in each direction
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor interface control logic
• Input Ready (IR) and Almost-Full (AF) flags synchronized by
CLKA
The IDT723631/723641/723651 is a monolithic high-speed, low-power,
CMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz
and has read access times as fast as 12ns. The 512/1,024/2,048 x 36
dual-port SRAM FIFO buffers data from port A to Port B. The FIFO memory
has retransmit capability, which allows previously read data to be ac-
cessed again. The FIFO has flags to indicate empty and full conditions and
two programmable flags (Almost-Full and Almost-Empty) to indicate when a
selected number of words is stored in memory. Communication between
each port may take place with two 36-bit mailbox registers. Each mailbox
FUNCTIONALBLOCKDIAGRAM
MBF1
Mail 1
Register
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
RAM ARRAY
512 x 36
1,024 x 36
2,048 x 36
Reset
Logic
RST
RTM
36
Read
Pointer
Write
Pointer
RFM
A
0
- A35
B0 - B35
Status Flag
OR
AE
IR
AF
Logic
FS
0
/SD
Flag Offset
Registers
FS /SEN
1
10
CLKB
CSB
W/RB
ENB
MBB
Port-B
Control
Logic
Mail 2
Register
3023 drw01
MBF2
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.TheSyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FEBRUARY 2009
1
©2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-2023/7
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
another and can be asynchronous or coincident. The enables for each
port are arranged to provide a simple interface between microprocessors
and/or buses with synchronous control.
The Input Ready (IR) flag and Almost-Full (AF) flag of the FIFO are
two-stage synchronized to CLKA. The Output Ready (OR) flag and Al-
most-Empty (AE) flag of the FIFO are two-stage synchronized to CLKB.
Offset values for the Almost-Full and Almost-Empty flags of the FIFO can be
programmed from port A or through a serial input.
DESCRIPTION(CONTINUED)
register has a flag to signal when new mail has been stored. Two or more
devices may be used in parallel to create wider data paths. Expansion is
also possible in word depth.
These devices are a clocked FIFO, which means each port employs a
synchronous interface. All data transfers through a port are gated to the
LOW-to-HIGH transition of a continuous (free-running) port clock by en-
able signals. The continuous clocks for each port are independent of one
PINCONFIGURATION
NC
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
NC
NC
B
B
B
B
35
34
33
32
*
A
A
A
A
V
A
A
35
34
33
32
CC
31
30
GND
B
B
B
B
B
B
31
30
29
28
27
26
GND
A
A
A
A
A
A
A
29
28
27
26
25
24
23
V
CC
B
25
B24
GND
B
B
B
B
B
B
23
22
21
20
19
18
GND
98
A
V
A
A
A
A
22
CC
21
20
19
18
97
96
95
GND
94
B
17
16
93
B
92
GND
V
CC
91
A
A
A
A
A
V
A
17
16
15
14
13
CC
12
B
15
14
13
12
90
B
B
B
89
88
87
GND
NC
86
85
NC
84
NC
3023 drw02
* Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
NOTES:
1. NC – No Connection
2. Uses Yamaichi socket IC51-1324-828
PQFP (PQ132-1, ORDER CODE: PQF)
TOP VIEW
2
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PINCONFIGURATION(CONTINUED)
A35
A34
A33
A32
VCC
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
GND
A22
VCC
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
VCC
A12
1
B35
B34
B33
B32
GND
B31
B30
B29
B28
B27
B26
VCC
B25
B24
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
VCC
B15
B14
B13
B12
GND
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
3023 drw03
TQFP (PN120-1, ORDER CODE: PF)
TOP VIEW
NOTE:
1. NC – No Connection
3
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PIN DESCRIPTION
Symbol
A0-A35
AE
Name
I/O
I/O
O
Description
Port-AData
36-bitbidirectionaldataportforsideA.
Almost-Empty
Flag
Programmable flag synchronized to CLKB. It is LOW when the number of words in the FIFO is less than or equal to the value in
theAlmost-Emptyregister(X).
AF
Almost-Full
Flag
O
Programmable flag synchronized to CLKA. It is LOW when the number of empty locations in FIFO is less than or equal to the
valueintheAlmost-FullOffsetregister(Y).
B0-B35
CLKA
Port-BData
I/O
I
36-bitbidirectionaldataportforsideB.
Port-A Clock
CLKAis acontinuous clockthatsynchronizes alldatatransfers throughport-Aandmaybeasynchronous orcoincidenttoCLKB.
IR and AF are synchronous to the LOW-to-HIGH transition of CLKA.
CLKB
CSA
Port-B Clock
I
I
I
CLKBis acontinuous clockthatsynchronizes alldatatransfers throughport-Bandmaybeasynchronous orcoincidenttoCLKA.
OR and AE are synchronous to the LOW-to-HIGH transition of CLKB.
Port-A Chip
Select
CSA mustbe LOWtoenable a LOW-to-HIGHtransitionofCLKAtoreadorwrite data onport-A. The A0-A35outputs are inthe
high-impedance state when CSA is HIGH.
CSB
Port-B Chip
Select
CSB mustbe LOWtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onport-B. The B0-B35outputs are inthe
high-impedance state when CSB is HIGH.
ENA
ENB
Port-AEnable
Port-BEnable
I
I
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B.
FS1/
SEN,
Flag-Offset
Select1/
SerialEnable
FS1/SENandFS0/SDaredual-purposeinputsusedforflagOffsetregisterprogramming.Duringadevicereset,FS1/SENand
FS0/SDselectstheflagoffsetprogrammingmethod.ThreeOffsetregisterprogrammingmethodsareavailable:automatically
loadoneoftwopresetvalues,parallelloadfromportA,andserialload.
FS0/SD
IR
FlagOffset0/
SerialData
WhenserialloadisselectedforflagOffsetregisterprogramming,FS1/SENisusedasanenablesynchronoustotheLOW-to-
HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load the bit present on FS0/SD into the X and Y
registers.ThenumberofbitwritesrequiredtoprogramtheOffsetregistersis18/20/22.ThefirstbitwritestorestheY-register
MSBandthe lastbitwrite stores the X-registerLSB.
InputReady
Flag
O
IR is synchronized to the LOW-to-HIGH transition of CLKA. When IR is LOW, the FIFO is full and writes to its array are
disabled.WhentheFIFOisinretransmitmode,IRindicateswhenthememoryhasbeenfilledtothepointoftheretransmit
dataandpreventsfurtherwrites. IR is set LOW during reset and is set HIGH after reset.
MBA
MBB
MBF1
MBF2
OR
Port-A Mailbox
Select
I
A HIGH level chooses a mailbox register for a port-A read or write operation.
Port-B Mailbox
Select
I
A HIGH level chooses a mailbox register for a port-B read or write operation. When the B0-B35 outputs are active, a HIGH
levelonMBBselects datafromthemail1registerforoutputandaLOWlevelselects FIFOdataforoutput.
Mail1Register
Flag
O
O
O
MBF1 is set LOW by the LOW-to-HIGH transition of CLKA that writes data to the mail1 register. MBF1 is set HIGH by a
LOW-to-HIGH transition of CLKB when a port-B readis selected and MBB is HIGH. MBF1 is set HIGH by a reset.
Mail2Register
Flag
MBF2 is set LOW by the LOW-to-HIGH transition of CLKB that writes data to the mail2 register. MBF2 is set HIGH by a
LOW-to-HIGH transition of CLKA when a port-A read is selected and MBA is HIGH. MBF2 is set HIGH by a reset.
OutputReady
Flag
OR is synchronized to the LOW-to-HIGH transition of CLKB. When OR is LOW, the FIFO is empty and reads are disabled.
Ready data is present in the output register of the FIFO when OR is HIGH. OR is forced LOW during the reset and goes
HIGH on the third LOW-to-HIGH transition of CLKB after a word is loaded to empty memory.
RFM
RST
ReadFrom
Mark
I
I
I
When the FIFO is in retransmit mode, a HIGH on RFM enables a LOW-to-HIGH transition of CLKB to reset the read pointer
tothebeginningretransmitlocationandoutputthefirstselectedretransmitdata.
Reset
To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST
is LOW. The LOW-to-HIGH transition of RST latches the status ofFS0andFS1for AF and AE offset selection.
RTM
Retransmit
Mode
When RTM is HIGH and valid data is present in the FIFO output register (OR is HIGH), a LOW-to-HIGH transition of CLKB
selectsthedataforthebeginningofaretransmitandputstheFIFOinretransmitmode.Theselectedwordremainstheinitial
retransmitpointuntila LOW-to-HIGHtransitionofCLKBoccurs while RTMis LOW, takingthe FIFOoutofretransmitmode.
W/RA
W/RB
Port-AWrite/
ReadSelect
I
I
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH transition of CLKA. The
A0-A35outputs are inthe high-impedance state whenW/RAis HIGH.
Port-BWrite/
ReadSelect
A LOW selects a write operation and a HIGH selects a read operation on port B for a LOW-to-HIGH transition of CLKB. The
B0-B35outputsareinthehigh-impedancestatewhenW/RBisLOW.
4
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ABSOLUTEMAXIMUMRATINGSOVEROPERATINGFREE-AIRTEMPERATURE
RANGE(UNLESSOTHERWISENOTED)(2)
Symbol
Rating
Commercial
Unit
VCC
Supply Voltage Range
Input Voltage Range
Output Voltage Range
–0.5 to 7
V
(2)
VI
–0.5 to VCC+0.5
–0.5 to VCC+0.5
±20
V
VO(2)
IIK
V
Input Clamp Current, (VI < 0 or VI > VCC)
Output Clamp Current, (VO = < 0 or VO > VCC)
Continuous Output Current, (VO = 0 to VCC)
Continuous Current Through VCC or GND
Storage Temperature Range
mA
mA
mA
mA
°C
IOK
±50
IOUT
ICC
±50
±400
TSTG
–65 to 150
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions
for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDEDOPERATINGCONDITIONS
Symbol
VCC
VIH
Parameter
Min.
4.5
2
Max.
5.5
—
0.8
–4
Unit
Supply Voltage
V
HIGH Level Input Voltage
LOW-Level Input Voltage
HIGH-Level Output Current
LOW-Level Output Current
Operating Free-air Temperature
V
VIL
—
—
—
0
V
IOH
mA
mA
°C
IOL
8
TA
70
ELECTRICALCHARACTERISTICSOVERRECOMMENDEDOPERATING
FREE-AIRTEMPERATURERANGE(UNLESSOTHERWISENOTED)
IDT723631
IDT723641
IDT723651
Commercial & Industrial(1)
tA = 15, 20 ns
Parameter
VOH
VOL
Test Conditions
Min.
2.4
—
—
—
—
—
—
—
—
—
—
—
Typ.(2)
—
—
—
—
—
0
Max.
—
0.5
±5
±5
400
—
—
1
Unit
V
VCC = 4.5V,
VCC = 4.5V,
VCC = 5.5V,
VCC = 5.5V,
VCC = 5.5V,
VCC = 5.5V,
IOH = –4 mA
IOL = 8 mA
V
ILI
VI = VCC or 0
VO = VCC or 0
µA
µA
µA
mA
ILO
ICC
VI = VCC –0.2V or 0
One Input at 3.4V,
(3,4)
∆ICC
CSA = VIH
CSB = VIH
CSA = VIL
CSB = VIL
All Other Inputs
A0-A35
B0-B35
A0-A35
B0-35
Other Inputs at VCC or GND
0
—
—
—
4
1
1
CIN
VI = 0,
f = 1 MHz
f = 1 MHZ
—
—
pF
pF
COUT
VO = 0,
8
NOTES:
1. Industrial temperature range product for 20ns is available as a standard device.
2. All typical values are at VCC = 5V, TA = 25°C.
3. This is the supply current when each input is at least one of the specified TTL voltage levels rather than 0V or VCC.
4. For additional ICC information, see the following page.
5
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
250
fdata = 1/2 fS
TA
= 25°C
CL
= 0pF
VCC = 5.5V
200
150
100
50
VCC = 5.0V
VCC= 4.5V
0
0
10
20
30
40
50
60
70
3023 drw04
fS
⎯ Clock Frequency ⎯ MHz
Figure 1. Typical Characteristics: Supply vs Clock Frequency
CALCULATING POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing the FIFO on the IDT723641 with CLKA and CLKB set
to fS. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were disconnected to
normalize the graph to a zero-capacitance load. Once the capacitance load per data-output channel and the number of IDT723631/723641/723651
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
2
PT = VCC x [ICC(f) + (N x ∆ICC x dc)] + Σ(CL x VCC x fO)
where:
N
∆ICC
dc
CL
fO
=
=
=
=
=
number of inputs driven by TTL levels
increase in power supply current for each input at a TTL HIGH level
duty cycle of inputs at a TTL HIGH level of 3.4
output capacitance load
switching frequency of an output
When no reads or writes are occurring on these devices, the power dissipated by a single clock (CLKA or CLKB) input running at frequency fS is
calculated by:
PT = VCC x fS x 0.209 mA/MHz
6
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ACELECTRICALCHARACTERISTICSOVERRECOMMENDEDRANGESOF
SUPPLYVOLTAGEANDOPERATINGFREE-AIRTEMPERATURE
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5.0V ± 10%, TA = -40°C to +85°C)
Commercial
IDT723631L15
IDT723641L15
IDT723651L15
Com’l & Ind’l(1)
IDT723631L20
IDT723641L20
IDT723651L20
Symbol
fS
Parameter
Min.
Max.
Min.
–
Max.
Unit
MHz
ns
ns
Clock Frequency, CLKA or CLKB
–
15
6
6
5
5
7
6
5
9
5
5
0
0
0
0
5
0
0
0
0
9
12
66.7
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
50
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
tCLK
Clock Cycle Time, CLKA or CLKB
20
8
tCLKH
tCLKL
tDS
Pulse Duration, CLKA or CLKB HIGH
Pulse Duration, CLKA or CLKB LOW
8
ns
Setup Time, A0-A35 before CLKA↑and B0-B35 before CLKB↑
Setup Time, ENA to CLKA↑; ENB to CLKB↑
Setup Time, CSA, W/RA, and MBA to CLKA↑; CSB, W/RB and MBB to CLKB↑
Setup Time, RTM and RFM to CLKB↑
6
ns
ns
ns
ns
ns
ns
tENS1
tENS2
tRMS
6
7.5
6.5
6
(2)
tRSTS
tFSS
Setup Time, RST LOW before CLKA↑ or CLKB↑
Setup Time, FS0 and FS1 before RST HIGH
10
6
tSDS(3)
tSENS(3)
tDH
Setup Time, FS0/SD before CLKA↑
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Setup Time, FS1/SEN before CLKA↑
6
Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑
Hold Time, ENA after CLKA↑; ENB after CLKB↑
Hold Time, CSA, W/RA, and MBA after CLKA↑; CSB, W/RB and MBB after CLKB↑
Hold Time, RTM and RFM after CLKB↑
0
tENH1
tENH2
tRMH
tRSTH
tFSH
0
0
0
(2)
Hold Time, RST LOW after CLKA↑ or CLKB↑
6
Hold Time, FS0 and FS1 after RST HIGH
Hold Time, FS1/SEN HIGH after RST HIGH
Hold Time, FS0/SD after CLKA↑
0
(3)
tSPH
0
(3)
tSDH
0
(3)
tSENH
Hold Time, FS1/SEN after CLKA↑
0
tSKEW1(4) Skew Time, between CLKA↑ and CLKB↑ for OR and IR
tSKEW2(4) Skew Time, between CLKA↑and CLKB↑ for AE and AF
11
16
ns
NOTES:
1. Industrial temperature range product for 20ns is available as a standard device.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Only applies when serial load method is used to program flag Offset registers.
4. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
5. Design simulated but not tested (typical values).
7
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
ACELECTRICALCHARACTERISTICS
(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5.0V ± 10%, TA = -40°C to +85°C)
Commercial
Com’l & Ind’l(1)
IDT723631L20
IDT723641L20
IDT723651L20
IDT723631L15
IDT723641L15
IDT723651L15
Symbol
fS
Parameter
Clock Frequency, CLKA or CLKB
Access Time, CLKB↑ to B0-B35
Min.
Max.
Min.
–
Max.
50
Unit
MHz
ns
–
3
1
1
1
1
0
66.7
11
8
tA
3
13
tPIR
Propagation Delay Time, CLKA↑ to IR
Propagation Delay Time, CLKB↑ to OR
Propagation Delay Time, CLKB↑ to AE
Propagation Delay Time, CLKA↑ to AF
1
10
ns
tPOR
tPAE
tPAF
tPMF
8
1
10
ns
8
1
10
ns
8
1
10
ns
Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2
HIGH and CLKB↑ to MBF2 LOW or MBF1 HIGH
8
0
10
ns
tPMR
Propagation Delay Time, CLKA↑ to B0-B35(2) and
3
13.5
3
15
ns
CLKB↑ to A0-A35(3)
tMDV
tRSF
tEN
Propagation Delay Time, MBB to B0-B35 Valid
3
1
2
13
15
12
3
1
2
15
20
13
ns
ns
ns
Propagation Delay Time, RST LOW to AE LOW and AF HIGH
Enable Time, CSA and W/RA LOW to A0-A35 Active and
CSB LOW and W/RB HIGH to B0-B35 Active
tDIS
Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance
and CSB HIGH or W/RB LOW to B0-B35 at high-impedance
1
8
1
10
ns
NOTES:
1. Industrial temperature range product for 20ns is available as a standard device.
2. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
8
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
When the option to program the Offset registers serially is chosen, the
Input Ready (IR) flag remains LOW until all register bits are written. The IR
flag is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit is
loaded to allow normal FIFO operation. Timing diagrams for the serial load
of offset registers can be found in Figure 4.
SIGNALDESCRIPTION
RESET
The IDT723631/723641/723651 is reset by taking the Reset (RST)
input LOW for at least four port-A Clock (CLKA) and four port-B (CLKB)
LOW-to-HIGH transitions. The Reset input may switch asynchronously to
the clocks. A reset initializes the memory read and write pointers and
forces the Input Ready (IR) flag LOW, the Output Ready (OR) flag LOW,
the Almost-Empty (AE) flag LOW, and the Almost-Full (AF) flag HIGH.
Resetting the device also forces the Mailbox Flags (MBF1, MBF2) HIGH.
After a FIFO is reset, its Input Ready flag is set HIGH after at least two
clock cycles to begin normal operation. A FIFO must be reset after power
up before data is written to its memory.
FIFO WRITE/READ OPERATION
The state of the port-A data (A0-A35) outputs is controlled by the port-A
Chip Select (CSA) and the port-A Write/Read select (W/RA). The A0-A35
outputs are in the high-impedance state when either CSA or W/RA is
HIGH. The A0-A35 outputs are active when both CSA and W/RA are
LOW.
Data is loaded into the FIFO from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when CSA and the port-A Mailbox select (MBA) are
LOW, W/RA, the port-A Enable (ENA), and the Input Ready (IR) flag are
HIGH (see Table 2). Writes to the FIFO are independent of any concur-
rent FIFO read (see Figure 5).
The port-B control signals are identical to those of port-A with the excep-
tion that the port-B Write/Read select (W/RB) is the inverse of the port-A
Write/Read select (W/RA). The state of the port-B data (B0-B35) outputs is
controlled by the port-B Chip Select (CSB) and the port-B Write/Read
select (W/RB). The B0-B35 outputs are in the high-impedance state when
either CSB is HIGH or W/RB is LOW. The B0-B35 outputs are active
when CSB is LOW and W/RB is HIGH.
ALMOST-EMPTY FLAG AND ALMOST-FULL FLAG OFFSET
PROGRAMMING
Two registers in these devices are used to hold the offset values for the
Almost-Empty and Almost-Full flags. The Almost-Empty (AE) flag Offset
register is labeled X, and the Almost-Full (AF) flag Offset register is labeled
Y. The Offset register can be loaded with a value in three ways: one of two
preset values are loaded into the Offset registers, parallel load from port A,
or serial load. The Offset register programming mode is chosen by the flag
select (FS1, FS0) inputs during a LOW-to-HIGH transition on the RST
input (See Table 1).
Data is read from the FIFO to its output register on a LOW-to-HIGH
transition of CLKB when CSB and the port-B Mailbox select (MBB) are
LOW, W/RB, the port-B Enable (ENB), and the Output Ready (OR) flag
are HIGH (see Table 3). Reads from the FIFO are independent of any
concurrent FIFO writes (see Figure 6).
The setup- and hold-time constraints to the port clocks for the port Chip
Selects and Write/Read selects are only for enabling write and read op-
erations and are not related to high-impedance control of the data outputs.
If a port Enable is LOW during a clock cycle, the port Chip Select and
Write/Read select may change states during the setup- and hold time
window of the cycle.
When the OR flag is LOW, the next data word is sent to the FIFO output
register automatically by the CLKB LOW-to-HIGH transition that sets the
OR flag HIGH. When OR is HIGH, an available data word is clocked to the
FIFO output register only when a FIFO read is selected by the port-B
Chip Select (CSB), Write/Read select (W/RB), Enable (ENB), and Mailbox
select (MBB).
PRESET VALUES
If the preset value of 8 or 64 is chosen by the FS1 and FS0 inputs at the
time of a RST LOW-to-HIGH transition according to Table 1, the preset
value is automatically loaded into the X and Y registers. No other device
initialization is necessary to begin normal operation, and the IR flag is set
HIGH after two LOW-to-HIGH transitions on CLKA. For relevant Reset and
Preset value loading timing diagrams, see Figure 2.
PARALLEL LOAD FROM PORT A
To program the X and Y registers from port A, the device is reset with
FS0 and FS1 LOW during the LOW-to-HIGH transition of RST. After this
reset is complete, the IR flag is set HIGH after two LOW-to-HIGH transitions
on CLKA. The first two writes to the FIFO do not store data in its memory
but load the Offset registers in the order Y, X. Each Offset register of the
IDT723631, IDT723641, and IDT723651 uses port-A inputs (A8-A0), (A9-
A0), and (A10-A0), respectively. The highest number input is used as the
most significant bit of the binary number in each case. Each register value
can be programmed from 1 to 508 (IDT723631), 1 to 1,020 (IDT723641),
and 1 to 2,044 (IDT723651). After both Offset registers are programmed
from port A, subsequent FIFO writes store data in the SRAM. Timing
diagrams for the parallel load of offset registers can be found in Figure 3.
SYNCHRONIZED FIFO FLAGS
Each IDT723631/723641/723651 FIFO flag is synchronized to its port
Clock through at least two flip-flop stages. This is done to improve the flags’
reliability by reducing the probability of metastable events on their outputs
SERIAL LOAD
TABLE 1 — FLAG PROGRAMMING
To program the X and Y registers serially, the device is reset with FS0/
SD and FS1/SEN HIGH during the LOW-to-HIGH transition of RST. After
this reset is complete, the X and Y register values are loaded bitwise
through the FS0/SD input on each LOW-to-HIGH transition of CLKA that
the FS1/SEN input is LOW. There are 18-, 20-, or 22-bit writes needed to
complete the programming for the IDT723631, IDT723641, or IDT723651,
respectively. The first-bit write stores the most significant bit of the Y regis-
ter, and the last-bit write stores the least significant bit of the X register.
Each register value can be programmed from 1 to 508 (IDT723631), 1 to
1,020 (IDT723641), or 1 to 2,044 (IDT723651).
FS1
FS0
RST
X and Y Registers (1)
H
H
↑
Serial Load
H
L
↑
64
L
H
↑
8
L
L
↑
Parallel Load From Port A
NOTE:
1. X register holds the offset for AE; Y register holds the offset for AF.
9
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
when CLKA and CLKB operate asynchronously to one another. OR and INPUT READY FLAG (IR)
AE are synchronized to CLKB. IR and AF are synchronized to CLKA.
The Input Ready flag of a FIFO is synchronized to the port Clock that
Table 4 shows the relationship of each flag to the number of words stored writes data to its array (CLKA). When the IR flag is HIGH, a memory
in memory.
location is free in the SRAM to write new data. No memory locations are
free when the IR flag is LOW and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, its write pointer is incremented.
OUTPUT READY FLAG (OR)
The Output Ready flag of a FIFO is synchronized to the port Clock that The state machine that controls an IR flag monitors a write-pointer and
reads data from its array (CLKB). When the OR flag is HIGH, new data is read pointer comparator that indicates when the FIFO SRAM status is full,
present in the FIFO output register. When the OR flag is LOW, the previ- full-1, or full-2. From the time a word is read from a FIFO, its previous
ous data word is present in the FIFO output register and attempted FIFO memory location is ready to be written in a minimum of three cycles of
reads are ignored.
CLKA. Therefore, an IR flag is LOW if less than two cycles of CLKA have
A FIFO read pointer is incremented each time a new word is clocked to elapsed since the next memory write location has been read. The second
its output register. The state machine that controls an OR flag monitors a LOW-to-HIGH transition on CLKA after the read sets the Input Ready flag
write-pointer and read-pointer comparator that indicates when the FIFO HIGH, and data can be written in the following cycle.
SRAM status is empty, empty+1, or empty+2. From the time a word is
A LOW-to-HIGH transition on CLKA begins the first synchronization cycle
written to a FIFO, it can be shifted to the FIFO output register in a minimum of a read if the clock transition occurs at time tSKEW1 or greater after the
of three cycles of CLKB. Therefore, an OR flag is LOW if a word in read. Otherwise, the subsequent CLKA cycle may be the first synchroniza-
memory is the next data to be sent to the FIFO output register and three tion cycle (see Figure 8).
CLKB cycles have not elapsed since the time the word was written. The
OR flag of the FIFO remains LOW until the third LOW-to-HIGH transition of ALMOST-EMPTY FLAG (AE)
CLKB occurs, simultaneously forcing the OR flag HIGH and shifting the
word to the FIFO output register.
The Almost-Empty flag of a FIFO is synchronized to the port Clock that
reads data from its array (CLKB). The state machine that controls an AE
A LOW-to-HIGH transition on CLKB begins the first synchronization cycle flag monitors a write-pointer and read-pointer comparator that indicates
of a write if the clock transition occurs at time tSKEW1 or greater after the when the FIFO SRAM status is almost-empty, almost-empty+1, or almost-
write. Otherwise, the subsequent CLKB cycle may be the first synchroniza- empty+2. The almost-empty state is defined by the contents of register X.
tion cycle (see Figure 7).
This register is loaded with a preset value during a FIFO reset, pro-
TABLE 2 — PORT-A ENABLE FUNCTION TABLE
CSA
H
L
W/RA
ENA
MBA
CLKA
A0-A35 Outputs
Port Functions
X
X
X
X
InHigh-Impedance State
In High-Impedance State
In High-Impedance State
In High-Impedance State
Active, Mail2 Register
Active, Mail2 Register
Active, Mail2 Register
Active, Mail2 Register
None
H
L
X
X
None
L
H
H
L
↑
FIFO Write
L
H
H
H
↑
Mail1 Write
L
L
L
L
X
None
L
L
H
L
↑
None
None
L
L
L
H
X
L
L
H
H
↑
Mail2 Read (Set MBF2 HIGH)
TABLE 3 — PORT-B ENABLE FUNCTION TABLE
CSB
H
L
W/RB
ENB
MBB
CLKB
B0-A35 Outputs
InHigh-Impedance State
In High-Impedance State
In High-Impedance State
In High-Impedance State
Active, FIFO Output Register
Active, FIFO Output Register
Active, Mail1 Register
Port Functions
X
X
X
X
None
L
L
X
X
None
L
L
H
L
↑
None
L
L
H
H
↑
Mail2 Write
L
H
L
L
X
None
FIFO read
L
H
H
L
↑
L
H
L
H
X
None
L
H
H
H
↑
Active, Mail1 Register
Mail1 Read (Set MBF1 HIGH)
10
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
grammed from port A, or programmed serially (see Almost-Empty flag and LOW-to-HIGH transition of CLKA begins the first synchronization cycle if it
Almost-Full flag offset programming above). The AE flag is LOW when the occurs at time tSKEW2 or greater after the read that reduces the number of
FIFO contains X or less words and is HIGH when the FIFO contains (X+1) words in memory to [512/1,024/2,048-(Y+1)]. Otherwise, the subsequent
or more words. A data word present in the FIFO output register has been CLKA cycle may be the first synchronization cycle (see Figure 10).
read from memory.
Two LOW-to-HIGH transitions of CLKB are required after a FIFO write SYNCHRONOUS RETRANSMIT
for the AE flag to reflect the new level of fill; therefore, the AE flag of a FIFO
The synchronous retransmit feature of these devices allow FIFO data to
containing (X+1) or more words remains LOW if two cycles of CLKB have be read repeatedly starting at a user-selected position. The FIFO is first
not elapsed since the write that filled the memory to the (X+1) level. An AE put into retransmit mode to select a beginning word and prevent ongoing
flag is set HIGH by the second LOW-to-HIGH transition of CLKB after the FIFO write operations from destroying retransmit data. Data vectors with a
FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition of minimum length of three words can retransmit repeatedly starting at the
CLKB begins the first synchronization cycle if it occurs at time tSKEW2 or selected word. The FIFO can be taken out of retransmit mode at any time
greater after the write that fills the FIFO to (X+1) words. Otherwise, the and allow normal device operation.
subsequent CLKB cycle may be the first synchronization cycle (see Figure
9).
The FIFO is put in retransmit mode by a LOW-to-HIGH transition on
CLKB when the retransmit mode (RTM) input is HIGH and OR is HIGH.
The rising CLKB edge marks the data present in the FIFO output register
as the first retransmit data. The FIFO remains in retransmit mode until a
ALMOST-FULL FLAG (AF)
The Almost-Full flag of a FIFO is synchronized to the port Clock that LOW-to-HIGH transition occurs while RTM is LOW.
writes data to its array (CLKA). The state machine that controls an AF flag
When two or more reads have been done past the initial retransmit
monitors a write-pointer and read-pointer comparator that indicates when word, a retransmit is initiated by a LOW-to-HIGH transition on CLKB when
the FIFO SRAM status is almost-full, almost-full-1, or almost-full-2. The the read-from-mark (RFM) input is HIGH. This rising CLKB edge shifts the
almost-full state is defined by the contents of register Y. This register is first retransmit word to the FIFO output register and subsequent reads can
loaded with a preset value during a FIFO reset, programmed from port A, begin immediately. Retransmit loops can be done endlessly while the FIFO
or programmed serially (see Almost-Empty flag and Almost-Full flag offset is in retransmit mode. RFM must be LOW during the CLKB rising edge that
programming). The AF flag is LOW when the number of words in the FIFO takes the FIFO out of retransmit mode.
is greater than or equal to (512-Y), (1,024-Y), OR (2,048-Y) for the
When the FIFO is put into retransmit mode, it operates with two read
IDT723631, IDT723641, or IDT723651, respectively. The AF flag is HIGH pointers. The current read pointer operates normally, incrementing each
when the number of words in the FIFO is less than or equal to [512-(Y+1)], time a new word is shifted to the FIFO output register and used by the OR
[1,024-(Y+1)], or [2,048-(Y+1)] for the IDT723631, IDT723641, or and AE flags. The shadow read pointer stores the memory location at the
IDT723651, respectively. A data word present in the FIFO output register time the device is put into retransmit mode and does not change until the
has been read from memory.
device is taken out of retransmit mode. The shadow read pointer is used
Two LOW-to-HIGH transitions of CLKA are required after a FIFO read by the IR and AF flags. Data writes can proceed while the FIFO is in
for its AF flag to reflect the new level of fill. Therefore, the AF flag of a FIFO retransmit mode, but AF is set LOW by the write that stores (512-Y), (1,024
containing [512/1,024/2,048-(Y+1)] or less words remains LOW if two cycles - Y), or (2,048 - Y) words after the first retransmit word for the IDT723631,
of CLKA have not elapsed since the read that reduced the number of IDT723641, or IDT723651, respectively. The IR flag is set LOW by the
words in memory to [512/1,024/2,048-(Y+1)]. An AF flag is set HIGH by 512th, 1,024th, or 2,048th write after the first retransmit word for the
the second LOW-to-HIGH transition of CLKA after the FIFO read that IDT723631, IDT723641, or IDT723651, respectively.
reduces the number of words in memory to [512/1,024/2,048-(Y+1)]. A
TABLE 4 — FIFO FLAG OPERATION
(1,2,3)
Number of Words in the FIFO
Synchronized
to CLKB
Synchronized
to CLKA
IDT723631
IDT723641
IDT723651
OR
AE
L
AF
IR
H
H
H
H
L
0
1 to X
0
1 to X
0
1 to X
L
H
H
H
H
H
H
H
L
L
(X+1)to[512-(Y+1)]
(512-Y)to511
512
(X+1)to[1,024-(Y+1)]
(1,024-Y)to1,023
1,024
(X+1)to[2,048-(Y+1)]
(2,048-Y)to2,047
2,048
H
H
H
L
NOTES:
1. X is the Almost-Empty Offset for AE. Y is the Almost-Full Offset for AF.
2. When a word is present in the FIFO output register, its previous memory location is free.
3. Data in the output register does not count as a "word i n FIFO memory". Since in FWFT mode, the first words written to an empty FIFO goes unrequested to the output register
(no read operation necessary), it is not included in the memory count.
11
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
When the FIFO is in retransmit mode and RFM is HIGH, a rising CLKB FIFO for a port data transfer operation. A LOW-to-HIGH transition on
edge loads the current read pointer with the shadow read-pointer value CLKA writes A0-A35 data to the mail1 register when a port-A Write is
and the OR flag reflects the new level of fill immediately. If the retransmit selected by CSA, W/RA, and ENA with MBA HIGH. A LOW-to-HIGH
changes the FIFO status out of the almost-empty range, up to two CLKB transition on CLKB writes B0-B35 data to the mail2 register when a port-B
rising edges after the retransmit cycle are needed to switch AE high (see Write is selected by CSB, W/RB, and ENB with MBB HIGH. Writing data to
Figure 12). The rising CLKB edge that takes the FIFO out of retransmit a mail register sets its corresponding flag (MBF1 or MBF2) LOW.
mode shifts the read pointer used by the IR and AF flags from the shadow Attempted writes to a mail register are ignored while its mail flag is LOW.
to the current read pointer. If the change of read pointer used by IR and
When the port-B data (B0-B35) outputs are active, the data on the bus
AF should cause one or both flags to transmit HIGH, at least two CLKA comes from the FIFO output register when the port-B Mailbox select (MBB)
synchronizing cycles are needed before the flags reflect the change. A input is LOW and from the Mail1 register when MBB is HIGH. Mail2 data is
rising CLKA edge after the FIFO is taken out of retransmit mode is the first always present on the port-A data (A0-A35) outputs when they are active.
synchronizing cycle of IR if it occurs at time tSKEW1 or greater after the The Mail1 register Flag (MBF1) is set HIGH by a LOW-to-HIGH transition
rising CLKB edge (see Figure 13). A rising CLKA edge after the FIFO is on CLKB when a port-B Read is selected by CSB, W/RB, and ENB with
taken out of retransmit mode is the first synchronizing cycle of AF if it occurs MBB HIGH. The Mail2 register Flag (MBF2) is set HIGH by a LOW-to-
at time tSKEW2 or greater after the rising CLKB edge (see Figure 14).
HIGH transition on CLKA when a port-A Read is selected by CSA, W/RA,
and ENA with MBA HIGH. The data in a mail register remains intact after it
is read and changes only when new data is written to the register. Mail
MAILBOX REGISTERS
Two 36-bit bypass registers are on the IDT723631/723641/723651 to Register and Mail Register Flag timing can be found in Figure 15
pass command and control information between port A and port B. The and 16.
Mailbox select (MBA, MBB) inputs choose between a mail register and a
12
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
CLKA
CLKB
tRSTH
t
FSS
t
FSH
t
RSTS
RST
FS1,FS0
0,1
tPIR
tPIR
IR
tPOR
OR
AE
AF
t
RSF
t
RSF
t
RSF
MBF1,
MBF2
3023 drw05
Figure 2. FIFO Reset Loading X and Y with a Preset Value of Eight
CLKA
4
RST
tFSH
tFSS
FS1,FS0
IR
tPIR
tENS1
tENH1
ENA
tDS
tDH
A0 - A35
AF Offset
AE Offset
(X)
First Word
Stored in FIFO
(Y)
3023 drw06
NOTE:
1. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program Offset register on consecutive clock cycles.
Figure 3. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values from Port A
13
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
CLKA
4
RST
tPIR
IR
tSENS
t
FSS
tSENH
tSENS
tSENH
tSPH
FS1/SEN
t
FSH
tSDS
tSDH
t
FSS
tSDH
tSDS
FS0/SD
AF Offset
(Y) MSB
AE Offset
(X) LSB
3023 drw07
NOTE:
1. It is not necessary to program Offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IR is set HIGH.
Figure 4. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values Serially
tCLK
tCLKH
tCLKL
CLKA
IR
HIGH
tENS2
tENH2
CSA
tENS2
tENH2
W/RA
tENS2
tENH2
MBA
ENA
tENS1
tENS1
tENH1
tENH1
tENS1
tENH1
tDH
tDS
No Operation
A0 - A35
W1
W2
3023 drw08
Figure 5. FIFO Write Cycle Timing
tCLK
tCLKH
tCLKL
CLKB
OR HIGH
CSB
W/RB
MBB
ENB
t
ENH1
A
t
ENH1
t
ENH1
t
ENS1
tENS1
tENS1
No Operation
W3
t
DIS
t
t
MDV
t
A
tEN
B0 - B35
W2
W1
3023 drw09
Figure 6. FIFO Read Cycle Timing
14
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
t
t
CLKH CLK tCLKL
CLKA
CSA
LOW
HIGH
W/RA
t
ENS2
t
ENH2
ENH1
MBA
t
ENS1
t
ENA
IR HIGH
A0 - A35
tDH
tDS
W1
t
CLKtCLKL
(1)
SKEW1
t
tCLKH
1
2
3
CLKB
OR FIFO Empty
tPOR
t
POR
CSB
LOW
HIGH
LOW
W/RB
MBB
tENS1
tENH1
ENB
B0 -B35
NOTE:
tA
Old Data in FIFO Output Register
W1
3023 drw10
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output register in three CLKB
cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of OR HIGH and the first word load to the output register may
occur one CLKB cycle later than shown.
Figure 7. OR Flag Timing and First Data Word Fall Through when the FIFO is Empty
15
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tCLK
tCLKH
tCLKL
CLKB
LOW
CSB
HIGH
LOW
W/RB
MBB
tENS1
tENH1
ENB
HIGH
OR
tA
Previous Word in FIFO Output Register
Next Word From FIFO
B0 -B35
(1)
SKEW1
t
tCLK
tCLKH
tCLKL
1
2
CLKA
tPIR
tPIR
FIFO Full
LOW
IR
CSA
HIGH
W/RA
tENH2
tENS2
MBA
tENS1
tENH1
ENA
tDS
tDH
A0 - A35
Write
3023 drw11
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge
and rising CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.
Figure 8. IR Flag Timing and First Available Write when the FIFO is Full
CLKA
tENS1
tENH1
ENA
CLKB
AE
(1)
tSKEW2
1
2
t
PAE
t
PAE
X Word in FIFO
(X+1) Words in FIFO
ENS1
t
ENH1
t
ENB
3023 drw12
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.
2. FIFO write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW).
Figure 9. Timing for AE when FIFO is Almost-Empty
16
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
(1)
tSKEW2
1
2
CLKA
tENH1
tENS1
ENA
t
PAF
t
PAF
(Depth(2) -Y) Words in FIFO
[Depth(2)-(Y+1)] Words in FIFO
AF
CLKB
ENB
tENS1
tENH1
3023 drw13
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge
and rising CLKA edge is less than tSKEW2, then AF may transition HIGH one CLKA cycle later than shown.
2. Depth is 512 for the IDT723631, 1,024 for the IDT723641, and 2,048 for the IDT723651.
3. FIFO write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW).
Figure 10. Timing for AF when FIFO is Almost-Full
CLKB
t
ENH1
RMH
t
ENS1
ENB
RTM
RFM
t
RMS
t
RMS
tRMH
t
t
RMS
tRMH
HIGH
OR
tA
tA
tA
tA
W0
W0
W1
W2
Retransmit from
Selected Position
W1
B0-B35
End Retransmit
Mode
Initiate Retransmit Mode
with W0 as First Word
3023 drw14
NOTE:
1. CSB = LOW, W/RB = HIGH, MBB = LOW. No input enables other than RTM and RFM are needed to control retransmit mode or begin a retransmit. Other enables are shown
only to relate retransmit operations to the FIFO output register.
Figure 11. Retransmit Timing Showing Minimum Retransmit Length
1
CLKB
RTM
RFM
2
HIGH
t
RMS
tRMH
t
PAE
AE
X or fewer words from Empty
(X+1) or more
words from Empty
3023 drw15
NOTE:
1. X is the value loaded in the Almost-Empty flag Offset register.
Figure 12. AE Maximum Latency When Retransmit Increases the Number of Stored Words Above X.
17
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
(1)
tSKEW1
CLKA
IR
1
2
tPIR
FIFO Filled to First Restransmit Word
One or More Write Locations Available
CLKB
t
RMS
tRMH
RTM
3023 drw16
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge
and rising CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.
Figure 13. IR Timing from the End of Retransmit Mode when One or More Write Locations are Available
(1)
tSKEW2
CLKA
1
2
t
PAE
(Depth(2)-Y) or More Words Past First Restransmit Word
AF
(Y+1) or More Write Locations Available
CLKB
tRMH
t
RMS
RTM
3023 drw17
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge
and rising CLKA edge is less than tSKEW2, then AF may transition HIGH one CLKA cycle later than shown.
2. Depth is 512 for the IDT723631, 1,024 for the IDT723641, and 2,048 for the IDT723651.
3. Y is the value loaded in the Almost-Full flag Offset register.
Figure 14. AF Timing from the End of Retransmit Mode when (Y+1) or More Write Locations are Available
CLKA
tENS2
tENH2
CSA
tENH2
tENS2
W/RA
tENS2
tENH2
MBA
tENS2
tENH2
ENA
A0 - A35
CLKB
tDH
t
DS
W1
t
PMF
t
PMF
MBF1
CSB
W/RB
MBB
ENB
tENH1
tENS1
t
PMR
tEN
tDIS
t
MDV
FIFO Output Register
B0 - B35
W1 (Remains valid in Mail1 Register after read)
3023 drw18
Figure 15. Timing for Mail1 Register and MBF1 Flag
18
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
CLKB
t
ENS2
tENH2
tENH2
tENH2
CSB
tENS2
W/RB
tENS2
MBB
ENB
tENH2
tENS2
tDH
tDS
W1
B0 - B35
CLKA
t
PMF
t
PMF
MBF2
CSA
W/RA
MBA
ENA
tENH1
tENS1
tEN
t
PMR
tDIS
W1 (Remains valid in Mail2 Register after read)
A0 - A35
3023 drw19
Figure 16. Timing for Mail2 Register and MBF2 Flag
TRANSFER CLOCK
WRITE
WRITE CLOCK (CLKA)
READ
CLKB
CLKA
READ CLOCK (CLKB)
CHIP SELECT (CSB)
OUTPUT READY (OR)
READ ENABLE (ENB)
CHIP SELECT (CSA)
WRITESELECT(W/RA)
ENA
IR
OR
V
CC
ENB
WRITE ENABLE (ENA)
ALMOST-FULL FLAG (AF)
IDT
IDT
723631
723641
723651
723631
723641
723651
V
CC
CSB
CSA
READSELECT(W/RB)
A0-A35
n
MBB
MBA
ALMOST-EMPTY FLAG (AE)
DATA IN (Dn)
A0-A35
B0-B35
n
n
B0-B35
DATA OUT (Qn)
Qn
Dn
INPUT READY (IR)
MBA
V
CC
V
CC
W/RA
W/RB
MBB
3023 drw20
NOTES:
1. Mailbox feature is not supported in depth expansion applications. (MBA + MBB tie to GND)
2. Transfer clock should be set either to the Write Port Clock (CLKA) or the Read Port Clock (CLKB), whichever is faster.
3. Retransmit feature is not supported in depth expansion applications.
4. The amount of time it takes for OR of the last FIFO in the chain to go HIGH (i.e. valid data to appear on the last FIFO’s outputs) after a word has been written to the first FIFO is the
sum of the delays for each individual FIFO: (N - 1)*(4*transfer clock) + 3*TRCLK, where N is the number of FIFOs in the expansion and TRCLK is the CLKB period.
5. The amount of time is takes for IR of the first FIFO in the chain to go HIGH after a word has been read from the last FIFO is the sum of the delays for each individual FIFO:
(N - 1)*(3*transfer clock) + 2*TWCLK, where N is the number of FIFOs in the expansion and TWCLK is the CLKA period.
Figure 17. Block Diagram of 512 x 36, 1,024 x 36, 2,048 x 36 Synchronous FIFO Memory with
Programmable Flags used in Depth Expansion Configuration
19
IDT723631/723641/723651 CMOS SyncFIFO™
512 x 36, 1,024 x 36 and 2,048 x 36
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PARAMETER MEASUREMENT INFORMATION
5V
1.1 k Ω
From Output
Under Test
30 pF (1)
680 Ω
3 V
3 V
Timing
Input
1.5 V
High-Level
Input
1.5 V
1.5 V
1.5 V
GND
GND
th
t
S
tW
3 V
3 V
Data,
Enable
Input
1.5 V
1.5 V
Low-Level
Input
1.5 V
GND
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Enable
1.5 V
1.5 V
t
PZL
GND
tPLZ
3 V
≈3 V
Input
1.5 V
1.5 V
1.5 V
Low-Level
Output
GND
V
OL
tPD
tPD
t
PZH
V
OH
V
OH
≈OV
In-Phase
Output
1.5 V
1.5 V
High-Level
Output
1.5 V
V
t
PHZ
OL
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3023 drw21
NOTE:
1. Includes probe and jig capacitance
Figure 18. Load Circuit and Voltage Waveforms
20
ORDERINGINFORMATION
X
XXXXX
X
XX
X
X
Process /
Temperature
Range
Device Type
Power Speed
Package
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
Green
G
PF
PQF
Thin Quad Flat Pack (TQFP, PN120-1)
Plastic Quad Flat Pack (PQFP, PQ132-1)
Commercial Only
Commercial and Industrial
15
20
Clock Cycle Time (tCLK
)
Speed in Nanoseconds
L
Low Power
512 x 36 SyncFIFO
1,024 x 36 SyncFIFO
2,048 x 36 SyncFIFO
723631
723641
723651
3023
drw22
NOTES:
1. Industrial temperature range product for 20ns is available as a standard device.
2. Green parts are available, for specific speeds and packages contact your sales office.
DATASHEETDOCUMENTHISTORY
07/25/2001
02/11/2009
pgs. 1, 5, 7, 8 and 21.
pgs. 1 and 21.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
for Tech Support:
408-360-1753
email:FIFOhelp@idt.com
www.idt.com
21
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