723632L15PF8 [IDT]
TQFP-120, Reel;
| 型号： | 723632L15PF8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | TQFP-120, Reel 时钟 先进先出芯片 内存集成电路 |
| 文件： | 总25页 (文件大小：202K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2,
1,024 x 36 x 2
IDT723622
IDT723632
IDT723642
• Available in 132-pin Plastic Quad Flatpack (PQFP) or space-
saving 120-pin Thin Quad Flatpack (TQFP)
• Low-power 0.8-Micron Advanced CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
• Greenpartsavailable,seeorderinginformation
FEATURES:
• Memory storage capacity:
IDT723622
IDT723632
IDT723642
–
–
–
256 x 36 x 2
512 x 36 x 2
1,024 x 36 x 2
• Free-running CLKA and CLKB may be asynchronous or
coincident (simultaneous reading and writing of data on a single
clock edge is permitted)
• Two independent clocked FIFOs buffering data in opposite
directions
DESCRIPTION:
TheIDT723622/723632/723642areamonolithic,high-speed,low-power,
CMOSBidirectionalSyncFIFO(clocked)memorywhichsupports clockfre-
quencies up to 83MHz and have read access times as fast as 8ns. Two
independent256/512/1,024x36dual-portSRAMFIFOsonboardeachchip
buffer data in opposite directions. Communication between each port may
bypasstheFIFOsviatwo36-bitmailboxregisters.Eachmailboxregisterhas
a flag to signal when new mail has been stored.
• Mailbox bypass register for each FIFO
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor Interface Control Logic
• IRA, ORA, AEA, and AFA flags synchronized by CLKA
• IRB, ORB, AEB, and AFB flags synchronized by CLKB
• Supports clock frequencies up to 83MHz
• Fast access times of 8ns
These devices are a synchronous (clocked) FIFO, meaning each port
employsasynchronousinterface.Alldatatransfersthroughaportaregated
totheLOW-to-HIGHtransitionofaportclockbyenablesignals.Theclocksfor
FUNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
CLKA
CSA
W/RA
ENA
MBA
Port-A
Control
Logic
RAM
ARRAY
256 x 36
512 x 36
1,024 x 36
36
FIFO1,
Mail1
Reset
Logic
RST1
Write
Pointer
Read
Pointer
36
Status Flag
Logic
ORB
AEB
IRA
AFA
FIFO 1
Programmable Flag
Offset Registers
FS
0
1
B0 - B35
FS
A
0
- A35
10
FIFO 2
ORA
AEA
Status Flag
Logic
IRB
AFB
36
Read
Pointer
Write
Pointer
36
FIFO2,
Mail2
Reset
Logic
RST2
RAM
ARRAY
256 x 36
512 x 36
CLKB
CSB
Port-B
Control
Logic
1,024 x 36
W/RB
ENB
MBB
Mail 2
Register
3022 drw 01
MBF2
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. SyncBiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
FEBRUARY 2009
COMMERCIAL TEMPERATURE RANGE
1
©
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-3022/5
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
two-stagesynchronizedtotheportclockthatreadsdatafromitsarray.Offset
values for the Almost-Full and Almost-Empty flags of both FIFOs can be
programmedfromPortA.
DESCRIPTION(CONTINUED)
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectionalinterfacebetweenmicroprocessorsand/orbuseswithsynchro-
nouscontrol.
Two or more devices may be used in parallel to create wider data paths.
If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol
inputswillimmediatelytakethedeviceoutofthepowerdownstate.
The723622/723632/723642arecharacterizedforoperationfrom0°Cto
70°C. Industrialtemperature range (-40°Cto+85°C)is availablebyspecial
order.TheyarefabricatedusingIDT'shighspeed,submicronCMOStechnology.
EachFIFOhasaprogrammableAlmost-Emptyflag(AEAandAEB)anda
progammableAlmost-Fullflag(AFAandAFB).AEAandAEBindicatewhen
aselectednumberofwordsremainintheFIFOmemory.AFAandAFBindicate
whenthe FIFOcontains more thana selectednumberofwords.
The Input Ready (IRA, IRB) and Almost-Full (AFA, AFB) flags of a FIFO
aretwo-stagesynchronizedtotheportclockthatwritesdataintoitsarray.The
OutputReady(ORA,ORB)andAlmost-Empty(AEA,AEB)flagsofaFIFOare
PIN CONFIGURATION
NC
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
NC
NC
B
B
B
B
35
34
33
32
A
A
A
A
V
A
A
35
34
33
32
CC
31
30
GND
B
B
B
B
B
B
31
30
29
28
27
26
GND
A
A
A
A
A
A
A
29
28
27
26
25
24
23
V
CC
B
25
B24
GND
B
B
B
B
B
B
23
22
21
20
19
18
GND
98
A
V
A
A
A
A
22
CC
21
20
19
18
97
96
95
GND
94
B
17
16
93
B
92
GND
V
CC
91
A
A
A
A
A
V
A
17
16
15
14
13
CC
12
B
15
14
13
12
90
B
B
B
89
88
87
GND
NC
86
85
NC
84
NC
3022 drw 02
PQFP (PQ132-1, order code: PQF)
TOP VIEW
NOTES:
1. NC – no internal connection
2. Uses Yamaichi socket IC51-1324-828
2
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
PINCONFIGURATION(CONTINUED)
B
B
B
B
35
34
33
32
A
A
A
A
35
34
33
32
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
1
2
3
4
GND
V
CC
5
B
B
B
B
B
B
V
B
B
31
30
29
28
27
26
CC
25
24
A
31
6
A30
7
GND
8
A
A
A
A
A
A
A
29
28
27
26
25
24
23
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GND
B
B
B
B
B
B
23
22
21
20
19
18
GND
A
22
CC
V
A
21
20
19
18
A
A
A
GND
B
B
V
B
B
B
B
17
16
CC
15
14
13
12
GND
A
A
A
A
A
17
16
15
14
13
V
CC
GND
A12
3022 drw 03
TQFP (PN120-1, order code: PF)
TOP VIEW
3
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS
Symbol
Name
I/O
Description
A0-A35
PortAData
I/0
O
36-bitbidirectionaldataportforsideA.
ProgrammableAlmost-EmptyflagsynchronizedtoCLKA.ItisLOWwhenthenumberofwords
AEA
PortAAlmost-
EmptyFlag
(Port A) inFIFO2is less thanorequaltothevalueintheAlmost-EmptyAOffsetregister,X2.
ProgrammableAlmost-EmptyflagsynchronizedtoCLKB.ItisLOWwhenthenumberofwords
(Port B) inFIFO1is less thanorequaltothevalueintheAlmost-EmptyBOffsetregister,X1.
ProgrammableAlmost-FullflagsynchronizedtoCLKA.ItisLOWwhenthenumberofempty
(Port A) locationsinFIFO1islessthanorequaltothevalueintheAlmost-FullAOffsetregister,Y1.
ProgrammableAlmost-FullflagsynchronizedtoCLKB.ItisLOWwhenthenumberofempty
(Port B) locationsinFIFO2islessthanorequaltothevalueintheAlmost-FullBOffsetregister,Y2.
AEB
AFA
AFB
PortBAlmost-
EmptyFlag
O
PortAAlmost-
Full Flag
O
PortBAlmost-
Full Flag
O
B0 - B35
CLKA
PortBData
I/O
I
36-bitbidirectionaldataportforsideB.
PortAClock
CLKAis acontinuous clockthatsynchronizes alldatatransfers throughportAandcanbe
asynchronous or coincident to CLKB. IRA, ORA, AFA, and AEA are all synchronized to the
LOW-to-HIGHtransitionofCLKA.
CLKB
PortBClock
I
CLKBis acontinuous clockthatsynchronizes alldatatransfers throughportBandcanbe
asynchronous or coincident to CLKA. IRB, ORB, AFB, and AEB are synchronized to the LOW-
to-HIGHtransitionofCLKB.
CSA
CSB
Port A Chip
Select
I
I
CSA mustbe LOWtoenable a LOW-to-HIGHtransitionofCLKAtoreadorwrite onportA.
The A0-A35outputs are inthe high-impedance state whenCSA is HIGH.
Port B Chip
Select
CSB mustbe LOWtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data on
portB. The B0-B35outputs are inthe high-impedance state whenCSB is HIGH.
ENA
ENB
PortAEnable
PortBEnable
I
I
I
ENAmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKAtoreadorwrite data onportA.
ENBmustbe HIGHtoenable a LOW-to-HIGHtransitionofCLKBtoreadorwrite data onportB.
FS1, FS0 FlagOffset
Selects
TheLOW-to-HIGHtransitionofaFlFO’s Resetinputlatches thevalues ofFS0andFS1.
If either FS0 or FS1 is HIGH when a Reset goes HIGH, one of three preset values is selected as
theoffsetfortheFlFOsAlmost-FullandAlmost-Emptyflags.IfbothFIFOsareresetsimultaneously
and both FS0 and FS1 are LOW when RST1 and RST2 go HIGH, the first four writes to FIFO1
loadtheAlmost-EmptyandAlmost-FulloffsetsforbothFlFOs.
IRA
Input Ready
Flag
O
IRAissynchronizedtotheLOW-to-HIGHtransitionofCLKA.WhenIRAisLOW,FIFO1isfull
(Port A) and writes to its array are disabled. IRA is set LOW when FIFO1 is reset and is set HIGH on the
secondLOW-to-HIGHtransitionofCLKA afterreset.
IRB
Input Ready
Flag
O
IRBissynchronizedtotheLOW-to-HIGHtransitionofCLKB.WhenIRBisLOW,FIFO2isfull
(Port B) and writes to its array are disabled. IRB is set LOW when FIFO2 is reset and is set HIGH on the
secondLOW-to-HIGHtransitionofCLKBafterreset.
MBA
MBB
MBF1
Port A Mailbox
Select
I
I
A HIGH level on MBA chooses a mailbox register for a port A read or write operation.
WhentheA0-A35outputs areactive,aHIGHlevelonMBAselects datafromthemail2registerfor
outputandaLOWlevelselectsFIFO2outputregisterdataforoutput.
Port B Mailbox
Select
A HIGH level on MBB chooses a mailbox register for a port B read or write operation. When the
B0-B35outputs areactive,aHIGHlevelonMBBselects datafromthemail1registeroroutputand
aLOWlevelselectsFIFO1outputregisterdataforoutput.
Mail1Register
Flag
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1
register.Writes tothemail1registerareinhibitedwhileMBF1is LOW.MBF1is setHIGHby
a LOW-to-HIGH transition of CLKB when a port B read is selected and MBB is HIGH. MBF1 is
set HIGH when FIFO1 is reset.
MBF2
Mail2Register
Flag
O
MBF2issetLOWbyaLOW-to-HIGHtransitionofCLKBthatwritesdata tothemail2register.
Writes tothe mail2registerare inhibitedwhileMBF2 is LOW. MBF2 is setHIGHbya LOW-
to-HIGH transition of CLKA when a port A read is selected and MBA is HIGH. MBF2 is also
set HIGH when FIFO2 is reset.
4
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/O
Description
ORA
OutputReady
Flag
O
ORAissynchronizedtotheLOW-to-HIGHtransitionofCLKA.WhenORAisLOW,FIFO2is
(Port A) emptyandreads fromits memoryaredisabled.Readydatais presentontheoutputregister
of FIFO2 when ORA is HIGH. ORA is forced LOW when FlFO2 is reset and goes HIGH on the
thirdLOW-to-HIGHtransitionofCLKA aftera word is loaded toempty memory.
ORB
RST1
RST2
OutputReady
Flag
O
ORBissynchronizedtotheLOW-to-HIGHtransitionofCLKB.WhenORBisLOW,FlFO1is
(Port B) emptyandreadsfromitsmemoryaredisabled.ReadydataispresentontheoutputregisterofFIFO1
when ORB is HIGH. ORB is forced LOW when FIFO1 is reset and goes HIGH on the third LOW-to-
HIGHtransitionofCLKBafterawordis loadedtoemptymemory.
FIFO1Reset
FIFO2Reset
I
ToresetFIFO1,fourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKB
mustoccurwhileRST1isLOW.TheLOW-to-HIGHtransitionofRST1 latchesthestatusofFS0
andFS1for AFA and AEB offsetselection. FIFO1mustbe resetuponpowerupbefore data is
writtentoitsRAM.
I
ToresetFIFO2,fourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKB
mustoccurwhileRST2isLOW.TheLOW-to-HIGHtransitionofRST2latchesthestatusofFS0
andFS1for AFB and AEA offsetselection. FIFO2mustbe resetuponpowerupbefore data is
writtentoitsRAM.
W/RA
W/RB
PortAWrite/
ReadSelect
I
I
A HIGHselects a write operationanda LOWselects a readoperationonportAfora LOW-to-HIGH
transitionofCLKA.TheA0-A35outputs areintheHIGHimpedancestatewhenW/RAis HIGH.
PortBWrite/
ReadSelect
A LOW selects a write operationanda HIGHselects a readoperationonportBfora LOW-to-HIGH
transitionofCLKB.TheB0-B35outputsareinthehigh-impedancestatewhenW/RBisLOW.
5
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGSOVEROPERATINGFREE-AIR
TEMPERATURERANGE(Unlessotherwisenoted)(1)
Symbol
Rating
Commercial
–0.5to7
–0.5toVCC+0.5
–0.5toVCC+0.5
±20
Unit
V
VCC
SupplyVoltageRange
(2)
VI
InputVoltageRange
V
VO(2)
OutputVoltageRange
V
IIK
Input Clamp Current (VI < 0 or VI > VCC)
Output Clamp Current (VO = < 0 or VO > VCC)
Continuous OutputCurrent(VO =0toVCC)
ContinuousCurrentThroughVCC orGND
StorageTemperatureRange
mA
mA
mA
mA
°C
IOK
IOUT
ICC
±50
±50
±400
TSTG
–65to150
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect
device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIH
Parameter
Min.
4.5
2
Typ.
5.0
—
Max.
5.5
—
0.8
–4
Unit
V
SupplyVoltage(Commercial)
High-LevelInputVoltage(Commercial)
Low-LevelInputVoltage(Commercial)
High-LevelOutputCurrent(Commercial)
Low-LevelOutputCurrent(Commercial)
OperatingTemperature(Commercial)
V
VIL
—
—
—
0
—
V
IOH
—
mA
mA
°C
IOL
—
8
TA
—
70
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-
AIR TEMPERATURE RANGE (Unless otherwise noted)
IDT723622
IDT723632
IDT723642
Commercial
tCLK = 12, 15 ns
Symbol
VOH
VOL
Parameter
OutputLogic"1"Voltage
OutputLogic"0"Voltage
InputLeakageCurrent(AnyInput)
OutputLeakageCurrent
Test Conditions
IOH = –4 mA
Min.
2.4
—
—
—
—
—
—
—
Typ.(2)
—
—
—
—
—
—
4
Max.
—
0.5
±10
±10
8
Unit
V
VCC = 4.5V,
VCC = 4.5V,
VCC = 5.5V,
VCC = 5.5V,
IOL = 8 mA
V
ILI
VI = VCC or 0
µ A
µ A
mA
mA
pF
ILO
VO = VCC or 0
VI = VCC –0.2V or 0V
VI = VCC –0.2V or 0V
f = 1 MHz
ICC2(3)
ICC3(3)
Standby Current (with CLKA & CLKB running) VCC = 5.5V,
StandbyCurrent(noclocksrunning)
InputCapacitance
VCC = 5.5V,
VI = 0,
1
(4)
CIN
—
—
(4)
COUT
OutputCapacitance
VO = 0,
f = 1 MHZ
8
pF
NOTES:
1. Industrial temperature range product is available by special order.
2. All typical values are at VCC = 5V, TA = 25°C.
3. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
4. Characterized values, not currently tested.
6
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723622/723632/723642 with CLKA
andCLKBsettofS. Alldatainputs anddataoutputs changestateduringeachclockcycletoconsumethehighestsupplycurrent. Dataoutputs were
disconnectedtonormalizethegraphtoazerocapacitanceload. Oncethecapacitanceloadperdata-outputchannelandthenumberofthesedevice's
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
WithICC(f) takenfromFigure 1, the maximumpowerdissipation(PT)ofthese FIFOs maybe calculatedby:
2
PT = VCC x [ICC(f) + (N x ∆ICC x dc)] + Σ(CL x VCC X fo)
where:
N
∆ICC
dc
CL
fo
=
=
=
=
=
numberofoutputs=36
increase in power supply current for each input at a TTL HIGH level
duty cycle of inputs at a TTL HIGH level of 3.4 V
outputcapacitanceload
switchingfrequencyofanoutput
300
250
f
data = 1/2 fS
T
A
= 25°C
C
L
= 0pF
VCC = 5.5V
VCC = 5.0V
200
150
100
VCC = 4.5V
50
0
0
10
20
30
40
50
60
70
80
90
3022 drw 03a
fS
⎯ Clock Frequency ⎯ MHz
Figure 1. Typical Characteristics: Supply Current (ICC) vs Clock Frequency (fS)
7
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
TIMINGREQUIREMENTSOVERRECOMMENDEDRANGESOFSUPPLY
VOLTAGEANDOPERATINGFREE-AIRTEMPERATURE
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
Commercial
IDT723622L12
IDT723632L12
IDT723642L12
IDT723622L15
IDT723632L15
IDT723642L15
Symbol
fS
Parameter
Min.
—
12
5
Max.
Min.
Max.
Unit
MHz
ns
Clock Frequency, CLKA or CLKB
83
—
—
—
—
—
—
—
—
—
—
—
15
6
66.7
—
—
—
—
—
—
—
—
—
—
tCLK
tCLKH
tCLKL
tDS
Clock Cycle Time, CLKA or CLKB
Pulse Duration, CLKA or CLKB HIGH
ns
PulseDuration,CLKAandCLKBLOW
5
6
ns
SetupTime, A0-A35before CLKA↑andB0-B35before CLKB↑
SetupTime, CSA andW/RAbefore CLKA↑;CSB andW/RBbefore CLKB↑
Setup Time, ENA and MBA, before CLKA↑;ENBandMBBbefore CLKB↑
SetupTime,RST1orRST2LOWbeforeCLKA orCLKB
Setup Time, FS0 and FS1 before RST1 and RST2 HIGH
HoldTime,A0-A35afterCLKA↑andB0-B35afterCLKB↑
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB,
andMBBafterCLKB↑
Hold Time, RST1 or RST2 LOW after CLKA↑ or CLKB↑
3
4
ns
tENS1
tENS2
tRSTS
tFSS
4
4.5
4.5
5
ns
3
ns
(2)
5
ns
7.5
0.5
0.5
7.5
1
ns
tDH
ns
tENH
1
ns
(2)
tRSTH
tFSH
4
2
—
—
—
—
4
2
—
—
—
—
ns
ns
ns
ns
Hold Time, FS0 and FS1 after RST1 and RST2 HIGH
tSKEW1(3) Skew Time, between CLKA↑ and CLKB↑ for ORA, ORB, IRA, and IRB
tSKEW2(3,4) Skew Time, between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and AFB
7.5
12
7.5
12
NOTES:
1. Industrial temperature range product is available by special order.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
8
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICSOVERRECOMMENDEDRANGESOFSUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30 PF
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
Commercial
IDT723622L12
IDT723632L12
IDT723642L12
IDT723622L15
IDT723632L15
IDT723642L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
tA
Access Time,CLKA↑toA0-A35andCLKB↑toB0-B35
2
2
1
1
1
0
8
8
8
8
8
8
2
2
1
1
1
0
10
8
ns
tPIR
PropagationDelayTime, CLKA↑ toIRAandCLKB↑ toIRB
PropagationDelayTime, CLKA↑toORAandCLKB↑toORB
PropagationDelayTime, CLKA↑toAEA andCLKB↑toAEB
PropagationDelayTime, CLKA↑toAFA andCLKB↑to AFB
ns
ns
ns
ns
ns
tPOR
tPAE
tPAF
tPMF
8
8
8
Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH and
CLKB↑ to MBF2 LOW or MBF1 HIGH
8
tPMR
tMDV
tRSF
PropagationDelayTime, CLKA↑ toB0-B35(2) andCLKB↑ toA0-A35(3)
2
2
1
8
8
2
2
1
10
10
15
ns
ns
ns
Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 Valid
Propagation Delay Time, RST1 LOW to AEB LOW, AFA HIGH, and
MBF1 HIGH, and RST2 LOW to AEA LOW, AFB HIGH, and MBF2 HIGH
10
tEN
tDIS
Enable Time, CSA andW/RALOWtoA0-A35Active andCSB LOW
and W/RB HIGH to B0-B35 Active
2
1
6
6
2
1
10
8
ns
ns
Disable Time, CSA orW/RAHIGHtoA0-A35athigh-impedance and
CSB HIGHor W/RBLOWtoB0-B35athigh-impedance
NOTES:
1. Industrial temperature range product is available by special order.
2. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
9
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
— PARALLEL LOAD FROM PORT A
SIGNALDESCRIPTION
ToprogramtheX1,X2,Y1,andY2registersfromportA,bothFlFOsshould
be reset simultaneously with FS0 and FS1 LOW during the LOW-to-HIGH
transitionoftheResetinputs.Afterthisresetiscomplete,thefirstfourwritesto
FIFO1donotstoredataintheFIFOmemorybutloadtheoffsetregistersinthe
order Y1, X1, Y2, X2. The port A data inputs used by the offset registers are
(A7-A0),(A8-A0),or(A9-A0)fortheIDT723622,IDT723632,orIDT723642,
respectively. Thehighestnumberedinputisusedasthemostsignificantbitof
thebinarynumberineachcase. Validprogrammingvalues fortheregisters
rangesfrom1to252fortheIDT723622;1to508fortheIDT723632;and1to
1,020fortheIDT723642. Afteralltheoffsetregistersareprogrammedfromport
A,theportBInputReadyflag(IRB)issetHIGH,andbothFIFOsbeginnormal
operation.SeeFigure3forrelevantoffsetregisterparallelprogrammingtiming
diagram.
RESET
After power up, a Master Reset operation must be performed by
providingaLOWpulsetoRSTIandRST2simultaneously. Afterwards,theFIFO
memories ofthe IDT723622/723632/723642are resetseparatelybytaking
theirReset(RST1,RST2)inputsLOWforatleastfourportAClock(CLKA)and
fourportBClock(CLKB)LOW-to-HIGHtransitions.TheResetinputscanswitch
asynchronouslytotheclocks.AFIFOresetinitializestheinternalreadandwrite
pointers andforces theInputReadyflag(IRA,IRB)LOW,theOutputReady
flag(ORA,ORB)LOW,theAlmost-Emptyflag(AEA,AEB)LOW,andtheAlmost-
Full flag (AFA, AFB) HIGH. Resetting a FIFO also forces the Mailbox Flag
(MBF1,MBF2)oftheparallelmailboxregisterHIGH.AfteraFlFOisreset,its
InputReadyflagissetHIGHaftertwoclockcyclestobeginnormaloperation.
ALOW-to-HIGHtransitiononaFlFOReset(RST1,RST2)inputlatches
thevalueoftheFlagSelect(FS0,FS1)inputsforchoosingtheAlmost-Fulland
Almost-Empty offset programming method (for details see Table 1, Flag
Programming and the Almost-Empty Flag and Almost-Full Flag Offset
Programmingsectionthatfollows).TherelevantFIFOResettimingdiagramcan
be found in Figure 2.
FIFO WRITE/READ OPERATION
ThestateoftheportAdata(A0-A35)outputsiscontrolledbyportAChip
Select(CSA)andportAWrite/Readselect(W/RA).TheA0-A35outputsare
inthehigh-impedancestatewheneitherCSAorW/RAisHIGH.TheA0-A35
outputs are active whenbothCSA andW/RAare LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
transitionofCLKAwhenCSAis LOW,W/RAis HIGH,ENAis HIGH,MBAis
LOW,andIRAis HIGH. Datais readfromFIFO2totheA0-A35outputs bya
LOW-to-HIGHtransitionofCLKAwhenCSA is LOW, W/RAis LOW,ENAis
HIGH,MBAis LOW,andORAis HIGH(seeTable2).FIFOreads andwrites
onportAareindependentofanyconcurrentportBoperation.WriteandRead
cycle timing diagrams for port A can be found in Figure 4 and 7.
TheportBcontrolsignalsareidenticaltothoseofportAwiththeexception
thattheportBWrite/Readselect(W/RB)istheinverseoftheportAWrite/Read
select(W/RA).ThestateoftheportBdata(B0-B35)outputsiscontrolledbythe
portBChipSelect(CSB)andportBWrite/Readselect(W/RB).TheB0-B35
outputsareinthehigh-impedancestatewheneitherCSBisHIGHorW/RBis
LOW.TheB0-B35outputsareactivewhenCSBisLOWandW/RBisHIGH.
Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH
transitionofCLKBwhenCSBisLOW,W/RBisLOW,ENBisHIGH,MBBisLOW,
andIRBis HIGH. Data is readfromFIFO1tothe B0-B35outputs bya LOW-
to-HIGHtransitionofCLKBwhenCSBisLOW,W/RBisHIGH,ENBisHIGH,
MBBisLOW,andORBisHIGH(seeTable3).FIFOreadsandwritesonport
BareindependentofanyconcurrentportAoperation.WriteandReadcycle
timing diagrams for port B can be found in Figure 5 and 6.
ALMOST-EMPTY FLAG AND ALMOST-FULL FLAG OFFSET PRO-
GRAMMING
Four registers in these devices are used to hold the offset values for
theAlmost-EmptyandAlmost-Fullflags.TheportBAlmost-Emptyflag(AEB)
OffsetregisterislabeledX1andtheportAAlmost-Emptyflag(AEA)Offsetregister
islabeledX2.TheportAAlmost-Fullflag(AFA)OffsetregisterislabeledY1and
theportBAlmost-Fullflag(AFB)OffsetregisterislabeledY2.Theindexofeach
register name corresponds to its FIFO number. The offset registers can be
loadedwithpresetvaluesduringtheresetofaFIFOortheycanbeprogrammed
from port A (see Table 1).
— PRESET VALUES
ToloadtheFIFO'sAlmost-EmptyflagandAlmost-FullflagOffsetregisters
withoneofthethreepresetvalueslistedinTable1,atleastoneoftheflagselect
inputsmustbeHIGHduringtheLOW-to-HIGHtransitionofitsResetinput.For
example,toloadthepresetvalueof64intoX1andY1,FS0andFS1mustbe
HIGHwhenFlFO1Reset(RST1)returnsHIGH.Flagoffsetregistersassociated
withFIFO2areloadedwithoneofthepresetvaluesinthesamewaywithFIFO2
Reset(RST2)toggledsimultaneouslywithFIFO1Reset(RST1).Forpreset
value loadingtimingdiagram, see Figure 2.
TABLE 1 — FLAG PROGRAMMING
FS1
FS0
H
H
L
RST1
RST2
X
↑
X1 AND Y1 REGlSTERS(1)
X2 AND Y2 REGlSTERS(2)
H
↑
64
X
H
X
↑
X
64
H
X
↑
16
X
H
L
X
↑
X
16
L
L
H
H
L
X
↑
8
X
X
↑
X
8
L
↑
ProgrammedfromportA
ProgrammedfromportA
NOTES:
1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
10
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
The setupandholdtime constraints tothe portClocks forthe portChip
AFIFOreadpointeris incrementedeachtime a newwordis clockedto
Selects and Write/Read selects are only for enabling write and read itsoutputregister.ThestatemachinethatcontrolsanOutputReadyflagmonitors
operations and are not related to high-impedance control of the data a write pointer and read pointer comparator that indicates when the FIFO
outputs. If a port enable is LOW during a clock cycle, the port’s Chip Select memorystatusisempty,empty+1,orempty+2.Fromthetimeawordiswritten
and Write/Read select may change states during the setup and hold time toaFIFO,itcanbeshiftedtotheFIFOoutputregisterinaminimumofthreecycles
window of the cycle.
oftheOutputReadyflagsynchronizingclock.Therefore,anOutputReadyflag
When a FIFO Output Ready flag is LOW, the next word written is isLOWifawordinmemoryisthenextdatatobesenttotheFlFOoutputregister
automaticallysenttotheFIFOoutputregisterautomaticallybytheLOW-to-HIGH andthreecyclesoftheportClockthatreadsdatafromtheFIFOhavenotelapsed
transitionoftheportclockthatsetstheOutputReadyflagHIGH. WhentheOutput sincethetimethewordwaswritten.TheOutputReadyflagoftheFIFOremains
ReadyflagisHIGH,subsequentdataisclockedtotheoutputregistersonlywhen LOWuntilthethirdLOW-to-HIGHtransitionofthesynchronizingclockoccurs,
aFIFOreadisselectedusingtheport’sChipSelect,Write/Readselect,Enable, simultaneouslyforcingtheOutputReadyflagHIGHandshiftingthewordtothe
andMailboxselect.
FIFOoutputregister.
ALOW-to-HIGHtransitiononanOutputReadyflagsynchronizingclock
beginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccursat
SYNCHRONIZED FIFO FLAGS
EachFIFOissynchronizedtoitsportclockthroughatleasttwoflip-flop timetSKEW1orgreaterafterthewrite.Otherwise,thesubsequentclockcyclecan
stages. This is done to improve flag-signal reliability by reducing the bethefirstsynchronizationcycle(seeFigures8and9forORAandORBtiming
probability of metastable events when CLKA and CLKB operate asynchro- diagrams).
nouslytooneanother.ORA,AEA,IRA,andAFAaresynchronizedtoCLKA.
ORB, AEB, IRB, and AFB are synchronized to CLKB. Tables 4 and 5 show
INPUT READY FLAGS (IRA, IRB)
the relationshipofeachportflagtoFIFO1andFIFO2.
TheInputReadyflagofaFlFOissynchronizedtotheportclockthatwrites
datatoitsarray.WhentheInputReadyflagisHIGH,amemorylocationisfree
intheFIFOtoreceivenewdata.NomemorylocationsarefreewhentheInput
Readyflagis LOWandattemptedwrites totheFIFOareignored.
EachtimeawordiswrittentoaFIFO,itswritepointerisincremented.The
statemachinethatcontrolsanInputReadyflagmonitorsawritepointerandread
pointercomparatorthatindicateswhentheFlFOmemorystatusisfull,full-1,or
OUTPUTREADYFLAGS(ORA, ORB)
The Output Ready flag of a FIFO is synchronized to the port clock that
reads data from its array. When the Output Ready flag is HIGH, new data
is present in the FIFO output register. When the Output Ready flag is LOW,
thepreviousdatawordispresentintheFIFOoutputregisterandattemptedFIFO
reads are ignored.
TABLE 2 — PORT A ENABLE FUNCTION TABLE
CSA
H
L
W/RA
ENA
MBA
CLKA
Data A (A0-A35) I/O
High-Impedance
Input
PORT FUNCTION
X
X
X
X
X
↑
None
None
H
L
X
L
H
H
L
Input
FIFO1write
Mail1write
L
H
H
H
↑
Input
L
L
L
L
X
↑
Output
None
L
L
H
L
Output
FIFO2 read
None
L
L
L
H
X
↑
Output
L
L
H
H
Output
Mail2 read (set MBF2 HIGH)
TABLE 3 — PORT B ENABLE FUNCTION TABLE
CSB
H
L
W/RB
ENB
MBB
CLKB
Data B (B0-B35) I/O
High-Impedance
Input
PORT FUNCTION
X
X
X
X
X
↑
None
None
L
L
X
L
L
H
L
Input
FIFO2write
Mail2write
L
L
H
H
↑
Input
L
H
L
L
X
↑
Output
None
L
H
H
L
Output
FIFO1 read
None
L
H
L
H
X
↑
Output
L
H
H
H
Output
Mail1 read (set MBF1 HIGH)
11
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
full-2.FromthetimeawordisreadfromaFIFO,itspreviousmemorylocation almost-emptystateisdefinedbythecontentsofregisterX1forAEBandregister
is ready to be written in a minimum of two cycles of the Input Ready flag X2forAEA.TheseregistersareloadedwithpresetvaluesduringaFIFOreset
synchronizing clock. Therefore, an Input Ready flag is LOW if less than two orprogrammedfromportA(seeAlmost-EmptyflagandAlmost-Fullflagoffset
cyclesoftheInputReadyflagsynchronizingclockhaveelapsedsincethenext programmingsection).AnAlmost-EmptyflagisLOWwhenitsFIFOcontains
memorywritelocationhasbeenread.ThesecondLOW-to-HIGHtransitionon Xorless words andis HIGHwhenits FIFOcontains (X+1)ormore words. A
theInputReadyflagsynchronizingClockafterthereadsetstheInputReady data wordpresentinthe FIFOoutputregisterhas beenreadfrommemory.
flagHIGH.
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizing
A LOW-to-HIGH transition on an Input Ready flag synchronizing clock clockarerequiredafteraFIFOwriteforitsAlmost-Emptyflagtoreflectthenew
beginsthefirstsynchronizationcycleofareadiftheclocktransitionoccursat leveloffill.Therefore,theAlmost-FullflagofaFIFOcontaining(X+1)ormore
timetSKEW1orgreateraftertheread.Otherwise,thesubsequentclockcyclecan wordsremainsLOWiftwocyclesofitssynchronizingclockhavenotelapsed
bethefirstsynchronizationcycle(seeFigures10and11fortimingdiagrams). sincethewritethatfilledthememorytothe(X+1)level. AnAlmost-Emptyflag
issetHIGHbythesecondLOW-to-HIGHtransitionofitssynchronizingclockafter
ALMOST-EMPTY FLAGS (AEA, AEB)
theFIFOwritethatfillsmemorytothe(X+1)level.ALOW-to-HIGHtransitionof
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads anAlmost-Emptyflagsynchronizingclockbeginsthefirstsynchronizationcycle
datafromitsarray.ThestatemachinethatcontrolsanAlmost-Emptyflagmonitors ifitoccursattimetSKEW2orgreaterafterthewritethatfillstheFIFOto(X+1)words.
a write pointer and read pointer comparator that indicates when the FIFO Otherwise,thesubsequentsynchronizingclockcyclemaybethefirstsynchro-
memory status is almost-empty, almost-empty+1, or almost-empty+2. The nization cycle. (See Figures 12 and 13).
TABLE 4 — FIFO1 FLAG OPERATION
Synchronized
to CLKB
Synchronized
to CLKA
(1,2)
Number of Words in FIFO
IDT723622(3)
IDT723632(3)
IDT723642(3)
ORB
AEB
AFA
IRA
0
0
0
L
H
H
H
H
L
H
H
H
L
H
H
H
H
L
1toX1
(X1+1)to[256-(Y1+1)]
(256-Y1)to255
256
1toX1
(X1+1)to[512-(Y1+1)]
(512-Y1)to511
512
1toX1
(X1+1)to[1,024-(Y1+1)]
(1,024-Y1)to1,023
1,024
L
H
H
H
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since the first word written to an empty FIFO goes unrequested to the output register (no read
operation necessary), it is not included in the FIFO memory count.
3. X1 is the Almost-Empty offset for FIFO1 used by AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a reset of FIFO1 or
programmed from port A.
TABLE 5 — FIFO2 FLAG OPERATION
Synchronized
to CLKA
Synchronized
to CLKB
(1,2)
Number of Words in FIFO
IDT723622(3)
IDT723632(3)
IDT723642(3)
ORA
AEA
AFB
IRB
0
1toX2
0
1toX2
0
1toX2
L
H
H
H
H
L
H
H
H
L
H
H
H
H
L
L
(X2+1)to[256-(Y2+1)]
(256-Y2)to255
256
(X2+1)to[512-(Y2+1)]
(512-Y2)to511
512
(X2+1)to[1,024-(Y2+1)]
(1,024-Y2)to1,023
1,024
H
H
H
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since the first word written to an empty FIFO goes unrequested to the output register (no read
operation necessary), it is not included in the FIFO memory count.
3. X2 is the Almost-Empty offset for FIFO2 used by AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a reset of FIFO2 or
programmed from port A.
12
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
inmemoryto[256/512/1,024-(Y+1)]. Otherwise,thesubsequentsynchroniz-
ingclockcyclemaybethefirstsynchronizationcycle (seeFigures14and15).
ALMOST-FULL FLAGS (AFA, AFB)
TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwrites
datatoitsarray.ThestatemachinethatcontrolsanAlmost-Fullflagmonitorsa
writepointerandreadpointercomparatorthatindicateswhentheFIFOmemory
statusisalmost-full,almost-full-1,oralmost-full-2.Thealmost-fullstateisdefined
bythecontentsofregisterY1forAFAandregisterY2forAFB.Theseregisters
are loaded with preset values during a FlFO reset or programmed from port
A(seeAlmost-EmptyflagandAlmost-Fullflagoffsetprogrammingsection).
AnAlmost-FullflagisLOWwhenthenumberofwordsinitsFIFOisgreaterthan
orequalto(256-Y),(512-Y),or(1,024-Y)fortheIDT723622,IDT723632,or
IDT723642respectively. AnAlmost-FullflagisHIGHwhenthenumberofwords
inits FIFOis less thanorequalto[256-(Y+1)], [512-(Y+1)], or[1,024-(Y+1)]
fortheIDT723622,IDT723632,orIDT723642respectively. Notethatadata
wordpresentinthe FIFOoutputregisterhas beenreadfrommemory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclock
arerequiredafteraFIFOreadforitsAlmost-Fullflagtoreflectthenewlevelof
fill.Therefore,theAlmost-FullflagofaFIFOcontaining[256/512/1,024-(Y+1)]
or less words remains LOW if two cycles of its synchronizing clock have not
elapsedsincethereadthatreducedthenumberofwordsinmemoryto[256/
512/1,024-(Y+1)]. AnAlmost-FullflagissetHIGHbythesecondLOW-to-HIGH
transitionofitssynchronizingclockaftertheFIFOreadthatreducesthenumber
ofwordsinmemoryto[256/512/1,024-(Y+1)]. ALOW-to-HIGHtransitionofan
Almost-Fullflagsynchronizingclockbeginsthefirstsynchronizationcycleifit
occursattimetSKEW2orgreaterafterthereadthatreducesthenumberofwords
MAILBOX REGISTERS
Each FIFO has a 36-bit bypass register to pass command and control
information between port A and port B without putting it in queue. The
Mailbox select (MBA, MBB) inputs choose between a mail register and a
FIFOfora portdata transferoperation. ALOW-to-HIGHtransitiononCLKA
writesA0-A35datatothemail1registerwhenaportAWriteisselectedbyCSA,
W/RA,andENAandwithMBAHIGH.ALOW-to-HIGHtransitiononCLKBwrites
B0-B35datatothemail2registerwhenaportBWriteisselectedbyCSB,W/
RB, and ENB and with MBB HIGH. Writing data to a mail register sets its
correspondingflag(MBF1orMBF2)LOW.Attemptedwritestoamailregister
areignoredwhilethemailflagis LOW.
Whendataoutputs ofaportareactive,thedataonthebus comes from
theFIFOoutputregisterwhentheportMailboxselectinputisLOWandfrom
the mail register when the port-mailbox select input is HIGH. The Mail1
RegisterFlag(MBF1)issetHIGHbyaLOW-to-HIGHtransitiononCLKBwhen
aportBReadisselectedbyCSB,W/RB,andENBandwithMBBHIGH.The
Mail2RegisterFlag(MBF2)issetHIGHbyaLOW-to-HIGHtransitiononCLKA
whenaportAreadisselectedbyCSA,W/RA,andENAandwithMBAHIGH.
Thedatainamailregisterremainsintactafteritisreadandchangesonlywhen
newdataiswrittentotheregister.FormailregisterandMailRegisterflagtiming
diagrams, see Figure 16 and 17.
13
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
CLKB
tRSTH
t
RSTS
t
FSS
tFSH
RST1
FS1,FS0
IRA
0,1
tPIR
tPIR
tPOR
ORB
AEB
AFA
t
RSF
RSF
t
tRSF
MBF1
3022 drw 04
NOTE:
1. FIFO2 is reset in the same manner to load X2 and Y2 with a preset value.
Figure 2. FIFO1 Reset and Loading X1 and Y1 with a Preset Value of Eight(1)
CLKA
1
2
4
t
FSS
RST1,
RST2
tFSH
FS1,FS0
0,0
tPIR
IRA
(1)
SKEW1
tENS2
tENH
t
ENA
tDH
tDS
A0 - A35
CLKB
First Word to FIFO1
AFA Offset
AEB Offset
AFB Offset
AEA Offset
(Y1)
(X1)
(Y2)
(X2)
1
2
tPIR
IRB
3022 drw 05
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and
rising edge of CLKB is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown.
2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles.
Figure 3. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
14
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
IRA HIGH
tENS1
tENH
CSA
t
ENS1
t
ENH
ENH
ENH
W/RA
tENS2
t
MBA
tENS2
tENS2
t
tENH
tENS2
tENH
ENA
tDH
tDS
(1)
W2(1)
No Operation
A0 - A35
W1
3022 drw 06
NOTE:
1. Written to FIFO1.
Figure 4. Port A Write Cycle Timing for FIFO1
tCLK
tCLKH
tCLKL
CLKB
IRB
HIGH
tENS1
tENH
CSB
tENS1
tENH
W/RB
MBB
ENB
t
ENS2
t
ENH
t
ENS2
tENS2
t
ENH
tENS2
tENH
tENH
tDH
tDS
(1)
W2(1)
B0 - B35
No Operation
W1
3022 drw 07
NOTE:
1. Written to FIFO2.
Figure 5. Port B Write Cycle Timing for FIFO2
15
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
ORB HIGH
CSB
W/RB
MBB
ENB
tENS2
tENS2
tENH
tENH
tENH
tENS2
No Operation
W3(1)
t
DIS
t
MDV
tA
tA
tEN
W2(1)
W1(1)
B0 - B35
3022 drw 08
NOTE:
1. Read From FIFO1.
Figure 6. Port B Read Cycle Timing for FIFO1
tCLK
tCLKH
tCLKL
CLKA
ORA
CSA
W/RA
MBA
ENA
t
ENS2
tENH
t
ENH
t
ENH
tENS2
t
ENS2
No Operation
W3(1)
t
DMV
tDIS
t
(1)
A
t
A
tEN
W1
W2(1)
A0 - A35
3022 drw 09
NOTE:
1. Read From FIFO2.
Figure 7. Port A Read Cycle Timing for FIFO2
16
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKL
tCLKH
CLKA
CSA
LOW
HIGH
WRA
tENS2
tENH
MBA
tENS2
tENH
ENA
IRA
HIGH
tDH
tDS
A0 - A35
W1
t
CLK
(1)
SKEW1
t
tCLKH
tCLKL
1
2
3
CLKB
tPOR
tPOR
FIFO1 Empty
LOW
ORB
CSB
HIGH
LOW
W/RB
MBB
tENH
tENS2
ENB
tA
Old Data in FIFO1 Output Register
W1
B0 - B35
4660 drw 10
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.
If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB
cycle later than shown.
Figure 8. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty
17
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
LOW
LOW
CSB
W/RB
tENS2
tENH
MBB
ENB
tENH
tENS2
IRB HIGH
B0 - B35
tDS
tDH
W1
t
CLK
(1)
SKEW1
t
tCLKH
t
CLKL
1
2
3
CLKA
ORA
t
POR
tPOR
FIFO2 Empty
CSA LOW
W/RA LOW
LOW
MBA
tENS2
tENH
ENA
tA
Old Data in FIFO2 Output Register
W1
A0-A35
3022 drw 11
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.
If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA
cycle later than shown.
Figure 9. ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty
18
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
LOW
CSB
W/RB
HIGH
LOW
MBB
tENH
tENS2
ENB
ORB
HIGH
tA
Previous Word in FIFO1 Output Register
SKEW1
Next Word From FIFO1
B0 -B35
(1)
t
tCLK
tCLKH
tCLKL
1
2
CLKA
tPIR
tPIR
IRA
FIFO1 Full
LOW
CSA
W/RA
HIGH
tENS2
tENH
MBA
tENS2
tENH
ENA
A0-A35
NOTE:
tDS
tDH
Write
To FIFO1
3022 drw 12
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
Figure 10. IRA Flag Timing and First Available Write when FIFO1 is Full
19
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
CSA
LOW
W/RA
LOW
LOW
MBA
ENA
tENS2
tENH
ORA HIGH
tA
Previous Word in FIFO2 Output Register
SKEW1
Next Word From FIFO2
A0 -A35
(1)
t
tCLK
tCLKH
tCLKL
1
2
CLKB
IRB
tPIR
tPIR
FIFO2 FULL
CSB LOW
LOW
W/RB
tENH
tENS2
MBB
tENS2
tENH
ENB
tDS
tDH
Wriite
B0 - B35
To FIFO2
3022 drw 13
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown.
Figure 11. IRB Flag Timing and First Available Write when FIFO2 is Full
CLKA
tENS2
tENH
ENA
(1)
tSKEW2
1
2
CLKB
t
PAE
t
PAE
(X1+1) Words in FIFO1
ENS2
X1 Words in FIFO1
AEB
t
tENH
ENB
3022 drw 14
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
Figure 12. Timing for AEB when FIFO1 is Almost-Empty
20
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKB
tEN2S
tENH
ENB
(1)
tSKEW2
1
CLKA
2
t
PAE
t
PAE
X2 Words in FIFO2
(X2+1) Words in FIFO2
ENS2
AEA
t
tENH
ENA
3022 drw 15
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge
and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
Figure 13. Timing for AEA when FIFO2 is Almost-Empty
(1)
tSKEW2
1
2
CLKA
ENA
AFA
t
ENS2
tENH
t
PAF
t
PAF
(D-Y1) Words in FIFO1
[D-(Y1+1)] Words in FIFO1
CLKB
ENB
tENH
tENS2
3022 drw 16
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT723622, 512 for the IDT723632, 1,024 for the IDT723642.
Figure 14. Timing for AFA when FIFO1 is Almost-Full
21
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
(1)
tSKEW2
1
2
CLKB
tENS2
tENH
tPAF
ENB
tPAF
(D-Y2) Words in FIFO2
AFB
[D-(Y2+1)] Words in FIFO2
CLKA
tENH
tENS2
ENA
3022 drw 17
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge
and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKB cycle later than shown.
2. FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT723622, 512 for the IDT723632, 1,024 for the IDT723642.
Figure 15. Timing for AFB when FIFO2 is Almost-Full
CLKA
tENH
tENS1
CSA
W/RA
MBA
t
ENH
t
ENS1
ENS2
t
ENH
t
tENH
tENS2
ENA
A0 - A35
CLKB
tDH
t
DS
W1
t
PMF
t
PMF
MBF1
CSB
W/RB
MBB
ENB
tENS2
tENH
t
MDV
tEN
t
PMR
tDIS
FIFO1 Output Register
W1 (Remains valid in Mail1 Register after read)
B0 - B35
3022 drw 18
Figure 16. Timing for Mail1 Register and MBF1 Flag
22
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKB
tENS1
tENH
CSB
W/RB
MBB
ENB
t
ENS1
ENS2
t
ENH
t
t
ENH
tENS2
t
t
ENH
DH
tDS
W1
B0-B35
CLKA
t
PMF
tPMF
MBF2
CSA
W/RA
MBA
ENA
tENH
tENS2
t
PMR
tEN
tDIS
t
MDV
W1 (Remains valid in Mail 2 Register after read)
A0-A35
3022 drw19
FIFO2 Output Register
Figure 17. Timing for Mail2 Register and MBF2 Flag
23
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
PARAMETER MEASUREMENT INFORMATION
5 V
1.1 k Ω
From Output
Under Test
30 pF(1)
680Ω
PROPAGATION DELAY
LOAD CIRCUIT
3 V
3 V
Timing
Input
1.5 V
High-Level
1.5 V
Input
1.5 V
GND
GND
3 V
t
S
th
t
W
3 V
Data,
Enable
Input
1.5 V
1.5 V
Low-Level
1.5 V
1.5 V
GND
Input
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Enable
1.5 V
1.5 V
t
PZL
GND
t
PLZ
3 V
GND
≈
3 V
Input
1.5 V
1.5 V
1.5 V
Low-Level
Output
V
OL
t
PD
t
PZH
tPD
V
OH
V
OH
OV
In-Phase
Output
1.5 V
1.5 V
High-Level
Output
1.5 V
t
PHZ
V
OL
≈
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3022 drw 20
NOTE:
1. Includes probe and jig capacitance.
Figure 18. Load Circuit and Voltage Waveforms
24
ORDERING INFORMATION
XXXXXX
X
XX
X
X
X
Device Type Power
Speed
Package
Process/
Temperature
Range
BLANK
Commercial (0°C to +70°C)
Green
G
PF
Thin Quad Flat Pack (TQFP, PN120-1)
Plastic Quad Flat Pack (PQFP, PQ132-1)
PQF
12
15
Clock Cycle Time (tCLK
)
Commercial Only
Speed in Nanoseconds
Low Power
L
723622
723632
723642
256 x 36 x 2 ⎯ SyncBiFIFO
™
™
512 x 36 x 2 ⎯ SyncBiFIFO
1,024 x 36 x 2 ⎯ SyncBiFIFO
™
3022 drw 21
NOTES:
1. Industrial temperature range is available by special order.
2. Green parts are available. For specific speeds and packages please contact your sales office.
DATASHEETDOCUMENTHISTORY
10/04/2000
03/21/2001
08/01/2001
12/18/2001
02/05/2009
pgs. 1 through 25, except pages 35.
pgs. 6 and 7.
pgs. 1, 6, 8, 9 and 25.
pg. 23.
pgs. 1 and 25.
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
6024 Silver Creek Valley Road
San Jose, CA 95138
800-345-7015 or 408-284-8200
fax: 408-284-2775
408-360-1753
email:FIFOhelp@idt.com
www.idt.com
25
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