723632L15PFG [IDT]
CMOS SyncBiFIFO;
| 型号： | 723632L15PFG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | CMOS SyncBiFIFO 先进先出芯片 |
| 文件： | 总24页 (文件大小：188K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
CMOS SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2,
1,024 x 36 x 2
IDT723622
IDT723632
IDT723642
• Fast access times of 10ns
• Available in space-saving 120-pin Thin Quad Flatpack (TQFP)
• Green parts available
FEATURES:
• Memory storage capacity:
IDT723622
IDT723632
IDT723642
–
–
–
256 x 36 x 2
512 x 36 x 2
1,024 x 36 x 2
DESCRIPTION:
• Free-running CLKA and CLKB may be asynchronous or
TheIDT723622/723632/723642areamonolithic,high-speed,low-power,
coincident (simultaneous reading and writing of data on a single CMOS Bidirectional SyncFIFO (clocked) memory which supports clock fre-
clock edge is permitted)
• Two independent clocked FIFOs buffering data in opposite
directions
• Mailbox bypass register for each FIFO
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor Interface Control Logic
• IRA, ORA, AEA, and AFA flags synchronized by CLKA
• IRB, ORB, AEB, and AFB flags synchronized by CLKB
• Supports clock frequencies up to 66.7MHz
quencies up to 66.7MHz and have read access times as fast as 10ns.
Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs on board
each chip buffer data in opposite directions. Communication between
each port may bypass the FIFOs via two 36-bit mailbox registers. Each
mailbox register has a flag to signal when new mail has been stored.
These devices are a synchronous (clocked) FIFO, meaning each port
employsasynchronousinterface.Alldatatransfersthroughaportaregated
totheLOW-to-HIGHtransitionofaportclockbyenablesignals.Theclocksfor
each port are independent of one another and can be asynchronous or
FUNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
CLKA
Port-A
Control
Logic
CSA
W/RA
ENA
RAM
ARRAY
MBA
256 x 36
512 x 36
1,024 x 36
36
FIFO1,
Mail1
Reset
Logic
RST1
Write
Pointer
Read
Pointer
36
Status Flag
Logic
ORB
AEB
IRA
AFA
FIFO 1
Programmable Flag
Offset Registers
FS
0
1
B0 - B35
FS
A
0
- A35
10
FIFO 2
ORA
AEA
Status Flag
Logic
IRB
AFB
36
Read
Pointer
Write
Pointer
36
FIFO2,
Mail2
Reset
Logic
RST2
RAM
ARRAY
256 x 36
512 x 36
CLKB
CSB
Port-B
Control
Logic
1,024 x 36
W/RB
ENB
MBB
Mail 2
Register
3022 drw 01
MBF2
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc. SyncBiFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
FEBRUARY2015
COMMERCIAL TEMPERATURE RANGE
1
©
2015 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-3022/6
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
two-stagesynchronizedtotheportclockthatreadsdatafromitsarray.Offset
values for the Almost-Full and Almost-Empty flags of both FIFOs can be
programmedfromPortA.
DESCRIPTION(CONTINUED)
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with syn-
chronous control.
Two or more devices may be used in parallel to create wider data paths.
If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol
inputswillimmediatelytakethedeviceoutofthepowerdownstate.
The 723622/723632/723642 are characterized for operation from
0°C to 70°C. They are fabricated using high speed, submicron CMOS
technology.
Each FIFO has a programmable Almost-Empty flag (AEA and AEB)
and a progammable Almost-Full flag (AFA and AFB). AEA and AEB
indicate when a selected number of words remain in the FIFO memory.
AFA and AFB indicate when the FIFO contains more than a selected
number of words.
The Input Ready (IRA, IRB) and Almost-Full (AFA, AFB) flags of a FIFO
aretwo-stagesynchronizedtotheportclockthatwritesdataintoitsarray.The
OutputReady(ORA,ORB)andAlmost-Empty(AEA,AEB)flagsofaFIFOare
PIN CONFIGURATION
B
B
B
B
35
34
33
32
A
A
A
A
35
34
33
32
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
1
2
3
4
GND
V
CC
5
B
B
B
B
B
B
V
B
B
31
30
29
28
27
26
CC
25
24
A
31
6
A30
7
GND
8
A
A
A
A
A
A
A
29
28
27
26
25
24
23
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GND
B
B
B
B
B
B
23
22
21
20
19
18
GND
A
22
CC
V
A
21
20
19
18
A
A
A
GND
B
B
V
B
B
B
B
17
16
CC
15
14
13
12
GND
A
A
A
A
A
17
16
15
14
13
V
CC
GND
A12
3022 drw 03
TQFP (PNG120, order code: PF)
TOP VIEW
2
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS
Symbol
Name
I/O
Description
A0-A35
PortAData
I/0
36-bitbidirectionaldataportforsideA.
AEA
PortAAlmost-
EmptyFlag
O
ProgrammableAlmost-EmptyflagsynchronizedtoCLKA.ItisLOWwhenthenumberofwords
inFIFO2islessthanorequaltothevalueintheAlmost-EmptyAOffsetregister, X2.
(Port A)
AEB
AFA
AFB
PortBAlmost-
EmptyFlag
O
ProgrammableAlmost-EmptyflagsynchronizedtoCLKB.ItisLOWwhenthenumberofwords
inFIFO1islessthanorequaltothevalueintheAlmost-EmptyBOffsetregister, X1.
(Port B)
PortAAlmost-
Full Flag
O
ProgrammableAlmost-FullflagsynchronizedtoCLKA.ItisLOWwhenthenumberofempty
locationsinFIFO1islessthanorequaltothevalueintheAlmost-FullAOffsetregister, Y1.
(Port A)
PortBAlmost-
Full Flag
O
ProgrammableAlmost-FullflagsynchronizedtoCLKB.ItisLOWwhenthenumberofempty
locationsinFIFO2islessthanorequaltothevalueintheAlmost-FullBOffsetregister, Y2.
(Port B)
B0 - B35
CLKA
PortBData
PortAClock
I/O
I
36-bitbidirectionaldataportforsideB.
CLKAisacontinuousclockthatsynchronizesalldatatransfersthroughportAandcanbe
asynchronous or coincident to CLKB. IRA, ORA, AFA, and AEA are all synchronized to the
LOW-to-HIGHtransitionofCLKA.
CLKB
PortBClock
I
CLKBisacontinuousclockthatsynchronizesalldatatransfersthroughportBandcanbe
asynchronous or coincident to CLKA. IRB, ORB, AFB, and AEB are synchronized to the LOW-
to-HIGHtransitionofCLKB.
CSA
CSB
Port A Chip
Select
I
I
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write on port A.
The A0-A35 outputs are in the high-impedance state when CSA is HIGH.
Port B Chip
Select
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on
port B. The B0-B35 outputs are in the high-impedance state when CSB is HIGH.
ENA
ENB
Port A Enable
Port B Enable
I
I
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
FS1, FS0 FlagOffset
Selects
TheLOW-to-HIGHtransitionofaFlFO’sResetinputlatchesthevaluesofFS0andFS1.
If either FS0 or FS1 is HIGH when a Reset goes HIGH, one of three preset values is selected as
theoffsetfortheFlFOsAlmost-FullandAlmost-Emptyflags.IfbothFIFOsareresetsimultaneously
and both FS0 and FS1 are LOW when RST1 and RST2 go HIGH, the first four writes to FIFO1
loadtheAlmost-EmptyandAlmost-FulloffsetsforbothFlFOs.
IRA
Input Ready
Flag
O
IRAissynchronizedtotheLOW-to-HIGHtransitionofCLKA.WhenIRAisLOW,FIFO1isfull
and writes to its array are disabled. IRA is set LOW when FIFO1 is reset and is set HIGH on the
secondLOW-to-HIGHtransitionofCLKA afterreset.
(Port A)
IRB
Input Ready
Flag
O
IRBissynchronizedtotheLOW-to-HIGHtransitionofCLKB.WhenIRBisLOW,FIFO2isfull
and writes to its array are disabled. IRB is set LOW when FIFO2 is reset and is set HIGH on the
secondLOW-to-HIGHtransitionofCLKBafterreset.
(Port B)
MBA
MBB
MBF1
Port A Mailbox
Select
I
I
A HIGH level on MBA chooses a mailbox register for a port A read or write operation.
WhentheA0-A35outputsareactive, aHIGHlevelonMBAselectsdatafromthemail2registerfor
outputandaLOWlevelselectsFIFO2outputregisterdataforoutput.
Port B Mailbox
Select
A HIGH level on MBB chooses a mailbox register for a port B read or write operation. When the
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register or output and
aLOWlevelselectsFIFO1outputregisterdataforoutput.
Mail1Register
Flag
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1
register. Writestothemail1registerareinhibitedwhile MBF1isLOW. MBF1issetHIGHby
a LOW-to-HIGH transition of CLKB when a port B read is selected and MBB is HIGH. MBF1 is
set HIGH when FIFO1 is reset.
MBF2
Mail2Register
Flag
O
MBF2issetLOWbyaLOW-to-HIGHtransitionofCLKBthatwritesdata tothemail2register.
Writes to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-
to-HIGH transition of CLKA when a port A read is selected and MBA is HIGH. MBF2 is also
set HIGH when FIFO2 is reset.
3
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/O
Description
ORA
OutputReady
Flag
O
ORAissynchronizedtotheLOW-to-HIGHtransitionofCLKA.WhenORAisLOW,FIFO2is
emptyandreadsfromitsmemoryaredisabled. Readydataispresentontheoutputregister
of FIFO2 when ORA is HIGH. ORA is forced LOW when FlFO2 is reset and goes HIGH on the
third LOW-to-HIGH transition of CLKA after a word is loaded to empty memory.
(Port A)
ORB
OutputReady
Flag
O
ORBissynchronizedtotheLOW-to-HIGHtransitionofCLKB.WhenORBisLOW,FlFO1is
emptyandreadsfromitsmemoryaredisabled.ReadydataispresentontheoutputregisterofFIFO1
when ORB is HIGH. ORB is forced LOW when FIFO1 is reset and goes HIGH on the third LOW-to-
HIGHtransitionofCLKBafterawordisloadedtoemptymemory.
(Port B)
RST1
RST2
FIFO1Reset
FIFO2Reset
I
I
ToresetFIFO1,fourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKB
mustoccurwhileRST1isLOW.TheLOW-to-HIGHtransitionofRST1 latchesthestatusofFS0
and FS1 for AFA and AEB offset selection. FIFO1 must be reset upon power up before data is
writtentoitsRAM.
ToresetFIFO2,fourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKB
mustoccurwhileRST2isLOW.TheLOW-to-HIGHtransitionofRST2latchesthestatusofFS0
and FS1 for AFB and AEA offset selection. FIFO2 must be reset upon power up before data is
writtentoitsRAM.
W/RA
W/RB
PortAWrite/
ReadSelect
I
I
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH
transitionofCLKA. TheA0-A35outputsareintheHIGHimpedancestatewhenW/RAisHIGH.
PortBWrite/
ReadSelect
A LOW selects a write operation and a HIGH selects a read operation on port B for a LOW-to-HIGH
transitionofCLKB.TheB0-B35outputsareinthehigh-impedancestatewhenW/RBisLOW.
4
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGSOVEROPERATINGFREE-AIR
TEMPERATURERANGE(Unlessotherwisenoted)(1)
Symbol
Rating
Commercial
–0.5to7
–0.5toVCC+0.5
–0.5toVCC+0.5
±20
Unit
V
VCC
VI(2)
VO(2)
IIK
SupplyVoltageRange
InputVoltageRange
V
OutputVoltageRange
V
Input Clamp Current (VI < 0 or VI > VCC)
Output Clamp Current (VO = < 0 or VO > VCC)
Continuous Output Current (VO = 0 to VCC)
ContinuousCurrentThroughVCC or GND
StorageTemperatureRange
mA
mA
mA
mA
°C
IOK
±50
IOUT
ICC
±50
±400
TSTG
–65to150
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect
device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
VIH
Parameter
Min.
4.5
2
Typ.
5.0
—
Max.
5.5
—
Unit
V
SupplyVoltage(Commercial)
High-LevelInputVoltage(Commercial)
Low-LevelInputVoltage(Commercial)
High-LevelOutputCurrent(Commercial)
Low-LevelOutputCurrent(Commercial)
OperatingTemperature(Commercial)
V
VIL
—
—
—
0
—
0.8
–4
V
IOH
—
mA
mA
°C
IOL
—
8
TA
—
70
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-
AIR TEMPERATURE RANGE (Unless otherwise noted)
IDT723622
IDT723632
IDT723642
Commercial
tCLK = 15 ns
Symbol
VOH
Parameter
Output Logic "1" Voltage
Output Logic "0" Voltage
Input Leakage Current (Any Input)
Output Leakage Current
Test Conditions
IOH = –4 mA
Min.
2.4
—
Typ.(1)
—
—
—
—
—
—
4
Max.
—
Unit
V
VCC = 4.5V,
VCC = 4.5V,
VCC = 5.5V,
VCC = 5.5V,
VOL
IOL = 8 mA
0.5
±10
±10
8
V
ILI
VI = VCC or 0
—
μA
μA
mA
mA
pF
pF
ILO
VO = VCC or 0
VI = VCC –0.2V or 0V
VI = VCC –0.2V or 0V
f = 1 MHz
—
ICC2(2)
ICC3(2)
CIN(3)
Standby Current (with CLKA & CLKB running) VCC = 5.5V,
—
Standby Current (no clocks running)
VCC = 5.5V,
VI = 0,
—
1
Input Capacitance
—
—
COUT(3) Output Capacitance
VO = 0,
f = 1 MHZ
—
8
—
NOTES:
1. All typical values are at VCC = 5V, TA = 25°C.
2. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
3. Characterizedvalues,notcurrentlytested.
5
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723622/723632/723642 with CLKA
andCLKBsettofS. Alldatainputsanddataoutputschangestateduringeachclockcycletoconsumethehighestsupplycurrent. Dataoutputswere
disconnectedtonormalizethegraphtoazerocapacitanceload. Oncethecapacitanceloadperdata-outputchannelandthenumberofthesedevice's
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
2
PT = VCC x [ICC(f) + (N x ΔICC x dc)] + Σ(CL x VCC X fo)
where:
N
ΔICC
dc
CL
fo
=
=
=
=
=
numberofoutputs=36
increase in power supply current for each input at a TTL HIGH level
duty cycle of inputs at a TTL HIGH level of 3.4 V
outputcapacitanceload
switchingfrequencyofanoutput
300
250
f
data = 1/2 fS
T
A
= 25°C
C
L
= 0pF
VCC = 5.5V
VCC = 5.0V
200
150
100
VCC = 4.5V
50
0
0
10
20
30
40
50
60
70
80
90
3022 drw 03a
fS ⎯ Clock Frequency ⎯ MHz
Figure 1. Typical Characteristics: Supply Current (ICC) vs Clock Frequency (fS)
6
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
TIMINGREQUIREMENTSOVERRECOMMENDEDRANGESOFSUPPLY
VOLTAGEANDOPERATINGFREE-AIRTEMPERATURE
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
Commercial
IDT723622L15
IDT723632L15
IDT723642L15
Symbol
fS
Parameter
Min.
—
15
6
Max.
66.7
—
Unit
MHz
ns
Clock Frequency, CLKA or CLKB
tCLK
Clock Cycle Time, CLKA or CLKB
tCLKH
tCLKL
tDS
Pulse Duration, CLKA or CLKB HIGH
—
ns
Pulse Duration, CLKA and CLKB LOW
6
—
ns
Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑
Setup Time, CSA and W/RA before CLKA↑; CSB and W/RB before CLKB↑
Setup Time, ENA and MBA, before CLKA↑; ENB and MBB before CLKB↑
Setup Time, RST1 or RST2 LOW before CLKA or CLKB
Setup Time, FS0 and FS1 before RST1 and RST2 HIGH
Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑
4
—
ns
tENS1
tENS2
tRSTS
tFSS
4.5
4.5
5
—
ns
—
ns
(2)
—
ns
7.5
1
—
ns
tDH
—
ns
tENH
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB,
and MBB after CLKB↑
Hold Time, RST1 or RST2 LOW after CLKA↑ or CLKB↑
Hold Time, FS0 and FS1 after RST1 and RST2 HIGH
Skew Time, between CLKA↑ and CLKB↑ for ORA, ORB, IRA, and IRB
Skew Time, between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and AFB
1
—
ns
(2)
tRSTH
tFSH
tSKEW1(2)
tSKEW2(2,3)
4
2
—
—
—
—
ns
ns
ns
ns
7.5
12
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. SkewtimeisnotatimingconstraintforproperdeviceoperationandisonlyincludedtoillustratethetimingrelationshipbetweenCLKAcycleandCLKBcycle.
3. Designsimulated,nottested.
7
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICSOVERRECOMMENDEDRANGESOFSUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30 PF
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C)
Commercial
IDT723622L15
IDT723632L15
IDT723642L15
Symbol
Parameter
Min.
Max.
Unit
ns
tA
Access Time, CLKA↑ to A0-A35 and CLKB↑ to B0-B35
Propagation Delay Time, CLKA↑ to IRA and CLKB↑ to IRB
Propagation Delay Time, CLKA↑ to ORA and CLKB↑ to ORB
Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to AEB
Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to AFB
2
2
1
1
1
0
10
8
tPIR
tPOR
tPAE
tPAF
tPMF
ns
8
ns
8
ns
8
ns
Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH and
CLKB↑ to MBF2 LOW or MBF1 HIGH
8
ns
tPMR
tMDV
tRSF
Propagation Delay Time, CLKA↑ to B0-B35(1) and CLKB↑ to A0-A35(2)
2
2
1
10
10
15
ns
ns
ns
Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 Valid
Propagation Delay Time, RST1 LOW to AEB LOW, AFA HIGH, and
MBF1 HIGH, and RST2 LOW to AEA LOW, AFB HIGH, and MBF2 HIGH
tEN
tDIS
Enable Time, CSA and W/RA LOW to A0-A35 Active and CSB LOW
and W/RB HIGH to B0-B35 Active
2
1
10
8
ns
ns
Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance and
CSB HIGH or W/RB LOW to B0-B35 at high-impedance
NOTES:
1. Writingdatatothemail1registerwhentheB0-B35outputsareactiveandMBBisHIGH.
2. Writingdatatothemail2registerwhentheA0-A35outputsareactiveandMBAisHIGH.
8
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
SIGNALDESCRIPTION
— PARALLEL LOAD FROM PORT A
ToprogramtheX1,X2,Y1,andY2registersfromportA,bothFlFOsshould
be reset simultaneously with FS0 and FS1 LOW during the LOW-to-HIGH
transitionoftheResetinputs.Afterthisresetiscomplete,thefirstfourwritesto
FIFO1donotstoredataintheFIFOmemorybutloadtheoffsetregistersinthe
order Y1, X1, Y2, X2. The port A data inputs used by the offset registers are
(A7-A0),(A8-A0),or(A9-A0)fortheIDT723622,IDT723632,orIDT723642,
respectively. Thehighestnumberedinputisusedasthemostsignificantbitof
thebinarynumberineachcase. Validprogrammingvaluesfortheregisters
rangesfrom1to252fortheIDT723622;1to508fortheIDT723632;and1to
1,020fortheIDT723642. Afteralltheoffsetregistersareprogrammedfromport
A,theportBInputReadyflag(IRB)issetHIGH,andbothFIFOsbeginnormal
operation.SeeFigure3forrelevantoffsetregisterparallelprogrammingtiming
diagram.
RESET
After power up, a Master Reset operation must be performed by
providing a LOW pulse to RST1 and RST2 simultaneously. Afterwards,
the FIFO memories of the IDT723622/723632/723642 are reset sepa-
rately by taking their Reset (RST1, RST2) inputs LOW for at least four port
A Clock (CLKA) and four port B Clock (CLKB) LOW-to-HIGH transitions.
The Reset inputs can switch asynchronously to the clocks. A FIFO reset
initializes the internal read and write pointers and forces the Input Ready
flag (IRA, IRB) LOW, the Output Ready flag (ORA, ORB) LOW, the Almost-
Empty flag (AEA, AEB) LOW, and the Almost-Full flag (AFA, AFB) HIGH.
Resetting a FIFO also forces the Mailbox Flag (MBF1, MBF2) of the
parallel mailbox register HIGH. After a FlFO is reset, its Input Ready flag
is set HIGH after two clock cycles to begin normal operation.
ALOW-to-HIGHtransitiononaFlFOReset(RST1,RST2)inputlatches
thevalueoftheFlagSelect(FS0,FS1)inputsforchoosingtheAlmost-Fulland
Almost-Empty offset programming method (for details see Table 1, Flag
Programming and the Almost-Empty Flag and Almost-Full Flag Offset
Programmingsectionthatfollows).TherelevantFIFOResettimingdiagramcan
be found in Figure 2.
FIFO WRITE/READ OPERATION
ThestateoftheportAdata(A0-A35)outputsiscontrolledbyportAChip
Select(CSA)andportAWrite/Readselect(W/RA).TheA0-A35outputsare
inthehigh-impedancestatewheneitherCSAorW/RAisHIGH.TheA0-A35
outputs are active when both CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
transitionofCLKAwhenCSAisLOW, W/RAisHIGH, ENAisHIGH, MBAis
LOW, andIRAisHIGH. DataisreadfromFIFO2totheA0-A35outputsbya
LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA isLOW, ENA is
HIGH, MBAisLOW, andORAisHIGH(seeTable2). FIFOreadsandwrites
onportAareindependentofanyconcurrentportBoperation.WriteandRead
cycle timing diagrams for port A can be found in Figure 4 and 7.
TheportBcontrolsignalsareidenticaltothoseofportAwiththeexception
thattheportBWrite/Readselect(W/RB)istheinverseoftheportAWrite/Read
select(W/RA).ThestateoftheportBdata(B0-B35)outputsiscontrolledbythe
portBChipSelect(CSB)andportBWrite/Readselect(W/RB). TheB0-B35
outputsareinthehigh-impedancestatewheneitherCSBisHIGHorW/RBis
LOW. TheB0-B35outputsareactivewhenCSBisLOWandW/RBisHIGH.
Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH
transitionofCLKBwhenCSBisLOW,W/RBisLOW,ENBisHIGH,MBBisLOW,
and IRB is HIGH. Data is read from FIFO1 to the B0-B35 outputs by a LOW-
to-HIGHtransitionofCLKBwhenCSBisLOW,W/RBisHIGH,ENBisHIGH,
MBBisLOW,andORBisHIGH(seeTable3).FIFOreadsandwritesonport
BareindependentofanyconcurrentportAoperation. WriteandReadcycle
ALMOST-EMPTY FLAG AND ALMOST-FULL FLAG OFFSET PRO-
GRAMMING
Four registers in these devices are used to hold the offset values for
theAlmost-EmptyandAlmost-Fullflags.TheportBAlmost-Emptyflag(AEB)
OffsetregisterislabeledX1andtheportAAlmost-Emptyflag(AEA)Offsetregister
islabeledX2.TheportAAlmost-Fullflag(AFA)OffsetregisterislabeledY1and
theportBAlmost-Fullflag(AFB)OffsetregisterislabeledY2.Theindexofeach
register name corresponds to its FIFO number. The offset registers can be
loadedwithpresetvaluesduringtheresetofaFIFOortheycanbeprogrammed
from port A (see Table 1).
— PRESET VALUES
ToloadtheFIFO'sAlmost-EmptyflagandAlmost-FullflagOffsetregisters
withoneofthethreepresetvalueslistedinTable1,atleastoneoftheflagselect
inputsmustbeHIGHduringtheLOW-to-HIGHtransitionofitsResetinput.For
example,toloadthepresetvalueof64intoX1andY1,FS0andFS1mustbe
HIGHwhenFlFO1Reset(RST1)returnsHIGH.Flagoffsetregistersassociated
withFIFO2areloadedwithoneofthepresetvaluesinthesamewaywithFIFO2
Reset(RST2)toggledsimultaneouslywithFIFO1Reset(RST1). Forpreset
value loading timing diagram, see Figure 2.
TABLE 1 — FLAG PROGRAMMING
FS1
FS0
RST1
RST2
X1 AND Y1 REGlSTERS(1)
X2 AND Y2 REGlSTERS(2)
H
H
↑
X
64
X
H
H
X
↑
X
64
H
L
↑
X
16
X
H
L
X
↑
X
16
L
H
↑
X
8
X
L
L
H
X
↑
X
8
L
↑
↑
ProgrammedfromportA
ProgrammedfromportA
NOTES:
1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
9
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
timing diagrams for port B can be found in Figure 5 and 6.
reads are ignored.
A FIFO read pointer is incremented each time a new word is clocked to
The setup and hold time constraints to the port Clocks for the port Chip
Selects and Write/Read selects are only for enabling write and read itsoutputregister.ThestatemachinethatcontrolsanOutputReadyflagmonitors
operations and are not related to high-impedance control of the data a write pointer and read pointer comparator that indicates when the FIFO
outputs. If a port enable is LOW during a clock cycle, the port’s Chip Select memorystatusisempty,empty+1,orempty+2.Fromthetimeawordiswritten
and Write/Read select may change states during the setup and hold time toaFIFO,itcanbeshiftedtotheFIFOoutputregisterinaminimumofthreecycles
window of the cycle.
oftheOutputReadyflagsynchronizingclock.Therefore,anOutputReadyflag
When a FIFO Output Ready flag is LOW, the next word written is isLOWifawordinmemoryisthenextdatatobesenttotheFlFOoutputregister
automaticallysenttotheFIFOoutputregisterautomaticallybytheLOW-to-HIGH andthreecyclesoftheportClockthatreadsdatafromtheFIFOhavenotelapsed
transitionoftheportclockthatsetstheOutputReadyflagHIGH. WhentheOutput sincethetimethewordwaswritten.TheOutputReadyflagoftheFIFOremains
ReadyflagisHIGH,subsequentdataisclockedtotheoutputregistersonlywhen LOWuntilthethirdLOW-to-HIGHtransitionofthesynchronizingclockoccurs,
aFIFOreadisselectedusingtheport’sChipSelect,Write/Readselect,Enable, simultaneouslyforcingtheOutputReadyflagHIGHandshiftingthewordtothe
andMailboxselect.
FIFOoutputregister.
ALOW-to-HIGHtransitiononanOutputReadyflagsynchronizingclock
beginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccursat
SYNCHRONIZED FIFO FLAGS
EachFIFOissynchronizedtoitsportclockthroughatleasttwoflip-flop timetSKEW1orgreaterafterthewrite.Otherwise,thesubsequentclockcyclecan
stages. This is done to improve flag-signal reliability by reducing the bethefirstsynchronizationcycle(seeFigures8and9forORAandORBtiming
probability of metastable events when CLKA and CLKB operate asynchro- diagrams).
nouslytooneanother.ORA,AEA,IRA,andAFAaresynchronizedtoCLKA.
ORB, AEB, IRB, and AFB are synchronized to CLKB. Tables 4 and 5 show
INPUT READY FLAGS (IRA, IRB)
the relationship of each port flag to FIFO1 and FIFO2.
TheInputReadyflagofaFlFOissynchronizedtotheportclockthatwrites
datatoitsarray.WhentheInputReadyflagisHIGH,amemorylocationisfree
intheFIFOtoreceivenewdata.NomemorylocationsarefreewhentheInput
ReadyflagisLOWandattemptedwritestotheFIFOareignored.
EachtimeawordiswrittentoaFIFO,itswritepointerisincremented.The
statemachinethatcontrolsanInputReadyflagmonitorsawritepointerandread
OUTPUT READY FLAGS (ORA, ORB)
The Output Ready flag of a FIFO is synchronized to the port clock that
reads data from its array. When the Output Ready flag is HIGH, new data
is present in the FIFO output register. When the Output Ready flag is LOW,
thepreviousdatawordispresentintheFIFOoutputregisterandattemptedFIFO
TABLE 2 — PORT A ENABLE FUNCTION TABLE
CSA
H
L
W/RA
ENA
MBA
CLKA
Data A (A0-A35) I/O
High-Impedance
Input
PORT FUNCTION
X
H
H
H
L
X
X
X
X
↑
↑
X
↑
X
↑
None
None
L
X
L
H
L
Input
FIFO1 write
Mail1write
L
H
H
Input
L
L
L
Output
None
L
L
H
L
Output
FIFO2 read
None
L
L
L
H
Output
L
L
H
H
Output
Mail2 read (set MBF2 HIGH)
TABLE 3 — PORT B ENABLE FUNCTION TABLE
CSB
H
L
W/RB
ENB
MBB
CLKB
Data B (B0-B35) I/O
PORT FUNCTION
X
L
X
X
X
X
↑
↑
X
↑
X
↑
High-Impedance
Input
None
None
L
X
L
L
H
L
Input
FIFO2 write
Mail2write
L
L
H
H
Input
L
H
H
H
H
L
L
Output
None
L
H
L
Output
FIFO1 read
None
L
L
H
Output
L
H
H
Output
Mail1 read (set MBF1 HIGH)
10
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
pointer comparator that indicates when the FlFO memory status is full, a write pointer and read pointer comparator that indicates when the FIFO
full-1, or full-2. From the time a word is read from a FIFO, its previous memory status is almost-empty, almost-empty+1, or almost-empty+2. The
memory location is ready to be written in a minimum of two cycles of the almost-empty state is defined by the contents of register X1 for AEB and
Input Ready flag synchronizing clock. Therefore, an Input Ready flag is register X2 for AEA. These registers are loaded with preset values during
LOW if less than two cycles of the Input Ready flag synchronizing clock a FIFO reset or programmed from port A (see Almost-Empty flag and
have elapsed since the next memory write location has been read. The Almost-Full flag offset programming section). An Almost-Empty flag is
second LOW-to-HIGH transition on the Input Ready flag synchronizing LOW when its FIFO contains X or less words and is HIGH when its FIFO
Clock after the read sets the Input Ready flag HIGH.
contains (X+1) or more words. A data word present in the FIFO output
A LOW-to-HIGH transition on an Input Ready flag synchronizing register has been read from memory.
clock begins the first synchronization cycle of a read if the clock transition
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizing
occurs at time tSKEW1 or greater after the read. Otherwise, the subsequent clockarerequiredafteraFIFOwriteforitsAlmost-Emptyflagtoreflectthenew
clock cycle can be the first synchronization cycle (see Figures 10 and 11 leveloffill.Therefore,theAlmost-FullflagofaFIFOcontaining(X+1)ormore
for timing diagrams).
wordsremainsLOWiftwocyclesofitssynchronizingclockhavenotelapsed
sincethewritethatfilledthememorytothe(X+1)level. AnAlmost-Emptyflag
issetHIGHbythesecondLOW-to-HIGHtransitionofitssynchronizingclockafter
ALMOST-EMPTY FLAGS (AEA, AEB)
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads theFIFOwritethatfillsmemorytothe(X+1)level.ALOW-to-HIGHtransitionof
datafromitsarray.ThestatemachinethatcontrolsanAlmost-Emptyflagmonitors anAlmost-Emptyflagsynchronizingclockbeginsthefirstsynchronizationcycle
ifitoccursattimetSKEW2orgreaterafterthewritethatfillstheFIFOto(X+1)words.
TABLE 4 — FIFO1 FLAG OPERATION
Synchronized
to CLKB
Synchronized
to CLKA
Number of Words in FIFO(1,2)
IDT723632(3)
IDT723622(3)
IDT723642(3)
ORB
AEB
AFA
IRA
0
0
1 to X1
0
L
H
H
H
H
L
L
H
H
H
L
H
1 to X1
(X1+1)to[256-(Y1+1)]
(256-Y1)to255
256
1 to X1
(X1+1)to[1,024-(Y1+1)]
(1,024-Y1)to1,023
1,024
H
H
H
L
(X1+1)to[512-(Y1+1)]
(512-Y1)to511
512
H
H
H
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since the first word written to an empty FIFO goes unrequested to the output register (no read
operation necessary), it is not included in the FIFO memory count.
3. X1 is the Almost-Empty offset for FIFO1 used by AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a reset of FIFO1 or
programmed from port A.
TABLE 5 — FIFO2 FLAG OPERATION
Synchronized
to CLKA
Synchronized
to CLKB
Number of Words in FIFO(1,2)
IDT723632(3)
IDT723622(3)
IDT723642(3)
ORA
AEA
AFB
IRB
0
1 to X2
0
1 to X2
0
1 to X2
L
H
H
H
H
L
L
H
H
H
L
H
H
(X2+1)to[256-(Y2+1)]
(256-Y2)to255
256
(X2+1)to[512-(Y2+1)]
(512-Y2)to511
512
(X2+1)to[1,024-(Y2+1)]
(1,024-Y2)to1,023
1,024
H
H
H
H
H
L
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since the first word written to an empty FIFO goes unrequested to the output register (no read
operation necessary), it is not included in the FIFO memory count.
3. X2 is the Almost-Empty offset for FIFO2 used by AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a reset of FIFO2 or
programmed from port A.
11
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
512/1,024-(Y+1)]. An Almost-Full flag is set HIGH by the second LOW-
to-HIGH transition of its synchronizing clock after the FIFO read that
reduces the number of words in memory to [256/512/1,024-(Y+1)]. A
LOW-to-HIGH transition of an Almost-Full flag synchronizing clock begins
the first synchronization cycle if it occurs at time tSKEW2 or greater after the
read that reduces the number of words in memory to [256/512/1,024-
(Y+1)]. Otherwise, the subsequent synchronizing clock cycle may be the
first synchronization cycle (see Figures 14 and 15).
Otherwise, the subsequent synchronizing clock cycle may be the first
synchronization cycle. (See Figures 12 and 13).
ALMOST-FULL FLAGS (AFA, AFB)
The Almost-Full flag of a FIFO is synchronized to the port clock that
writes data to its array. The state machine that controls an Almost-Full flag
monitors a write pointer and read pointer comparator that indicates when
the FIFO memory status is almost-full, almost-full-1, or almost-full-2. The
almost-full state is defined by the contents of register Y1 for AFA and
register Y2 for AFB. These registers are loaded with preset values during
a FlFO reset or programmed from port A (see Almost-Empty flag and
Almost-Full flag offset programming section). An Almost-Full flag is
LOW when the number of words in its FIFO is greater than or equal to
(256-Y), (512-Y), or (1,024-Y) for the IDT723622, IDT723632, or
IDT723642 respectively. An Almost-Full flag is HIGH when the number
of words in its FIFO is less than or equal to [256-(Y+1)], [512-(Y+1)], or
[1,024-(Y+1)] for the IDT723622, IDT723632, or IDT723642 respec-
tively. Note that a data word present in the FIFO output register has been
read from memory.
MAILBOX REGISTERS
Each FIFO has a 36-bit bypass register to pass command and control
information between port A and port B without putting it in queue. The
Mailbox select (MBA, MBB) inputs choose between a mail register and a
FIFO for a port data transfer operation. A LOW-to-HIGH transition on CLKA
writesA0-A35datatothemail1registerwhenaportAWriteisselectedbyCSA,
W/RA,andENAandwithMBAHIGH.ALOW-to-HIGHtransitiononCLKBwrites
B0-B35datatothemail2registerwhenaportBWriteisselectedbyCSB, W/
RB, and ENB and with MBB HIGH. Writing data to a mail register sets its
correspondingflag(MBF1orMBF2)LOW.Attemptedwritestoamailregister
areignoredwhilethemailflagisLOW.
Whendataoutputsofaportareactive, thedataonthebuscomesfrom
theFIFOoutputregisterwhentheportMailboxselectinputisLOWandfrom
the mail register when the port-mailbox select input is HIGH. The Mail1
RegisterFlag(MBF1)issetHIGHbyaLOW-to-HIGHtransitiononCLKBwhen
aportBReadisselectedbyCSB, W/RB,andENBandwithMBBHIGH.The
Mail2RegisterFlag(MBF2)issetHIGHbyaLOW-to-HIGHtransitiononCLKA
whenaportAreadisselectedbyCSA,W/RA,andENAandwithMBAHIGH.
Thedatainamailregisterremainsintactafteritisreadandchangesonlywhen
newdataiswrittentotheregister.FormailregisterandMailRegisterflagtiming
diagrams, see Figure 16 and 17.
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclock
arerequiredafteraFIFOreadforitsAlmost-Fullflagtoreflectthenewlevelof
fill.Therefore,theAlmost-FullflagofaFIFOcontaining[256/512/1,024-(Y+1)]
or less words remains LOW if two cycles of its synchronizing clock have not
elapsedsincethereadthatreducedthenumberofwordsinmemoryto[256/
12
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKA
CLKB
tRSTH
t
RSTS
t
FSS
tFSH
RST1
FS1,FS0
IRA
0,1
tPIR
tPIR
tPOR
ORB
AEB
AFA
t
RSF
RSF
t
tRSF
MBF1
3022 drw 04
NOTE:
1. FIFO2 is reset in the same manner to load X2 and Y2 with a preset value.
Figure 2. FIFO1 Reset and Loading X1 and Y1 with a Preset Value of Eight(1)
CLKA
1
2
4
t
FSS
RST1,
RST2
tFSH
FS1,FS0
0,0
tPIR
IRA
(1)
SKEW1
tENS2
tENH
t
ENA
tDH
tDS
A0 - A35
CLKB
First Word to FIFO1
AFA Offset
AEB Offset
AFB Offset
AEA Offset
(Y1)
(X1)
(Y2)
(X2)
1
2
tPIR
IRB
3022 drw 05
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and
rising edge of CLKB is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown.
2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles.
Figure 3. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset
13
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
IRA HIGH
tENS1
tENH
CSA
t
ENS1
t
ENH
ENH
ENH
W/RA
tENS2
t
MBA
tENS2
tENS2
t
tENH
tENS2
tENH
ENA
tDH
tDS
(1)
W2(1)
No Operation
A0 - A35
W1
3022 drw 06
NOTE:
1. Written to FIFO1.
Figure 4. Port A Write Cycle Timing for FIFO1
tCLK
tCLKH
tCLKL
CLKB
IRB
HIGH
tENS1
tENH
CSB
tENS1
tENH
W/RB
MBB
ENB
t
ENS2
t
ENH
t
ENS2
tENS2
t
ENH
tENS2
tENH
tENH
tDH
tDS
(1)
W2(1)
B0 - B35
No Operation
W1
3022 drw 07
NOTE:
1. Written to FIFO2.
Figure 5. Port B Write Cycle Timing for FIFO2
14
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
ORB HIGH
CSB
W/RB
MBB
ENB
tENS2
tENS2
tENH
tENH
tENH
tENS2
No Operation
W3(1)
t
DIS
t
MDV
tA
tA
tEN
W2(1)
W1(1)
B0 - B35
3022 drw 08
NOTE:
1. Read From FIFO1.
Figure 6. Port B Read Cycle Timing for FIFO1
tCLK
tCLKH
tCLKL
CLKA
ORA
CSA
W/RA
MBA
ENA
t
ENS2
tENH
t
ENH
t
ENH
tENS2
t
ENS2
No Operation
W3(1)
t
DMV
tDIS
t
(1)
A
t
A
tEN
W1
W2(1)
A0 - A35
3022 drw 09
NOTE:
1. Read From FIFO2.
Figure 7. Port A Read Cycle Timing for FIFO2
15
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKL
tCLKH
CLKA
CSA
LOW
HIGH
WRA
tENS2
tENH
MBA
tENS2
tENH
ENA
IRA
HIGH
tDH
tDS
A0 - A35
W1
t
CLK
(1)
SKEW1
t
tCLKH
tCLKL
1
2
3
CLKB
tPOR
tPOR
FIFO1 Empty
LOW
ORB
CSB
HIGH
LOW
W/RB
MBB
tENH
tENS2
ENB
tA
Old Data in FIFO1 Output Register
W1
B0 - B35
4660 drw 10
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.
If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB
cycle later than shown.
Figure 8. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty
16
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
LOW
LOW
CSB
W/RB
tENS2
tENH
MBB
ENB
tENH
tENS2
IRB HIGH
B0 - B35
tDS
tDH
W1
t
CLK
(1)
SKEW1
t
tCLKH
t
CLKL
1
2
3
CLKA
ORA
t
POR
tPOR
FIFO2 Empty
CSA LOW
W/RA LOW
LOW
MBA
tENS2
tENH
ENA
tA
Old Data in FIFO2 Output Register
W1
A0-A35
3022 drw 11
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.
If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA
cycle later than shown.
Figure 9. ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty
17
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
LOW
CSB
W/RB
HIGH
LOW
MBB
tENH
tENS2
ENB
ORB
HIGH
tA
Previous Word in FIFO1 Output Register
SKEW1
Next Word From FIFO1
B0 -B35
(1)
t
tCLK
tCLKH
tCLKL
1
2
CLKA
tPIR
tPIR
IRA
FIFO1 Full
LOW
CSA
W/RA
HIGH
tENS2
tENH
MBA
tENS2
tENH
ENA
A0-A35
NOTE:
tDS
tDH
Write
To FIFO1
3022 drw 12
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
Figure 10. IRA Flag Timing and First Available Write when FIFO1 is Full
18
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
CSA
LOW
W/RA
LOW
LOW
MBA
ENA
tENS2
tENH
ORA HIGH
tA
Previous Word in FIFO2 Output Register
SKEW1
Next Word From FIFO2
A0 -A35
(1)
t
tCLK
tCLKH
tCLKL
1
2
CLKB
IRB
tPIR
tPIR
FIFO2 FULL
CSB LOW
LOW
W/RB
tENH
tENS2
MBB
tENS2
tENH
ENB
tDS
tDH
Wriite
B0 - B35
To FIFO2
3022 drw 13
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown.
Figure 11. IRB Flag Timing and First Available Write when FIFO2 is Full
CLKA
tENS2
tENH
ENA
(1)
tSKEW2
1
2
CLKB
t
PAE
t
PAE
(X1+1) Words in FIFO1
ENS2
X1 Words in FIFO1
AEB
t
tENH
ENB
3022 drw 14
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
Figure 12. Timing for AEB when FIFO1 is Almost-Empty
19
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKB
tEN2S
tENH
ENB
(1)
tSKEW2
1
CLKA
2
t
PAE
t
PAE
X2 Words in FIFO2
(X2+1) Words in FIFO2
ENS2
AEA
t
tENH
ENA
3022 drw 15
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge
and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
Figure 13. Timing for AEA when FIFO2 is Almost-Empty
(1)
tSKEW2
1
2
CLKA
ENA
AFA
t
ENS2
tENH
t
PAF
t
PAF
(D-Y1) Words in FIFO1
[D-(Y1+1)] Words in FIFO1
CLKB
ENB
tENH
tENS2
3022 drw 16
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge
and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT723622, 512 for the IDT723632, 1,024 for the IDT723642.
Figure 14. Timing for AFA when FIFO1 is Almost-Full
20
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
(1)
tSKEW2
1
2
CLKB
tENS2
tENH
tPAF
ENB
tPAF
(D-Y2) Words in FIFO2
AFB
[D-(Y2+1)] Words in FIFO2
CLKA
tENH
tENS2
ENA
3022 drw 17
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge
and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKB cycle later than shown.
2. FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT723622, 512 for the IDT723632, 1,024 for the IDT723642.
Figure 15. Timing for AFB when FIFO2 is Almost-Full
CLKA
tENH
tENS1
CSA
W/RA
MBA
t
ENH
t
ENS1
ENS2
t
ENH
t
tENH
tENS2
ENA
A0 - A35
CLKB
tDH
t
DS
W1
t
PMF
t
PMF
MBF1
CSB
W/RB
MBB
ENB
tENS2
tENH
t
MDV
tEN
t
PMR
tDIS
FIFO1 Output Register
W1 (Remains valid in Mail1 Register after read)
B0 - B35
3022 drw 18
Figure 16. Timing for Mail1 Register and MBF1 Flag
21
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
CLKB
tENS1
tENH
CSB
W/RB
MBB
ENB
t
ENS1
ENS2
t
ENH
t
t
ENH
tENS2
t
t
ENH
DH
tDS
W1
B0-B35
CLKA
t
PMF
tPMF
MBF2
CSA
W/RA
MBA
ENA
tENH
tENS2
t
PMR
tEN
tDIS
t
MDV
W1 (Remains valid in Mail 2 Register after read)
A0-A35
3022 drw19
FIFO2 Output Register
Figure 17. Timing for Mail2 Register and MBF2 Flag
22
IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIALTEMPERATURERANGE
PARAMETER MEASUREMENT INFORMATION
5 V
1.1 k Ω
From Output
Under Test
30 pF(1)
680Ω
PROPAGATION DELAY
LOAD CIRCUIT
3 V
3 V
Timing
Input
1.5 V
High-Level
1.5 V
Input
1.5 V
GND
GND
3 V
t
S
th
t
W
3 V
Data,
Enable
Input
1.5 V
1.5 V
Low-Level
1.5 V
1.5 V
GND
Input
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Enable
1.5 V
1.5 V
t
PZL
GND
t
PLZ
3 V
GND
≈
3 V
Input
1.5 V
1.5 V
1.5 V
Low-Level
Output
V
OL
t
PD
t
PZH
tPD
V
OH
V
OH
OV
In-Phase
Output
1.5 V
1.5 V
High-Level
Output
1.5 V
t
PHZ
V
OL
≈
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
3022 drw 20
NOTE:
1. Includes probe and jig capacitance.
Figure 18. Load Circuit and Voltage Waveforms
23
ORDERING INFORMATION
XXXXXX
X
XX
X
X
X
X
Device Type Power
Speed
Package
Process/
Temperature
Range
BLANK
8
Tube or Tray
Tape and Reel
BLANK
Commercial (0°C to +70°C)
Green
G
PF
Thin Quad Flat Pack (TQFP, PNG120)
Clock Cycle Time (tCLK
)
Commercial Only
Low Power
15
L
Speed in Nanoseconds
723622
723632
723642
256 x 36 x 2 - SyncBiFIFO
512 x 36 x 2 - SyncBiFIFO
1,024 x 36 x 2 - SyncBiFIFO
™
™
™
3022 drw 21
DATASHEETDOCUMENTHISTORY
10/04/2000
03/21/2001
08/01/2001
12/18/2001
02/05/2009
02/19/2015
pgs. 1 through 25, except pages 35.
pgs. 6 and 7.
pgs. 1, 6, 8, 9 and 25.
pg. 23.
pgs. 1 and 25.
pgs. 1, 2, 5, 7, 8, 9 and 24.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
for Tech Support:
408-360-1753
email:FIFOhelp@idt.com
www.idt.com
24
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