72401L35PDG [IDT]

FIFO, 64X4, Asynchronous, CMOS, PDIP16;


型号：	72401L35PDG
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	FIFO, 64X4, Asynchronous, CMOS, PDIP16 时钟先进先出芯片光电二极管内存集成电路
文件：	总9页 (文件大小：275K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT72401

IDT72403

CMOSPARALLELFIFO

64 x 4

hasanOutputEnable(OE)pin.TheFlFOsaccept4-bit dataatthedatainput

(D0-D3). The stored data stack up on a first-in/first-out basis.

AShiftOut(SO)signalcausesthedataatthenexttolastwordtobeshifted

totheoutputwhileallotherdatashiftsdownonelocationinthestack.TheInput

Ready (IR) signal acts like a flag to indicate when the input is ready for new

data(IR=HIGH)or tosignalwhentheFIFOisfull(IR=LOW). TheIRsignal

canalsobeusedtocascademultipledevicestogether.TheOutputReady(OR)

signal is a flag to indicate that the output remains valid data (OR = HIGH) or

to indicate that the FIFO is empty (OR = LOW). The OR can also be used to

cascademultipledevicestogether.

FEATURES:

• First-ln/First-Out Dual-Port memory

• 64 x 4 organization (IDT72401/72403)

• RAM-based FIFO with low falI-through time

• Low-power consumption

— Active: 175mW (typ.)

• Maximum shift rate — 45MHz

• High data output drive capability

• Asynchronous and simultaneous read and write

• Fully expandable by bit width

WidthexpansionisaccomplishedbylogicallyANDingtheIRandORsignals

toformcompositesignals.

• Fully expandable by word depth

• IDT72403 have Output Enable pin to enable output data

• High-speed data communications applications

• High-performance CMOS technology

• Available in CERDIP, plastic DIP and SOIC

• Military product compliant to MlL-STD-883, Class B

• Standard Military Drawing #5962-86846 and

5962-89523 is listed on this function.

• Green parts available, see ordering information

Depthexpansionisaccomplishedbytyingthedatainputsofonedeviceto

thedataoutputsofthepreviousdevice. TheIRpinofthereceivingdeviceis

connectedtotheSOpinofthesendingdeviceandtheORpinofthesending

device is connected to the Shift In (SI) pin of the receiving device.

Readingandwritingoperationsarecompletelyasynchronousallowingthe

FIFO to be used as a buffer between two digital machines of widely varying

operatingfrequencies.The45MHzspeedmakestheseFlFOsidealforhigh-

speed communicationandcontrollerapplications.

MilitarygradeproductismanufacturedincompliancewiththeofMIL-STD-

883, Class B.

DESCRIPTION:

The IDT72401 and IDT72403 are asynchronous high-performance

First-ln/First-Outmemoriesorganized64wordsby4bits. TheIDT72403 also

FUNCTIONALBLOCKDIAGRAM

INPUT

CONTROL

LOGIC

WRITE POINTER

OUTPUT

ENABLE

WRITE MULTIPLEXER

(IDT72403 only)

MEMORY

ARRAY

D0-3

DATA IN

Q0-3

MASTER

RESET

READ MULTIPLEXER

READ POINTER

MASTER

RESET

2747 drw01

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.

FASTisatrademarkofNationalSemiconductor,Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

JUNE 2012

DSC-2747/13

IDT72401/72403

CMOS PARALLEL FIFO 64 x 4, 64 x 5

MILITARY AND COMMERCIAL

TEMPERATURE RANGES

PINCONFIGURATIONS

IDT72401/IDT72403

NC/OE⁽¹⁾

Vcc

15 SO

GND

2747 drw 02

PLASTIC DIP (P16-1, ORDER CODE: P)

CERDIP (D16-1, ORDER CODE: D)

SOIC (SO16-1, ORDER CODE: SO)

TOP VIEW

NOTE:

1. Pin 1: NC - No Connection IDT72401, OE - IDT72403

RECOMMENDEDOPERATING

CONDITIONS

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

Symbol

Parameter

Min. Typ. Max. Unit

Symbol

Rating

Commercial

Military

Unit

VCC

Supply Voltage Commercial/Military 4.5

5.0

5.5

VTERM

TerminalVoltagewith

Respect to GND

–0.5 to +7.0

GND SupplyVoltage

VIH

InputHighVoltage

2.0

—

0.8

TSTG

IOUT

StorageTemp.

–55 to +125

–50 to +50

–65 to +150

–50 to +50

°C

VIL⁽¹⁾InputHighVoltage

DCOutputCurrent

OperatingTemperatureCommercial

OperatingTemperatureMilitary

—

°C

NOTE:

–55

125 °C

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

NOTE:

1. 1.5V undershoots are allowed for 10ns once per cycle.

DCELECTRICALCHARACTERISTICS

(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V

± 10%, TA = –55°C to +125°C)

IDT72401

IDT72403

IDT72401

IDT72403⁽⁵⁾

Commercial

Military

fIN = 45, 35, 25, 15, 10 MHz

fIN = 35, 25, 15, 10 MHz

Symbol

IIL

Parameter

Low-LevelInputCurrent

Test Conditions

VCC = Max., GND ≤ VI ≤ VCC

VCC= Max., GND ≤ VI ≤ VCC

VCC= Min., IOL = 8mA

Min.

–10

—

Max.

—

Min.

–10

—

Max.

—

Unit

μA

IIH

High-LevelInputCurrent

Low-LevelOutputVoltage

High-LevelOutputVoltage

OutputShort-CircuitCurrent

HIGH Impedance Output Current

LOWImpedanceOutputCurrent

Active Supply Current

VOL

—

0.4

—

0.4

—

VOH

IOS⁽¹⁾

IHZ⁽²⁾

ILZ⁽²⁾

ICC^(3,4)

VCC= Min., IOH = –4mA

VCC= Max., VO = GND

VCC= Max., VO = 2.4V

VCC= Max., VO = 0.4V

VCC= Max., f = 10MHz

2.4

–20

—

2.4

–20

—

–110

μA

–20

—

–20

—

NOTES:

1. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Guaranteed but not tested.

2. IDT72403 only.

3. Tested with outputs open (IOUT = 0). OE is HIGH for IDT72403.

4. For frequencies greater than 10MHz, ICC = 35mA + (1.5mA x [f –10MHz]) commercial, and ICC = 45mA + (1.5mA x [f –10MHz]) military.

5. Military availability for IDT72403 is 10MHz, 35MHz. IDT72401 is available for all MHz.

JUNE 29, 2012

IDT72401/72403

CMOS PARALLEL FIFO 64 x 4, 64 x 5

MILITARY AND COMMERCIAL

TEMPERATURE RANGES

OPERATINGCONDITIONS

(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C)

Commercial

Commercial and Military⁽⁵⁾

IDT72401L45

IDT72403L45

IDT72401L35

IDT72403L35

IDT72401L25

IDT72403L25

IDT72401L15

IDT72403L15

IDT72401L10

IDT72403L10

Symbol

tSIH⁽¹⁾

tSIL

Parameter

Shift in HIGH Time

Figure Min.

Max.

—

Min.

Max.

—

Min.

Max.

—

Min.

Max.

—

Min.

Max.

—

Unit

Shift in LOW TIme

tIDS

InputDataSet-up

tIDH

tSOH⁽¹⁾

InputDataHoldTime

Shift Out HIGH Time

Shift Out LOW Time

Master Reset Pulse

Master Reset Pulse to SI

Data Set-up to IR

tSOL

tMRW

tMRS

tSIR

tHIR

tSOR⁽⁴⁾

Data Hold from IR

Data Set-up to OR HIGH

ACELECTRICALCHARACTERISTICS

(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C)

Commercial

Commercial and Military⁽⁵⁾

IDT72401L45

IDT72403L45

IDT72401L35

IDT72403L35

IDT72401L25

IDT72403L25

IDT72401L15

IDT72403L15

IDT72401L10

IDT72403L10

Symbol

fIN

Parameter

Figure Min.

Max.

—

Min.

—

Max.

—

Min.

—

Max.

—

Min.

—

Max.

—

Min.

—

Max.

—

Unit

MHz

ShiftInRate

—

tIRL⁽¹⁾

tIRH⁽¹⁾

fOUT

Shift In to Input Ready LOW

Shift In to Input Ready HIGH

ShiftOutRate

MHz

tORL⁽¹⁾

tORH⁽¹⁾

tODH

Shift Out to Output Ready LOW

Shift Out to Output Ready HIGH

OutputDataHold(PreviousWord)

OutputDataShift(NextWord)

DataThroughputor"Fall-Through"

Master Reset to OR LOW

tODS

—

tPT

4, 7

tMRORL

tMRIRH

Master Reset to IR HIGH

tMRQ

MasterResettoDataOutputLOW

Output Valid from OE LOW

—

tOOE⁽³⁾

tHZOE^(3,4)Output High-Z from OE HIGH

tIPH^(2,4)

Input Ready Pulse HIGH

Output Ready Pulse HIGH

tOPH^(2,4)

NOTES:

1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding and decoupling

are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding.

A monolithic ceramic capacitor of 0.1μF directly between VCC and GND with very short lead length is recommended.

2. This parameter applies to FIFOs communicating with each other in a cascaded mode. IDT FIFOs are guaranteed to cascade with other IDT FIFOs of like speed grades.

3. IDT72403 only.

4. Guaranteed by design but not currently tested.

5. Military availability for IDT72403 is 10MHz, 35MHz. IDT72401 is available for all MHz.

JUNE 29, 2012

IDT72401/72403

CMOS PARALLEL FIFO 64 x 4, 64 x 5

MILITARY AND COMMERCIAL

TEMPERATURE RANGES

ALLINPUTPULSES:

ACTESTCONDITIONS

InputPulseLevels

GND to 3.0V

3ns

3.0V

90%

10%

InputRise/FallTimes

InputTimingReferenceLevels

OutputReferenceLevels

OutputLoad

10%

1.5V

GND

1.5V

<3ns

2747 drw 04

SeeFigure1

1.1KΩ

CAPACITANCE

OUTPUT

30pF*

(TA = +25°C, f = 1.0MHz)

560Ω

Symbol

CIN

Parameter

Conditions

VIN = 0V

Max.

Unit

InputCapacitance

OutputCapacitance

2747 drw 05

COUT

VOUT = 0V

NOTE:

1. Characterized values, not currently tested.

orequivalentcircuit

Figure 1. AC Test Load

*Includingscopeandjig

INPUT READY (IR)

SIGNALDESCRIPTIONS

WhenInputReadyisHIGH,theFIFOisreadyfornewinputdatatobewritten

toit.WhenIRisLOWtheFIFOisunavailablefornewinputdata. IRisalsoused

to cascade many FlFOs together, as shown in Figures 10 and 11.

INPUTS:

DATA INPUT (D0-3)

Data input lines. The IDT72401 and IDT72403 have a 4-bit data input.

OUTPUTREADY(OR)

WhenOutputReadyisHIGH,theoutput(Q0-3)containsvaliddata. When

OR is LOW, the FIFO is unavailable for new output data. OR is also used to

cascade many FlFOs together, as shown in Figures 10 and 11.

CONTROLS:

SHIFT IN (SI)

ShiftIncontrolstheinputofthedataintotheFIFO. WhenSIisHIGH, data

can be written to the FIFO via the D0-3 lines.

OUTPUT ENABLE (OE) (IDT72403 ONLY)

Output enable is used to read FIFO data onto a bus. OE is active LOW.

SHIFT OUT (SO)

ShiftOutcontrolstheoutputofdataoftheFIFO. WhenSOisHIGH,datacan

be read from the FIFO via the Data Output (Q0-3) lines.

OUTPUTS:

DATAOUTPUT(Q0-3)

DataOutputlines.TheIDT72401andIDT72403havea4-bitdataoutput.

MASTER RESET (MR)

MasterResetclearstheFIFOofanydatastoredwithin. Uponpowerup,the

FIFO should be cleared with a MR. MR is active LOW.

JUNE 29, 2012

IDT72401/72403

CMOS PARALLEL FIFO 64 x 4, 64 x 5

MILITARY AND COMMERCIAL

TEMPERATURE RANGES

DATAOUTPUT

FUNCTIONALDESCRIPTION

DataisshiftedoutontheHlGH-to-LOWtransitionofShiftOut(SO). Thiscauses

the internal read pointer to be advanced to the next word location. If data is

present,validdatawillappearontheoutputsandOutputReady(OR)will go

HIGH. Ifdataisnotpresent,ORwillstayLOWindicatingtheFIFOisempty. The

lastvalidwordreadfromtheFIFOwillremainattheFlFOsoutputwhenitisempty.

WhentheFIFOisnotempty,ORgoesLOWontheLOW-to-HIGHtransitionof

SO. PreviousdataremainsontheoutputuntiltheHIGH-to-LOWtransitionof

SO).

The 64x4FIFOisdesigned usinga dual port RAMarchitecture asopposed

to the traditional shift register approach. This FIFO architecture has a write

pointer, a read pointer and control logic, which allow simultaneous read and

writeoperations. ThewritepointerisincrementedbythefallingedgeoftheShift

In(Sl)control;thereadpointerisincrementedbythefallingedgeoftheShiftOut

(SO). TheInputReady(IR)signalswhentheFIFOhasanavailablememory

location; Output Ready (OR) signals when there is valid data on the output.

OutputEnable(OE)providesthecapabilityofthree-statingtheFIFOoutputs.

FALL THROUGH MODE

TheFIFOoperatesinafall-throughmodewhendatagetsshiftedintoanempty

FIFO. Afterafall-throughdelaythedatapropagatestotheoutput. Whenthe

datareachestheoutput,theOutputReady(OR)goesHIGH. Fall-throughmode

alsooccurswhentheFIFOiscompletelyfull. Whendataisshiftedoutofthefull

FIFO,alocationisavailablefornewdata. Afterafall-throughdelay,theInput

Ready (IR) goes HIGH. If Shift In (SI) is HIGH, the new data can be written

to the FIFO.

SincetheseFlFOsarebasedonaninternaldual-portRAMarchitecturewith

separatereadandwritepointers,thefall-throughtime(tPT)isonecyclelong.

AwordmaybewrittenintotheFIFOonaclockcycleandcanbeaccessedon

thenextclockcycle.

FIFO RESET

TheFIFOmustberesetuponpowerupusingtheMasterReset(MR)signal.

ThiscausestheFlFOtoenteranemptystate,signifiedbyOutputReady(OR)

beingLOWandInputReady(IR)beingHIGH. Inthisstate, thedataoutputs

(Q0-3) will be LOW.

DATAINPUT

DataisshiftedinontheLOW-to-HlGHtransitionofShiftIn(Sl).Thisloads

inputdataintothefirstwordlocationoftheFIFOandcausesInputReady(IR)

togoLOW.OntheHlGH-to-LOWtransitionofSI,thewritepointerismovedto

thenextwordpositionandIRgoesHIGH,indicatingthereadinesstoacceptnew

data. If the FIFO is full, IR will remain LOW until a word of data is shifted out.

1/fIN

tSIH

tSIL

tIRH

tIDS

tIRL

tIDH

INPUT DATA

2747 drw 06

Figure 2. Input Timing

SI⁽⁷⁾

(2)

(4)

(1)

(5)

(3)

(6)

INPUT DATA

STABLE DATA

2747 drw 07

NOTES:

1. IR HIGH indicates space is available and a SI pulse may be applied.

2. Input Data is loaded into the first word.

3. IR goes LOW indicating the first word is full.

4. The write pointer is incremented.

5. The FIFO is ready for the next word.

6. If the FIFO is full then the IR remains LOW.

7. SI pulses applied while IR is LOW will be ignored (see Figure 4).

Figure 3. The Mechanism of Shifting Data Into the FIFO

JUNE 29, 2012

IDT72401/72403

CMOS PARALLEL FIFO 64 x 4, 64 x 5

MILITARY AND COMMERCIAL

TEMPERATURE RANGES

(2)

(3)

(5)

tIPH

tPT

(4)

(1)

tSIR

tHIR

INPUT DATA

STABLE DATA

2747 drw 08

NOTES:

1. FIFO is initially full.

2. SO pulse is applied.

3. SI is held HIGH.

4. As soon as IR becomes HIGH the Input Data is loaded into the FIFO.

5. The write pointer is incremented. SI should not go LOW until (tPT + tIPH).

Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH

1/fOUT

tSOH

tSOL

(2)

tORH

tORL

tODS

tODH

(1)

A-DATA

B-DATA

C-DATA

OUTPUT DATA

2747 drw 09

NOTES:

1. This data is loaded consecutively A, B, C.

2. Data is shifted out when SO makes a HIGH to LOW transition.

Figure 5. Output TIming

SO⁽⁷⁾

(2)

(4)

(1)

(5)

(3)

(6)

A or B

OUTPUT DATA

A- DATA

B- DATA

2747 drw 10

NOTES:

1. OR HIGH indicates that data is available and a SO pulse may be applied.

2. SO goes HIGH causing the next step.

3. OR goes LOW.

4. The read pointer is incremented.

5. OR goes HIGH indicating that new data (B) is now available at the FIFO outputs.

6. If the FIFO has only one word loaded (A DATA) then OR stays LOW and the A DATA remains unchanged at the outputs.

7. SO pulses applied when OR is LOW will be ignored.

Figure 6. The Mechanism of Shifting Data Out of the FIFO

JUNE 29, 2012

IDT72401/72403

CMOS PARALLEL FIFO 64 x 4, 64 x 5

MILITARY AND COMMERCIAL

TEMPERATURE RANGES

tOPH

tPT

(1)

tSOR

DATA VALID

DATA OUTPUT

2747 drw 11

NOTE:

1. FIFO initially empty.

Figure 7. tPT and tOPH Specification

tMRW

MRIRH

(1)

MRORL

tMRS

tMRQ

DATA OUTPUT

NOTE:

2747 drw 12

1. Worst case, FIFO initially full.

Figure 8. Master Reset Timing

HZOE

tOOE

DATA OUT

2747 drw 13

NOTE:

1. High-Z transitions are referenced to the steady-state VOH –500mV and VOL +500mV levels on the output. tHZOE is tested with 5pF load capacitance instead of 30pF as

shown in Figure 1.

Figure 9. Output Enable Timing, IDT72403 Only

OUTPUT READY

SHIFT OUT

SHIFT IN

INPUT READY

DATA OUT

DATA IN

2747 drw 14

NOTE:

1. FIFOs can be easily cascaded to any desired path. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the devices.

Figure 10. 128 x 4 Depth Expansion

JUNE 29, 2012

IDT72401/72403

CMOS PARALLEL FIFO 64 x 4, 64 x 5

MILITARY AND COMMERCIAL

TEMPERATURE RANGES

SHIFT OUT

COMPOSITE

INPUT

COMPOSITE

OUTPUT

READY

SHIFT IN

2747 drw 15

NOTES:

1. When the memory is empty, the last word will remain on the outputs until the MR is strobed or a new data word falls through to the output. However, OR will remain LOW,

indicating data at the output is not valid.

2. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data and stays LOW until the new data

has appeared on the outputs. Anytime OR is HIGH, there is valid stable data on the outputs.

3. If SO is held HIGH while the memory is empty and a word is written into the input, that word will appear at the output after a fall-through time. OR will go HIGH for one

internal cycle (at least tORL) and then go back LOW again. The stored word will remain on the outputs. If more words are written into the FIFO, they will line up behind the

first word and will not appear on the outputs until SO has been brought LOW.

4. When the MR is brought LOW, the outputs are cleared to LOW, IR goes HIGH and OR goes LOW. If SI is HIGH when the MR goes HIGH, the data on the inputs will be

written into the memory and IR will return to the LOW state until SI is brought LOW. If SI is LOW when the MR is ended, IR will go HIGH, but the data in the inputs will not

enter the memory until SI goes HIGH.

5. FIFOs are expandable on depth and width. However, in forming wider words, two external gates are required to generate composite Input and OR flags. This is due to the

variation of delays of the FIFOs.

Figure 11. 192 x 12 Depth and Width Expansion

JUNE 29, 2012

ORDERINGINFORMATION

XXXXX

Device Type Power Speed Package

Process/

Temperature

Range

Blank

Tube or Tray

Tape and Reel

Blank

Commercial (0°C to+70°C)

Military (-55°C to+125°C)

Compliant to MIL-STD-883, Class B

G⁽²⁾

Green

P⁽³⁾

Plastic DIP

CERDIP

Small Outline IC

300 mil, P16-1

300 mil, D16-1

SOIC, SO16-1

Commercial Only

Commercial and Military

Commercial and Military>72401 only

Commercial and Military>72401only

Commercial and Military

Shift Frequency (fs)

Speed in MHz

Low Power

72401 64 x 4 FIFO

72403 64 x 4 FIFO

2747 drw 16

NOTES:

1. Industrial temperature range is available by special order.

2. Green parts are available, for specific speeds and packages contact your sales office.

3. For “P”, Plastic Dip, when ordering green package, the suffix is “PDG”.

DATASHEETDOCUMENTHISTORY

07/10/2003 pgs. 2, 3, and 9.

10/27/2005 pgs. 1- 9.

04/25/2008 pgs. 1- 9.

02/11/2009 pg. 9.

06/29/2012 pgs. 1 and 9.

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

800-345-7015 or 408-284-8200

fax: 408-284-2775

for Tech Support:

408-360-1753

email:FIFOhelp@idt.com

www.idt.com

72401L35PDG [IDT]

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