72805LB25BG8 [IDT]
PBGA-121, Reel;
| 型号： | 72805LB25BG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PBGA-121, Reel |
| 文件： | 总26页 (文件大小：281K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT72805LB
IDT72815LB
IDT72825LB
IDT72835LB
IDT72845LB
CMOS DUAL SyncFIFO™
DUAL 256 x 18, DUAL 512 x 18,
DUAL 1,024 x 18, DUAL 2,048 x 18
and DUAL 4,096 x 18
• Single or double register-buffered Empty and Full Flags
• Easily expandable in depth and width
• Asynchronous or coincident Read and Write clocks
• Asynchronous or synchronous programmable Almost-Empty
and Almost-Full flags with default settings
FEATURES:
• The IDT72805LB is equivalent to two IDT72205LB 256 x 18 FIFOs
• The IDT72815LB is equivalent to two IDT72215LB 512 x 18 FIFOs
• The IDT72825LBis equivalenttotwoIDT72225LB1,024 x 18FIFOs
• The IDT72835LBis equivalenttotwoIDT72235LB2,048 x 18FIFOs
• The IDT72845LBis equivalenttotwoIDT72245LB4,096 x 18FIFOs
• Offers optimal combination of large capacity (8K), high speed,
design flexibility, and small footprint
• Half-Full flag capability
• Output Enable puts output data bus in high-impedance state
• High-performance submicron CMOS technology
• Available in the 128-pin Thin Quad Flatpack (TQFP). Also
available for the IDT72805LB/72815LB/72825LB, in the 121-lead,
16 x 16 mm plastic Ball Grid Array (PBGA)
• Ideal for the following applications:
-
-
-
-
-
-
Network switching
Two level prioritization of parallel data
Bidirectional data transfer
Bus-matching between 18-bit and 36-bit data paths
Width expansion to 36-bit per package
Depth expansion to 8,192 words per package
• Industrial temperature range (–40°C to +85°C) is available
• Green parts available, see ordering information
DESCRIPTION:
TheIDT72805LB/72815LB/72825LB/72835LB/72845LBaredual18-bit-wide
synchronous(clocked)First-in,First-out(FIFO)memories.OnedualIDT72805LB/
• 10ns read/write cycle time, 6.5ns access time
• IDT Standard or First Word Fall Through timing
FUNCTIONAL BLOCK DIAGRAM
HFA/(WXOA)
PAEA
FFA/IRA
EFA/
ORA
WCLKA
WCLKB
DA0-DA17
WENA
LDA
WENB
DB0-DB17
LDB
PAFA
INPUT
OFFSET
INPUT
OFFSET
REGISTER
REGISTER
REGISTER
REGISTER
FFB/IRB
FLAG
PAFB
WRITE
FLAG
LOGIC
WRITE
EFB/ORB
PAEB
HFB/(WXOB)
CONTROL
LOGIC
RAM
LOGIC
CONTROL
LOGIC
ARRAY
RAM
256 x 18
512 x 18
1,024 x 18
2,048 x 18
4,096 x 18
ARRAY
256 x 18
512 x 18
1,024 x 18
2,048 x 18
4,096 x 18
READ
POINTER
WRITE
READ
POINTER
WRITE
POINTER
POINTER
READ
CONTROL
LOGIC
FLA
WXIA
(HFA)/WXOA
RXIA
READ
CONTROL
LOGIC
EXPANSION
LOGIC
EXPANSION
LOGIC
OUTPUT
REGISTER
OUTPUT
RXOA
REGISTER
RESET
LOGIC
RSA
RESET
LOGIC
RSB
RXOB
RXIB
(HFB)/WXOB
WXIB
FLB
RCLKB
RCLKA
OEB
QA0-QA17
RENB
RENA
OEA
QB0-QB17
3139 drw 01
IDTandtheIDTlogoareregisteredtrademarks.TheSyncFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
JANUARY 2009
©2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-3139/8
IDT72805LB/72815LB/72825LB/72835LB/72845LBCMOSDualSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
Almost-Empty(PAE)andAlmost-Full(PAF).Theoffsetloadingoftheprogram-
mableflagsiscontrolledbyasimplestatemachine,andisinitiatedbyasserting
the Load pin (LD). A Half-Full flag (HF) is available for each FIFO that is
implemented as a single device configuration.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard Mode, the first word written to an empty FIFO will not
appear on the data output lines unless a specific read operation is performed.
Areadoperation,whichconsistsofactivatingRENandenablingarisingRCLK
edge, will shift the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A REN does
not have to be asserted for accessing the first word.
Thesedevicesaredepthexpandableusingadaisy-chaintechniqueorFirst
WordFallThrough(FWFT)mode. TheXI and XO pins areusedtoexpandthe
FIFOs.Indepthexpansionconfiguration,FLisgroundedonthefirstdeviceand
set to HIGH for all other devices in the Daisy Chain.
DESCRIPTION (Continued)
72815LB/72825LB/72835LB/72845LB device is functionally equivalent to two
IDT72205LB/72215LB/72225LB/72235LB/72245LB FIFOs in a single pack-
agewithallassociatedcontrol,data,andflaglinesassignedtoindependentpins.
These devices are very high-speed, low-power First-In, First-Out (FIFO)
memorieswithclockedreadandwritecontrols.TheseFIFOsareapplicablefor
awidevarietyofdatabufferingneeds,suchasopticaldiskcontrollers,LocalArea
Networks(LANs),andinterprocessorcommunication.
Each of the two FIFOs contained in these devices has an 18-bit input and
output port. Each input port is controlled by a free-running clock (WCLK), and
an input enable pin (WEN). Data is read into the synchronous FIFO on every
clock when WEN is asserted. The output port of each FIFO bank is controlled
by another clock pin (RCLK) and another enable pin (REN). The Read Clock
can be tied to the Write Clock for single clock operation or the two clocks can
run asynchronous of one another for dual-clock operation. An Output Enable
pin(OE)is providedonthereadportofeachFIFOforthree-statecontrolofthe
output.
The IDT72805LB/72815LB/72825LB/72835LB/72845LB are fabricated
using IDT’s high-speed submicron CMOS technology.
The synchronous FIFOs have two fixed flags, Empty Flag/Output Ready
(EF/OR) and Full Flag/Input Ready (FF/IR), and two programmable flags,
PIN CONFIGURATIONS
PIN 1
LDB
OEB
DB17
VCC
VCC
VCC
RSB
EFB
A
B
C
D
E
F
WCLKA
PAFA
FFA
DA3
DA1
WENA
WXIA
QA2
DA0
DA2
DA5
FLA
DB13
DB16 RCLKB
QB17
QB15
QB13
QB10
QB9
QB16
QB14
QB11
QB8
RENB
GND
DB7
DA4
DB12
DB14
DB8
DB15
DB11
DB10
DB9
RXIA
GND
QB12
VCC
GND
RXOA
QA1
QA0
QA4
QA6
WXOA/
HFA
PAEA
GND
QA3
DB6
QB7
QA5
GND
VCC
VCC
GND
GND
PAEB
QB6
QB5
WXOB/
HFB
G
QA7
QA9
VCC
DA6
DA7
DA9
QB3
QB4
QB1
RXOB
FFB
FLB
DB5
DB2
DB0
H
J
QA8
QA10
QA13
QA15
QA17
QA12
GND
EFA
VCC
DA17
OEA
LDA
DA10
DA11
DA15
DA16
DA8
QB2
WXIB
WENB
DB1
QB0
RXIB
QA11
QA14
QA16
GND
DA14
DA12
DA13
RENA
RCKLA
PAFB
WCLKB
K
L
DB4
DB3
RSA
1
2
3
4
5
6
7
8
9
10
11
3139 drw 02
PBGA(BG121-1,ordercode:BG)
TOP VIEW
NOTE:
1. The PBGA is only available for the IDT72805LB/72815LB/72825LB in the 15 or 25 ns speed grade.
JANUARY 13, 2009
2
IDT72805LB/72815LB/72825LB/72835LB/72845LBCMOSDualSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
PIN CONFIGURATIONS (Continued)
INDEX
V
PAFA
RXIA
CC
LDA
OEA
RSA
1
2
3
4
5
6
7
8
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
FFA
VCC
WXOA/HFA
RXOA
QA0
GND
EFA
QA17
QA16
GND
QA15
QA1
GND
QA2
QA3
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
VCC
VCC
QA14
QA13
GND
QA12
QA11
QA4
GND
QA5
QA6
QA7
QA8
GND
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
PAEB
VCC
QA10
QA9
DB8
DB9
DB10
DB11
DB12
DB13
DB14
DB15
DB16
DB17
GND
RCLKB
RENB
LDB
FLB
WCLKB
WENB
WXIB
V
PAFB
RXIB
CC
OEB
RSB
VCC
FFB
GND
EFB
WXOB/HFB
RXOB
3139 drw 02a
TQFP (PK128-1, order code: PF)
TOP VIEW
JANUARY13,2009
3
IDT72805LB/72815LB/72825LB/72835LB/72845LBCMOSDualSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
PIN DESCRIPTION
Symbol
Name
I/O
Description
DA0–DA17
DB0-DB17
DataInputs
I
Datainputsforan18-bitbus.
RSA
RSB
WCLKA
WCLKB
Reset
I
I
I
I
I
I
I
When RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF and
PAF go HIGH, and PAE and EF go LOW. A reset is required before an initial WRITE after power-up.
When WEN is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK, if the FIFO is not full.
Write Clock
Write Enable
Read Clock
Read Enable
Output Enable
Load
WENA
WENB
RCLKA
RCLKB
When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. When WEN is
HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the FF is LOW.
When REN is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the FIFO is not empty.
RENA
RENB
OEA
OEB
LDA
LDB
When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. When REN is HIGH,
the output register holds the previous data. Data will not be read from the FIFO if the EF is LOW.
When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance
state.
When LD is LOW, data on the inputs D0–D11 is written to the offset and depth registers on the LOW-to-HIGH
transition of the WCLK, when WEN is LOW. When LD is LOW, data on the outputs Q0–Q11 is read from the
offset and depth registers on the LOW-to-HIGH transition of the RCLK, when REN is LOW.
FLA
FLB
First Load
I
I
I
In the single device or width expansion configuration, FL together with WXI and RXI determine if the mode is
IDT Standard mode or First Word Fall Through (FWFT) mode, as well as whether the PAE/PAF flags are
synchronous or asynchronous. (See Table I.) In the Daisy Chain Depth Expansion configuration, FL is grounded
on the first device (first load device) and set to HIGH for all other devices in the Daisy Chain.
WXIA
WXIB
Write Expansion
Input
In the single device or width expansion configuration, WXI together with FL and RXI determine if the mode is
IDT Standard mode or FWFT mode, as well as whether the PAE/PAF flags are synchronous or asynchronous.
(See Table 1.) In the Daisy Chain Depth Expansion configuration, WXI is connected to WXO (Write Expansion
Out) of the previous device.
RXIA
RXIB
Read Expansion
Input
In the single device or width expansion configuration, RXI together with FL and WXI, determine if the mode is
IDT Standard mode or FWFT mode, as well as whether the PAE/PAF flags are synchronous or asynchronous.
(See Table 1.) In the Daisy Chain Depth Expansion configuration, RXI is connected to RXO (Read Expansion
Out) of the previous device.
FFA/IRA
FFB/IRB
Full Flag/
Input Ready
O
O
O
O
O
In the IDT Standard mode, the FF function is selected FF indicates whether or not the FIFO memory is full. In
the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to
the FIFO memory.
EFA/ORA
EFB/ORB
Empty Flag/
Output Ready
In the IDT Standard mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty.
In FWFT mode, the OR function is selected. OR indicates whether or not there is valid data available at the
outputs.
PAEA
PAEB
Programmable
Almost-Empty flag
When PAE is LOW, the FIFO is almost-empty based on the offset programmed into the FIFO. The default
offset at reset is 31 from empty for IDT72805LB, 63 from empty for IDT72815LB, and 127 from empty for
IDT72825LB/72835LB/72845LB.
PAFA
PAFB
Programmable
Almost-Full flag
When PAF is LOW, the FIFO is almost-full based on the offset programmed into the FIFO. The default offset
at reset is 31 from full for IDT72805LB, 63 from full for IDT72815LB, and 127 from full for IDT72825LB/72835LB/
72845LB.
WXOA/HFA
WXOB/HFB
WriteExpansion
Out/Half-FullFlag
Inthe single device orwidthexpansionconfiguration, the device is more thanhalffullwhen HF is LOW. Inthe
depthexpansionconfiguration,apulseis sentfromWXOtoWXIofthenextdevicewhenthelastlocationin
the FIFO is written.
RXOA
RXOB
QA0–QA17
QB0-QB17
Read Expansion
Out
O
O
In the depth expansion configuration, a pulse is sent from RXO to RXI of the next device when the last location
in the FIFO is read.
Data Outputs
Data outputs for an 18-bit bus.
VCC
Power
+5V power supply pins.
Ground pins.
GND
Ground
JANUARY 13, 2009
4
IDT72805LB/72815LB/72825LB/72835LB/72845LBCMOSDualSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RECOMMENDED DC OPERATING
CONDITIONS
ABSOLUTE MAXIMUM RATINGS
Symbol
Rating
Commercial
Unit
VTERM
Terminal Voltage
–0.5 to +7.0
V
Symbol
Parameter
Min.
4.5
0
Typ.
5.0
0
Max.
5.5
0
Unit
V
with respect to GND
VCC
Supply Voltage (Com’l/Ind’l)
Supply Voltage (Com’l/Ind’l)
Input High Voltage (Com’l/Ind’l)
Input Low Voltage (Com’l/Ind’l)
TSTG
IOUT
Storage
Temperature
–55 to +125
–50 to +50
°C
GND
VIH
V
2.0
⎯
0
⎯
⎯
⎯
⎯
0.8
70
V
DC Output Current
mA
(1)
VIL
V
NOTE:
TA
TA
OperatingTemperature
Commercial
°C
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS maycause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
OperatingTemperature
Industrial
-40
⎯
85
°C
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V 10%, TA = -40°C to +85°C)
IDT72805LB
IDT72815LB
IDT72825LB
IDT72835LB
IDT72845LB
(1)
Com’l & Ind’l
tCLK = 10, 15, 25 ns
Symbol
Parameter
Min.
–1
Typ.
—
Max.
Unit
(2)
ILI
Input Leakage Current (any input)
Output Leakage Current
1
µA
µA
V
(3)
ILO
–10
2.4
—
—
10
—
0.4
VOH
VOL
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
—
—
V
(4,5,6)
ICC1
ICC2
Active Power Supply Current
Standby Current
—
—
—
—
100
10
mA
mA
(4,7)
NOTES:
1. Industrial Temperature Range Product for the 15ns speed grade is available as a standard device.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OE ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs open (IOUT = 0).
4. RCLK and WCLK toggle at 20 MHZ and data inputs switch at 10 MHz.
5. For the IDT72805LB/72815LB/72825LB the typical ICC1 = 2[1.81 + 1.12*fS + 0.02*CL*fS] (in mA);
for the IDT72835LB/72845LB the typical ICC1 = 2[2.85 + 1.30*fS + 0.02*CL*fS] (in mA).
These equations are valid under the following conditions:
VCC = 5V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE(TA = +25°C, f = 1.0MHz)
Symbol
Parameter(1)
Conditions
Max.
Unit
(2)
CIN
Input
VIN = 0V
10
pF
Capacitance
(1,2)
COUT
Output
VOUT = 0V
10
pF
Capacitance
NOTES:
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
JANUARY13,2009
5
IDT72805LB/72815LB/72825LB/72835LB/72845LBCMOSDualSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V 10%, TA = -40°C + 85°C)
Commercial
Com’l & Ind’l(1)
Commercial
IDT72805LB10
IDT72815LB10
IDT72825LB10
IDT72835LB10
IDT72845LB10
IDT72805LB15
IDT72815LB15
IDT72825LB15
IDT72835LB15
IDT72845LB15
IDT72805LB25
IDT72815LB25
IDT72825LB25
IDT72835LB25
IDT72845LB25
Symbol
fS
Parameter
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Min.
—
Max.
100
Min.
—
2
15
6
6
4
1
4
Max.
Min.
—
3
25
10
10
6
1
6
1
25
15
15
—
0
—
1
—
—
—
Max.
40
15
—
—
—
—
—
—
—
—
—
—
25
—
12
12
15
15
35
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
66.7
10
—
—
—
—
—
—
—
—
—
—
15
—
8
tA
2
10
4.5
4.5
3
0
3
0
10
8
8
—
0
—
1
—
—
—
6.5
—
—
—
—
—
—
—
—
—
—
15
—
6
tCLK
tCLKH
tCLKL
tDS
Data Setup Time
Data Hold Time
tDH
tENS
tENH
tRS
tRSS
tRSR
tRSF
tOLZ
tOE
Enable Setup Time
Enable Hold Time
Reset Pulse Width(2)
Reset Setup Time
Reset Recovery Time
Reset to Flag and Output Time
Output Enable to Output in Low-Z
Output Enable to Output Valid
Output Enable to Output in High-Z
Write Clock to Full Flag
1
15
10
10
—
0
—
1
—
—
—
(3)
(3)
tOHZ
tWFF
tREF
tPAFA
6
8
6.5
6.5
17
10
10
20
Read Clock to Empty Flag
Clock to Asynchronous Programmable
Almost-Full Flag
tPAFS
tPAEA
tPAES
Write Clock to Synchronous
Programmable Almost-Full Flag
Clock to Asynchronous Programmable
Almost-Empty Flag
Read Clock to Synchronous
Programmable Almost-Empty Flag
Clock to Half-Full flag
Clock to Expansion Out
Expansion In Pulse Width
Expansion In Setup Time
—
—
—
8
17
8
—
—
—
10
20
10
—
—
—
12
35
12
ns
ns
ns
tHF
tXO
tXI
—
—
3
3
5
17
6.5
—
—
—
—
—
6.5
5
20
10
—
—
—
—
—
10
10
10
35
15
—
—
—
ns
ns
ns
ns
ns
tXIS
tSKEW1
Skew time between Read Clock &
Write Clock for FF/IR and EF/OR
Skew time between Read Clock &
Write Clock for PAE and PAF
6
(4)
tSKEW2
12
—
15
—
17
—
ns
NOTES:
1. Industrial Temperature Range Product for the 15ns speed grade is available as a standard device.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
4. tSKEW2 applies to synchronous PAE and synchronous PAF only.
5V
1.1K
AC TEST CONDITIONS
D.U.T.
Input Pulse Levels
GND to 3.0V
3ns
30pF*
680Ω
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
1.5V
3139 drw 03
1.5V
Figure 1. Output Load
* Includes jig and scope capacitances.
See Figure 1
JANUARY 13, 2009
6
IDT72805LB/72815LB/72825LB/72835LB/72845LBCMOSDualSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
thedeviceis31awayfromcompletelyemptyforIDT72805LB,63awayfrom
completely empty for IDT72815LB, and 127 away from completely empty
for IDT72825LB/72835LB/72845LB. Continuing read operations will cause
the FIFOtobe empty. Whenthe lastwordhas beenreadfromthe FIFO, the
EF will go LOW inhibiting further read operations. REN is ignored when the
FIFO is empty.
FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72805LB/72815LB/72825LB/72835LB/72845LB support two
different timing modes of operation. The selection of which mode will
operate is determined during configuration at Reset (RS). During a RS
operation, the First Load (FL), Read Expansion Input ( RXI) and Write
Expansion Input (WXI) pins are used to select the timing mode per the truth
table shown in Table 3. In IDT Standard Mode, the first word written to an
empty FIFO will not appear on the data output lines unless a specific read
operationis performed. Areadoperation, whichconsists ofactivatingRead
Enable (REN) and enabling a rising Read Clock (RCLK) edge, will shift the
word from internal memory to the data output lines. In FWFT mode, the first
word written to an empty FIFO is clocked directly to the data output lines
after three transitions of the RCLK signal. A REN does not have to be
asserted for accessing the first word.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE and OR operate in the
manner outlined in Table 2. To write data into to the FIFO, WEN must be
LOW. Data presented to the DATA IN lines will be clocked into the FIFO on
subsequent transitions of WCLK. After the first write is performed, the
Output Ready (OR) flag will go LOW. Subsequent writes will continue to fill
up the FIFO. PAE will go HIGH after n + 2 words have been loaded into the
FIFO, where n is the Empty offset value. The default setting for this value
is stated in the footnote of Table 2. This parameter is also user program-
mable. See section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the HF would toggle to LOW once the 130th
(72805LB), 258th (72815LB), 514th (72825LB), 1,026th (72835LB), and
2,050th (72845LB) word respectively was written into the FIFO. Continuing
to write data into the FIFO will cause the PAF to go LOW. Again, if no reads
areperformed,thePAFwillgoLOWafter(257-m)writesfortheIDT72805LB,
(513-m) writes for the IDT72815LB, (1,025-m) writes for the IDT72825LB,
(2,049–m) writes for the IDT72835LB and (4,097–m) writes for the
IDT72845LB, where m is the Full offset value. The default setting for this
value is stated in the footnote of Table 2.
When the FIFO is full, the Input Ready (IR) flag will go HIGH, inhibiting
further write operations. If no reads are performed after a reset, IR will go
HIGH after D writes to the FIFO. D = 257 writes for the IDT72805LB, 513
for the IDT72815LB, 1,025 for the IDT72825LB, 2,049 for the IDT72835LB
and4,097fortheIDT72845LB.NotethattheadditionalwordinFWFTmode
is due to the capacity of the memory plus output register.
IftheFIFOisfull,thefirstreadoperationwillcausetheIRflagtogoLOW.
Subsequent read operations will cause the PAF and HF to go HIGH at the
conditions described in Table 2. If further read operations occur, without
write operations, the PAE will go LOW when there are n + 1 words in the
FIFO,wherenistheEmptyoffsetvalue.IfthereisnoEmptyoffsetspecified,
the PAE willbe LOWwhenthe device is 32awayfromcompletelyemptyfor
IDT72805LB, 64 away from completely empty for IDT72815LB, and 128
awayfromcompletelyemptyforIDT72825LB/72835LB/72845LB.Continu-
ingreadoperationswillcausetheFIFOtobeempty.Whenthelastwordhas
beenreadfromtheFIFO,ORwillgoHIGHinhibitingfurtherreadoperations.
REN is ignored when the FIFO is empty.
Various signals, both input and output signals operate differently de-
pending on which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE and EF operate in the
manner outlined in Table 1. To write data into to the FIFO, Write Enable
(WEN) must be LOW. Data presented to the DATA IN lines will be clocked
intotheFIFOonsubsequenttransitionsoftheWriteClock(WCLK).Afterthe
first write is performed, the Empty Flag (EF) will go HIGH. Subsequent
writes will continue to fill up the FIFO. The Programmable Almost-Empty
flag (PAE) will go HIGH after n + 1 words have been loaded into the FIFO,
where n is the Empty offset value. The default setting for this value is stated
in the footnote of Table 1. This parameter is also user programmable. See
section on Programmable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (HF) would toggle to LOW
once the 129th (IDT72805LB), 257th (IDT72815LB), 513th (IDT72825LB),
1,025th (IDT72835LB), and 2,049th (IDT72845LB) word respectively was
written into the FIFO. Continuing to write data into the FIFO will cause the
Programmable Almost-Full flag (PAF) to go LOW. Again, if no reads are
performed, the PAF will go LOW after (256-m) writes for the IDT72805LB,
(512-m) writes for the IDT72815LB, (1,024-m) writes for the IDT72825LB,
(2,048–m) writes for the IDT72835LB and (4,096–m) writes for the
IDT72845LB. The offset “m” is the Full offset value. This parameter is also
user programmable. See section on Programmable Flag Offset Loading. If
there is no Full offset specified, the PAF will be LOW when the device is 31
away from completely full for IDT72805LB, 63 away from completely full for
IDT72815LB, and 127 away from completely full for the IDT72825LB/
72835LB/72845LB.
PROGRAMMABLE FLAG LOADING
Full and Empty flag Offset values can be user programmable. The
IDT72805LB/72815LB/72825LB/72835LB/72845LB has internal registers
for these offsets. Default settings are stated in the footnotes of Table 1 and
Table2.OffsetvaluesareloadedintotheFIFOusingthedatainputlinesD0-
D11. To load the offset registers, the Load (LD) pin and WEN pin must be
heldLOW. Data presentonD0-D11 willbe transferredintothe EmptyOffset
registeronthe firstLOW-to-HIGHtransitionofWCLK. Bycontinuingtohold
the LD and WEN pin low, data present on D0-D11 will be transferredintothe
Full Offset register on the next transition of the WCLK. The third transition
againwritestotheEmptyOffsetregister.Writingalloffsetregistersdoesnot
havetooccuratonetime.Oneortwooffsetregisterscanbewrittenandthen
When the FIFO is full, the Full Flag (FF) will go LOW, inhibiting further
write operations. If no reads are performed after a reset, FF will go LOW
after D writes to the FIFO. D = 256 writes for the IDT72805LB, 512 for the
IDT72815LB, 1,024 for the IDT72825LB, 2,048 for the IDT72835LB and
4,096 for the IDT72845LB, respectively.
If the FIFO is full, the first read operation will cause FF to go HIGH.
Subsequent read operations will cause PAF and the Half-Full flag (HF) to
go HIGH at the conditions described in Table 1. If further read operations
occur, without write operations, the Programmable Almost-Empty flag
(PAE)willgoLOWwhentherearenwordsintheFIFO,wherenistheEmpty
offsetvalue.Ifthereis noEmptyoffsetspecified,thePAE willbeLOWwhen
JANUARY13,2009
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IDT72805LB/72815LB/72825LB/72835LB/72845LBCMOSDualSyncFIFOTM
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COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
by bringing the LD pin HIGH, the FIFO is returned to normal read/write grams, see Figure 13 for asynchronous PAE timing and Figure 14 for
operation. When the LD pin and WEN are again set LOW, the next offset asynchronous PAF timing.
register in sequence is written.
If synchronous PAE/PAF configuration is selected, the PAE is asserted
The contents of the offset registers can be read on the data output lines andupdatedonthe risingedge ofRCLKonlyandnotWCLK. Similarly, PAF
Q0-Q11 when the LD pin is set LOW and REN is set LOW. Data can then be isassertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.For
read on the next LOW-to-HIGH transition of RCLK. The first transition of detail timing diagrams, see Figure 22 for synchronous PAE timing and
RCLK will present the Empty Offset value to the data output lines. The next Figure 23 for synchronous PAF timing.
transition of RCLK will present the Full offset value. Offset register content
can be read out in the IDT Standard mode only. It cannot be read in the REGISTER-BUFFERED FLAG OUTPUT SELECTION
FWFT mode.
TheIDT72805LB/72815LB/72825LB/72835LB/72845LBcanbeconfig-
ured during the "Configuration at Reset" cycle described in Table 4 with
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG TIM- single, double or triple register-buffered flag output signals. The various
ING SELECTION combinations available are described in Table 4 and Table 5. In general,
TheIDT72805LB/72815LB/72825LB/72835LB/72845LBcanbeconfig- going from single to double or triple buffered flag outputs removes the
ured during the "Configuration at Reset" cycle described in Table 3 with possibility of metastable flag indications on boundary states (i.e, empty or
either asynchronous or synchronous timing for PAE and PAF flags.
full conditions). The trade-off is the addition of clock cycle delays for the
Ifasynchronous PAE/PAF configurationis selected(as perTable3),the respective flagtobe asserted. Notallcombinations ofregister-bufferedflag
PAEisassertedLOWontheLOW-to-HIGHtransitionofRCLK.PAEisreset outputs are supported. Register-buffered outputs apply to the Empty Flag
to HIGH on the LOW-to-HIGH transition of WCLK. Similarly, the PAF is and Full Flag only. Partial flags are not effected. Table 4 and Table 5
asserted LOW on the LOW-to-HIGH transition of WCLK and PAF is reset summarize the options available.
to HIGH on the LOW-to-HIGH transition of RCLK. For detail timing dia-
TABLE 1 — STATUS FLAGS FOR IDT STANDARD MODE
Number of Words in FIFO
IDT72805LB
IDT72815LB
IDT72825LB
IDT72835LB
IDT72845LB
FF PAF HF PAE EF
0
0
0
0
0
H
H
H
H
H
L
H
H
H
H
L
H
H
H
L
L
L
L
L
L
H
H
H
H
H
1 to n(1)
1 to n(1)
1 to n(1)
1 to n(1)
1 to n(1)
(n + 1) to 128
129 to (256-(m+1))(2)
(256-m) to 255
256
(n + 1) to 256
257 to (512-(m+1))(2)
(512-m)to 511
512
(n + 1) to 512
513 to (1,024-(m+1))(2)
(1,024-m) to 1,023
1,024
(n + 1) to 1,024
1,025 to (2,048-(m+1))(2)
(2,048-m) to 2,047
2,048
(n + 1) to 2,048
2,049 to (4,096-(m+1))(2)
(4,096-m) to 4,095
4,096
H
H
H
H
L
NOTES:
1. n = Empty offset (Default Values : IDT72805LB n=31, IDT72815LB n = 63, IDT72825LB/72835LB/72845LB n = 127)
2. m = Full offset (Default Values : IDT72805LB m=31, IDT72815LB m = 63, IDT72825LB/72835LB/72845LB m = 127)
TABLE 2 — STATUS FLAGS FOR FWFT MODE
Number of Words in FIFO
IDT72805LB
IDT72815LB
IDT72825LB
IDT72835LB
IDT72845LB
IR PAF HF PAE OR
0
0
0
0
0
L
L
L
L
L
H
H
H
H
H
L
H
H
H
L
L
L
L
L
H
L
L
L
L
L
1 to (n + 1)(1)
(n + 2) to 129
130 to (257-(m+1))(2)
(257-m) to 256
257
1 to (n + 1)(1)
(n + 2) to 257
258 to (513-(m+1))(2)
(513-m) to 512
513
1 to (n + 1)(1)
(n + 2) to 513
514 to (1,025-(m+1))(2)
(1,025-m) to 1,024
1,025
1 to (n + 1)(1)
1 to (n + 1)(1)
(n + 2) to 1,025
1,026 to (2,049-(m+1))(2)
(2,049-m) to 2,048
2,049
(n + 2) to 2,049
2,050 to (4,097-(m+1))(2)
(4,097-m) to 4,096
4,097
H
H
H
H
L
NOTES:
1. n = Empty offset (Default Values : IDT72805LB n = 31, IDT72815LB n = 63, IDT72825LB/72835LB/72845LB n = 127)
2. m = Full Offset (Default Values : IDT72805LB m = 31, IDT72815LB m = 63, IDT72825LB/72835LB/72845LB m = 127)
JANUARY 13, 2009
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IDT72805LB/72815LB/72825LB/72835LB/72845LBCMOSDualSyncFIFOTM
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COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
TABLE 3 — TRUTH TABLE FOR CONFIGURATION AT RESET
FL
RXI
WXI
EF/OR
FF/IR
PAE, PAF
FIFO TIMING MODE
0
0
0
Single register-buffered
Empty Flag
Single register-buffered
Full Flag
Asynchronous
Standard
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
Triple register-buffered
Output Ready Flag
Double register-buffered
Input Ready Flag
Asynchronous
Asynchronous
Asynchronous
Synchronous
Synchronous
Synchronous
Asynchronous
FWFT
Standard
Standard
Standard
FWFT
Double register-buffered
Empty Flag
Double register-buffered
Full Flag
0(1)
1
Single register-buffered
Empty Flag
Single register-buffered
Full Flag
Single register-buffered
Empty Flag
Single register-buffered
Full Flag
1
Triple register-buffered
Output Ready Flag
Double register-buffered
Input Ready Flag
1
Double register-buffered
Empty Flag
Double register-buffered
Full Flag
Standard
Standard
1(2)
Single register-buffered
Empty Flag
Single register-buffered
Full Flag
NOTES:
1. In a daisy-chain depth expansion, FL is held LOW for the "first load device". The RXI and WXI inputs are driven by the corresponding RXO and WXO outputs of the preceding device.
2. In a daisy-chain depth expansion, FL is held HIGH for members of the expansion other than the "first load device". The RXI and WXI inputs are driven by the corresponding RXO and
WXO outputs of the preceding device.
TABLE 4 — REGISTER-BUFFERED FLAG OUTPUT OPTIONS — IDT STANDARD MODE
Empty Flag (EF)
Buffered Output
Full Flag (FF)
Buffered Output
Partial Flags
Timing Mode
Programming at Reset
Flag Timing
Diagrams
FL
RXI
WXI
Single
Single
Double
Double
Single
Single
Double
Double
Asynch
Sync
0
1
0
1
0
0
1
1
0
0
0
0
Figure 9, 10
Figure 9, 10
Figure 24, 26
Figure 24, 26
Asynch
Synch
TABLE 5 — REGISTER-BUFFERED FLAG OUTPUT OPTIONS — FWFT MODE
Output Ready (OR)
Input Ready (IR)
Partial Flags
Programming at Reset
Flag Timing
Diagrams
FL
RXI
WXI
Triple
Triple
Double
Double
Asynch
Sync
0
1
0
0
1
1
Figure 27
Figure 20, 21
JANUARY13,2009
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IDT72805LB/72815LB/72825LB/72835LB/72845LBCMOSDualSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
LD
WEN
WCLK
Selection
Writing to offset registers:
Empty Offset
SIGNAL DESCRIPTIONS:
0
0
INPUTS:
DATA IN (D0 - D17)
Full Offset
Data inputs for 18-bit wide data.
CONTROLS:
0
1
1
0
No Operation
RESET (RSA/RSB)
Write Into FIFO
Reset is accomplished whenever the Reset (RSA/RSB) input is taken to
a LOW state. During reset, both internal read and write pointers are set to
the first location. A reset is required after power-up before a write operation
can take place. The Half-Full flag (HFA/HFB) and Programmable Almost-
Full flag (PAFA/PAFB) will be reset to HIGH after tRSF. The Programmable
Almost-Empty flag (PAEA/PAEB) will be reset to LOW after tRSF. The Full
Flag (FFA/FFB) will reset to HIGH. The Empty Flag (EFA/EFB) will reset to
LOW in IDT Standard mode but will reset to HIGH in FWFT mode. During
reset, the output register is initialized to all zeros and the offset registers are
initialized to their default values.
1
1
No Operation
NOTE:
1. The same selection sequence applies to reading from the registers. REN is enabled and
read is performed on the LOW-to-HIGH transition of RCLK.
Figure 2. Writing to Offset Registers
17
17
11
11
0
0
EMPTY OFFSET REGISTER
DEFAULT VALUE
001FH (72805) 003FH (72815):
007FH (72825/72835/72845)
WRITE CLOCK (WCLKA/WCLKB)
A write cycle is initiated on the LOW-to-HIGH transition of the Write
Clock (WCLKA/WCLKB). Data setup and hold times must be met with
respect to the LOW-to-HIGH transition of WCLK.
FULL OFFSET REGISTER
DEFAULT VALUE
001FH (72805) 003FH (72815):
007FH (72825/72835/72845)
The Write and Read Clocks can be asynchronous or coincident.
WRITE ENABLE (WENA/WENB)
3139 drw 04
WhentheWENA/WENBinputisLOW,datamaybeloadedintotheFIFO NOTE:
1. Any bits of the offset register not being programmed should be set to zero.
RAM array on the rising edge of every WCLK cycle if the device is not full.
Data is stored in the RAM array sequentially and independently of any
ongoing read operation.
Figure 3. Offset Register Location and Default Values
empty. Once a write is performed, EF willgoHIGHallowinga readtooccur.
The EF flag is updated on the rising edge of RCLK.
When WEN is HIGH, no new data is written in the RAM array on each
WCLK cycle.
To prevent data overflow in the IDT Standard Mode, FF will go LOW,
inhibitingfurtherwriteoperations.Uponthecompletionofavalidreadcycle,
FFwillgoHIGHallowingawritetooccur.TheFFflagisupdatedontherising
edge of WCLK.
To prevent data overflow in the FWFT mode, Input Ready(IRA,IRB) will
go HIGH, inhibiting further write operations. Upon the completion of a valid
read cycle, IR will go LOW allowing a write to occur. The IR flag is updated
on the rising edge of WCLK.
Inthe FWFTmode, the firstwordwrittentoanemptyFIFOautomatically
goes to the outputs Qn, on the third valid LOW to HIGH transition of RCLK
+tSKEW afterthefirstwrite.RENdoesnotneedtobeassertedLOW.Inorder
to access all other words, a read must be executed using REN. The RCLK
LOW to HIGH transition after the last word has been read from the FIFO,
Output Ready (ORA/ORB) will go HIGH with a true read (RCLK with REN
= LOW), inhibiting further read operations. REN is ignored when the FIFO
is empty.
WEN is ignored when the FIFO is full in either FWFT or IDT Standard
mode.
OUTPUT ENABLE (OEA/OEB)
When Output Enable (OEA/OEB) is enabled (LOW), the parallel output
buffers receive data from the output register. When OE is disabled (HIGH),
the Q output data bus is in a high-impedance state.
READ CLOCK (RCLKA/RCLKB)
Data can be read on the outputs on the LOW-to-HIGH transition of the
Readclock(RCLKA/RCLKB),whenOutputEnable(OEA/OEB)issetLOW.
The Write and Read Clocks can be asynchronous or coincident.
LOAD (LDA/LDB)
The IDT72805LB/72815LB/72825LB/72835LB/72845LB devices con-
taintwo12-bitoffsetregisterswithdataontheinputs,orreadontheoutputs.
When the Load (LDA/LDB) pin is set LOW and WEN is set LOW, data on
the inputs D0-D11 is written into the Empty Offset register on the first LOW-
to-HIGH transition of the Write clock (WCLK). When the LD pin and WEN
are held LOW then data is written into the Full Offset register on the second
LOW-to-HIGHtransitionofWCLK.ThethirdtransitionofWCLKagainwrites
to the Empty Offset register.
READ ENABLE (RENA/RENB)
WhenReadEnable(RENA/RENB)isLOW,dataisloadedfromtheRAM
array into the output register on the rising edge of every RCLK cycle if the
device is not empty.
WhentheRENinputis HIGH,theoutputregisterholds theprevious data
and no new data is loaded into the output register. The data outputs Q0-Qn
maintain the previous data value.
However, writing all offset registers does not have to occur at one time.
One or two offset registers can be written and then by bringing the LD pin
HIGH,theFIFOis returnedtonormalread/writeoperation.WhentheLDpin
issetLOW,andWENisLOW,thenextoffsetregisterinsequenceiswritten.
IntheIDTStandardmode,everywordaccessedatQn,includingthefirst
word written to an empty FIFO, must be requested using REN. When the
last word has been read from the FIFO, the Empty Flag (EFA/EFB) will go
LOW, inhibiting further read operations. REN is ignored when the FIFO is
JANUARY 13, 2009
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IDT72805LB/72815LB/72825LB/72835LB/72845LBCMOSDualSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Whenthe LD pinis LOWandWEN is HIGH, the WCLKinputis disabled;
then a signal at this input can neither increment the write offset register
pointer, nor execute a write.
EF/OR is synchronous and updated on the rising edge of RCLK.
PROGRAMMABLE ALMOST-FULL FLAG (PAFA/PAFB)
The contents ofthe offsetregisters canbe readonthe outputlines when
The Programmable Almost-Full flag (PAFA/PAFB) will go LOW when
the LD pin is set LOW and REN is set LOW; then, data can be read on the FIFO reaches the almost-full condition. In IDT Standard mode, if no reads
LOW-to-HIGH transition of the Read clock (RCLK). The act of reading the areperformedafterReset(RS),thePAFwillgoLOWafter(256-m)writesfor
controlregistersemploysadedicatedreadoffsetregisterpointer.(Theread the IDT72805LB, (512-m) writes for the IDT72815LB, (1,024-m) writes for
and write pointers operate independently). Offset register content can be theIDT72825LB,(2,048–m)writesfortheIDT72835LBand(4,096–m)writes
read out in the IDT Standard mode only. It is inhibited in the FWFT mode. for the IDT72845LB. The offset “m” is defined in the Full Offset register.
A read and a write should not be performed simultaneously to the offset
registers.
In FWFT mode, if no reads are performed, PAF will go LOW after (257-
m) writes for the IDT72805LB, (513-m) writes for the IDT72815LB, (1,025-
m) writes for the IDT72825LB, (2,049-m) writes for the IDT72835LB and
(4,097-m) writes for the IDT72845LB. The default values for m are noted in
FIRST LOAD (FLA/FLB)
For the single device mode, see Table I for additional information. In the Table 1 and 2.
Daisy Chain Depth Expansion configuration, FLA/FLB is grounded to
If asynchronous PAF configuration is selected, the PAF is asserted
indicate it is the first device loaded and is set to HIGH for all other devices LOW on the LOW-to-HIGH transition of the Write Clock (WCLK). PAF is
in the Daisy Chain. (See Operating Configurations for further details.)
reset to HIGH on the LOW-to-HIGH transition of the Read Clock (RCLK). If
synchronous PAF configuration is selected (see Table I), the PAF is
updated on the rising edge of WCLK.
WRITE EXPANSION INPUT (WXIA/WXIB)
This is a dual purpose pin. For single device mode, see Table I for
additional information. WXIA/WXIB is connected to Write Expansion Out PROGRAMMABLE ALMOST-EMPTY FLAG (PAEA/PAEB)
(WXOA/WXOB)oftheprevious deviceintheDaisyChainDepthExpansion
The PAE flag will go LOW when the FIFO reads the almost-empty
condition. In IDT Standard mode, PAE will go LOW when there are n words
or less in the FIFO. In FWFT mode, the PAE will go LOW when there are
n+1 words or less in the FIFO. The offset “n” is defined as the Empty offset.
mode.
READ EXPANSION INPUT (RXIA/RXIB)
This is a dual purpose pin. For single device mode, see Table I for The default values for n are noted in Table 1 and 2.
additional information. RXIA/RXIB is connected to Read Expansion Out
If asynchronous PAE configuration is selected, the PAE is asserted
(RXOA/RXOB) of the previous device in the Daisy Chain Depth Expansion LOW on the LOW-to-HIGH transition of the Read Clock (RCLK). PAE is
mode.
reset to HIGH on the LOW-to-HIGH transition of the Write Clock (WCLK).
If synchronous PAE configuration is selected (see Table I), the PAE is
updated on the rising edge of RCLK.
OUTPUTS:
FULL FLAG/INPUT READY (FFA/IRA, FFB/IRB)
WRITE EXPANSION OUT/HALF-FULL FLAG
This is a dual purpose pin. In IDT Standard mode, the Full Flag (FFA/
FFB) function is selected. When the FIFO is full, FF will go LOW, inhibiting
further write operations. When FF is HIGH, the FIFO is not full. If no reads
are performed after a reset, FF will go LOW after D writes to the FIFO. D =
256 writes for the IDT72805LB, 512 for the IDT72815LB, 1,024 for the
IDT72825LB, 2,048 for the IDT72835LB and 4,096 for the IDT72845LB.
In FWFT mode, the Input Ready (IRA/IRB) function is selected. IR goes
LOW when memory space is available for writing in data. When there is no
longeranyfree space left, IR goes HIGH, inhibitingfurtherwrite operations.
IR will go HIGH after D writes to the FIFO. D = 257 writes for the
IDT72805, 513 for the IDT72815, 1,025 for the IDT72825, 2,049 for the
IDT72835 and 4,097 for the IDT72845. Note that the additional word in
FWFT mode is due to the capacity of the memory plus output register.
FF/IR is synchronous and updated on the rising edge of WCLK.
(WXOA/HFA, WXOB/HFB)
Thisisadual-purposeoutput.IntheSingleDeviceandWidthExpansion
mode, when Write Expansion In (WXIA/WXIB) and/or Read Expansion In
(RXIA/RXIB) are grounded, this output acts as an indication of a half-full
memory.
After half of the memory is filled, and at the LOW-to-HIGH transition of
the nextwrite cycle, the Half-Fullflaggoes LOWandwillremainsetuntilthe
difference between the write pointer and read pointer is less than or equal
to one half of the total memory of the device. The Half-Full flag (HFA/HFB)
is then reset to HIGH by the LOW-to-HIGH transition of the Read Clock
(RCLK). The HF is asynchronous.
In the Daisy Chain Depth Expansion mode, WXI is connected to WXO
of the previous device. This output acts as a signal to the next device in the
DaisyChainbyprovidinga pulse whenthe previous device writes tothe last
location of memory.
EMPTY FLAG/OUTPUT READY (EFA/ORA, EFB/ORB)
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag
(EFA/EFB) function is selected. When the FIFO is empty, EF will go LOW,
inhibiting further read operations. When EF is HIGH, the FIFO is not empty.
In FWFT mode, the Output Ready (ORA/ORB) function is selected. OR
goes LOW at the same time that the first word written to an empty FIFO
appears valid on the outputs. OR stays LOW after the RCLK LOW to HIGH
transition that shifts the last word from the FIFO memory to the outputs. OR
goes HIGH only with a true read (RCLK with REN = LOW). The previous
data stays at the outputs, indicating the last word was read. Further data
reads are inhibited until OR goes LOW again.
READ EXPANSION OUT (RXOA/RXOB)
In the Daisy Chain Depth Expansion configuration, Read Expansion In
(RXIA/RXIB) is connected to Read Expansion Out (RXOA/RXOB) of the
previous device. This output acts as a signal to the next device in the Daisy
Chain by providing a pulse when the previous device reads from the last
location of memory.
DATA OUTPUTS (Q0-Q17, QB0-QB17)
Q0-Q17 are data outputs for 18-bit wide data.
JANUARY13,2009
11
IDT72805LB/72815LB/72825LB/72835LB/72845LBCMOSDualSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tRS
RS
tRSR
REN, WEN, LD
FL, RXI, WXI (1)
tRSR
t
RSS
CONFIGURATION SETTING
RCLK, WCLK (2)
FF/IR
t
RSF
t
t
t
RSF
RSF
RSF
FWFT Mode
EF/OR
IDT Standard Mode
PAF, WXO/
HF, RXO
PAE
t
RSF
OE = 1(3)
Q0 - Q17
3139 drw 05
OE = 0
NOTES:
1. Single device mode (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0). FL, RXI, WXI should be static (tied to VCC or GND).
2. The clocks (RCLK, WCLK) can be free-running asynchronously or coincidentally.
3. After reset, the outputs will be LOW if OE = 0 and tri-state if OE = 1.
Figure 5. Reset Timing(2)
tCLK
tCLKH
tCLKL
WCLK
tDS
tDH
D0
- D17
DATA IN VALID
tENH
tENS
NO OPERATION
WEN
FF
tWFF
tWFF
(1)
SKEW1
t
RCLK
3139 drw 06
REN
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge
of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 6. Write Cycle Timing with Single Register-Buffered FF (IDT Standard Mode)
JANUARY 13, 2009
12
IDT72805LB/72815LB/72825LB/72835LB/72845LBCMOSDualSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLK
tCLKH
tENH
tCLKL
RCLK
REN
tENS
NO OPERATION
tREF
tREF
EF
tA
VALID DATA
Q0 - Q17
OE
tOLZ
tOHZ
tOE
(1)
tSKEW1
WCLK
WEN
3139 drw 07
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH during the current clock cycle. If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 7. Read Cycle Timing with Single Register-Buffered EF (IDT Standard Mode)
WCLK
tDS
D0 (first valid write)
D0
- D17
D1
D2
D3
D4
tENS
WEN
(1)
FRL
t
tSKEW1
RCLK
tREF
EF
tENS
REN
tA
tA
Q0
- Q17
D0
D1
tOLZ
tOE
OE
3139 drw 08
NOTES:
1. When tSKEW1 minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2*tCLK + tSKEW1 or tCLK + tSKEW1. The Latency Timing
applies only at the Empty Boundary (EF = LOW).
2. The first word is available the cycle after EF goes HIGH, always.
3. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 8. First Data Word Latency with Single Register-Buffered EF (IDT Standard Mode)
JANUARY13,2009
13
IDT72805LB/72815LB/72825LB/72835LB/72845LBCMOSDualSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
NO WRITE
NO WRITE
(1)
WCLK
(1)
tSKEW1
t
SKEW1
tDS
tDS
DATA
WRITE
D0
- D17
DATA WRITE
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENS
tENS
tENH
tENH
REN
OE
LOW
tA
tA
Q0
- Q17
DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
3139 drw 09
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the rising edge
of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 9. Single Register-Buffered Full Flag Timing (IDT Standard Mode)
WCLK
tDS
tDS
DATA WRITE 1
tENH
DATA WRITE 2
tENH
D0 - D17
tENS
tENS
WEN
(1)
(1)
tFRL
tFRL
tSKEW1
tSKEW1
RCLK
tREF
tREF
tREF
EF
REN
OE LOW
tA
Q0 - Q17
NOTES:
DATA IN OUTPUT REGISTER
DATA READ
3139 drw 10
1. When tSKEW1 minimum specification, tFRL (maximum) = tCLK + tSKEW1. When tSKEW1 < minimum specification, tFRL (maximum) = either 2 * tCLK + tSKEW1, or tCLK + tSKEW1. The Latency Timing
apply only at the Empty Boundary (EF = LOW).
2. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,1,1), (1,0,0) or (1,1,1) during Reset.
Figure 10. Single Register-Buffered Empty Flag Timing (IDT Standard Mode)
JANUARY 13, 2009
14
IDT72805LB/72815LB/72825LB/72835LB/72845LBCMOSDualSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLK
tCLKH
tCLKL
WCLK
tENS
tENH
LD
tENS
WEN
tDS
tDH
PAE OFFSET
D0-D15
3139 drw 11
PAE OFFSET
PAF OFFSET
D0-D11
Figure 11. Write Programmable Registers (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
RCLK
tENS
tENH
LD
tENS
REN
tA
PAE OFFSET
Q0-Q15
UNKNOWN
PAE OFFSET
PAF OFFSET
3139 drw 12
Figure 12. Read Programmable Registers (IDT Standard Mode)
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
(2)
(2)
tPAEA
n words in FIFO
,
n words in FIFO
n + 1 words in FIFO
,
(2)
n+1wordsinFIFO
,
(3)
(3)
PAE
RCLK
REN
n + 1 words in FIFO
(3)
n+2wordsinFIFO
tPAEA
tENS
3139 drw 13
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during Reset.
Figure 13. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
JANUARY13,2009
15
IDT72805LB/72815LB/72825LB/72835LB/72845LBCMOSDualSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tCLKH
tCLKL
WCLK
(1)
tENS
tENH
WEN
PAF
tPAFA
D - (m + 1) words in FIFO
D - (m + 1) words in FIFO
D - m words in FIFO
tPAFA
RCLK
tENS
REN
3139 drw 14
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D = 256 for the IDT72805, 512 for the IDT72815, 1,024 for the IDT72825, 2,048 for the IDT72835 and 4,096 for the IDT72845.
In FWFT Mode: D = 257 for the IDT72805, 513 for the IDT72815, 1,025 for the IDT72825, 2,049 for the IDT72835 and 4,097 for the IDT72845.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (0,1,1) or (1,1,1) during Reset.
Figure 14. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
HF
tHF
D/2 + 1 words in FIFO(2),
D-1
2
D/2 words in FIFO(2)
,
D/2 words in FIFO(2)
D-1
2
,
[
+ 2
words in FIFO(3)
]
D-1
[
+ 1
]
words in FIFO(3)
[
+ 1
words in FIFO(3)
]
2
tHF
RCLK
tENS
REN
3139 drw 15
NOTES:
1. D = maximum FIFO Depth.
In IDT Standard Mode: D = 256 for the IDT72805, 512 for the IDT72815, 1,024 for the IDT72825, 2,048 for the IDT72835 and 4,096 for the IDT72845.
In FWFT Mode: D = 257 for the IDT72805, 513 for the IDT72815, 1,025 for the IDT72825, 2,049 for the IDT72835 and 4,097 for the IDT72845.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. Select this mode by setting (FL, RXI, WXI) = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or (1,1,0) during Reset.
Figure 15. Half-Full Flag Timing (IDT Standard and FWFT Modes)
JANUARY 13, 2009
16
IDT72805LB/72815LB/72825LB/72835LB/72845LBCMOSDualSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
tCLKH
WCLK
Note 1
tXO
tXO
WXO
WEN
tENS
3139 drw 16
NOTE:
1. Write to Last Physical Location.
Figure 16. Write Expansion Out Timing
tCLKH
RCLK
Note 1
tXO
tXO
RXO
REN
tENS
3139 drw 17
NOTE:
1. Read from Last Physical Location.
Figure 17. Read Expansion Out Timing
tXI
WXI
tXIS
WCLK
3139 drw 18
Figure 18. Write Expansion In Timing
tXI
RXI
tXIS
RCLK
3139 drw 19
Figure 19. Read Expansion In Timing
JANUARY13,2009
17
IDT72805LB/72815LB/72825LB/72835LB/72845LBCMOSDualSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
JANUARY 13, 2009
18
IDT72805LB/72815LB/72825LB/72835LB/72845LBCMOSDualSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
JANUARY13,2009
19
IDT72805LB/72815LB/72825LB/72835LB/72845LBCMOSDualSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
PAE
n words in FIFO(2)
,
n Words in FIFO(2),
n + 1 words in FIFO(3)
n + 1 words in FIFO(2)
n + 2 words in FIFO(3)
,
n + 1words in FIFO(3)
(4)
t
PAES
tSKEW2
t
PAES
RCLK
tENH
tENS
3139 drw 22
REN
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for PAE to go HIGH during the current clock cycle. If the time between the rising edge of WCLK and the
rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of RCLK only.
6. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.
Figure 22. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
t
PAFS
D-(m+1) Words in FIFO
D -(m+1) Words
in FIFO
PAF
D - m Words in FIFO
(3)
SKEW2
t
PAFS
t
RCLK
tENH
tENS
3139 drw 23
REN
NOTES:
1. m = PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D = 256 for the IDT72805, 512 for the IDT72815, 1,024 for the IDT72825, 2,048 for the IDT72835 and 4,096 for the IDT72845.
In FWFT Mode: D = 257 for the IDT72805, 513 for the IDT72815, 1,025 for the IDT72825, 2,049 for the IDT72835 and 4,097 for the IDT72845.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to go HIGH during the current clock cycle. If the time between the rising edge of RCLK and
the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed an extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting (FL, RXI, WXI) = (1,0,0), (1,0,1), or (1,1,0) during Reset.
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
JANUARY 13, 2009
20
IDT72805LB/72815LB/72825LB/72835LB/72845LBCMOSDualSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
NO WRITE
NO WRITE
2
1
WCLK
1
2
(1)
SKEW1
(1)
SKEW1
tDS
tDS
t
t
DATA WRITE
Wd
D0
- D17
t
WFF
tWFF
t
WFF
FF
WEN
RCLK
tENH
tENH
tENS
tENS
REN
OE
LOW
tA
tA
NEXT DATA READ
Q0
- Q17
DATA IN OUTPUT REGISTER
DATA READ
3139 drw 24
NOTES:
1. SKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus tWFF. If the time between the rising edge of RCLK
t
and the rising edge of WCLK is less than tSKEW1, then the FF deassertion time may be delayed an extra WCLK cycle.
2. LD = HIGH.
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
Figure 24. Double Register-Buffered Full Flag Timing (IDT Standard Mode)
tCLK
t
CLKH
tCLKL
1
2
WCLK
tDS
tDH
D0
-
D17
DATA IN VALID
ENS
tENH
t
NO OPERATION
WEN
FF
t
WFF
tWFF
(1)
tSKEW1
RCLK
3139 drw 25
REN
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH after one WCLK cycle plus tRFF. If the time between the rising edge
of RCLK and the rising edge of WCLK is less than tSKEW1, then the FF deassertion may be delayed an extra WCLK cycle.
2. LD = HIGH.
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
Figure 25. Write Cycle Timing with Double Register-Buffered FF (IDT Standard Mode)
JANUARY13,2009
21
IDT72805LB/72815LB/72825LB/72835LB/72845LBCMOSDualSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
tCLK
tCLKL
tCLKH
1
2
RCLK
tENH
tENS
NO OPERATION
REN
EF
t
REF
t
REF
tA
Q0
-
Q17
LAST WORD
tOLZ
tOHZ
tOE
OE
(1)
SKEW1
t
WCLK
tENH
tENS
WEN
tDH
tDS
FIRST WORD
D0
-
D17
3139 drw 26
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH after one RCLK cycle plus tREF. If the time between the rising edge
of WCLK and the rising edge of RCLK is less than tSKEW1. then the EF deassertion may be delayed an extra RCLK cycle.
2. LD = HIGH
3. Select this mode by setting (FL, RXI, WXI) = (0,1,0) or (1,1,0) during Reset.
Figure 26. Read Cycle Timing with Double Register-Buffered EF (IDT Standard Timing)
WCLK
t
ENH
t
ENS
WEN
t
DS
tDH
t
DS
W[n+3]
W4
W[n +2]
W1
W2
W3
D0
-
D17
(1)
t
SKEW1
2
1
RCLK
3
REN
t
A
Q0
-
Q17
DATA IN OUTPUT REGISTER
W1
t
REF
t
REF
3139 drw 27
OR
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for OR to go HIGH during the current cycle. If the time between the rising edge of WLCK and the rising
edge of RCLK is less than tSKEW1, then the OR deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH, OE = LOW
3. Select this mode by setting (FL, RXI, WXI) = (0,0,1) or (1,0,1) during Reset.
Figure 27. OR Flag Timing and First Word Fall Through when FIFO is Empty (FWFT mode)
JANUARY 13, 2009
22
IDT72805LB/72815LB/72825LB/72835LB/72845LBCMOSDualSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
the application requirements are for 256/512/1,024/2,048/4,096 words or
less. These FIFOs are in a single Device Configuration when the First Load
(FL), Write Expansion In (WXI) and Read Expansion In (RXI) control inputs
are configured as (FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or
(1,1,0) during reset (Figure 28).
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION
Each of the two FIFOs contained in a single IDT72805LB/72815LB/
72825LB/72835LB/72845LB may be used as a stand-alone device when
RESET (RS)
WRITE CLOCK (WCLK)
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
WRITE ENABLE (WEN)
IDT
72805
LOAD (LD)
72815
72825
72835
72845
DATA IN (D0 - D17)
DATA OUT (Q0 - Q17)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE (PAE)
HALF-FULL FLAG (HF)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE (PAF)
FIFO A OR B
FL
RXI
WXI
3139 drw 28
Figure 28. Block Diagram of Single 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 Synchronous FIFO
(One of the two FIFOs contained in the IDT72805LB/72815LB/72825LB/72835LB/72845LB)
Flags/Input Ready. Figure 29 demonstrates a 36-word width by using one
IDT72805LB/72815LB/72825LB/72835LB/72845LBs. Any word width can
be attained by adding additional IDT72805LB/72815LB/72825LB/72835LB/
72845LBs. These FIFOs are in a single Device Configuration when the First
Load (FL), Write Expansion In (WXI) and Read Expansion In (RXI) control
inputs are configured as (FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0),
(1,0,1) or (1,1,0) during reset (Figure 29). Please see the Application Note
AN-83.
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of FIFO A and B. Status flags can be detected from any one device.
The exceptions are the Empty Flag/Output Ready and Full Flag/Input
Ready. Because of variations in skew between RCLK and WCLK, it is
possible for flag assertion and deassertion to vary by one cycle between
FIFOs. To avoid problems the user must create composite flags by gating
the Empty Flags/Output Ready of every FIFO, and separately gating all Full
RESET (RS)
RESET (RS)
DATA IN (D) 36
18
18
READ CLOCK (RCLK)
READ ENABLE (REN)
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAF)
LOAD (LD)
PROGRAMMABLE (PAE)
FIFO A
FIFO B
EMPTY FLAG/OUTPUT
READY (EF/OR)
HALF FULL FLAG (HF)
FF/IR
EF/OR
FF/IR
EF/OR
18
DATA OUT (Q)
36
FULL FLAG/INPUT
READY (FF/IR)
FL WXI RXI
FL WXI RXI
18
3139 drw 29
NOTE:
1. Do not connect any output control signals directly together.
Figure 29. Block Diagram of the two FIFOs contained in one IDT72805LB/72815LB/72825LB/72835LB/72845LB
configured for a 36-bit Width Expansion
JANUARY13,2009
23
IDT72805LB/72815LB/72825LB/72835LB/72845LBCMOSDualSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
DEPTH EXPANSION CONFIGURATION — DAISY CHAIN TECHNIQUE
4. The Read Expansion Out (RXO) pin of each device must be tied to the
Read Expansion In (RXI) pin of the next device. See Figure 30.
5. All Load (LD) pins are tied together.
6. The Half-Full flag (HF) is not available in this Depth Expansion
Configuration.
7. EF, FF, PAE, and PAF are created with composite flags by ORing
together every respective flags for monitoring. The composite PAE and
PAF flags are not precise.
8. In Daisy Chain mode, the flag outputs are single register-buffered and
the partial flags are in asynchronous timing mode.
(WITH PROGRAMMABLE FLAGS)
These devices can easily be adapted to applications requiring more than
256/512/1,024/2,048/4,096 words of buffering. Figure 30 shows Depth
ExpansionusingoneIDT72805LB/72815LB/72825LB/72835LB/72845LBs.
Maximum depth is limited only by signal loading. Follow these steps:
1.ThefirstdevicemustbedesignatedbygroundingtheFirstLoad(FL)controlinput.
2. All other devices must have FL in the HIGH state.
3. The Write Expansion Out (WXO) pin of each device must be tied to the
Write Expansion In (WXI) pin of the next device. See Figure 30.
IDT72845
WXOA RXOA
WCLKA
WENA
RSA
RCLKA
RENA
OEA
LDA
FIFO A
4,096 x 18
DAn
QAn
Vcc
FLA
FFA/IRA EFA/ORA
PAEA
PAFA
WXIA RXIA
DATA IN
DATA OUT
RXOB
RCLKB
RENB
WXOB
WRITE CLOCK
WRITE ENABLE
RESET
WCLKB
READ CLOCK
WENB
READ ENABLE
OUTPUT ENABLE
RSB
OEB
DBn
QBn
LDB
LOAD
FIFO B
4,096 x 18
FFA/IRA EFA/ORA
EF/OR
FF/IR
PAE
PAF
PAFB
WXIB
PAEB
RXIB
FIRST LOAD (FL)
3139 drw 30
Figure 30. Block Diagram of 8,192 x 18 Synchronous
FIFO Memory With Programmable Flags used in Depth Expansion Configuration
JANUARY 13, 2009
24
IDT72805LB/72815LB/72825LB/72835LB/72845LBCMOSDualSyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DEPTH EXPANSION CONFIGURATION (FWFT MODE)
tSKEW1 specificationis notmetbetweenWCLKandtransferclock, orRCLK
and transfer clock, for the OR flag.
The “ripple down” delay is only noticeable for the first word written to an
In FWFT mode, the FIFOs can be connected in series (the data outputs
of one FIFO connected to the data inputs of the next) with no external logic empty depth expansion configuration. There will be no delay evident for
necessary. The resulting configuration provides a total depth equivalent to subsequent words written to the configuration.
the sum of the depths associated with each single FIFO. Figure 31 shows
a depth expansion using one IDT72805LB/72815LB/72825LB/72835LB/ configuration will “bubble up” from the last FIFO to the previous one until it
72845LB devices. finally moves into the first FIFO of the chain. Each time a free location is
The first free location created by reading from a full depth expansion
Care should be taken to select FWFT mode during Master Reset for all created in one FIFO of the chain, that FIFO’s IR line goes LOW, enabling
FIFOs in the depth expansion configuration. The first word written to an the preceding FIFO to write a word to fill it.
emptyconfigurationwillpass fromone FIFOtothe next(“ripple down”)until
Fora fullexpansionconfiguration, the amountoftime ittakes forIR ofthe
it finally appears at the outputs of the last FIFO in the chain–no read first FIFO in the chain to go LOW after a word has been read from the last
operation is necessary but the RCLK of each FIFO must be free-running. FIFO is the sum of the delays for each individual FIFO:
Each time the data word appears at the outputs of one FIFO, that device’s
OR line goes LOW, enabling a write to the next FIFO in line.
Foranemptyexpansionconfiguration, the amountoftime ittakes forOR
of the last FIFO in the chain to go LOW (i.e. valid data to appear on the last
FIFO’s outputs) after a word has been written to the first FIFO is the sum of
the delays for each individual FIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. Note that extra cycles should be added for the possibility that the
tSKEW1 specificationis notmetbetweenRCLKandtransferclock, orWCLK
and transfer clock, for the IR flag.
The Transfer Clock line should be tied to either WCLK or RCLK,
whichever is faster. Both these actions result in data moving, as quickly as
(N – 1)*(4*transfer clock) + 3*TRCLK
where N is the number of FIFOs in the expansion and TRCLK is the RCLK possible, to the end of the chain and free locations to the beginning of the
period. Note that extra cycles should be added for the possibility that the chain.
HF
HF
PAF
PAE
TRANSFER CLOCK
READ CLOCK
READ ENABLE
WRITE CLOCK
WRITE ENABLE
WCLK
WEN
IR
RCLK
WCLK
RCLK
OR
WEN
REN
72805
72815
72825
72835
72845
72805
72815
72825
72835
72845
INPUT READY
OUTPUT READY
OUTPUT ENABLE
REN
OE
OR
OE
Qn
IR
GND
n
DATA OUT
n
n
DATA IN
Dn
Qn
Dn
FL
RXI
FL
WXI
RXI
WXI
3139 drw 31
(0,1)
(0,1)
V
CC
VCC
GND
GND
Figure 31. Block Diagram of 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18, 8,192 x 18 Synchronous
FIFO Memory With Programmable Flags used in Depth Expansion Configuration
JANUARY13,2009
25
ORDERING INFORMATION
X
XXXXX
Device Type
X
XX
Speed
X
X
Power
Package
Process /
Temperature
Range
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(2)
Green
BG(3)
PF
Ball Grid Array (PBGA, BG121-1)
Thin Quad Flatpack (TQFP, PK128-1)
Commercial Only
Com'l & Ind'l
Commercial Only
10
15
20
Clock Cycle Time (tCLK
Speed in Nanoseconds
)
Low Power
LB
256 x18 ⎯ Dual SyncFIFO
512 x18 ⎯ Dual SyncFIFO
1,024 x18 ⎯ Dual SyncFIFO
2,048 x18 ⎯ Dual SyncFIFO
4,096 x18 ⎯ Dual SyncFIFO
72805
72815
72825
72835
72845
3139 drw32
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
2. Green parts are available. For specific speeds and packages contact your sales office.
3. The PBGA is only available for the IDT72805LB/72815LB/72825LB in the 15 or 25 ns speed grade.
DATASHEETDOCUMENTHISTORY
05/01/2001
02/12/2003
11/30/2004
02/22/2006
01/13/2003
pgs. 1, 5, 6, and 26.
pgs. 1, 2, and 26.
pg. 5.
pgs. 1 and 26.
pg. 26.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
800-345-7015 or 408-284-8200
fax: 408-284-2775
for Tech Support:
408-360-1753
email:FIFOhelp@idt.com
www.idt.com
26
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