72T18115L10BBG [IDT]
FIFO, 256KX18, 4.5ns, Synchronous, CMOS, PBGA240, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-240;
| 型号： | 72T18115L10BBG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | FIFO, 256KX18, 4.5ns, Synchronous, CMOS, PBGA240, 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-240 先进先出芯片 |
| 文件： | 总55页 (文件大小：510K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
2.5 VOLT HIGH-SPEED TeraSync™ FIFO
18-BIT/9-BITCONFIGURATIONS
2,048 x 18/4,096 x 9, 4,096 x 18/8,192 x 9, 8,192 x 18/16,384 x 9,
16,384 x 18/32,768 x 9, 32,768 x 18/65,536 x 9, 65,536 x 18/131,072 x 9,
131,072 x 18/262,144 x 9, 262,144 x 18/524,288 x 9, 524,288 x 18/1,048,576 x 9
IDT72T1845, IDT72T1855
IDT72T1865, IDT72T1875
IDT72T1885, IDT72T1895
IDT72T18105, IDT72T18115
IDT72T18125
Empty and Almost-Full flags
FEATURES:
• Separate SCLK input for Serial programming of flag offsets
• User selectable input and output port bus-sizing
- x9 in to x9 out
- x9 in to x18 out
- x18 in to x9 out
• Choose among the following memory organizations:
IDT72T1845
IDT72T1855
IDT72T1865
IDT72T1875
IDT72T1885
IDT72T1895
IDT72T18105
IDT72T18115
IDT72T18125
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
2,048 x 18/4,096 x 9
4,096 x 18/8,192 x 9
8,192 x 18/16,384 x 9
16,384 x 18/32,768 x 9
32,768 x 18/65,536 x 9
65,536 x 18/131,072 x 9
131,072 x 18/262,144 x 9
262,144 x 18/524,288 x 9
524,288 x 18/1,048,576 x 9
- x18 in to x18 out
• Big-Endian/Little-Endian user selectable byte representation
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
• Empty, Full and Half-Full flags signal FIFO status
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• JTAG port, provided for Boundary Scan function
• Available in 144-pin (13mm x 13mm) or 240-pin (19mm x 19mm)
PlasticBallGridArray(PBGA)
• Easily expandable in depth and width
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
• Green parts are available, see ordering information
• Up to 225 MHz Operation of Clocks
• User selectable HSTL/LVTTL Input and/or Output
• Read Enable & Read Clock Echo outputs aid high speed operation
• User selectable Asynchronous read and/or write port timing
• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage
• 3.3V Input tolerant
• Mark & Retransmit, resets read pointer to user marked position
• Write Chip Select (WCS) input enables/disables Write operations
• Read Chip Select (RCS) synchronous to RCLK
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
• Program programmable flags by either serial or parallel means
• Selectable synchronous/asynchronous timing modes for Almost-
FUNCTIONALBLOCKDIAGRAM
D0 -Dn (x18 or x9)
LD SEN
SCLK
WEN
WCLK/WR
WCS
INPUT REGISTER
OFFSET REGISTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
WRITE CONTROL
LOGIC
ASYW
FLAG
LOGIC
RAM ARRAY
2,048 x 18 or 4,096 x 9
4,096 x 18 or 8,192 x 9
WRITE POINTER
8,192 x 18 or 16,384 x 9
16,384 x 18 or 32,768 x 9
32,768 x 18 or 65,536 x 9
65,536 x 18 or 131,072 x 9
131,072 x 18 or 262,144 x 9
262,144 x 18 or 524,288 x 9
524,288 x 18 or 1,048,576 x 9
BE
CONTROL
LOGIC
READ POINTER
IP
IW
BUS
CONFIGURATION
OW
RT
READ
CONTROL
LOGIC
MARK
ASYR
MRS
PRS
OUTPUT REGISTER
RESET
LOGIC
TCK
TRST
TMS
TDO
JTAG CONTROL
(BOUNDARY SCAN)
RCLK/RD
REN
RCS
TDI
Vref
WHSTL
RHSTL
SHSTL
HSTL I/0
CONTROL
EREN
OE
5909 drw01
Q0 -Qn (x18 or x9)
ERCLK
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FEBRUARY 2009
1
©
2009 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5909/19
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
PINCONFIGURATIONS
A1 BALL PAD CORNER
A
WCS
PRS
LD
OW
HF
BE
ASYR
PFM
EREN
EF/OR
REN
FF/IR
IP
MARK
RCLK
RT
B
C
WCLK MRS FWFT/SI PAF
SHSTL
RHSTL
PAE
FSEL0
FSEL1
DNC
WHSTL
WEN
ASYW
VDDQ
VDDQ
VDDQ
VCC
VCC
V
DDQ
VDDQ
VDDQ
D
E
SEN
IW
V
DDQ
VCC
VCC
GND
GND
GND
GND
VCC
VCC
VDDQ
RCS
OE
VCC
GND
GND
GND
VCC
VDDQ
GND
GND
SCLK
VREF
D15
D13
D11
D9
VDDQ
Q17
Q16
Q15
F
D17
D16
D14
D12
D10
VCC
GND
GND
VCC
VDDQ
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
G
VCC
VCC
VDDQ
H
J
VDDQ
VDDQ
Q14
Q12
Q10
VCC
VCC
Q13
Q11
Q9
VDDQ
VCC
VDDQ
VCC
GND
GND
VCC
VCC
K
L
VDDQ
VDDQ
VCC
VCC
V
DDQ
VDDQ
VDDQ
VDDQ
D7
D5
D6
2
D3
D4
3
D1
D2
4
TCK
TMS
6
TDI
TD0
7
ERCLK
Q0
Q1
Q2
9
Q3
Q4
10
Q5
Q6
11
Q8
TRST
D0
M
Q7
D8
1
5
8
12
5909 drw02
NOTE:
1. DNC - Do Not Connect.
IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895 Only
PBGA: 1mm pitch, 13mm x 13mm (BB144-1, order code: BB)
TOP VIEW
2
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
PINCONFIGURATIONS(CONTINUED)
A1 BALL PAD CORNER
A
PRS
MRS
LD
FF
PAF
HF
EREN
EF
OE
RCS
RT
V
V
V
V
V
V
CC
CC
CC
CC
V
V
V
V
V
CC
CC
CC
V
V
CC
CC
V
V
V
CC
CC
CC
V
CC
CC
V
V
V
CC
CC
CC
WCLK
GND
GND
RCLK
V
V
DDQ
DDQ
V
DDQ
V
V
DDQ
DDQ
V
V
DDQ
DDQ
VDDQ
B
C
D
E
F
V
V
V
DDQ
DDQ
VDDQ
WEN
REN
V
V
V
V
CC
V
CC
MARK
V
DDQ
V
DDQ
V
V
V
V
V
DDQ
DDQ
VDDQ
WCS
PAE
IP
GND
GND
OW
ASYR
CC
CC
CC FWFT/SI
FS0
SHSTL
FS1
DNC
RHSTL
PFM
GND
GND
GND
V
DDQ
V
V
V
DDQ
BE
CC
CC
CC
CC
GND
GND
V
V
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
V
CC
G
H
J
DDQ
V
CC
SCLK WHSTL
V
DDQ
V
DDQ
SEN
V
CC
VCC
V
CC
GND
GND
GND
GND
GND
GND
GND
V
DDQ
V
V
DDQ
DDQ
V
V
V
DDQ
DDQ
ASYW
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
CC
CC
V
V
CC
CC
V
V
CC
CC
VREF
VDDQ
K
L
V
IW
V
DDQ
V
DDQ
DDQ
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
D17
DNC
DNC
DNC
DNC
GND
GND
GND
GND
VDDQ
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
DNC
M
N
P
R
T
DNC
DNC
DNC
DNC
Q14
Q15
GND
GND
GND
GND
Q2
GND
Q3
GND
Q8
DNC
DNC
DNC
DNC
D13
GND
D10
D11
GND
D5
GND
D4
GND
D1
GND
TMS
GND
TDO
TDI
GND
Q0
GND
Q11
U
V
D14
D7
D8
D2
Q1
Q6
Q5
Q9
Q12
TRST
DNC
Q17
17
V
CC
D16
D15
D0
ERCLK
Q4
Q7
Q10
Q13
V
DDQ
D12
D9
D6
D3
TCK
GND
Q16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
18
5909 drw02a
NOTE:
1. DNC - Do Not Connect.
IDT72T18105/72T18115/72T18125 Only
PBGA: 1mm pitch, 19mm x 19mm (BB240-1, order code: BB)
TOP VIEW
3
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
operation,whichconsistsofactivatingRENandenablingarisingRCLKedge,
willshiftthewordfrominternalmemorytothedataoutputlines.
InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectly
tothedataoutputlinesafterthreetransitionsoftheRCLKsignal.ARENdoes
not have to be asserted for accessing the first word. However, subsequent
wordswrittentotheFIFOdorequireaLOWonRENforaccess. Thestateof
theFWFT/SIinputduringMasterResetdeterminesthetimingmodeinuse.
ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFO
canprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs
inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding
data inputs of the next). No external logic is required.
These FIFOs have five flagpins, EF/OR (EmptyFlagorOutputReady),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Emptyflag)andPAF(ProgrammableAlmost-Fullflag). TheEFandFF
functions are selected in IDT Standard mode. The IR and OR functions are
selected in FWFT mode. HF, PAE and PAF are always available for use,
irrespectiveoftimingmode.
PAEandPAFcanbeprogrammedindependentlytoswitchatanypointin
memory. Programmableoffsetsdeterminetheflagswitchingthresholdandcan
beloadedbytwomethods:parallelorserial. Eightdefaultoffsetsettingsarealso
provided,sothatPAEcanbesettoswitchatapredefinednumberoflocations
from the empty boundary and the PAF threshold can also be set at similar
predefinedvaluesfromthefullboundary. Thedefaultoffsetvaluesaresetduring
MasterResetbythe state ofthe FSEL0, FSEL1, and LD pins.
For serial programming, SEN together with LD on each rising edge of
SCLK,areusedtoloadtheoffsetregistersviatheSerialInput(SI). Forparallel
programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused
toloadtheoffsetregistersviaDn. RENtogetherwithLDoneachrisingedge
ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether
serialorparalleloffsetloadinghasbeenselected.
DESCRIPTION:
The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/
72T18105/72T18115/72T18125 are exceptionally deep, extremely high
speed,CMOSFirst-In-First-Out(FIFO)memorieswithclockedreadandwrite
controls and a flexible Bus-Matching x18/x9 data flow. These FIFOs offer
severalkeyuserbenefits:
• Flexible x18/x9 Bus-Matching on both read and write ports
• AuserselectableMARKlocationforretransmit
• User selectable I/O structure for HSTL or LVTTL
• Asynchronous/Synchronous translationonthereadorwriteports
• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan
emptyFIFOtothe time itcanbe read, is fixedandshort.
• Highdensityofferingsupto9Mbit
Bus-MatchingTeraSyncFIFOs are particularlyappropriate fornetwork,
video,telecommunications,datacommunicationsandotherapplicationsthat
needtobufferlargeamountsofdataandmatchbussesofunequalsizes.
EachFIFOhas a data inputport(Dn)anda data outputport(Qn), bothof
whichcanassumeeithera18-bitora9-bitwidthasdeterminedbythestateof
externalcontrolpins InputWidth(IW)andOutputWidth(OW)pinduringthe
MasterResetcycle.
TheinputportcanbeselectedaseitheraSynchronous(clocked)interface,
or Asynchronous interface. During Synchronous operation the input port is
controlledbyaWriteClock(WCLK)inputandaWriteEnable(WEN)input. Data
presentontheDndatainputs is writtenintotheFIFOoneveryrisingedgeof
WCLKwhenWENisasserted.DuringAsynchronousoperationonlytheWR
inputisusedtowritedataintotheFIFO.DataiswrittenonarisingedgeofWR,
theWENinputshouldbetiedtoitsactivestate,(LOW).
TheoutputportcanbeselectedaseitheraSynchronous(clocked)interface,
orAsynchronousinterface.DuringSynchronousoperationtheoutputportis
controlledbyaReadClock(RCLK)inputandReadEnable(REN)input. Data
is read from the FIFO on every rising edge of RCLK when REN is asserted.
DuringAsynchronousoperationonlytheRDinputisusedtoreaddatafromthe
FIFO.Datais readonarisingedgeofRD,theRENinputshouldbetiedtoits
activestate,LOW.WhenAsynchronousoperationisselectedontheoutputport
theFIFOmustbeconfiguredforStandardIDTmode,alsotheRCSshouldbe
tiedLOWandtheOEinputusedtoprovidethree-statecontroloftheoutputs,Qn.
Theoutputportcanbeselectedforeither2.5VLVTTLorHSTLoperation,
thisoperationisselectedbythestateoftheRHSTLinputduringamasterreset.
AnOutputEnable(OE)inputisprovidedforthree-statecontroloftheoutputs.
AReadChipSelect(RCS)inputisalsoprovided,theRCSinputissynchronized
tothereadclock,andalsoprovidesthree-statecontroloftheQndataoutputs.
When RCS is disabled, the data outputs will be high impedance. During
Asynchronousoperationoftheoutputport,RCSshouldbeenabled,heldLOW.
Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are
provided.Theseareoutputs fromthereadportoftheFIFOthatarerequired
forhighspeeddatacommunication,toprovidetightersynchronizationbetween
thedatabeingtransmittedfromtheQnoutputsandthedatabeingreceivedby
theinputdevice.Datareadfromthereadportisavailableontheoutputbuswith
respect to EREN and ERCLK, this is very useful when data is being read at
highspeed.TheERCLKandERENoutputsarenon-functionalwhentheRead
portissetupforAsynchronousmode.
DuringMasterReset(MRS)thefollowingeventsoccur: thereadandwrite
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standardmode orFWFTmode.
The Partial Reset (PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, programmable flag
programmingmethod,anddefaultorprogrammedoffsetsettingsexistingbefore
PartialResetremainunchanged.Theflagsareupdatedaccordingtothetiming
modeandoffsetsineffect. PRSisusefulforresettingadeviceinmid-operation,
whenreprogrammingprogrammableflagswouldbeundesirable.
ItisalsopossibletoselectthetimingmodeofthePAE(ProgrammableAlmost-
Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing
modescanbesettobeeitherasynchronousorsynchronousforthePAEand
PAFflags.
IfasynchronousPAE/PAFconfigurationisselected, thePAEisasserted
LOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGHontheLOW-
to-HIGHtransitionofWCLK.Similarly,thePAFisassertedLOWontheLOW-
to-HIGHtransitionofWCLKandPAF is resettoHIGHonthe LOW-to-HIGH
transitionofRCLK.
IfsynchronousPAE/PAFconfigurationisselected,thePAEisassertedand
updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is
assertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.Themode
desiredisconfiguredduringMasterResetbythestateoftheProgrammableFlag
Mode (PFM) pin.
ThisdeviceincludesaRetransmitfromMarkfeaturethatutilizestwocontrol
inputs,MARKand,RT(Retransmit).IftheMARKinputisenabledwithrespect
totheRCLK,thememorylocationbeingreadatthatpointwillbemarked.Any
subsequentretransmitoperation,RTgoesLOW,willresetthereadpointerto
this‘marked’location.
ThefrequenciesofboththeRCLKandtheWCLKsignalsmayvaryfrom0
tofMAXwithcompleteindependence. Therearenorestrictionsonthefrequency
oftheoneclockinputwithrespecttotheother.
Therearetwopossibletimingmodesofoperationwiththesedevices:IDT
Standard mode and First Word Fall Through (FWFT) mode.
InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear
onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread
4
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
Thedevicecanbeconfiguredwithdifferentinputandoutputbuswidthsas currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol
shown in Table 1.
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
ABig-Endian/Little-Endiandatawordformatis provided.This functionis
Both an Asynchronous Output Enable pin (OE) and Synchronous Read
useful when data is written into the FIFO in long word format (x18) and read ChipSelectpin(RCS)areprovidedontheFIFO.TheSynchronousReadChip
outoftheFIFOinsmallword(x9)format.IfBig-Endianmodeisselected,then SelectissynchronizedtotheRCLK.Boththeoutputenableandreadchipselect
themostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwillberead control the output buffer of the FIFO, causing the buffer to be either HIGH
outoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endianformat impedanceorLOWimpedance.
isselected,thentheleastsignificantbyteofthelongwordwrittenintotheFIFO
AJTAGtestportisprovided,heretheFIFOhasfullyfunctionalBoundary
willbereadoutfirst,followedbythemostsignificantbyte.Themodedesiredis Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and
configuredduringmasterresetbythestateoftheBig-Endian(BE)pin.
BoundaryScanArchitecture.
TheInterspersed/Non-InterspersedParity(IP)bitfunctionallowstheuser
TheTeraSyncFIFOhas thecapabilityofoperatingits ports (writeand/or
to select the parity bit in the word loaded into the parallel port (D0-Dn) when read)ineitherLVTTLorHSTLmode,eachportsselectionindependentofthe
programmingtheflagoffsets.IfInterspersedParitymodeisselected,thenthe other.ThewriteportselectionismadeviaWHSTLandthereadportselection
FIFOwillassumethattheparitybitislocatedinbitpositionsD8duringtheparallel via RHSTL. AnadditionalinputSHSTLis alsoprovided, this allows the user
programmingoftheflagoffsets. IfNon-InterspersedParitymodeisselected, toselectHSTLoperationforotherpinsonthedevice(notassociatedwiththe
then D8 is assumed to be a valid bit and D16 and D17 are ignored. IP mode write or read ports).
is selectedduring MasterResetbythestateoftheIPinputpin.This modeis
relevantonlywhenthe inputwidthis settox18mode.
The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/
72T18105/72T18115/72T18125arefabricatedusingIDT’shighspeedsub-
If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill micronCMOStechnology.
automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply
5
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
PARTIAL RESET (PRS) MASTER RESET (MRS)
WRITE CLOCK (WCLK/WR)
WRITE ENABLE (WEN)
READ CLOCK (RCLK/RD)
READ ENABLE (REN)
OUTPUT ENABLE (OE)
WRITE CHIP SELECT (WCS)
IDT
LOAD (LD)
READ CHIP SELECT (RCS)
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
72T18105
72T18115
72T18125
(x18, x9) DATA IN (D
0
- Dn)
(x18, x9) DATA OUT (Q0 - Qn)
RCLK ECHO, ERCLK
REN ECHO, EREN
MARK
SERIAL CLOCK (SCLK)
SERIAL ENABLE(SEN)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
EMPTY FLAG/OUTPUT READY (EF/OR)
PROGRAMMABLE ALMOST-EMPTY (PAE)
HALF-FULL FLAG (HF)
FULL FLAG/INPUT READY (FF/IR)
PROGRAMMABLE ALMOST-FULL (PAF)
BIG-ENDIAN/LITTLE-ENDIAN (BE)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
5909 drw03
OUTPUT WIDTH (OW)
INPUT WIDTH (IW)
Figure 1. Single Device Configuration Signal Flow Diagram
TABLE 1 — BUS-MATCHING CONFIGURATION MODES
IW
OW
Write Port Width
Read Port Width
L
L
x18
x18
x9
x18
x9
L
H
H
H
L
x18
x9
H
x9
6
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
PINDESCRIPTION
Symbol
Name
I/OTYPE
Description
(1)
ASYR Asynchronous
LVTTL
INPUT
AHIGHonthisinputduringMasterResetwillselectSynchronousreadoperationfortheoutputport.ALOW
willselectAsynchronousoperation.IfAsynchronousisselectedtheFIFOmustoperateinIDTStandardmode.
ReadPort
(1)
ASYW Asynchronous
LVTTL
INPUT
AHIGHonthis inputduringMasterResetwillselectSynchronous writeoperationfortheinputport.ALOW
willselectAsynchronousoperation.
WritePort
(1)
BE
Big-Endian/
Little-Endian
LVTTL
INPUT
DuringMasterReset, a LOWonBE willselectBig-Endianoperation. AHIGHonBE duringMasterReset
willselectLittle-Endianformat.
D0–D17 DataInputs
HSTL-LVTTL Data inputs foran18-or9-bitbus. Whenin18-or9-bitmode, the unusedinputpins shouldbe tiedtoGND.
INPUT
EF/OR EmptyFlag/
HSTL-LVTTL IntheIDTStandardmode,theEFfunctionisselected.EFindicateswhetherornottheFIFOmemoryisempty.
OUTPUT InFWFTmode,theORfunctionis selected.ORindicates whetherornotthereis validdataavailableatthe
outputs.
OutputReady
ERCLK RCLK Echo
HSTL-LVTTL ReadclockEchooutput, onlyavailable whenthe Readis setupforSynchronous mode.
OUTPUT
EREN Read Enable Echo HSTL-LVTTL Read Enable Echo output, only available when the Read is setup for Synchronous mode.
OUTPUT
FF/IR
Full Flag/
Input Ready
HSTL-LVTTL Inthe IDTStandardmode, the FF functionis selected. FF indicates whetherornotthe FIFOmemoryis
OUTPUT full. Inthe FWFTmode, the IRfunctionis selected. IR indicates whetherornotthereis spaceavailablefor
writingtotheFIFOmemory.
FSEL0(1) FlagSelectBit0
FSEL1(1) FlagSelectBit1
FWFT/ FirstWordFall
LVTTL
INPUT
DuringMasterReset,thisinputalongwithFSEL1andtheLDpin,willselectthedefaultoffsetvaluesforthe
programmableflags PAE andPAF.Thereareuptoeightpossiblesettings available.
DuringMasterReset,thisinputalongwithFSEL0andtheLDpinwillselectthedefaultoffsetvaluesforthe
programmableflags PAE andPAF.Thereareuptoeightpossiblesettings available.
LVTTL
INPUT
HSTL-LVTTL DuringMasterReset,selects FirstWordFallThroughorIDTStandardmode.AfterMasterReset,this pin
SI
Through/Serial In
Half-FullFlag
InterspersedParity
InputWidth
INPUT
functionsasaserialinputforloadingoffsetregisters.IfAsynchronousoperationofthereadporthasbeen
selectedthentheFIFOmustbesetupinIDTStandardmode.
HF
IP(1)
HSTL-LVTTL HFindicates whethertheFIFOmemoryis moreorless thanhalf-full.
OUTPUT
LVTTL
INPUT
DuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode.AHIGHwillselectInterspersed
Paritymode.
(1)
IW
LVTTL
INPUT
This pin,alongwithOW,selects thebus widthofthewriteport.SeeTable1forbus sizeconfiguration.
LD
Load
HSTL-LVTTL This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1,
INPUT
determinesoneofeightdefaultoffsetvaluesforthePAEandPAFflags,alongwiththemethodbywhichthese
offsetregisterscanbeprogrammed,parallelorserial(seeTable2).AfterMasterReset,thispinenableswriting
to and reading from the offset registers. THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE
OR READ DATA TO/FROM THE FIFO MEMORY.
MARK MarkforRetransmit HSTL-LVTTL Whenthispinisassertedthecurrentlocationofthereadpointerwillbemarked.AnysubsequentRetransmit
INPUT operationwillresetthereadpointertothisposition.
MRS
MasterReset
HSTL-LVTTL MRSinitializes thereadandwritepointers tozeroandsets theoutputregistertoallzeroes.DuringMaster
INPUT
Reset,theFIFOisconfiguredforeitherFWFTorIDTStandardmode,Bus-Matchingconfigurations,
Synchronous/Asynchronousoperationofthereadorwriteport,oneofeightprogrammableflagdefaultsettings,
serialorparallelprogrammingoftheoffsetsettings,Big-Endian/Little-Endianformat,zerolatencytimingmode,
interspersedparity,andsynchronousversusasynchronousprogrammableflagtimingmodes.
OE
OutputEnable
OutputWidth
HSTL-LVTTL OEprovidesAsynchronousthree-statecontrolofthedataoutputs,Qn.DuringaMasterorPartialResetthe
INPUT
OEinputistheonlyinputthatprovideHigh-Impedancecontrolofthedataoutputs.
(1)
OW
LVTTL
INPUT
This pin, alongwithIW, selects the bus widthofthe readport. See Table 1forbus size configuration.
PAE
PAF
Programmable
HSTL-LVTTL PAEgoesLOWifthenumberofwordsintheFIFOmemoryislessthanoffsetn,whichisstoredintheEmpty
OUTPUT Offsetregister.PAEgoesHIGHifthenumberofwordsintheFIFOmemoryisgreaterthanorequaltooffsetn.
Almost-EmptyFlag
Programmable
Almost-FullFlag
HSTL-LVTTL PAFgoes HIGHifthenumberoffreelocations intheFIFOmemoryis morethanoffsetm,whichis storedin
OUTPUT theFullOffsetregister.PAFgoesLOWifthenumberoffreelocationsintheFIFOmemoryislessthanorequal
tom.
(1)
PFM
Programmable
Flag Mode
LVTTL DuringMasterReset,aLOWonPFMwillselectAsynchronousProgrammableflagtimingmode.AHIGHon
INPUT
PFMwillselectSynchronousProgrammableflagtimingmode.
7
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
PINDESCRIPTION(CONTINUED)
Symbol
Name
I/OTYPE
Description
PRS
PartialReset
HSTL-LVTTL PRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes.DuringPartialReset,
INPUT
theexistingmode(IDTorFWFT),programmingmethod(serialorparallel),andprogrammableflagsettings
are allretained.
Q0–Q17 DataOutputs
RCLK/ ReadClock/
HSTL-LVTTL Data outputs foran18-or9-bitbus. Whenin9-bitmode, anyunusedoutputpins shouldnotbe connected.
OUTPUT Outputsarenot5VtolerantregardlessofthestateofOE andRCS.
HSTL-LVTTL IfSynchronousoperationofthereadporthasbeenselected,whenenabledbyREN,therisingedgeofRCLK
RD
ReadStrobe
INPUT
readsdatafromtheFIFOmemoryandoffsetsfromtheprogrammableregisters.IfLDisLOW,thevaluesloaded
intotheoffsetregistersisoutputonarisingedgeofRCLK.IfAsynchronousoperationofthereadporthasbeen
selected,arisingedgeonRDreadsdatafromtheFIFOinanAsynchronousmanner.RENshouldbetiedLOW.
RCS
REN
ReadChipSelect HSTL-LVTTL RCSprovidessynchronouscontrolofthereadportandoutputimpedanceofQn,synchronoustoRCLK.During
INPUT
aMasterorPartialResettheRCS inputis don’tcare,ifOE is LOWthedataoutputs willbeLow-Impedance
regardless ofRCS.
ReadEnable
HSTL-LVTTL If Synchronous operationofthe readporthas beenselected, REN enables RCLKforreadingdata fromthe
INPUT
FIFOmemoryandoffsetregisters.IfAsynchronous operationofthereadporthas beenselected,theREN
inputshouldbetiedLOW.
(1)
RHSTL Read Port HSTL
Select
LVTTL
INPUT
This pin is used to select HSTL or 2.5V LVTTL outputs for the FIFO. If HSTL or eHSTL outputs are
required,thisinputmustbetiedHIGH.OtherwiseitshouldbetiedLOW.
RT
Retransmit
HSTL-LVTTL RTassertedontherisingedgeofRCLKinitializestheREADpointertozero,setstheEFflagtoLOW(ORtoHIGH
INPUT
inFWFTmode)anddoesn’tdisturbthewritepointer,programmingmethod,existingtimingmodeorprogrammable
flagsettings.IfamarkhasbeensetviatheMARKinputpin,thenthereadpointerwilljumptothe‘mark’location.
SCLK SerialClock
SEN SerialEnable
HSTL-LVTTL ArisingedgeonSCLKwillclocktheserialdatapresentontheSIinputintotheoffsetregisters providingthat
INPUT SEN is enabled.
HSTL-LVTTL SENenablesserialloadingofprogrammableflagoffsets.
INPUT
SHSTL SystemHSTL
Select
LVTTL
INPUT
Allinputs notassociatedwiththe write orreadportcanbe selectedforHSTLoperationvia the SHSTLinput.
(2)
TCK
JTAGClock
HSTL-LVTTL ClockinputforJTAGfunction.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.Testoperations
INPUT
of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and
outputschangeonthefallingedgeofTCK.IftheJTAGfunctionisnotusedthissignalneedstobetiedtoGND.
(2)
TDI
JTAGTestData HSTL-LVTTL OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,test
Input
INPUT
dataseriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister,IDRegisterandBypass
Register.Aninternalpull-upresistorforcesTDIHIGHifleftunconnected.
(2)
TDO
JTAGTestData HSTL-LVTTL OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,test
Output
OUTPUT dataseriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstructionRegister,IDRegister
andBypassRegister.Thisoutputishighimpedanceexceptwhenshifting,whileinSHIFT-DRandSHIFT-IR
controllerstates.
TMS(2) JTAGMode
Select
HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the
INPUT
thedevicethroughitsTAPcontrollerstates.Aninternalpull-upresistorforcesTMSHIGHifleftunconnected.
(2)
TRST JTAGReset
HSTL-LVTTL TRSTisanasynchronousresetpinfortheJTAGcontroller.TheJTAGTAPcontrollerdoesnotautomatically
INPUT
resetuponpower-up,thus itmustberesetbyeitherthis signalorbysettingTMS=HIGHforfiveTCKcycles.
IftheTAPcontrollerisnotproperlyresetthentheFIFOoutputswillalwaysbeinhigh-impedance.IftheJTAG
function is used but the user does not want to use TRST, then TRST can be tied with MRS to ensure proper
FIFOoperation.IftheJTAGfunctionis notusedthenthis signalneeds tobetiedtoGND.
WEN
WCS
WriteEnable
HSTL-LVTTL WhenSynchronousoperationofthewriteporthasbeenselected,WENenablesWCLKforwritingdatainto
INPUT
theFIFOmemoryandoffsetregisters.IfAsynchronousoperationofthewriteporthasbeenselected,the
WENinputshouldbetiedLOW.
WriteChipSelect HSTL-LVTTL The WCS pin can be regarded as a second WEN input, enabling/disabling write operations.
INPUT
WCLK/ WriteClock/
WR WriteStrobe
HSTL-LVTTL IfSynchronousoperationofthewriteporthasbeenselected,whenenabledbyWEN,therisingedgeofWCLK
INPUT
writesdataintotheFIFO.IfAsynchronousoperationofthewriteporthasbeenselected,WRwritesdatainto
the FIFO on a rising edge in an Asynchronous manner, (WEN should be tied to its active state).
8
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
PINDESCRIPTION(CONTINUED)
Symbol
Name
I/OTYPE
Description
(1)
WHSTL WritePortHSTL
Select
LVTTL
INPUT
ThispinisusedtoselectHSTLor2.5VLVTTLinputsfortheFIFO.IfHSTLinputsarerequired,thisinputmust
betiedHIGH.OtherwiseitshouldbetiedLOW.
VCC
GND
Vref
+2.5VSupply
GroundPin
Reference
Voltage
I
I
I
These are VCC supply inputs and must be connected to the 2.5V supply rail.
These are Ground pins and must be connected to the GND rail.
ThisisaVoltageReferenceinputandmustbeconnectedtoavoltageleveldeterminedfromthetable,
“RecommendedDCOperatingConditions”.This provides thereferencevoltagewhenusingHSTLclass
inputs.IfHSTLclass inputs arenotbeingused,this pinshouldbetiedLOW.
VDDQ
O/PRailVoltage
I
This pin should be tied to the desired voltage rail for providing power to the output drivers.
NOTES:
1. Inputs should not change state after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 29-32 and Figures 6-8.
9
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
ABSOLUTEMAXIMUMRATINGS
CAPACITANCE(TA = +25°C, f = 1.0MHz)
Parameter(1)
Conditions
Max.
Unit
Symbol
Rating
Commercial
Unit
Symbol
VTERM
TerminalVoltage
with respect to GND
–0.5 to +3.6(2)
V
(2,3)
(3)
CIN
Input
Capacitance
VIN = 0V
10
pF
(1,2)
TSTG
IOUT
StorageTemperature
DCOutputCurrent
–55 to +125
–50 to +50
°C
mA
COUT
Output
Capacitance
VOUT = 0V
10
pF
NOTES:
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
1. With output deselected, (OE ≥ VIH).
2. Characterized values, not currently tested.
3. CIN for Vref is 20pF.
2. Compliant with JEDEC JESD8-5. VCC terminal only.
RECOMMENDED DC OPERATING CONDITIONS
Symbol
Parameter
Min.
2.375
0
Typ.
2.5
0
Max.
2.625
0
Unit
V
VCC
SupplyVoltage
SupplyVoltage
GND
V
VIH
InputHighVoltage
⎯ LVTTL
⎯ eHSTL
⎯ HSTL
1.7
VREF+0.2
VREF+0.2
—
—
—
3.45
VDDQ+0.3
VDDQ+0.3
V
V
V
VIL
InputLowVoltage
⎯ LVTTL
⎯ eHSTL
⎯ HSTL
-0.3
-0.3
-0.3
—
—
—
0.7
VREF-0.2
VREF-0.2
V
V
V
VREF(1)
VoltageReferenceInput ⎯ eHSTL
⎯ HSTL
0.8
0.68
0.9
0.75
1.0
0.9
V
V
TA
TA
OperatingTemperatureCommercial
OperatingTemperatureIndustrial
0
—
—
70
85
°C
°C
-40
NOTE:
1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.
2. Outputs are not 3.3V tolerant.
10
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
DCELECTRICALCHARACTERISTICS
(Commercial: VCC = 2.5V ± 0.125V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)
Symbol
Parameter
Min.
–10
Max.
10
Unit
µA
µA
V
V
V
ILI
InputLeakageCurrent
OutputLeakageCurrent
OutputLogic“1”Voltage,
ILO
–10
10
(5)
VOH
IOH = –8 mA @VDDQ = 2.5V 0.125V (LVTTL)
IOH = –8 mA @VDDQ = 1.8V 0.1V (eHSTL)
IOH = –8 mA @VDDQ = 1.5V 0.1V (HSTL)
VDDQ-0.4
VDDQ-0.4
VDDQ-0.4
—
—
—
VOL
OutputLogic“0”Voltage,
IOL = 8 mA @VDDQ = 2.5V 0.125V (LVTTL)
IOL = 8 mA @VDDQ = 1.8V 0.1V (eHSTL)
IOL = 8 mA @VDDQ = 1.5V 0.1V (HSTL)
—
—
—
0.4V
0.4V
0.4V
V
V
V
IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895
ICC1(1,2)
ICC2(1)
Active VCC Current (VCC = 2.5V)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
40
60
60
mA
mA
mA
Standby VCC Current (VCC = 2.5V) I/O = LVTTL
—
—
—
10
50
50
mA
mA
mA
I/O = HSTL
I/O = eHSTL
IDT72T18105/72T18115/72T18125
ICC1(1,2)
ICC2(1)
Active VCC Current (VCC = 2.5V)
I/O = LVTTL
I/O = HSTL
I/O = eHSTL
—
—
—
50
70
70
mA
mA
mA
Standby VCC Current (VCC = 2.5V) I/O = LVTTL
—
—
—
20
60
60
mA
mA
mA
I/O = HSTL
I/O = eHSTL
NOTES:
1. Both WCLK and RCLK toggling at 20MHz. Data inputs toggling at 10MHz. WCS = HIGH, REN or RCS = HIGH.
2. For the IDT72T18105/72T18115/72T18125, typical ICC1 calculation (with data outputs in Low-Impedance):
for LVTTL I/O ICC1 (mA) = 1.0 x fs, fs = WCLK = RCLK frequency (in MHz)
for HSTL or eHSTL I/O ICC1 (mA) = 30 + (1.0 x fs), fs = WCLK = RCLK frequency (in MHz)
For the IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895, typical ICC1 calculation (with data outputs in Low-Impedance):
for LVTTL I/O ICC1 (mA) = 0.7mA x fs, fs = WCLK = RCLK frequency (in MHz)
for HSTL or eHSTL I/O ICC1 (mA) = 30 + (0.7 x fs), fs = WCLK = RCLK frequency (in MHz).
3. For all devices, typical IDDQ calculation: with data outputs in High-Impedance: IDDQ (mA) = 0.15 x fs, fs = WCLK = RCLK frequency (in MHz)
with data outputs in Low-Impedance: IDDQ (mA) = (CL x VDDQ x fs x N)/2000
fs = WCLK = RCLK frequency (in MHz), VDDQ = 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL, CL = capacitive load (pf), tA = 25°C,
N= Number of outputs switching.
4. Total Power consumed: PT = (VCC x ICC) + VDDQ x IDDQ).
5. Outputs are not 3.3V tolerant.
11
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
ACELECTRICALCHARACTERISTICS(1) ⎯ SYNCHRONOUSTIMING
(Commercial: VCC = 2.5V 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V 5%, TA = -40°C to +85°C)
Commercial
Com’l & Ind’l(2)
Commercial
Commercial
IDT72T1845L4-4 IDT72T1845L5
IDT72T1855L4-4 IDT72T1855L5
IDT72T1865L4-4 IDT72T1865L5
IDT72T1875L4-4 IDT72T1875L5
IDT72T1885L4-4 IDT72T1885L5
IDT72T1895L4-4 IDT72T1895L5
IDT72T1845L6-7
IDT72T1855L6-7
IDT72T1865L6-7
IDT72T1875L6-7
IDT72T1885L6-7
IDT72T1895L6-7
IDT72T18105L4-4 IDT72T18105L5 IDT72T18105L6-7 IDT72T18105L10
IDT72T18115L4-4 IDT72T18115L5 IDT72T18115L6-7 IDT72T18115L10
IDT72T18125L4-4 IDT72T18125L5 IDT72T18125L6-7 IDT72T18125L10
Symbol
fC
Parameter
Clock Cycle Frequency (Synchronous)
DataAccessTime
Min.
—
0.6
4.44
2.0
2.0
1.2
0.5
1.2
0.5
1.2
0.5
1.2
0.5
—
100
45
Max.
225
3.4
—
—
—
—
—
—
—
—
—
—
—
10
Min.
—
0.6
5
Max.
200
3.6
—
—
—
—
—
—
—
—
—
—
—
10
Min.
—
0.6
6.7
2.8
2.8
2.0
0.5
2.0
0.5
2.0
0.5
2.0
0.5
—
100
45
45
Max.
150
3.8
—
—
—
—
—
—
—
—
—
—
—
10
Min.
—
0.6
10
4.5
4.5
3.0
0.5
3.0
0.5
3.0
0.5
3.0
0.5
—
100
45
45
15
5
Max.
100
4.5
—
—
—
—
—
—
—
—
—
—
—
10
Unit
MHz
ns
tA
tCLK
Clock Cycle Time
ns
tCLKH
tCLKL
tDS
Clock High Time
2.3
2.3
1.5
0.5
1.5
0.5
1.5
0.5
1.5
0.5
—
100
45
45
15
5
ns
Clock Low Time
ns
DataSetupTime
ns
tDH
DataHoldTime
ns
tENS
EnableSetupTime
ns
tENH
tLDS
EnableHoldTime
ns
LoadSetupTime
ns
tLDH
LoadHoldTime
ns
tWCSS
tWCSH
fS
WCSsetuptime
WCSholdtime
Clock Cycle Frequency (SCLK)
ns
ns
MHz
ns
tSCLK
tSCKH
tSCKL
tSDS
Serial Clock Cycle
—
—
—
—
—
—
—
—
—
—
—
10
—
—
—
—
—
—
—
—
—
—
—
12
—
—
—
—
—
—
—
—
—
—
—
15
—
—
—
—
—
—
—
—
—
—
—
15
Serial Clock High
ns
Serial Clock Low
45
ns
SerialDataInSetup
15
15
ns
tSDH
tSENS
tSENH
tRS
Serial Data In Hold
5
5
ns
SerialEnableSetup
5
5
5
5
ns
SerialEnableHold
ResetPulseWidth(3)
5
5
5
5
ns
30
30
15
4
30
30
15
4
ns
tRSS
ResetSetupTime
15
15
ns
tHRSS
tRSR
HSTLResetSetupTime
ResetRecoveryTime
ResettoFlagandOutputTime
Write Clock to FF or IR
Read Clock to EF or OR
WriteClocktoSynchronousProgrammableAlmost-FullFlag
ReadClocktoSynchronousProgrammableAlmost-EmptyFlag
RCLK to Echo RCLK output
RCLK to Echo REN output
4
4
µs
ns
10
10
—
—
—
—
—
—
—
—
—
4
10
10
—
—
—
—
—
—
—
—
—
7
tRSF
—
—
—
—
—
—
—
—
—
3.5
4
—
—
—
—
—
—
—
—
—
5
ns
tWFF
tREF
3.4
3.4
3.4
3.4
3.8
3.4
3.4
3.4
—
—
3.6
3.6
3.6
3.6
4
3.8
3.8
3.8
3.8
4.3
3.8
3.8
3.8
—
—
4.5
4.5
4.5
4.5
5
ns
ns
tPAFS
tPAES
tERCLK
tCLKEN
tRCSLZ
ns
ns
ns
3.6
3.6
3.6
—
—
4.5
4.5
4.5
—
—
ns
(4)
RCLK to Active from High-Z
ns
(4)
tRCSHZ RCLK to High-Z
ns
tSKEW1 Skew time between RCLK and WCLK for EF/OR and FF/IR
tSKEW2 Skew time between RCLK and WCLK for PAE and PAF
ns
5
6
8
ns
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.
3. Pulse widths less than minimum values are not allowed.
4. Values guaranteed by design, not currently tested.
12
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
ACELECTRICALCHARACTERISTICS⎯ ASYNCHRONOUSTIMING
(Commercial: VCC = 2.5V 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V 5%, TA = -40°C to +85°C)
Commercial
Com’l & Ind’l(2)
Commercial
Commercial
IDT72T1845L4-4
IDT72T1855L4-4
IDT72T1865L4-4
IDT72T1875L4-4
IDT72T1885L4-4
IDT72T1895L4-4
IDT72T1845L5
IDT72T1855L5
IDT72T1865L5
IDT72T1875L5
IDT72T1885L5
IDT72T1895L5
IDT72T1845L6-7
IDT72T1855L6-7
IDT72T1865L6-7
IDT72T1875L6-7
IDT72T1885L6-7
IDT72T1895L6-7
IDT72T18105L4-4 IDT72T18105L5 IDT72T18105L6-7 IDT72T18105L10
IDT72T18115L4-4 IDT72T18115L5 IDT72T18115L6-7 IDT72T18115L10
IDT72T18125L4-4 IDT72T18125L5 IDT72T18125L6-7 IDT72T18125L10
Symbol
fA
Parameter
Cycle Frequency (Asynchronous)
DataAccessTime
Min.
—
0.6
10
Max.
100
8
Min.
—
0.6
12
5
Max.
83
Min.
—
0.6
15
7
Max.
66
Min.
—
0.6
20
8
Max.
50
Unit
MHz
ns
tAA
10
12
14
tCYC
Cycle Time
—
—
—
—
8
—
—
—
—
10
—
—
—
—
12
—
—
—
—
14
ns
tCYH
tCYL
Cycle HIGH Time
4.5
4.5
8
ns
Cycle LOW Time
5
7
8
ns
tRPE
Read Pulse after EF HIGH
Clock to Asynchronous FF
Clock to Asynchronous EF
ClocktoAsynchronousProgrammableAlmost-FullFlag
ClocktoAsynchronousProgrammableAlmost-EmptyFlag
10
—
—
—
—
0
12
—
—
—
—
0
14
—
—
—
—
0
ns
tFFA
tEFA
tPAFA
tPAEA
tOLZ
tOE
—
—
—
—
0
ns
8
10
12
14
ns
8
10
12
14
ns
8
10
12
14
ns
(3)
OutputEnabletoOutputinLowZ
—
3.4
3.4
8
—
3.6
3.6
10
—
3.8
3.8
12
—
4.5
4.5
14
ns
OutputEnabletoOutputValid
—
—
—
—
—
—
—
—
—
—
—
—
ns
(3)
tOHZ
tHF
OutputEnabletoOutputinHighZ
ns
Clock to HF
ns
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.
3. Values guaranteed by design, not currently tested.
13
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
AC TEST LOADS
HSTL
1.5V AC TEST CONDITIONS
VDDQ/2
InputPulseLevels
0.25to1.25V
0.4ns
50
Ω
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
0.75
Z0 = 50Ω
I/O
VDDQ/2
5909 drw04
NOTE:
1. VDDQ = 1.5V±.
Figure 2a. AC Test Load
EXTENDEDHSTL
1.8V AC TEST CONDITIONS
6
5
4
3
2
1
InputPulseLevels
0.4 to 1.4V
0.4ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
0.9
VDDQ/2
NOTE:
1. VDDQ = 1.8V±.
20 30 50 80 100
200
Capacitance (pF)
5909 drw04a
Figure 2b. Lumped Capacitive Load, Typical Derating
2.5VLVTTL
2.5V AC TEST CONDITIONS
InputPulseLevels
GND to 2.5V
1ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
VCC/2
VDDQ/2
NOTE:
1. For LVTTL VCC = VDDQ.
14
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
OUTPUT ENABLE & DISABLE TIMING
Output
Enable
Output
Disable
VIH
OE
VIL
tOE &
tOLZ
tOHZ
V
2
CC
Output
Normally
LOW
V
2
CC
100mV
100mV
100mV
V
OL
V
OH
Output
Normally
HIGH
VCC
100mV
VCC
2
2
5909 drw04b
NOTES:
1. REN is HIGH.
2. RCS is LOW.
READ CHIP SELECT ENABLE & DISABLE TIMING
VIH
tENH
RCS
VIL
tENS
RCLK
tRCSHZ
tRCSLZ
Output
Normally
LOW
VCC
2
V
2
CC
100mV
100mV
100mV
VOL
VOH
Output
Normally
HIGH
VCC
100mV
VCC
2
2
5909 drw04c
NOTES:
1. REN is HIGH.
2. OE is LOW.
15
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
IDT72T1845,(8,192-m)writesfortheIDT72T1855,(16,384-m)writesforthe
IDT72T1865,(32,768-m)writesfortheIDT72T1875,(65,536-m)writesforthe
IDT72T1885,(131,072-m)writesfortheIDT72T1895,(262,144-m)writesfor
theIDT72T18105,(524,288-m)writesfortheIDT72T18115and(1,048,576-m)
writesfortheIDT72T18125.Theoffset“m”isthefulloffsetvalue.Thedefault
settingforthesevaluesarestatedinthefootnoteofTable2.Thisparameteris
alsouserprogrammable.SeesectiononProgrammableFlagOffsetLoading.
WhentheFIFOisfull,theFullFlag(FF)willgoLOW,inhibitingfurtherwrite
operations.Ifnoreadsareperformedafterareset,FFwillgoLOWafterDwrites
totheFIFO.Ifthex18Inputorx18OutputbusWidthisselected,D=2,048writes
for the IDT72T1845, 4,096 writes for the IDT72T1855, 8,192 writes for the
IDT72T1865, 16,384 writes for the IDT72T1875, 32,768 writes for the
IDT72T1885, 65,536 writes for the IDT72T1895, 131,072 writes for the
IDT72T18105,262,144writesfortheIDT72T18115and524,288writesforthe
IDT72T18125.Ifbothx9Inputandx9OutputbusWidthsareselected,D=4,096
writesfortheIDT72T1845,8,192writesfortheIDT72T1855,16,384writesfor
the IDT72T1865, 32,768 writes for the IDT72T1875, 65,536 writes for the
IDT72T1885, 131,072 writes for the IDT72T1895, 262,144 writes for the
IDT72T18105,524,288writesfortheIDT72T18115and1,048,576writesfor
theIDT72T18125,respectively.
If the FIFO is full, the first read operation will cause FF to go HIGH.
SubsequentreadoperationswillcausePAFandHFtogoHIGHattheconditions
describedinTable3.Iffurtherreadoperationsoccur,withoutwriteoperations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offsetvalue.ContinuingreadoperationswillcausetheFIFOtobecomeempty.
WhenthelastwordhasbeenreadfromtheFIFO,theEFwillgoLOWinhibiting
further read operations. REN is ignored when the FIFO is empty.
WhenconfiguredinIDTStandardmode,theEFandFFoutputsaredouble
register-bufferedoutputs.
FUNCTIONALDESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/
72T18105/72T18115/72T18125supporttwodifferenttimingmodesofopera-
tion: IDT Standard mode or First Word Fall Through (FWFT) mode. The
selectionofwhichmodewilloperateisdeterminedduringMasterReset,bythe
stateoftheFWFT/SIinput.
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode
willbeselected.ThismodeusestheEmptyFlag(EF)toindicatewhetherornot
thereareanywordspresentintheFIFO.ItalsousestheFullFlagfunction(FF)
to indicate whether or not the FIFO has any free space for writing. In IDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (REN) and RCLK.
If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe
selected.ThismodeusesOutputReady(OR)toindicatewhetherornotthere
isvaliddataatthedataoutputs(Qn).ItalsousesInputReady(IR)toindicate
whetherornottheFIFOhasanyfreespaceforwriting.IntheFWFTmode,the
firstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLKrising
edges, REN=LOWis notnecessary.Subsequentwords mustbeaccessed
using the Read Enable (REN) and RCLK.
Varioussignals,bothinputandoutputsignalsoperatedifferentlydepending
onwhichtimingmodeisineffect.
IDT STANDARD MODE
In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the
manneroutlinedinTable3.TowritedataintototheFIFO,WriteEnable(WEN)
mustbeLOW.DatapresentedtotheDATAINlineswillbeclockedintotheFIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed,theEmptyFlag(EF)willgoHIGH.Subsequentwriteswillcontinue
tofilluptheFIFO.TheProgrammableAlmost-Emptyflag(PAE)willgoHIGH
aftern + 1wordshavebeenloadedintotheFIFO,wherenistheemptyoffset
value.ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable2.
Thisparameterisalsouserprogrammable.SeesectiononProgrammableFlag
OffsetLoading.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHalf-Fullflag(HF)wouldtoggletoLOWonce
(D/2+1)wordswerewrittenintotheFIFO.Ifx18Inputorx18OutputbusWidth
isselected,(D/2+1)=the1,025thwordfortheIDT72T1845,2,049thwordfor
IDT72T1855, 4,097th word for the IDT72T1865, 8,193rd word for the
IDT72T1875, 16,385th word for the IDT72T1885, 32,769th word for the
IDT72T1895, 65,537th word for the IDT72T18105, 131,073rd word for the
IDT72T18115and262,145thwordfortheIDT72T18125.Ifbothx9Inputand
x9 Output bus Widths are selected, (D/2 + 1) = the 2,049th word for the
IDT72T1845,4,097thwordforIDT72T1855,8,193rdwordfortheIDT72T1865,
16,385th word for the IDT72T1875, 32,769th word for the IDT72T1885,
65,537th word for the IDT72T1895, 131,073rd word for the IDT72T18105,
262,145thwordfortheIDT72T18115and524,289thwordfortheIDT72T18125.
ContinuingtowritedataintotheFIFOwillcausetheProgrammableAlmost-Full
flag(PAF)togoLOW.Again,ifnoreadsareperformed,thePAFwillgoLOW
after(D-m)writestotheFIFO.Ifx18Inputorx18OutputbusWidthisselected,
(D-m) = (2,048-m) writes for the IDT72T1845, (4,096-m) writes for the
IDT72T1855,(8,192-m)writesfortheIDT72T1865,(16,384-m)writesforthe
IDT72T1875,(32,768-m)writesfortheIDT72T1885,(65,536-m)writesforthe
IDT72T1895, (131,072-m) writes for the IDT72T18105, (262,144-m) writes
fortheIDT72T18115and(524,288-m)writesfortheIDT72T18125.Ifbothx9
Inputandx9OutputbusWidthsareselected,(D-m) = (4,096-m)writesforthe
Relevanttimingdiagrams forIDTStandardmodecanbefoundinFigure
11, 12, 13 and 18.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the
manneroutlinedinTable4.TowritedataintototheFIFO,WENmustbeLOW.
DatapresentedtotheDATAINlineswillbeclockedintotheFIFOonsubsequent
transitionsofWCLK.Afterthefirstwriteisperformed,theOutputReady(OR)
flagwillgoLOW.SubsequentwriteswillcontinuetofilluptheFIFO.PAEwillgo
HIGHaftern + 2wordshavebeenloadedintotheFIFO,wherenistheempty
offsetvalue.Thedefaultsettingforthesevalues arestatedinthefootnoteof
Table2.Thisparameterisalsouserprogrammable.SeesectiononProgram-
mableFlagOffsetLoading.
If one continued to write data into the FIFO, and we assumed no read
operationsweretakingplace,theHFwouldtoggletoLOWoncethe(D/2+2)
wordswerewrittenintotheFIFO.Ifx18Inputorx18OutputbusWidthisselected,
(D/2+ 2) = the1,026thwordfortheIDT72T1845,2,050thwordforIDT72T1855,
4,098thwordfortheIDT72T1865,8,194thwordfortheIDT72T1875,16,386th
wordfortheIDT72T1885,32,770thwordfortheIDT72T1895,65,538thword
for the IDT72T18105, 131,074th word for the IDT72T18115 and 262,146th
word for the IDT72T18125. If both x9 Input and x9 Output bus Widths are
selected,(D/2 + 2) = the2,050thwordfortheIDT72T1845,4,098thwordfor
IDT72T1855, 8,194th word for the IDT72T1865, 16,386th word for the
IDT72T1875, 32,770th word for the IDT72T1885, 65,538th word for the
IDT72T1895, 131,074thwordforthe IDT72T18105, 262,146thwordforthe
IDT72T18115and524,290thwordfortheIDT72T18125.Continuingtowrite
data into the FIFO will cause the PAF to go LOW. Again, if no reads are
performed,thePAFwillgoLOWafter(D-m)writestotheFIFO.Ifx18Inputor
x18OutputbusWidthisselected,(D-m) = (2,049-m)writesfortheIDT72T1845,
16
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
(4,097-m)writes fortheIDT72T1855,(8,193-m)writes fortheIDT72T1865, IDT72T18125.Ifbothx9Inputandx9OutputbusWidthsareselected,D=4,097
(16,385-m)writesfortheIDT72T1875,(32,769-m)writesfortheIDT72T1885, writes for the IDT72T1845, 8,193 writes for the IDT72T1855, 16,385 writes
(65,536-m)writesfortheIDT72T1895,(131,073-m)writesfortheIDT72T18105, fortheIDT72T1865,32,769writesfortheIDT72T1875,65,537writesforthe
(262,145-m) writes for the IDT72T18115 and (524,289-m) writes for the IDT72T1885, 131,073 writes for the IDT72T1895, 262,145 writes for the
IDT72T18125.Ifbothx9Inputandx9OutputbusWidthsareselected,(D-m) IDT72T18105,524,289writesfortheIDT72T18115and1,048,577writesfor
=(4,097-m)writesfortheIDT72T1845,(8,193-m)writesfortheIDT72T1855, theIDT72T18125,respectively.NotethattheadditionalwordinFWFTmode
(16,385-m)writesfortheIDT72T1865,(32,769-m)writesfortheIDT72T1875, isduetothecapacityofthememoryplusoutputregister.
(65,537-m)writesfortheIDT72T1885,(131,073-m)writesfortheIDT72T1895,
IftheFIFOisfull,thefirstreadoperationwillcausetheIRflagtogoLOW.
(262,145-m) writes for the IDT72T18105, (524,289-m) writes for the Subsequent read operations will cause the PAF and HF to go HIGH at the
IDT72T18115and(1,048,577-m)writes forthe IDT72T18125. The offsetm conditionsdescribedinTable4.Iffurtherreadoperationsoccur,withoutwrite
isthefulloffsetvalue.Thedefaultsettingforthesevaluesarestatedinthefootnote operations,thePAEwillgoLOWwhentherearen+1wordsintheFIFO,where
of Table 2.
nistheemptyoffsetvalue.ContinuingreadoperationswillcausetheFIFOto
WhentheFIFOisfull,theInputReady(IR)flagwillgoHIGH,inhibitingfurther becomeempty.WhenthelastwordhasbeenreadfromtheFIFO,ORwillgo
writeoperations.Ifnoreadsareperformedafterareset,IRwillgoHIGHafter HIGH inhibiting further read operations. REN is ignored when the FIFO is
DwritestotheFIFO.Ifx18Inputorx18OutputbusWidthisselected,D = 2,049 empty.
writesfortheIDT72T1845,4,097writesfortheIDT72T1855,8,193writesfor
the IDT72T1865, 16,385 writes for the IDT72T1875, 32,769 writes for the buffered,andtheIRflagoutputisdoubleregister-buffered.
IDT72T1885, 65,536 writes for the IDT72T1895, 131,073 writes for the RelevanttimingdiagramsforFWFTmodecanbefoundinFigure14,15,
When configured in FWFT mode, the OR flag output is triple register-
IDT72T18105,262,145writesfortheIDT72T18115and524,289writesforthe 16 and 19.
TABLE 2 — DEFAULT PROGRAMMABLE
PROGRAMMING FLAG OFFSETS
FLAG OFFSETS
FullandEmptyFlagoffsetvaluesareuserprogrammable.TheIDT72T1845/
72T1855/72T1865/72T1875/72T1885/72T1895/72T18105/72T18115/
72T18125haveinternalregistersfortheseoffsets.Thereareeightdefaultoffset
valuesselectableduringMasterReset.TheseoffsetvaluesareshowninTable
2.OffsetvaluescanalsobeprogrammedintotheFIFOinoneoftwoways;serial
orparallelloadingmethod.Theselectionoftheloadingmethodisdoneusing
theLD(Load)pin.DuringMasterReset,thestateoftheLDinputdetermines
whetherserialorparallelflagoffsetprogrammingis enabled.AHIGHonLD
duringMasterResetselectsserialloadingofoffsetvalues.ALOWonLDduring
MasterResetselectsparallelloadingofoffsetvalues.
InadditiontoloadingoffsetvaluesintotheFIFO,itisalsopossibletoread
thecurrentoffsetvalues.Offsetvaluescanbereadviatheparalleloutputport
Q0-Qn,regardlessoftheprogrammingmodeselected(serialorparallel).Itis
notpossibletoreadtheoffsetvaluesinserialfashion.
Figure3,ProgrammableFlagOffsetProgrammingSequence,summaries
thecontrolpinsandsequenceforbothserialandparallelprogrammingmodes.
Foramoredetaileddescription,seediscussionthatfollows.
IDT72T1845
Offsets n,m
All Other x9 to x9
*LD
L
L
L
L
H
H
H
H
FSEL1
FSEL0
Modes
511
255
127
63
31
15
7
3
Mode
511
255
127
63
1,023
31
15
H
L
L
H
L
H
L
H
L
H
L
H
L
L
H
H
7
IDT72T1855, 72T1865, 72T1875, 72T1885,
72T1895, 72T18105, 72T18115, 72T18125
*LD
H
L
L
L
FSEL1
FSEL0
Offsets n,m
The offsetregisters maybe programmed(andreprogrammed)anytime
afterMasterReset,regardlessofwhetherserialorparallelprogramminghas
beenselected. Validprogrammingranges are from0toD-1.
L
H
L
L
L
H
L
H
L
1,023
511
255
127
63
31
15
7
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
The IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/
72T18105/72T18115/72T18125canbeconfiguredduringtheMasterReset
cyclewitheithersynchronousorasynchronoustimingforPAFandPAEflags
by use of the PFM pin.
If synchronous PAF/PAE configuration is selected (PFM, HIGH during
MRS),thePAFisassertedandupdatedontherisingedgeofWCLKonlyand
notRCLK.Similarly,PAEisassertedandupdatedontherisingedgeofRCLK
onlyandnotWCLK.Fordetailtimingdiagrams,seeFigure23forsynchronous
PAFtimingandFigure24forsynchronous PAE timing.
L
L
H
H
L
H
H
H
H
H
H
*LD
H
L
FSEL1
FSEL0
Program Mode
(3)
X
X
X
X
Serial
(4)
Parallel
*THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE
OR READ DATA TO/FROM THE FIFO MEMORY.
If asynchronous PAF/PAE configuration is selected (PFM, LOW during
MRS),thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand
PAFisresettoHIGHontheLOW-to-HIGHtransitionofRCLK.Similarly,PAE
isassertedLOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGH
ontheLOW-to-HIGHtransitionofWCLK.Fordetailtimingdiagrams,seeFigure25
forasynchronous PAF timingandFigure 26forasynchronous PAE timing.
NOTES:
1. n = empty offset for PAE.
2. m = full offset for PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.
17
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
TABLE 3 ⎯ STATUS FLAGS FOR IDT STANDARD MODE
IW = OW = x9
IDT72T1845
IDT72T1855
0
IDT72T1855
IDT72T1865
IDT72T1865
IDT72T1875
IDT72T1875
IW = x18 or
OW = x18
HF
FF PAF
PAE EF
IDT72T1845
IDT72T1885
0
0
H
H
H
L
L
L
0
0
H
H
H
H
H
H
H
H
L
1 to n (1)
1 to n(1)
1 to n (1)
1 to n (1)
(1)
Number of
Words in
FIFO
L
1 to n
H
H
H
H
H
(n+1) to 1,024
(n+1) to 2,048
(n+1) to 16,384
H
H
H
H
(n+1) to 4,096
4,097 to (8,192-(m+1))
(n+1) to 8,192
8,193 to (16,384-(m+1))
16,385 to (32,768-(m+1))
1,025 to (2048-(m+1))
2,049 to (4,096-(m+1))
(4,096-m) to 4,095
4,096
(2048-m)
(8,192-m)
to 8,191
to 16,383
H
L
L
to 2,047
(16,384-m)
(32,768-m) to 32,767
32,768
L
2,048
L
8,192
16,384
IDT72T1885
IDT72T1895
IDT72T18105
IDT72T18115
IDT72T18115
IDT72T18125
IW = OW = x9
IW = x18 or
OW = x18
HF
FF PAF
PAE EF
IDT72T18125
IDT72T1895
IDT72T18105
0
0
0
0
0
H
H
H
H
H
L
H
H
H
H
H
H
H
L
L
L
L
1 to n (1)
1 to n(1)
1 to n(1)
1 to n (1)
1 to n(1)
Number of
Words in
FIFO
H
H
H
(n+1) to 32,768
(n+1) to 65,536
(n+1) to 262,144
H
H
(n+1) to 131,072
(n+1) to 524,288
32,769 to (65,536-(m+1))
(65,536-m) to 65,535
65,536
65,537 to (131,072-(m+1)) 131,073 to (262,144-(m+1)) 262,145 to (524,288-(m+1)) 524,289 to (1,048,576-(m+1))
L
L
H
H
H
H
L
L
(131,072-m) to 131,071
131,072
(262,144-m) to 262,143
262,144
(524,288-m) to 524,287
524,288
(1,048,576-m) to 1,048,575
1,048,576
NOTE:
1. See table 2 for values for n, m.
TABLE 4 ⎯ STATUS FLAGS FOR FWFT MODE
IW = OW = x9
IDT72T1845
IDT72T1855
IDT72T1865
IDT72T1865
IDT72T1875
IDT72T1875
IDT72T1885
IW = x18 or
OW = x18
HF
IR PAF
PAE OR
IDT72T1845
IDT72T1855
0
0
H
H
H
L
L
L
H
L
L
L
L
L
0
0
0
L
L
L
L
H
H
H
H
L
1 to n+1 (1)
1 to n+1 (1)
1 to n+1 (1)
1 to n+1 (1)
1 to n+1 (1)
Number of
Words in
FIFO
(n+2) to 1,025
(n+2) to 2,049
2,050 to (4,097-(m+1))
(4,097-m) to 4,096
4,097
(n+2) to 16,385
16,386 to (32,769-(m+1))
H
H
H
H
(n+2) to 4,097
4,098 to (8,193-(m+1))
(n+2) to 8,193
8,194 to (16,385-(m+1))
1,026 to (2049-(m+1))
(2049-m)
to 2,048
(8,193-m)
to 8,192
to 16,384
L
L
(16,385-m)
16,385
(32,769-m) to 32,768
32,769
H
L
2,049
L
8,193
IW = OW = x9
IDT72T1885
IDT72T1895
IDT72T18105
IDT72T18105
IDT72T18115
IDT72T18115
IDT72T18125
IDT72T18125
IW = x18 or
OW = x18
IR PAF
PAE OR
HF
IDT72T1895
0
0
0
H
H
H
L
L
L
H
L
L
L
L
L
0
0
L
L
L
L
H
H
H
H
L
1 to n+1 (1)
1 to n+1 (1)
1 to n+1 (1)
1 to n+1 (1)
1 to n+1 (1)
Number of
Words in
FIFO
(n+2) to 32,769
(n+2) to 65,537
(n+2) to 262,145
H
H
H
H
(n+2) to 131,073
(n+2) to 524,289
32,770 to (65,537-(m+1))
65,538 to (131,073-(m+1)) 131,074 to (262,145-(m+1)) 262,146 to (524,289-(m+1)) 524,290 to (1,048,577-(m+1))
(65,537-m) to 65,536 (131,073-m) to 131,072
65,537 131,073
(262,145-m) to 262,144
262,145
(524,289-m) to 524,288
524,289
(1,048,577-m) to 1,048,576
1,048,577
L
L
H
L
L
5909 drw05
NOTE:
1. See table 2 for values for n, m.
2. Number of Words in FIFO = Depth + Output Register.
18
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
I
DT72T1845,
IDT72T1855
IDT72T1875
IDT72T1895
IDT72T1865,
IDT72T1885,
IDT72T18105, IDT72T18115
IDT72T18125
WCLK
RCLK
X
LD WEN REN SEN
0 0 1 1
Parallel write to registers:
x18 input
x18 input
x9 input
x9 input
(72T18105/115/125)
(72T1895/105/115/125)
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Empty Offset
Full Offset
Empty Offset (LSB) Empty Offset (LSB)
Empty Offset (MSB) Empty Offset
Full Offset (LSB)
Full Offset (MSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset
Full Offset (MSB)
Full Offset (MSB)
Parallel read from registers:
x18 input x9 input
(72T18105/115/125)
X
0
1
0
1
x18 input
x9 input
(72T1895/105/115/125)
Empty Offset Empty Offset (LSB) Empty Offset (LSB) Empty Offset (LSB)
Full Offset Empty Offset (MSB) Empty Offset (MSB) Empty Offset
Full Offset (LSB)
Full Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset
Full Offset (MSB)
x9 to x9 Mode
All Other Modes
Serial shift into registers:
22 bits for the IDT72T1845
24 bits for the IDT72T1855
26 bits for the IDT72T1865
28 bits for the IDT72T1875
30 bits for the IDT72T1885
32 bits for the IDT72T1895
34 bits for the IDT72T18105
36 bits for the IDT72T18115
38 bits for the IDT72T18125
Serial shift into registers:
24 bits for the IDT72T1845
26 bits for the IDT72T1855
28 bits for the IDT72T1865
30 bits for the IDT72T1875
32 bits for the IDT72T1885
34 bits for the IDT72T1895
36 bits for the IDT72T18105
38 bits for the IDT72T18115
40 bits for the IDT72T18125
0
1
1
0
X
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
Ending with Full Offset (MSB)
X
X
X
X
1
1
1
No Operation
1
1
0
X
0
X
X
Write Memory
X
X
X
Read Memory
No Operation
X
1
1
1
X
5909 drw06
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
Figure 3. Programmable Flag Offset Programming Sequence
19
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
1st Parallel Offset Write/Read Cycle
1st Parallel Offset Write/Read Cycle
D/Q8
D/Q0
D/Q8
D/Q0
EMPTY OFFSET REGISTER
EMPTY OFFSET REGISTER
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
2nd Parallel Offset Write/Read Cycle
D/Q8
D/Q0
EMPTY OFFSET REGISTER
2nd Parallel Offset Write/Read Cycle
D/Q8
16
15 14 13 12
11
10
9
D/Q0
EMPTY OFFSET REGISTER
3rd Parallel Offset Write/Read Cycle
D/Q8
D/Q0
16
15
14
13
12
11
10
9
EMPTY OFFSET REGISTER
20
19
18
17
3rd Parallel Offset Write/Read Cycle
D/Q8
4th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
D/Q0
FULL OFFSET REGISTER
FULL OFFSET REGISTER
8
7
6
5
4
3
2
1
8
7
6
5
4
3
2
1
5th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
FULL OFFSET REGISTER
15 14 13 12
4th Parallel Offset Write/Read Cycle
D/Q8
16
11
10
9
D/Q0
FULL OFFSET REGISTER
6th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
16
15
14
13
12
11
10
9
FULL OFFSET REGISTER
20
19
18
17
IDT72T1845/72T1855/72T1865/72T1875/
72T1885/72T1895(1)
⎯
x9 Bus Width
IDT72T1895/72T18105/72T18115/72T18125(1)
⎯ x9 Bus Width
1st Parallel Offset Write/Read Cycle
1st Parallel Offset Write/Read Cycle
D/Q17
D/Q17
D/Q16
Data Inputs/Outputs
D/Q16
D/Q0
Data Inputs/Outputs
D/Q0
EMPTY OFFSET (LSB) REGISTER
Non-Interspersed
Parity
EMPTY OFFSET REGISTER
Non-Interspersed
Parity
16 15 14 13 12 11 10
16 15 14 13 12 11 10
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
16
15 14 13 12 11 10
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
9
Interspersed
Parity
16 15 14 13 12 11 10
9
Interspersed
Parity
D/Q8
D/Q8
# of Bits Used
# of Bits Used
2nd Parallel Offset Write/Read Cycle
D/Q17
2nd Parallel Offset Write/Read Cycle
Data Inputs/Outputs
EMPTY OFFSET (MSB) REGISTER
D/Q0
D/Q16
D/Q17
Data Inputs/Outputs
FULL OFFSET REGISTER
D/Q0
D/Q16
19 18 17
19 18 17
16 15 14 13 12 11 10
16 15 14 13 12 11 10
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
9
D/Q8
3rd Parallel Offset Write/Read Cycle
D/Q17
Data Inputs/Outputs
D/Q0
D/Q16
FULL OFFSET (LSB) REGISTER
IDT72T1845/72T1855/72T1865/72T1875/
72T1885/72T1895
16 15 14 13 12 11 10
16 15 14 13 12 11 10
9
8
8
7
7
6
6
5
5
4
4
3
3
2
2
1
1
⎯
x18 Bus Width
9
D/Q8
x9 to x9 Mode
# of Bits Used:
All Other Modes
# of Bits Used:
4th Parallel Offset Write/Read Cycle
12 bits for the IDT72T1845
13 bits for the IDT72T1855
14 bits for the IDT72T1865
15 bits for the IDT72T1875
16 bits for the IDT72T1885
17 bits for the IDT72T1895
18 bits for the IDT72T18105
19 bits for the IDT72T18115
20 bits for the IDT72T18125
Note: All unused bits of the
11 bits for the IDT72T1845
12 bits for the IDT72T1855
13 bits for the IDT72T1865
14 bits for the IDT72T1875
15 bits for the IDT72T1885
16 bits for the IDT72T1895
17 bits for the IDT72T18105
18 bits for the IDT72T18115
19 bits for the IDT72T18125
D/Q17
Data Inputs/Outputs
FULL OFFSET (MSB) REGISTER
D/Q0
D/Q16
19 18 17
19 18 17
IDT72T18105/72T18115/72T18125
⎯ x18 Bus Width
Note: All unused bits of the
LSB & MSB are don’t care
5909 drw07
LSB & MSB are don’t care
NOTES:
1. When programming the IDT72T1895 with an input bus width of x9 and output bus width of x18, 4 write cycles will be required. When Reading the IDT72T1895 with an output
bus width of x9 and input bus width of x18, 4 read cycles will be required. A total of 6 program/read cycles will be required if both the input and output bus widths are set to x9.
2. Consecutive reads of the offset registers is not permitted. The read operation must be disabled for a minimum of one RCLK cycle in between offset register accesses. (Please
refer to Figure 22, Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for more details).
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
20
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
SERIAL PROGRAMMING MODE
Forexample,programmingPAEandPAFontheIDT72T1895configured
IfSerialProgrammingmodehasbeenselected,asdescribedabove,then forx18buswidthproceedsasfollows:whenLDandWENaresetLOW,data
programmingofPAEandPAFvaluescanbeachievedbyusingacombination ontheinputsDnarewrittenintotheLSBoftheEmptyOffsetRegisteronthefirst
oftheLD,SEN,SCLKandSIinputpins.ProgrammingPAEandPAFproceeds LOW-to-HIGHtransitionofWCLK.UponthesecondLOW-to-HIGHtransition
asfollows:whenLDandSENaresetLOW,dataontheSIinputarewritten,one ofWCLK,dataarewrittenintotheMSBoftheEmptyOffsetRegister.Onthethird
bitforeachSCLKrisingedge,startingwiththeEmptyOffsetLSBandending LOW-to-HIGHtransitionofWCLK,dataarewrittenintotheLSBoftheFullOffset
withthe FullOffsetMSB. Ifx9tox9mode is selected, a totalof24bits forthe Register.OnthefourthLOW-to-HIGHtransitionofWCLK,dataarewritteninto
IDT72T1845,26bitsfortheIDT72T1855,28bitsfortheIDT72T1865,30bits theMSBoftheFullOffsetRegister.ThefifthLOW-to-HIGHtransitionofWCLK,
fortheIDT72T1875,32bitsfortheIDT72T1885,34bitsfortheIDT72T1895, dataarewritten,onceagaintotheEmptyOffsetRegister.Notethatforx9bus
36bits fortheIDT72T18105,38bits fortheIDT72T18115and40bits forthe width,oneextraWritecycleisrequiredforboththeEmptyOffsetRegisterand
IDT72T18125.Foranyothermodeofoperation(thatincludesx18buswidth FullOffsetRegister. See Figure 21, ParallelLoadingofProgrammableFlag
oneithertheInputorOutput),minus 2bits fromthevalues above.So,atotal
of 22 bits for the IDT72T1845, 24 bits for the IDT72T1855, 26 bits for the
IDT72T1865,28bitsfortheIDT72T1875,30bitsfortheIDT72T1885,32bits
fortheIDT72T1895,34bitsfortheIDT72T18105,36bitsfortheIDT72T18115
and38bitsfortheIDT72T18125.SeeFigure20,SerialLoadingofProgram-
Registers,forthetimingdiagramforthismode.
Theactofwritingoffsetsinparallelemploysadedicatedwriteoffsetregister
pointer. The act of reading offsets employs a dedicated read offset register
pointer.Thetwopointersoperateindependently;however,areadandawrite
shouldnotbeperformedsimultaneouslytotheoffsetregisters. AMasterReset
initializesbothpointerstotheEmptyOffset(LSB)register.APartialResethas
mableFlagRegisters,forthetimingdiagramforthismode.
Using the serial method, individual registers cannot be programmed noeffectonthepositionofthesepointers.
selectively.PAEandPAFcanshowavalidstatusonlyafterthecompleteset
Write operations to the FIFO are allowed before and during the parallel
of bits (for all offset registers) has been entered. The registers can be programmingsequence.Inthiscase,theprogrammingofalloffsetregistersdoes
reprogrammedaslongasthecompletesetofnewoffsetbitsisentered.When nothavetooccuratonetime. One,twoormoreoffsetregisterscanbewritten
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
andthenbybringingLDHIGH,writeoperationscanberedirectedtotheFIFO
Write operations to the FIFO are allowed before and during the serial memory.WhenLDissetLOWagain,andWENisLOW,thenextoffsetregister
programmingsequence. Inthiscase,theprogrammingofalloffsetbitsdoesnot insequenceiswrittento.AsanalternativetoholdingWENLOWandtoggling
havetooccuratonce. AselectnumberofbitscanbewrittentotheSIinputand LD, parallel programming can also be interrupted by setting LD LOW and
then,bybringingLDandSENHIGH,datacanbewrittentoFIFOmemoryvia togglingWEN.
DnbytogglingWEN. WhenWENisbroughtHIGHwithLDandSENrestored
Notethatthestatusofaprogrammableflag(PAEorPAF)outputisinvalid
toaLOW,thenextoffsetbitinsequenceiswrittentotheregistersviaSI. Ifan during the programming process. From the time parallel programming has
interruptionofserialprogrammingisdesired,itissufficienteithertosetLDLOW begun,aprogrammableflagoutputwillnotbevaliduntiltheappropriateoffset
anddeactivateSENortosetSENLOWanddeactivateLD. OnceLDandSEN wordhasbeenwrittentotheregister(s)pertainingtothatflag.Measuringfrom
arebothrestoredtoaLOWlevel,serialoffsetprogrammingcontinues.
Fromthetimeserialprogramminghasbegun,neitherprogrammableflag twomorerisingWCLKedgesplustPAF,PAEwillbevalidafterthenexttworising
willbevaliduntilthefullsetofbitsrequiredtofillalltheoffsetregistershasbeen RCLK edges plus tPAE plus tSKEW2.
therisingWCLKedgethatachievestheabovecriteria;PAFwillbevalidafter
The act of reading the offset registers employs a dedicated read offset
registerpointer.ThecontentsoftheoffsetregisterscanbereadontheQ0-Qn
pins when LD is set LOW and REN is set LOW. It is important to note that
consecutivereadsoftheoffsetregistersisnotpermitted.Thereadoperationmust
be disabled for a minimum of one RCLK cycle in between offset register
accesses.IftheFIFOisconfiguredforaninputbuswidthandoutputbuswidth
bothsettox9,thenthetotalnumberofreadoperationsrequiredtoreadtheoffset
registersis4fortheIDT72T1845/72T1855/72T1865/72T1875/72T1885or6
for the IDT72T1895/72T18105/72T18115/72T18125. Refer to Figure 3,
Programmable FlagOffsetProgrammingSequence, fora detaileddiagram
ofthedatainputlinesD0-Dnusedduringparallelprogramming.IftheFIFOis
configuredforaninputtooutputbuswidthofx9tox18,x18tox9orx18tox18,
thenthefollowingnumberofreadoperations arerequired:foranoutputbus
widthofx18atotalof2readoperationswillberequiredtoreadtheoffsetregisters
fortheIDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895or4for
theIDT72T18105/72T18115/72T18125.Foranoutputbuswidthofx9atotal
of 4 read operations will be required to read the offset registers for the
IDT72T1845/72T1855/72T1865/72T1875/72T1885. A total of 6 will be re-
quiredfortheIDT72T1895/72T18105/72T18115/72T18125.RefertoFigure
3,ProgrammableFlagOffsetProgrammingSequence,foradetaileddiagram.
SeeFigure22,ParallelReadofProgrammableFlagRegisters,forthetiming
diagramforthismode.
written. MeasuringfromtherisingSCLKedgethatachievestheabovecriteria;
PAFwillbevalidafterthreemorerisingWCLKedgesplustPAF,PAEwillbevalid
afterthe nextthree risingRCLKedges plus tPAE.
ItisonlypossibletoreadtheflagoffsetvaluesviatheparalleloutputportQn.
PARALLELMODE
IfParallelProgrammingmodehasbeenselected,asdescribedabove,then
programmingofPAEandPAFvaluescanbeachievedbyusingacombination
oftheLD,WCLK,WENandDninputpins.IftheFIFOisconfiguredforaninput
bus width and output bus width both set to x9, then the total number of write
operations requiredtoprogramthe offsetregisters is 4forthe IDT72T1845/
72T1855/72T1865/72T1875/72T1885 or 6 for the IDT72T1895/72T18105/
72T18115/72T18125. Refer to Figure 3, Programmable Flag Offset Pro-
grammingSequence,foradetaileddiagramofthedatainputlinesD0-Dnused
duringparallelprogramming.IftheFIFOisconfiguredforaninputtooutputbus
widthofx9tox18, x18tox9orx18tox18, thenthe followingnumberofwrite
operationsarerequired.Foraninputbuswidthofx18atotalof2writeoperations
willberequiredtoprogramtheoffsetregistersfortheIDT72T1845/72T1855/
72T1865/72T1875/72T1885/72T1895or4fortheIDT72T18105/72T18115/
72T18125. For an input bus width of x9 a total of 4 write operations will be
requiredtoprogramtheoffsetregistersfortheIDT72T1845/72T1855/72T1865/
72T1875/72T1885.Atotalof6willberequiredfortheIDT72T1895/72T18105/
72T18115/72T18125. Refer to Figure 3, Programmable Flag Offset Pro-
grammingSequence,foradetaileddiagram.
Itispermissibletointerrupttheoffsetregisterreadsequencewithreadsor
writestotheFIFO. TheinterruptionisaccomplishedbydeassertingREN,LD,
21
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
orbothtogether.WhenRENandLDarerestoredtoaLOW level,readingof
DuringFWFTmodetheFIFOisputintoretransmitmodebyarisingRCLK
theoffsetregisterscontinueswhereitleftoff.Itshouldbenoted,andcareshould edgewhenthe‘MARK’inputisHIGHandORisLOW.TherisingRCLKedge
betakenfromthefactthatwhenaparallelreadoftheflagoffsetsisperformed, ‘marks’thedatapresentintheFIFOoutputregisterasthefirstretransmitdata.
the data wordthatwas presentonthe outputlines Qnwillbe overwritten.
TheFIFOremains inretransmitmodeuntilarisingRCLKedgeoccurs while
Parallelreadingofthe offsetregisters is always permittedregardless of MARKisLOW.
whichtimingmode (IDTStandardorFWFTmodes)has beenselected.
Onceamarkedlocationhasbeenset(andthedeviceisstillinretransmit
canbeinitiatedbyarisingRCLKedgewhiletheretransmitinput(RT)isLOW.
REN must be HIGH (reads disabled) before bringing RT LOW. The device
RETRANSMITFROMMARKOPERATION
TheRetransmitfromMarkfeatureallowsFIFOdatatobereadrepeatedly indicatesthestartofretransmitsetupbysettingORHIGH.
startingatauser-selectedposition.TheFIFOisfirstputintoretransmitmodethat
WhenORgoesLOW,retransmitsetupiscompleteandonthenextrising
will‘mark’abeginningwordandalsosetapointerthatwillpreventongoingFIFO RCLKedgeafterretransmitsetupiscomplete,(RTgoesHIGH),thecontents
writeoperationsfromover-writingretransmitdata.Theretransmitdatacanbe ofthefirstretransmitlocationareloadedontotheoutputregister.SinceFWFT
readrepeatedlyanynumberoftimesfromthe‘marked’position.TheFIFOcan modeisselected,thefirstwordappearsontheoutputsregardlessofREN,a
betakenoutofretransmitmodeatanytimetoallownormaldeviceoperation. LOWonRENisnotrequiredforthefirstword.Readingallsubsequentwords
The‘mark’positioncanbeselectedanynumberoftimes,eachselectionover- requires a LOW on REN to enable the rising RCLK edge. See Figure 19,
writingthepreviousmarklocation.RetransmitoperationisavailableinbothIDT RetransmitfromMarktiming(FWFTmode),fortherelevanttimingdiagram.
standardandFWFTmodes.
Note, for the IDT72T1845/72T1855/72T1865/72T1875/72T1885/
DuringIDTstandardmodetheFIFOisputintoretransmitmodebyaLow- 72T1895theremustbeaminimumof32bytesofdatabetweenthewritepointer
to-HightransitiononRCLKwhenthe ‘MARK’inputis HIGHandEF is HIGH. andreadpointerwhentheMARKisasserted,fortheIDT72T18105/72T18115
TherisingRCLKedge‘marks’thedatapresentintheFIFOoutputregisteras theremustbeaminimumof128bytesandfortheIDT72T18125theremustbe
thefirstretransmitdata.TheFIFOremainsinretransmitmodeuntilarisingedge aminimumof256bytes.Remember,2(x9)bytes =1(x18)word.(32bytes =
on RCLK occurs while MARK is LOW.
16word=8longwords).Also,oncetheMARKisset,thewritepointerwillnot
Oncea‘marked’locationhasbeenset(andthedeviceisstillinretransmit increment past the “marked” location until the MARK is deasserted. This
mode,MARKisHIGH),aretransmitcanbeinitiatedbyarisingedgeonRCLK prevents“overwriting”ofretransmitdata.
whiletheretransmitinput(RT)isLOW.RENmustbeHIGH(readsdisabled)
beforebringingRTLOW.Thedeviceindicatesthestartofretransmitsetupby HSTL/LVTTL I/O
settingEFLOW,alsopreventingreads.WhenEFgoesHIGH,retransmitsetup
Both the write port and read port are user selectable between HSTL or
iscompleteandreadoperationsmaybeginstartingwiththefirstdataattheMARK LVTTL I/O, via two select pins, WHSTL and RHSTL respectively. All other
location.SinceIDTstandardmodeisselected,everywordreadincludingthe controlpins are selectable via SHSTL, see Table 5fordetails ofgroupings.
first‘marked’wordfollowingaretransmitsetuprequiresaLOWonREN(read
enabled).
Note,thatwhenthewriteportisselectedforHSTLmode,theusercanreduce
thepowerconsumption(instand-bymodebyutilizingtheWCSinput).
All“StaticPins”mustbetiedtoVCCorGND.ThesepinsareLVTTLonly,
Note, write operations may continue as normal during all retransmit
functions,howeverwriteoperationstothe‘marked’locationwillbeprevented. andare purelydevice configurationpins.
See Figure 18, Retransmit from Mark (IDT standard mode), for the relevant
timingdiagram.
TABLE 5 — I/O CONFIGURATION
WHSTL SELECT
RHSTL SELECT
SHSTL SELECT
STATIC PINS
WHSTL: HIGH = HSTL
LOW = LVTTL
RHSTL: HIGH = HSTL
LOW = LVTTL
SHSTL: HIGH = HSTL
LOW = LVTTL
LVTTL ONLY
Dn (I/P)
RCLK/RD (I/P)
RCS (I/P)
MARK (I/P)
REN (I/P)
OE (I/P)
EF/OR (O/P)
SCLK (I/P)
LD (I/P)
MRS (I/P)
TCK (I/P)
TMS (I/P)
SEN (I/P)
FWFT/SI (I/P)
PRS (I/P)
IW (I/P)
BM (I/P)
OW (I/P)
ASYW (I/P)
BE (I/P)
FSEL0 (I/P)
PFM (I/P)
WHSTL (I/P)
WCLK/WR (I/P)
WEN (I/P)
WCS (I/P)
PAF (O/P)
EREN (O/P)
PAE (O/P)
FF/IR (O/P)
HF (O/P)
TRST (I/P)
TDI (I/P)
ASYR (I/P)
IP (I/P)
FSEL1 (I/P)
SHSTL (I/P)
RHSTL (I/P)
RT (I/P)
Qn (O/P)
ERCLK (O/P)
TDO (O/P)
22
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
ASYNCHRONOUS READ (ASYR)
SIGNALDESCRIPTION
ThereadportcanbeconfiguredforeitherSynchronousorAsynchronous
mode of operation. If during a Master Reset the ASYR input is LOW, then
Asynchronous operationofthereadportwillbeselected.DuringAsynchro-
nousoperationofthereadporttheRCLKinputbecomesRDinput,thisisthe
Asynchronousreadstrobeinput.ArisingedgeonRDwillreaddatafromthe
FIFO via the output register and Qn port. (REN must be tied LOW during
Asynchronous operationofthe readport).
The OE input provides three-state control of the Qn output bus, in an
asynchronousmanner.(RCS,providesthree-statecontrolofthereadportin
Synchronousmode).
WhenthereadportisconfiguredforAsynchronousoperationthedevice
mustbeoperatingonIDTstandardmode,FWFTmodeisnotpermissibleifthe
readportisAsynchronous.TheEmptyFlag(EF)operatesinanAsynchronous
manner,thatis,theemptyflagwillbeupdatedbasedonbothareadoperation
and a write operation. Refer to Figures 32, 33, 34 and 35 for relevant timing
andoperationalwaveforms.
INPUTS:
DATA IN (D0 - Dn)
Datainputsfor18-bitwidedata(D0-D17)ordatainputsfor9-bitwidedata
(D0 - D8).
CONTROLS:
MASTER RESET ( MRS )
AMasterResetisaccomplishedwhenevertheMRSinputistakentoaLOW
state.Thisoperationsetstheinternalreadandwritepointerstothefirstlocation
oftheRAMarray.PAEwill goLOW, PAFwillgoHIGH,and HFwillgoHIGH.
If FWFT/SI is LOW during Master Reset then the IDT Standard mode,
along with EF and FF are selected. EF will go LOW and FF will go HIGH. If
FWFT/SIisHIGH,thentheFirstWordFallThroughmode(FWFT),alongwith
IR and OR, are selected. OR will go HIGH and IR will go LOW.
AllcontrolsettingssuchasOW,IW,BE,RM,PFMandIParedefinedduring
theMasterResetcycle.
RETRANSMIT (RT)
DuringaMasterReset,theoutputregisterisinitializedtoallzeroes.AMaster
Resetisrequiredafterpowerup,beforeawriteoperationcantakeplace.MRS
isasynchronous.
The Retransmit (RT) input is used in conjunction with the MARK input,
togethertheyprovideameansbywhichdatapreviouslyreadoutoftheFIFO
canberereadanynumberoftimes.Ifretransmitoperationhasbeenselected
(i.e.theMARKinputisHIGH),arisingedgeonRCLKwhileRTisLOWwillreset
thereadpointerbacktothememorylocationsetbytheuserviatheMARKinput.
IfIDTstandardmodehasbeenselectedtheEFflagwillgoLOWandremain
LOWforthe time thatRT is heldLOW.RT canbe heldLOWforanynumber
ofRCLKcycles,thereadpointerbeingresettothemarkedlocation.Thenext
risingedge ofRCLKafterRT has returnedHIGH, willcause EF togoHIGH,
allowingreadoperationstobeperformedontheFIFO.Thenextreadoperation
willaccessdatafromthe‘marked’memorylocation.
Subsequentretransmitoperationsmaybeperformed,eachtimetheread
pointerreturningtothe‘marked’location.SeeFigure18,RetransmitfromMark
(IDTStandardmode)forthe relevanttimingdiagram.
IfFWFTmodehasbeenselectedtheORflagwillgoHIGHandremainHIGH
forthetimethatRTisheldLOW.RTcanbeheldLOWforanynumberofRCLK
cycles,thereadpointerbeingresettothe‘marked’location.ThenextRCLK
risingedgeafterRThasreturnedHIGH,willcauseORtogoLOWanddueto
FWFToperation,thecontentsofthemarkedmemorylocationwillbeloadedonto
the output register, a read operation being required for all subsequent data
reads.
See Figure 9, Master Reset Timing, forthe relevanttimingdiagram.
PARTIAL RESET (PRS)
APartialResetisaccomplishedwheneverthePRS inputistakentoaLOW
state.AsinthecaseoftheMasterReset,theinternalreadandwritepointers
aresettothefirstlocationoftheRAMarray,PAEgoesLOW, PAFgoesHIGH,
and HF goes HIGH.
WhichevermodeisactiveatthetimeofPartialReset,IDTStandardmode
orFirstWordFallThrough,thatmodewillremainselected. IftheIDTStandard
mode is active, then FF will go HIGH and EF will go LOW. If the First Word
Fall Through mode is active, then OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. Theprogrammingmethod(parallelorserial)currentlyactiveat
thetimeofPartialResetisalsoretained. Theoutputregisterisinitializedtoall
zeroes. PRS is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation,whenreprogrammingprogrammableflagoffsetsettingsmaynotbe
convenient.
See Figure 10, PartialResetTiming, forthe relevanttimingdiagram.
Subsequentretransmitoperationsmaybeperformedeachtimetheread
pointerreturningtothe‘marked’location.SeeFigure19,RetransmitfromMark
(FWFTmode)forthe relevanttimingdiagram.
ASYNCHRONOUS WRITE (ASYW)
ThewriteportcanbeconfiguredforeitherSynchronousorAsynchronous
mode of operation. If during Master Reset the ASYW input is LOW, then
Asynchronousoperationofthewriteportwillbeselected.DuringAsynchro-
nousoperationofthewriteporttheWCLKinputbecomesWRinput,thisisthe
Asynchronouswritestrobeinput.ArisingedgeonWRwillwritedatapresent
ontheDninputsintotheFIFO.(WENmustbetiedLOWwhenusingthewrite
portinAsynchronous mode).
WhenthewriteportisconfiguredforAsynchronousoperationthefullflag
(FF)operatesinanasynchronousmanner,thatis,thefullflagwillbeupdated
based in both a write operation and read operation. Note, if Asynchronous
modeis selected,FWFTis notpermissable.RefertoFigures 30,31,34and
35forrelevanttimingandoperationalwaveforms.
MARK
TheMARKinputisusedtoselectRetransmitmodeofoperation.AnRCLK
rising edge while MARK is HIGH will mark the memory location of the data
currently present on the output register, the device will also be placed into
retransmit mode. Note, for the IDT72T1845/72T1855/72T1865/72T1875/
72T1885/72T1895theremustbeaminimumof32bytesofdatabetweenthe
writepointerandreadpointerwhentheMARKisasserted,fortheIDT72T18105/
72T18115there mustbe a minimumof128bytes andforthe IDT72T18125
theremustbeaminimumof256bytes.Remember,2(x9)bytes=1(x18)word.
(32 bytes = 16 word = 8 long words). Also, once the MARK is set, the write
pointer will not increment past the “marked” location until the MARK is
deasserted.Thisprevents“overwriting”ofretransmitdata.
23
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
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IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
TheMARKinputmustremainHIGHduringthewholeperiodofretransmit
mode, a fallingedge ofRCLKwhile MARKis LOWwilltake the device outof
WENisignoredwhentheFIFOisfullineitherFWFTorIDTStandardmode.
IfAsynchronousoperationofthewriteporthasbeenselected,thenWEN
retransmitmodeandintonormalmode.AnynumberofMARKlocationscanbe mustbeheldactive,(tiedLOW).
setduringFIFOoperation,onlythelastmarkedlocationtakingeffect.Oncea
marklocationhasbeensetthewritepointercannotbeincrementedpastthis READ STROBE & READ CLOCK (RD/RCLK)
markedlocation.Duringretransmitmodewriteoperationstothedevicemay
continuewithouthindrance.
IfSynchronousoperationofthereadporthasbeenselectedviaASYR,this
inputbehavesasRCLK.A readcycleisinitiatedontherisingedgeoftheRCLK
input. Datacanbereadontheoutputs,ontherisingedgeoftheRCLKinput.
ItispermissibletostoptheRCLK. NotethatwhileRCLKisidle,theEF/OR,PAE
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dualpurpose pin. DuringMasterReset, the state ofthe FWFT/ andHFflagswillnotbeupdated.(NotethatRCLKisonlycapableofupdating
SIinputdetermineswhetherthedevicewilloperateinIDTStandardmodeor the HF flag to HIGH). The Write and Read Clocks can be independent or
First Word Fall Through (FWFT) mode.
coincident.
If Asynchronous operation has been selected this input is RD (Read
If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode
willbeselected. This modeuses theEmptyFlag(EF)toindicatewhetheror Strobe) . Data is Asynchronouslyreadfromthe FIFOvia the outputregister
notthereareanywordspresentintheFIFOmemory. ItalsousestheFullFlag wheneverthereisarisingedgeonRD.InthismodetheRENandRCSinputs
function(FF)toindicatewhetherornottheFIFOmemoryhasanyfreespace mustbetiedLOW.TheOEinputisusedtoprovideAsynchronouscontrolofthe
forwriting. InIDTStandardmode,everywordreadfromtheFIFO,including three-stateQnoutputs.
the first, mustbe requestedusingthe ReadEnable (REN)andRCLK.
If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe WRITE CHIP SELECT (WCS)
selected. ThismodeusesOutputReady(OR)toindicatewhetherornotthere
The WCS disables all Write Port inputs (data only) if it is held HIGH. To
isvaliddataatthedataoutputs(Qn). ItalsousesInputReady(IR)toindicate performnormaloperationsonthewriteport,theWCSmustbeenabled,held
whetherornottheFIFOmemoryhasanyfreespaceforwriting. IntheFWFT LOW.
mode,thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLK
rising edges, REN = LOW is not necessary. Subsequent words must be READ ENABLE (REN)
accessed using the Read Enable (REN) and RCLK.
When Read Enable is LOW, data is loaded from the RAM array into the
AfterMasterReset,FWFT/SIactsasaserialinputforloadingPAEandPAF outputregisterontherisingedgeofeveryRCLKcycleifthedeviceisnotempty.
offsetsintotheprogrammableregisters. Theserialinputfunctioncanonlybe
WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdata
usedwhentheserialloadingmethodhasbeenselectedduringMasterReset. andnonewdata is loadedintothe outputregister. The data outputs Q0-Qn
SerialprogrammingusingtheFWFT/SIpinfunctionsthesamewayinbothIDT maintainthepreviousdatavalue.
StandardandFWFTmodes.
IntheIDTStandardmode,everywordaccessedatQn,includingthefirst
wordwrittentoanemptyFIFO, mustbe requestedusingREN providedthat
RCSisLOW. WhenthelastwordhasbeenreadfromtheFIFO,theEmptyFlag
WRITE STROBE & WRITE CLOCK (WR/WCLK)
IfSynchronousoperationofthewriteporthasbeenselectedviaASYW,this (EF)willgoLOW,inhibitingfurtherreadoperations. RENisignoredwhenthe
inputbehavesasWCLK.
FIFOisempty.Onceawriteisperformed,EFwillgoHIGHallowingareadto
AwritecycleisinitiatedontherisingedgeoftheWCLKinput.Datasetup occur. TheEFflagisupdatedbytwoRCLKcycles+tSKEW afterthevalidWCLK
andholdtimesmustbemetwithrespecttotheLOW-to-HIGHtransitionofthe cycle.BothRCSandRENmustbeactive,LOWfordatatobereadoutonthe
WCLK.ItispermissibletostoptheWCLK. NotethatwhileWCLKisidle,theFF/ rising edge of RCLK.
IR,PAFandHFflagswillnotbeupdated. (NotethatWCLKisonlycapableof
updating HF flag to LOW). The Write and Read Clocks can either be totheoutputsQn,onthethirdvalidLOW-to-HIGHtransitionofRCLK+tSKEW
independentorcoincident.
IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes
afterthefirstwrite. RENandRCSdonotneedtobeassertedLOWfortheFirst
IfAsynchronousoperationhasbeenselectedthisinputisWR(writestrobe). Wordtofallthroughtotheoutputregister.Inordertoaccess allotherwords,
DataisAsynchronouslywrittenintotheFIFOviatheDninputswheneverthere a read must be executed using REN and RCS. The RCLK LOW-to-HIGH
is arisingedgeonWR.Inthis modetheWENinputmustbetiedLOW.
transitionafterthelastword hasbeenreadfromtheFIFO,OutputReady(OR)
willgoHIGHwithatrueread(RCLKwithREN=LOW;RCS=LOW),inhibiting
further read operations. REN is ignored when the FIFO is empty.
IfAsynchronousoperationoftheReadporthasbeenselected,thenREN
mustbeheldactive,(tiedLOW).
WRITE ENABLE (WEN)
WhentheWENinput isLOW,datamaybeloadedintotheFIFORAMarray
ontherisingedgeofeveryWCLKcycleifthedeviceisnotfull. Dataisstored
in the RAM array sequentially and independently of any ongoing read
operation.
WhenWENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK
cycle.
To prevent data overflow in the IDT Standard mode, FF will go LOW,
inhibitingfurtherwriteoperations. Uponthecompletionofavalidreadcycle,
FF will go HIGH allowing a write to occur. The FF is updated by two WCLK
cycles +tSKEW afterthe RCLKcycle.
Topreventdataoverflow intheFWFTmode, IR willgoHIGH,inhibiting
furtherwriteoperations. Uponthecompletionofavalidreadcycle,IRwillgo
LOWallowingawritetooccur. TheIRflagis updatedbytwoWCLKcycles +
tSKEW afterthe validRCLKcycle.
SERIAL ENABLE ( SEN )
TheSENinput isanenableusedonlyforserialprogrammingoftheoffset
registers. The serialprogrammingmethodmustbe selectedduringMaster
Reset. SENisalwaysusedinconjunctionwithLD. Whentheselinesareboth
LOW,dataattheSIinputcanbeloadedintotheprogramregisteronebitforeach
LOW-to-HIGHtransitionofSCLK.
When SEN is HIGH, the programmable registers retains the previous
settingsandnooffsetsareloaded. SENfunctionsthesamewayinbothIDT
StandardandFWFTmodes.
24
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
OUTPUT ENABLE (OE )
LOAD (LD)
WhenOutputEnableisenabled(LOW),theparalleloutputbuffersreceive
Thisisadualpurposepin. DuringMasterReset,thestateoftheLDinput,
alongwithFSEL0andFSEL1,determinesoneofeightdefaultoffsetvaluesfor
thePAEandPAFflags,alongwiththemethodbywhichtheseoffsetregisters
canbeprogrammed,parallelorserial(seeTable2). AfterMasterReset,LD
enableswriteoperationstoandreadoperationsfromtheoffsetregisters.Only
theoffsetloadingmethodcurrentlyselectedcanbeusedtowritetotheregisters.
Offsetregisters canbereadonlyinparallel.
datafromtheoutputregister. WhenOEisHIGH,theoutputdatabus(Qn)goes
intoahighimpedancestate.DuringMasteroraPartialResettheOEistheonly
inputthatcanplacetheoutputbusQn,intoHigh-Impedance.DuringResetthe
RCS inputcanbe HIGHorLOW, ithas noeffectonthe Qnoutputs.
READ CHIP SELECT ( RCS )
The Read Chip Select input provides synchronous control of the Read
outputport. WhenRCSgoesLOW,thenextrisingedgeofRCLKcausesthe
QnoutputstogototheLow-Impedancestate. WhenRCSgoesHIGH,thenext
RCLKrisingedgecausestheQnoutputstoreturntoHIGHZ.DuringaMaster
orPartialResettheRCSinputhasnoeffectontheQnoutputbus,OEistheonly
inputthatprovidesHigh-ImpedancecontroloftheQnoutputs.IfOEisLOWthe
QndataoutputswillbeLow-ImpedanceregardlessofRCSuntilthefirstrising
edgeofRCLKafteraResetiscomplete.ThenifRCSisHIGHthedataoutputs
willgotoHigh-Impedance.
TheRCSinputdoesnoteffecttheoperationoftheflags. Forexample,when
thefirstwordiswrittentoanemptyFIFO,theEFwillstillgofromLOWtoHIGH
based on a rising edge of RCLK, regardless of the state of the RCS input.
Also,whenoperatingtheFIFOinFWFTmodethefirstwordwrittentoan
emptyFIFOwillstillbeclockedthroughtotheoutputregisterbasedonRCLK,
regardlessofthestateofRCS.Forthisreasontheusermusttakecarewhen
adatawordiswrittentoanemptyFIFOinFWFTmode.IfRCSisdisabledwhen
anemptyFIFOiswritteninto,thefirstwordwillfallthroughtotheoutputregister,
butwillnotbeavailableontheQnoutputswhichareinHIGH-Z.Theusermust
takeRCSactiveLOWtoaccessthisfirstword,placetheoutputbusinLOW-Z.
RENmustremaindisabledHIGHforatleastonecycleafterRCShasgoneLOW.
ArisingedgeofRCLKwithRCSandRENactiveLOW,willreadoutthenext
word. Care mustbe takensoas nottolose the firstwordwrittentoanempty
FIFOwhenRCSisHIGH.RefertoFigure17,RCSandRENReadOperation
(FWFT Mode). The RCS pin must also be active (LOW) in order to perform
aRetransmit. SeeFigure13forReadCycleandReadChipSelectTiming(IDT
StandardMode). SeeFigure16forReadCycleandReadChipSelectTiming
(First Word Fall Through Mode).
AfterMasterReset,theLDpinisusedtoactivatetheprogrammingprocess
oftheflagoffsetvaluesPAEandPAF.PullingLDLOWwillbeginaserialloading
or parallel load or read of these offset values. THIS PIN MUST BE HIGH
AFTERMASTERRESETTOWRITEORREADDATATO/FROMTHEFIFO
MEMORY.
BUS-MATCHING (IW, OW)
The pins IWandOWare usedtodefine the inputandoutputbus widths.
DuringMasterReset,thestateofthesepinsisusedtoconfigurethedevicebus
sizes. SeeTable1forcontrolsettings. Allflagswilloperateontheword/byte
sizeboundaryasdefinedbytheselectionofbuswidth.SeeFigure5forBus-
MatchingByteArrangement.
BIG-ENDIAN/LITTLE-ENDIAN (BE)
During Master Reset, a LOW on BE will select Big-Endian operation. A
HIGHonBEduringMasterResetwillselectLittle-Endianformat.Thisfunction
isusefulwhendataiswrittenintotheFIFOinwordformat(x18)andreadout
of the FIFO in word format (x18) or byte format (x9). If Big-Endian mode is
selected,thenthemostsignificantbyteofthewordwrittenintotheFIFOwillbe
readoutoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endian
formatisselected,thentheleastsignificantbyteofthewordwrittenintotheFIFO
willbereadoutfirst,followedbythemostsignificantbyte.Themodedesired
isconfiguredduringmasterresetbythestateoftheBig-Endian(BE)pin.See
Figure 5 for Bus-Matching Byte Arrangement.
PROGRAMMABLEFLAGMODE(PFM)
DuringMasterReset,aLOWonPFMwillselectAsynchronousProgram-
mable flagtimingmode. AHIGHonPFMwillselectSynchronous Program-
mableflagtimingmode.IfasynchronousPAF/PAEconfigurationisselected
(PFM, LOW during MRS), the PAE is asserted LOW on the LOW-to-HIGH
transition of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of
WCLK.Similarly,thePAFisassertedLOWontheLOW-to-HIGHtransitionof
WCLKandPAFis resettoHIGHontheLOW-to-HIGHtransitionofRCLK.
If synchronous PAE/PAF configuration is selected (PFM, HIGH during
MRS),thePAEisassertedandupdatedontherisingedgeofRCLKonlyand
notWCLK.Similarly,PAFisassertedandupdatedontherisingedgeofWCLK
only and not RCLK. The mode desired is configured during master reset by
thestateoftheProgrammableFlagMode(PFM)pin.
IfAsynchronousoperationoftheReadporthasbeenselected,thenRCS
mustbeheldactive,(tiedLOW).OEprovidesthree-statecontrolofQn.
WRITE PORT HSTL SELECT (WHSTL)
Thecontrolinputs,datainputsandflagoutputsassociatedwiththewriteport
canbesetuptobeeitherHSTLorLVTTL.IfWHSTLisHIGHduringtheMaster
Reset,thenHSTLoperationofthewriteportwillbeselected.IfWHSTLisLOW
atMasterReset,thenLVTTLwillbeselected.
TheinputsandoutputsassociatedwiththewriteportarelistedinTable5.
READ PORT HSTL SELECT (RHSTL)
Thecontrolinputs,datainputsandflagoutputsassociatedwiththereadport
canbesetuptobeeitherHSTLorLVTTL.IfRHSTLisHIGHduringtheMaster
Reset,thenHSTLoperationofthereadportwillbeselected.IfRHSTLisLOW
atMasterReset,thenLVTTLwillbeselectedforthereadport,thenechoclock
and echo read enable will not be provided.
INTERSPERSED PARITY (IP)
During Master Reset, a LOW on IP will select Non-Interspersed Parity
mode.AHIGHwillselectInterspersedParitymode.TheIPbitfunctionallows
theusertoselecttheparitybitinthewordloadedintotheparallelport(D0-Dn)
whenprogrammingtheflagoffsets.IfInterspersedParitymodeisselected,then
theFIFOwillassumethattheparitybitislocatedinbitpositionD8andD17during
theparallelprogrammingoftheflagoffsets,andwillthereforeignoreD8when
loadingthe offsetregisterinparallelmode. This is alsoappliedtothe output
registerwhenreadingthevalueoftheoffsetregister.IfInterspersedParityis
selected then output Q8 will be invalid. If Non-Interspersed Parity mode is
selected,thenD16andD17 aretheparitybitsandareignoredduringparallel
TheinputsandoutputsassociatedwiththereadportarelistedinTable5.
SYSTEM HSTL SELECT (SHSTL)
Allinputsnotassociatedwiththewriteandreadportcanbesetuptobeeither
HSTLorLVTTL.IfSHSTLisHIGHduringMasterReset,thenHSTLoperation
ofalltheinputsnotassociatedwiththewriteandreadportwillbeselected.If
SHSTL is LOW at Master Reset, then LVTTL will be selected. The inputs
associatedwithSHSTLare listedinTable 5.
25
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
programmingoftheoffsets.(D8becomesavalidbit).Additionally,outputQ8will
become a valid bit when performing a read of the offset register. IP mode is
selectedduringMasterResetbythestateoftheIPinputpin.
again. See Figure 15, Read Timing (FWFT Mode), for the relevant timing
information.
EF/OR is synchronous and updated on the rising edge of RCLK.
InIDTStandardmode, EF is a double register-bufferedoutput. InFWFT
mode,ORisatripleregister-bufferedoutput.
OUTPUTS:
FULL FLAG (FF/IR)
PROGRAMMABLE ALMOST-FULL FLAG (PAF)
Thisisadualpurposepin.InIDTStandardmode,theFullFlag(FF)function
is selected. When the FIFO is full, FF will go LOW, inhibiting further write
operations. WhenFF is HIGH, the FIFOis notfull. Ifnoreads are performed
afterareset(eitherMRS orPRS), FFwillgoLOWafterDwrites totheFIFO.
Ifx18Inputorx18OutputbusWidthisselected,D=2,048fortheIDT72T1845,
4,096 for the IDT72T1855, 8,192 for the IDT72T1865, 16,384 for the
IDT72T1875, 32,768 for the IDT72T1885, 65,536 for the IDT72T1895,
131,072writesfortheIDT72T18105,262,144writesfortheIDT72T18115and
524,288writesfortheIDT72T18125.Ifbothx9Inputandx9OutputbusWidths
are selected, D = 4,096 for the IDT72T1845, 8,192 for the IDT72T1855,
16,384 for the IDT72T1865, 32,768 for the IDT72T1875, 65,536 for the
IDT72T1885, 131,072 for the IDT72T1895, 262,144 writes for the
IDT72T18105,524,288writesfortheIDT72T18115and1,048,576writesfor
the IDT72T18125. See Figure 11, Write Cycle and Full Flag Timing (IDT
StandardMode),fortherelevanttiminginformation.
In FWFT mode, the Input Ready (IR) function is selected. IR goes LOW
whenmemoryspace is available forwritingindata. Whenthere is nolonger
anyfreespaceleft,IRgoesHIGH,inhibitingfurtherwriteoperations.Ifnoreads
areperformedafterareset(eitherMRSorPRS),IRwillgoHIGHafterD writes
totheFIFO.Ifx18Inputorx18OutputbusWidthisselected,D = 2,049forthe
IDT72T1845,4,097fortheIDT72T1855,8,193fortheIDT72T1865,16,385
fortheIDT72T1875,32,769fortheIDT72T1885,65,537fortheIDT72T1895,
131,073writesfortheIDT72T18105,262,145writesfortheIDT72T18115and
524,289writesfortheIDT72T18125.Ifbothx9Inputandx9OutputbusWidths
areselected,D=4,097fortheIDT72T1845,8,193fortheIDT72T1855,16,385
fortheIDT72T1865,32,769fortheIDT72T1875,65,537fortheIDT72T1885,
131,073fortheIDT72T1895,262,145writesfortheIDT72T18105,524,289
writesfortheIDT72T18115and1,048,577writesfortheIDT72T18125.See
Figure 14, Write Timing(FWFTMode), forthe relevanttiminginformation.
TheIRstatusnotonlymeasuresthecontentsoftheFIFOmemory,butalso
countsthepresenceofawordintheoutputregister.Thus,inFWFTmode,the
totalnumberofwritesnecessarytodeassertIRisonegreaterthanneededto
assert FF in IDT Standard mode.
The Programmable Almost-Full flag (PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performedafterreset(MRS),PAFwillgoLOWafter(D-m)wordsarewritten
totheFIFO.Ifx18Inputorx18OutputbusWidthisselected,(D-m) = (2,048-m)
writes fortheIDT72T1845,(4,096-m)writes fortheIDT72T1855,(8,192-m)
writesfortheIDT72T1865,(16,384-m)writesfortheIDT72T1875,(32,768-m)
writesfortheIDT72T1885,(65,536-m)writesfortheIDT72T1895,(131,072-m)
writes for the IDT72T18105, (262,144-m) writes for the IDT72T18115 and
(524,288-m)writes forthe IDT72T18125. Ifbothx9Inputandx9Outputbus
Widthsareselected,(D-m)=(4,096-m)writesfortheIDT72T1845,(8,192-m)
writesfortheIDT72T1855,(16,384-m)writesfortheIDT72T1865,(32,768-m)
writesfortheIDT72T1875,(65,536-m)writesfortheIDT72T1885,(131,072-m)
writes for the IDT72T1895, (262,144-m) writes for the IDT72T18105,
(524,288-m) writes for the IDT72T18115 and (1,048,576-m) writes for the
IDT72T18125.Theoffset“m”isthefulloffsetvalue.Thedefaultsettingforthis
value is stated in Table 2.
InFWFTmode,ifx18Inputorx18Outputbus Widthis selected,thePAF
willgoLOWafter(2,049-m)writesfortheIDT72T1845,(4,097-m)writesforthe
IDT72T1855,(8,193-m)writesfortheIDT72T1865,(16,385-m)writesforthe
IDT72T1875,(32,769-m)writesfortheIDT72T1885,(65,537-m)writesforthe
IDT72T1895, (131,073-m)writes fortheIDT72T18105,(262,145-m)writes
fortheIDT72T18115and(524,289-m)writesfortheIDT72T18125.Ifbothx9
Inputandx9OutputbusWidthsareselected,thePAFwillgoLOWafter(4,097-
m)writesfortheIDT72T1845,(8,193-m)writesfortheIDT72T1855,(16,385-m)
writesfortheIDT72T1865,(32,769-m)writesfortheIDT72T1875,(65,537-m)
writesfortheIDT72T1885,(131,073-m)writesfortheIDT72T1895,(262,145-
m) writes for the IDT72T18105, (524,289-m) writes for the IDT72T18115
and(1,048,577-m)writesfortheIDT72T18125.Theoffsetmisthefulloffset
value.Thedefaultsettingforthis valueis statedinTable2.
SeeFigure23,SynchronousProgrammableAlmost-FullFlagTiming(IDT
StandardandFWFTMode),fortherelevanttiminginformation.
IfasynchronousPAFconfigurationisselected,thePAFisassertedLOW
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK).PAFisresettoHIGH
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK).IfsynchronousPAF
configurationisselected,thePAFisupdatedontherisingedgeofWCLK.See
Figure 25 for Asynchronous Programmable Almost-Full Flag Timing (IDT
Standard and FWFT Mode).
Note,whenthedeviceisinRetransmitmode,thisflagisacomparisonofthe
writepointertothe‘marked’location.Thisdiffersfromnormalmodewherethis
flagis acomparisonofthewritepointertothereadpointer.
FF/IRissynchronousandupdatedontherisingedgeofWCLK.FF/IRare
doubleregister-bufferedoutputs.
Note,whenthedeviceisinRetransmitmode,thisflagisacomparisonofthe
writepointertothe‘marked’location.Thisdiffersfromnormalmodewherethis
flagis acomparisonofthewritepointertothereadpointer.
EMPTYFLAG(EF/OR)
Thisisadualpurposepin.IntheIDTStandardmode,theEmptyFlag(EF)
functionisselected.WhentheFIFOisempty,EFwillgoLOW,inhibitingfurther
readoperations.WhenEFisHIGH,theFIFOisnotempty.SeeFigure12,Read
Cycle,EmptyFlagandFirstWordLatencyTiming(IDTStandardMode),for
therelevanttiminginformation.
InFWFTmode,theOutputReady(OR)functionisselected.ORgoesLOW
atthesametimethatthefirstwordwrittentoanemptyFIFOappearsvalidon
theoutputs.ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshiftsthe
lastwordfromtheFIFOmemorytotheoutputs.ORgoesHIGHonlywithatrue
read(RCLKwithREN=LOW).Thepreviousdatastaysattheoutputs,indicating
the last word was read. Further data reads are inhibited until OR goes LOW
PROGRAMMABLEALMOST-EMPTYFLAG(PAE)
TheProgrammableAlmost-Emptyflag(PAE)willgoLOWwhentheFIFO
reachesthealmost-emptycondition.InIDTStandardmode,PAEwillgoLOW
whenthere are nwords orless inthe FIFO. The offset“n”is the emptyoffset
value.Thedefaultsettingforthis valueis statedinTable2.
In FWFT mode, the PAE will go LOW when there are n+1 words or less
intheFIFO.Thedefaultsettingforthis valueis statedinTable2.
SeeFigure24, Synchronous ProgrammableAlmost-EmptyFlagTiming
(IDTStandardandFWFTMode), forthe relevanttiminginformation.
26
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
IfasynchronousPAEconfigurationisselected,thePAEisassertedLOW
ontheLOW-to-HIGHtransitionoftheReadClock(RCLK).PAEisresettoHIGH
ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK).IfsynchronousPAE
configurationisselected,thePAEisupdatedontherisingedgeofRCLK.See
Figure 26, Asynchronous Programmable Almost-Empty Flag Timing (IDT
StandardandFWFTMode),fortherelevanttiminginformation.
ECHO READ CLOCK (ERCLK)
TheEchoReadClockoutputisprovidedinbothHSTLandLVTTLmode,
selectableviaRHSTL.TheERCLKisafree-runningclockoutput,itwillalways
followthe RCLKinputregardless ofREN, RCS.
TheERCLKoutputfollowstheRCLKinputwithanassociateddelay.This
delayprovidestheuserwithamoreeffectivereadclocksourcewhenreading
data from the Qn outputs. This is especially helpful at high speeds when
variableswithinthedevicemaycausechangesinthedataaccesstimes.These
variations in access time maybe caused by ambient temperature, supply
voltage,devicecharacteristics.TheERCLKoutputalsocompensatesforany
tracelengthdelaysbetweentheQndataoutputsandreceivingdevicesinputs.
Anyvariationseffectingthedataaccesstimewillalsohaveacorresponding
effectontheERCLKoutputproducedbytheFIFOdevice,thereforetheERCLK
outputleveltransitionsshouldalwaysbeatthesamepositionintimerelativeto
thedataoutputs.Note,thatERCLKisguaranteedbydesigntobeslowerthan
the slowest Qn, data output. Refer to Figure 4, Echo Read Clock and Data
OutputRelationship,Figure28,EchoReadClock&ReadEnableOperation
and Figure 29, Echo RCLK & Echo REN Operation for timing information.
HALF-FULL FLAG (HF)
Thisoutputindicatesahalf-fullFIFO.TherisingWCLKedgethatfillstheFIFO
beyond half-full sets HF LOW. The flag remains LOW until the difference
betweenthewriteandreadpointersbecomeslessthanorequaltohalfofthe
totaldepthofthedevice;therisingRCLKedgethataccomplishesthiscondition
sets HF HIGH.
InIDTStandardmode,ifnoreadsareperformedafterreset(MRSorPRS),
HF willgoLOWafter(D/2 + 1)writes tothe FIFO. Ifx18Inputorx18Output
busWidthisselected,D = 2,048fortheIDT72T1845,4,096fortheIDT72T1855,
8,192 for the IDT72T1865, 16,384 for the IDT72T1875, 32,768 for the
IDT72T1885, 65,536 for the IDT72T1895, 131,072 for the IDT72T18105,
262,144forthe IDT72T18115and524,288forthe IDT72T18125. Ifbothx9
Inputandx9OutputbusWidthsareselected,D=4,096fortheIDT72T1845,
8,192 for the IDT72T1855, 16,384 for the IDT72T1865, 32,768 for the
IDT72T1875, 65,536 for the IDT72T1885, 131,072 for the IDT72T1895,
262,144fortheIDT72T18105,524,288fortheIDT72T18115and1,048,576
for the IDT72T18125.
InFWFTmode, ifnoreads are performedafterreset(MRS orPRS), HF
willgoLOWafter(D-1/2 + 2)writestotheFIFO.Ifx18Inputorx18Outputbus
Widthisselected,D=2,049fortheIDT72T1845,4,097fortheIDT72T1855,
8,193 for the IDT72T1865, 16,385 for the IDT72T1875, 32,769 for the
IDT72T1885, 65,537 for the IDT72T1895, 131,073 for the IDT72T18105,
262,145forthe IDT72T18115and524,289forthe IDT72T18125. Ifbothx9
Inputandx9OutputbusWidthsareselected,D = 4,097fortheIDT72T1845,
8,193 for the IDT72T1855, 16,385 for the IDT72T1865, 32,769 for the
IDT72T1875, 65,537 for the IDT72T1885, 131,073 for the IDT72T1895,
262,145fortheIDT72T18105,524,289fortheIDT72T18115and1,048,577
for the IDT72T18125.
ECHO READ ENABLE (EREN)
TheEchoReadEnableoutputisprovidedinbothHSTLandLVTTLmode,
selectableviaRHSTL.
The EREN output is provided to be used in conjunction with the ERCLK
outputandprovidesthereadingdevicewithamoreeffectiveschemeforreading
datafromtheQnoutputportathighspeeds.TheERENoutputiscontrolledby
internallogicthatbehavesasfollows:TheERENoutputisactiveLOWforthe
RCLKcycle thata newwordis readoutofthe FIFO. Thatis, a risingedge of
RCLKwillcauseERENtogoactive,LOWifbothRENandRCSareactive,LOW
and the FIFO is NOT empty.
SERIAL CLOCK (SCLK)
Duringserialloadingoftheprogrammingflagoffsetregisters,arisingedge
ontheSCLKinputisusedtoloadserialdatapresentontheSIinputprovided
thattheSENinputisLOW.
See Figure 27, Half-Full Flag Timing (IDT Standard and FWFT Mode),
fortherelevanttiminginformation.BecauseHFisupdatedbybothRCLKand
WCLK,itisconsideredasynchronous.
DATAOUTPUTS(Q0-Qn)
(Q0 - Q17) data outputs for 18-bit wide data or (Q0 - Q8) data outputs for
9-bitwidedata.
RCLK
tERCLK
tERCLK
ERCLK
tD
tA
Q
SLOWEST(3)
5909 drw08
NOTES:
1. REN is LOW;RCS is LOW.
2. tERCLK > tA, guaranteed by design.
3. Qslowest is the data output with the slowest access time, tA.
4. Time, tD is greater than zero, guaranteed by design.
Figure 4. Echo Read Clock and Data Output Relationship
27
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
B
A
Write to FIFO
Q17-Q9
Q8-Q0
BYTE ORDER ON OUTPUT PORT:
BE
IW
L
OW
L
A
B
Read from FIFO
L
(a) x18 INPUT to x18 OUTPUT - BIG ENDIAN
Q17-Q9
Q8-Q0
BE
IW
L
OW
L
B
A
Read from FIFO
H
(b) x18 INPUT to x18 OUTPUT - LITTLE ENDIAN
Q8-Q0
Q17-Q9
Q17-Q9
BE
IW
L
OW
H
A
1st: Read from FIFO
2nd: Read from FIFO
L
Q8-Q0
B
(c) x18 INPUT to x9 OUTPUT - BIG ENDIAN
Q17-Q9
Q8-Q0
BE
IW
L
OW
H
B
1st: Read from FIFO
H
Q17-Q9
Q8-Q0
A
2nd: Read from FIFO
(d) x18 INPUT to x9 OUTPUT - LITTLE ENDIAN
D17-D9
D8-D0
BYTE ORDER ON INPUT PORT:
A
1st: Write to FIFO
2nd: Write to FIFO
D17-Q9
D8-Q0
B
BYTE ORDER ON OUTPUT PORT:
Q17-Q9
Q8-Q0
BE
IW OW
A
B
Read from FIFO
L
H
L
(a) x9 INPUT to x18 OUTPUT - BIG ENDIAN
Q17-Q9
Q8-Q0
BE
IW
H
OW
L
A
B
Read from FIFO
H
(a) x9 INPUT to x18 OUTPUT - LITTLE ENDIAN
5909 drw09
Figure 5. Bus-Matching Byte Arrangement
28
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
JTAGTIMINGSPECIFICATION
tTCK
t4
t1
t2
TCK
t3
TDI/
TMS
tDS
tDH
TDO
TDO
tDO
t6
TRST
5909 drw10
Notes to diagram:
t1 = tTCKLOW
t2 = tTCKHIGH
t5
t3 = tTCKFALL
t4 = tTCKRISE
t5 = tRST (reset pulse width)
t6 = tRSR (reset recovery)
Figure 6. Standard JTAG Timing
JTAG
ACELECTRICALCHARACTERISTICS
SYSTEMINTERFACEPARAMETERS
(vcc = 2.5V 5%; Tcase = 0°C to +85°C)
IDT72T1845
IDT72T1855
IDT72T1865
IDT72T1875
IDT72T1885
IDT72T1895
IDT72T18105
IDT72T18115
IDT72T18125
Parameter
Symbol
Test
Conditions
Min. Max. Units
JTAGClockInputPeriod tTCK
-
-
-
-
-
-
-
100
40
40
-
-
-
ns
ns
ns
ns
ns
ns
ns
JTAGClockHIGH
JTAGClockLow
tTCKHIGH
tTCKLOW
tTCKRISE
tTCKFALL
tRST
-
Parameter
Symbol Test Conditions Min. Max. Units
JTAGClockRiseTime
JTAGClockFallTime
JTAGReset
5(1)
5(1)
-
(1)
DataOutput
tDO
-
20
-
ns
ns
ns
-
(1)
DataOutputHold tDOH
0
50
50
DataInput
tDS
tDH
trise=3ns
tfall=3ns
10
10
-
-
JTAG Reset Recovery
tRSR
-
NOTE:
1. 50pf loading on external output signals.
NOTE:
1. Guaranteed by design.
29
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
TheStandardJTAGinterfaceconsistsoffourbasicelements:
JTAGINTERFACE
•
•
•
•
Test Access Port (TAP)
TAPcontroller
Instruction Register (IR)
Data Register Port (DR)
Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to
support the JTAG boundary scan interface. The IDT72T1845/72T1855/
72T1865/72T1875/72T1885/72T1895/72T18105/72T18115/72T18125in-
corporatesthenecessarytapcontrollerandmodifiedpadcellstoimplementthe
JTAG facility.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
NotethatIDTprovidesappropriateBoundaryScanDescriptionLanguage
programfilesforthesedevices.
The Figure belowshows the standardBoundary-ScanArchitecture.
DeviceID Reg.
Mux
Boundary Scan Reg.
Bypass Reg.
TDO
TDI
T
A
clkDR, ShiftDR
UpdateDR
P
TMS
TAP
TCLK
Cont-
roller
TRST
Instruction Decode
clklR, ShiftlR
UpdatelR
Instruction Register
Control Signals
5909 drw11
Figure 7. Boundary Scan Architecture
THETAPCONTROLLER
TEST ACCESS PORT (TAP)
TheTapcontrollerisasynchronousfinitestatemachinethatrespondsto
TMSandTCLKsignalstogenerateclockandcontrolsignalstotheInstruction
andDataRegisters forcaptureandupdateofdata.
The Tap interface is a general-purpose port that provides access to the
internaloftheprocessor. Itconsistsoffourinputports(TCLK,TMS,TDI,TRST)
and one output port (TDO).
30
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
1
Test-Logic
Reset
0
1
0
1
1
Run-Test/
Idle
Select-
DR-Scan
Select-
IR-Scan
0
0
1
1
Capture-DR
Capture-IR
0
0
0
0
Shift-DR
Shift-IR
1
1
1
1
Input = TMS
Exit1-IR
EXit1-DR
0
0
0
0
Pause-DR
Pause-IR
1
1
Exit2-IR
Exit2-DR
0
0
1
1
Update-DR
Update-IR
1
0
1
0
5909 drw12
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).
3. TAP controller must be reset before normal FIFO operations can begin.
Figure 8. TAP Controller State Diagram
Capture-IRInthiscontrollerstate,theshiftregisterbankintheInstruction
RegisterparallelloadsapatternoffixedvaluesontherisingedgeofTCK.The
lasttwosignificantbits arealways requiredtobe“01”.
Shift-IR In this controller state, the instruction register gets connected
betweenTDIandTDO,andthecapturedpatterngetsshiftedoneachrisingedge
ofTCK.TheinstructionavailableontheTDIpinisalsoshiftedintotheinstruction
register.
Exit1-IRThisisacontrollerstatewhereadecisiontoentereitherthePause-
IRstateorUpdate-IRstateismade.
Pause-IRThis state is providedinordertoallowthe shiftingofinstruction
registertobetemporarilyhalted.
Exit2-DRThisisacontrollerstatewhereadecisiontoentereithertheShift-
IRstateorUpdate-IRstateismade.
Update-IRInthiscontrollerstate,theinstructionintheinstructionregisteris
latchedintothelatchbankoftheInstructionRegisteroneveryfallingedgeof
TCK.Thisinstructionalsobecomesthecurrentinstructiononceitislatched.
Capture-DRInthiscontrollerstate,thedataisparallelloadedintothedata
registersselectedbythecurrentinstructionontherisingedgeofTCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
controllerstates are similartothe Shift-IR, Exit1-IR, Pause-IR, Exit2-IRand
Update-IRstatesintheInstructionpath.
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1)forthefullstatediagram
AllstatetransitionswithintheTAPcontrolleroccurattherisingedgeofthe
TCLKpulse. TheTMSsignallevel(0or1)determinesthestateprogression
thatoccursoneachTCLKrisingedge. TheTAPcontrollertakesprecedence
overtheFIFOmemoryandmustberesetafterpowerupofthedevice. See
TRSTdescriptionformoredetails onTAPcontrollerreset.
Test-Logic-ResetAlltestlogicisdisabledinthiscontrollerstateenablingthe
normaloperationoftheIC.TheTAPcontrollerstatemachineisdesignedinsuch
awaythat,nomatterwhattheinitialstateofthecontrolleris,theTest-Logic-Reset
statecanbeenteredbyholdingTMSathighandpulsingTCKfivetimes.This
is the reason why the Test Reset (TRST) pin is optional.
Run-Test-IdleInthiscontrollerstate,thetestlogicintheICisactiveonlyif
certaininstructionsarepresent.Forexample,ifaninstructionactivatestheself
test,thenitwillbeexecutedwhenthecontrollerentersthisstate.Thetestlogic
intheICis idles otherwise.
Select-DR-ScanThis is a controllerstate where the decisiontoenterthe
DataPathortheSelect-IR-Scanstateismade.
Select-IR-Scan This is a controller state where the decision to enter the
InstructionPathismade.TheControllercanreturntotheTest-Logic-Resetstate
otherwise.
31
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
THE INSTRUCTION REGISTER
31(MSB)
Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)
0X0 0X33
28 27
12 11
1 0(LSB)
TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe
processor at the rising edge of TCLK.
1
TheInstructionis usedtoselectthetesttobeperformed,orthetestdata
registertobeaccessed,orboth. Theinstructionshiftedintotheregisterislatched
atthecompletionoftheshiftingprocesswhentheTAPcontrollerisatUpdate-
IRstate.
Theinstructionregistermustcontain4bitinstructionregister-basedcells
whichcanholdinstructiondata. Thesemandatorycellsarelocatednearestthe
serialoutputstheyaretheleastsignificantbits.
IDT72T1845/55/65/75/85/95/105/115/125JTAGDeviceIdentificationRegister
JTAG INSTRUCTION REGISTER
TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice
whentheTAPcontrollerisintheShift-IRstate. Theinstructionisdecodedto
performthefollowing:
•
Selecttestdataregistersthatmayoperatewhiletheinstructionis
current. Theothertestdataregistersshouldnotinterferewithchip
operationandtheselecteddataregister.
Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween
TDI and TDO during data register scanning.
TESTDATAREGISTER
•
TheTestDataregistercontainsthreetestdataregisters:theBypass,the
Boundary Scan register and Device ID register.
Theseregistersareconnectedinparallelbetweenacommonserialinput
andacommonserialdataoutput.
The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode
16differentpossibleinstructions. Instructionsaredecodedasfollows.
Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora
completedescription,refertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
Hex
Instruction
Function
Value
0x00
0x02
0x01
0x03
0x0F
EXTEST
IDCODE
SAMPLE/PRELOAD
HIGH-IMPEDANCE
BYPASS
SelectBoundaryScanRegister
SelectChipIdentificationdataregister
SelectBoundaryScanRegister
JTAG
TEST BYPASS REGISTER
TheregisterisusedtoallowtestdatatoflowthroughthedevicefromTDI
toTDO. Itcontainsasinglestageshiftregisterforaminimumlengthinserialpath.
Whenthebypassregisterisselectedbyaninstruction,theshiftregisterstage
is settoa logiczeroonthe risingedge ofTCLKwhenthe TAPcontrolleris in
theCapture-DRstate.
SelectBypassRegister
JTAG Instruction Register Decoding
Thefollowingsectionsprovideabriefdescriptionofeachinstruction. For
acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification
(IEEEStd. 1149.1-1990).
The operation of the bypass register should not have any effect on the
operationofthedeviceinresponsetotheBYPASSinstruction.
THE BOUNDARY-SCAN REGISTER
EXTEST
TheBoundaryScanRegisterallowsserialdataTDIbeloadedintoorread
outoftheprocessorinput/outputports. TheBoundaryScanRegisterisapart
oftheIEEE1149.1-1990StandardJTAGImplementation.
TherequiredEXTESTinstructionplacestheICintoanexternalboundary-
testmodeandselectstheboundary-scanregistertobeconnectedbetweenTDI
andTDO. Duringthis instruction, theboundary-scanregisteris accessedto
drivetestdataoff-chipviatheboundaryoutputsandreceivetestdataoff-chip
viatheboundaryinputs.Assuch,theEXTESTinstructionistheworkhorseof
IEEE.Std1149.1,providingforprobe-lesstestingofsolder-jointopens/shorts
andoflogicclusterfunction.
THE DEVICE IDENTIFICATION REGISTER
The Device IdentificationRegisteris a ReadOnly32-bitregisterusedto
specify the manufacturer, part number and version of the processor to be
determinedthroughtheTAPinresponsetotheIDCODEinstruction.
IDTJEDECIDnumberis0xB3.Thistranslatesto0x33whentheparityis
droppedinthe11-bitManufacturerIDfield.
For the IDT72T1845/72T1855/72T1865/72T1875/72T1885/72T1895/
72T18105/72T18115/72T18125,thePartNumberfieldcontainsthefollowing
values:
IDCODE
TheoptionalIDCODEinstructionallowstheICtoremaininitsfunctionalmode
andselectstheoptionaldeviceidentificationregistertobeconnectedbetween
TDIandTDO.Thedeviceidentificationregisterisa32-bitshiftregistercontaining
information regarding the IC manufacturer, device type, and version code.
Accessingthedeviceidentificationregisterdoesnotinterferewiththeoperation
oftheIC.Also,accesstothedeviceidentificationregistershouldbeimmediately
available,viaaTAPdata-scanoperation,afterpower-upoftheICorafterthe
TAPhasbeenresetusingtheoptionalTRSTpinorbyotherwisemovingtothe
Test-Logic-Resetstate.
Device
Part# Field
040E
IDT72T1845
IDT72T1855
IDT72T1865
IDT72T1875
IDT72T1885
IDT72T1895
IDT72T18105
IDT72T18115
IDT72T18125
040D
040C
040B
040A
0409
0419
0418
0417
SAMPLE/PRELOAD
TherequiredSAMPLE/PRELOADinstructionallows theICtoremainina
normalfunctionalmodeandselectstheboundary-scanregistertobeconnected
betweenTDIandTDO.Duringthisinstruction,theboundary-scanregistercan
beaccessedviaadatescanoperation,totakeasampleofthefunctionaldata
enteringandleavingtheIC.Thisinstructionisalsousedtopreloadtestdatainto
theboundary-scanregisterbeforeloadinganEXTESTinstruction.
32
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
HIGH-IMPEDANCE
TheoptionalHigh-Impedanceinstructionsetsalloutputs(includingtwo-state
BYPASS
The required BYPASS instruction allows the IC to remain in a normal
aswellasthree-statetypes)ofanICtoadisabled(high-impedance)stateand functional mode and selects the one-bit bypass register to be connected
selects the one-bit bypass register to be connected between TDI and TDO. between TDI and TDO. The BYPASS instruction allows serial data to be
Duringthisinstruction,datacanbeshiftedthroughthebypassregisterfromTDI transferredthroughtheICfromTDItoTDOwithoutaffectingtheoperationof
toTDOwithoutaffectingtheconditionoftheICoutputs.
theIC.
33
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
tRS
MRS
REN
t
RSR
RSR
t
RSS
RSS
t
t
WEN
tRSS
tRSR
FWFT/SI
tRSS
tRSR
LD
t
RSS
RSS
FSEL0,
FSEL1
t
OW, IW
WHSTL
t
t
t
HRSS
HRSS
HRSS
RHSTL
SHSTL
BE
t
RSS
RSS
RSS
t
t
PFM
IP
RT
t
RSS
RSS
t
SEN
t
RSF
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
EF/OR
t
RSF
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
FF/IR
PAE
t
RSF
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
5909 drw13
NOTE:
1. During Master Reset the High-Impedance control of the Qn data outputs is provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Master Reset
is complete.
Figure 9. Master Reset Timing
34
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
tRS
PRS
REN
tRSS
tRSR
tRSS
tRSR
WEN
RT
tRSS
tRSS
SEN
If FWFT = HIGH, OR = HIGH
If FWFT = LOW, EF = LOW
If FWFT = LOW, FF = HIGH
If FWFT = HIGH, IR = LOW
t
RSF
EF/OR
t
RSF
FF/IR
PAE
t
RSF
t
RSF
PAF, HF
t
RSF
OE = HIGH
OE = LOW
Q0 - Qn
5909 drw14
NOTE:
1. During Partial Reset the High-Impedance control of the Qn data outputs is provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Master Reset
is complete.
Figure 10. Partial Reset Timing
35
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
t
CLK
t
CLKH
t
CLKL
NO WRITE
NO WRITE
WCLK
2
1
(1)
1
(1)
2
t
SKEW1
t
DH
t
SKEW1
tDS
t
DH
tDS
DX+1
DX
D0 - Dn
tWFF
tWFF
tWFF
tWFF
FF
WEN
RCLK
tENS
tENS
t
ENH
tENH
REN
RCS
tENS
tA
tA
Q0
- Qn
NEXT DATA READ
DATA READ
5909 drw15
tRCSLZ
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle pus tWFF). If the time between the
rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.
2. LD = HIGH, OE = LOW, EF = HIGH.
3. WCS = LOW.
Figure 11. Write Cycle and Full Flag Timing (IDT Standard Mode)
tCLK
tCLKH
tCLKL
1
2
RCLK
REN
tENH
tENS
tENS
tENH
tENH
tENS
NO OPERATION
NO OPERATION
tREF
tREF
tREF
EF
tA
tA
tA
D0
LAST WORD
D1
LAST WORD
Q0 - Qn
tOLZ
tOHZ
t
OLZ
tOE
OE
WCLK
WEN
t
SKEW1(1)
tENS
tENH
tENH
tENS
tWCSS
tWCSH
WCS
tDS
tDH
tDH
tDS
D0
D1
D0 - Dn
5909 drw16
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.
4. RCS is LOW.
Figure 12. Read Cycle, Output Enable, Empty Flag and First Data Word Latency (IDT Standard Mode)
36
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
2
1
RCLK
tENS
REN
RCS
tENS
tENS
tENS
tENH
tREF
tREF
EF
tRCSHZ
tRCSHZ
tA
tA
tRCSLZ
tRCSLZ
LAST DATA-1
LAST DATA
Q0 - Qn
t
SKEW1(1)
WCLK
tENS
tENH
WEN
tDS
tDH
Dn
Dx
5909 drw 17
NOTES:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.
2. LD = HIGH.
3. First data word latency = tSKEW1 + 1*TRCLK + tREF.
4. OE is LOW.
Figure 13. Read Cycle and Read Chip Select (IDT Standard Mode)
37
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
38
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
39
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
40
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
RNE
ERN RNE
REN ERN
RSC
CRS RSC
RCS CRS
41
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
42
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
43
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
t
SCLK
tSCKH
t
SCKL
SENS
SCLK
tSENH
t
tENH
SEN
LD
tLDS
tLDS
tLDH
t
SDH
t
SDS
BIT 1
BIT X(1)
BIT X(1)
BIT 1
SI
5909 drw24
FULL OFFSET
EMPTY OFFSET
NOTES:
1. x9 to x9 mode: X =12 for the IDT72T1845, X = 13 for the IDT72T1855, X = 14 for the IDT72T1865, X = 15 for the IDT72T1875, X = 16 for the IDT72T1885, X = 17 for the IDT72T1895,
X = 18 for the IDT72T18105, X = 19 for the IDT72T18115 and X = 20 for the IDT72T18125.
2. All other modes: X=11 for the IDT72T1845, X = 12 for the IDT72T1855, X = 13 for the IDT72T1865, X = 14 for the IDT72T1875, X = 15 for the IDT72T1885 and X = 16 for the IDT72T1895,
X = 17 for the IDT72T18105, X = 18 for the IDT72T18115 and X = 19 for the IDT72T18125.
Figure 20. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
WCLK
LD
tLDS
t
LDH
tLDH
t
ENS
tENH
t
ENH
DH
WEN
tDS
tDS
tDS
tDS
t
t
DH
t
DH
tDH
D0 - D17
5909 drw25
PAE(2) OFFSET
PAF(2) OFFSET
PAE OFFSET
PAF OFFSET
NOTES:
1. This timing diagram is based on programming with a x18 bus width.
2. Overwrites previous offset value.
Figure 21. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
RCLK
tLDH
tLDH
tLDH
tLDS
tLDS
tLDS
LD
tENH
tENH
tENH
t
ENS
t
ENS
tENS
REN
t
A
t
A
tA
DATA IN OUTPUT REGISTER
PAE OFFSET VALUE
PAF OFFSET VALUE
PAE OFFSET
Q0 - Q17
5909 drw26
NOTES:
1. OE = LOW.
2. The timing diagram illustrates reading of offset registers with an output bus width of 18 bits.
3. The offset registers cannot be read on consecutive RCLK cycles. The read must be disabled (REN = HIGH) for a minimum of one RCLK cycle in between register accesses.
Figure 22. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
44
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
tCLKL
tCLKL
WCLK
WEN
PAF
1
2
2
1
t
ENS
tENH
t
PAFS
tPAFS
D - m words in FIFO(2)
D-(m+1) words
in FIFO(2)
D - (m +1) words in FIFO(2)
t
SKEW2(3)
RCLK
tENH
t
ENS
5909 drw27
REN
NOTES:
1. m = PAF offset .
2. D = maximum FIFO depth.
In IDT Standard mode: if x18 Input or x18 Output bus Width is selected, D = 2,048 for the IDT72T1845, 4,096 for the IDT72T1855, 8,192 for the IDT72T1865, 16,384 for the IDT72T1875,
32,768 for the IDT72T1885, 65,536 for the IDT72T1895, 131,072 for the IDT72T18105, 262,144 for the IDT72T18115 and 524,288 for the IDT72T18125. If both x9 Input and x9
Output bus Widths are selected, D = 4,096 for the IDT72T1845, 8,192 for the IDT72T1855, 16,384 for the IDT72T1865, 32,768 for the IDT72T1875, 65,536 for the IDT72T1885,
131,072 for the IDT72T1895, 262,144 for the IDT72T18105, 524,288 for the IDT72T18115 and 1,048,576 for the IDT72T18125.
In FWFT mode: if x18 Input or x18 Output bus Width is selected, D = 2,049 for the IDT72T1845, 4,097 for the IDT72T1855, 8,193 for the IDT72T1865, 16,385 for the IDT72T1875,
32,769 for the IDT72T1885, 65,537 for the IDT72T1895, 131,073 for the IDT72T18105, 262,145 for the IDT72T18115 and 524,289 for the IDT72T18125. If both x9 Input and x9
Output bus Widths are selected, D = 4,097 for the IDT72T1845, 8,193 for the IDT72T1855, 16,385 for the IDT72T1865, 32,769 for the IDT72T1875, 65,537 for the IDT72T1885,
131,073 for the IDT72T1895, 262,145 for the IDT72T18105, 524,289 for the IDT72T18115 and 1,048,577 for the IDT72T18125.
3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.
4. PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
6. RCS is LOW.
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
t
ENS
tENH
WEN
PAE
n words in FIFO(2)
n + 1 words in FIFO(3)
,
n words in FIFO(2)
n + 1 words in FIFO(3)
,
n + 1 words in FIFO(2)
n + 2 words in FIFO(3)
,
SKEW2(4)
t
PAES
t
PAES
t
1
2
1
2
RCLK
t
ENS
tENH
5909 drw28
REN
NOTES:
1. n = PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.
5. PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
7. RCS = LOW.
Figure 24. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
45
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
PAF
tPAFA
D - m words
in FIFO
D - (m + 1) words
in FIFO
D - (m + 1) words in FIFO
tPAFA
RCLK
tENS
REN
5909 drw29
NOTES:
1. m = PAF offset.
2. D = maximum FIFO depth.
In IDT Standard mode: if x18 Input or x18 Output bus Width is selected, D = 2,048 for the IDT72T1845, 4,096 for the IDT72T1855, 8,192 for the IDT72T1865, 16,384 for the IDT72T1875,
32,768 for the IDT72T1885, 65,536 for the IDT72T1895, 131,072 for the IDT72T18105, 262,144 for the IDT72T18115 and 524,288 for the IDT72T18125. If both x9 Input and x9
Output bus Widths are selected, D = 4,096 for the IDT72T1845, 8,192 for the IDT72T1855, 16,384 for the IDT72T1865, 32,768 for the IDT72T1875, 65,536 for the IDT72T1885,
131,072 for the IDT72T1895, 262,144 for the IDT72T18105, 524,288 for the IDT72T18115 and 1,048,576 for the IDT72T18125.
In FWFT mode: if x18 Input or x18 Output bus Width is selected, D = 2,049 for the IDT72T1845, 4,097 for the IDT72T1855, 8,193 for the IDT72T1865, 16,385 for the IDT72T1875,
32,769 for the IDT72T1885, 65,537 for the IDT72T1895, 131,073 for the IDT72T18105, 262,145 for the IDT72T18115 and 524,289 for the IDT72T18125. If both x9 Input and x9
Output bus Widths are selected, D = 4,097 for the IDT72T1845, 8,193 for the IDT72T1855, 16,385 for the IDT72T1865, 32,769 for the IDT72T1875, 65,537 for the IDT72T1885,
131,073 for the IDT72T1895, 262,145 for the IDT72T18105, 524,289 for the IDT72T18115 and 1,048,577 for the IDT72T18125.
3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
5. RCS is LOW.
Figure 25. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
tCLKH
tCLKL
WCLK
tENS
tENH
WEN
tPAEA
(2)
(2)
n words in FIFO
,
n words in FIFO
,
(2)
n + 1 words in FIFO
n + 2 words in FIFO
,
(3)
PAE
RCLK
REN
(3)
n + 1 words in FIFO
n + 1 words in FIFO
(3)
tPAEA
tENS
5909 drw30
NOTES:
1. n = PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
6. RCS = LOW.
Figure 26. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
46
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
tCLKH
tCLKL
WCLK
tENH
tENS
WEN
HF
tHF
D/2 + 1 words in FIFO(1),
D/2 words in FIFO(1)
,
D/2 words in FIFO(1)
,
D-1
[
+ 2]
words in FIFO(2)
D-1
2
2
D-1
[
+ 1
]
words in FIFO(2)
[
+ 1
words in FIFO(2)
]
2
tHF
RCLK
tENS
REN
5909 drw31
NOTES:
1. In IDT Standard mode: D = maximum FIFO depth. If x18 Input or x18 Output bus Width is selected, D = 2,048 for the IDT72T1845, 4,096 for the IDT72T1855, 8,192 for the IDT72T1865,
16,384 for the IDT72T1875, 32,768 for the IDT72T1885, 65,536 for the IDT72T1895, 131,072 for the IDT72T18105, 262,144 for the IDT72T18115 and 524,288 for the IDT72T18125.
If both x9 Input and x9 Output bus Widths are selected, D = 4,096 for the IDT72T1845, 8,192 for the IDT72T1855, 16,384 for the IDT72T1865, 32,768 for the IDT72T1875, 65,536
for the IDT72T1885, 131,072 for the IDT72T1895, 262,144 for the IDT72T18105, 524,288 for the IDT72T18115 and 1,048,576 for the IDT72T18125.
2. In FWFT mode: D = maximum FIFO depth. If x18 Input or x18 Output bus Width is selected, D = 2,049 for the IDT72T1845, 4,097 for the IDT72T1855, 8,193 for the IDT72T1865,
16,385 for the IDT72T1875, 32,769 for the IDT72T1885, 65,537 for the IDT72T1895, 131,073 for the IDT72T18105, 262,145 for the IDT72T18115 and 524,289 for the IDT72T18125.
If both x9 Input and x9 Output bus Widths are selected, D = 4,097 for the IDT72T1845, 8,193 for the IDT72T1855, 16,385 for the IDT72T1865, 32,769 for the IDT72T1875, 65,537
for the IDT72T1885, 131,073 for the IDT72T1895, 262,145 for the IDT72T18105, 524,289 for the IDT72T18115 and 1,048,577 for the IDT72T18125.
3. RCS = LOW.
Figure 27. Half-Full Flag Timing (IDT Standard and FWFT Modes)
47
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
48
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
WCLK
tENS
tENH
WEN
tDS
t
DH
tDS
t
DH
tDS
tDH
Wn+1
Wn+2
Wn+3
D0 - Dn
tSKEW1
1
2
RCLK
b
e
h
a
d
g
c
i
f
tERCLK
ERCLK
tENS
tENH
REN
RCS
tENS
tCLKEN
tCLKEN
tCLKEN
tCLKEN
EREN
Qn
tA
tA
t
RCSLZ
HIGH-Z
Wn+1
Wn+2
Wn+3
tREF
tREF
OR
tA
tA
tA
O/P
Reg.
Wn
Last Word
Wn+1
Wn+2
Wn+3
5909 drw33
NOTE:
1. The O/P Register is the internal output register. Its contents are available on the Qn output bus only when RCS and OE are both active, LOW, that is the bus is not in High-
Impedance state.
2. OE is LOW.
Cycle:
a&b. At this point the FIFO is empty, OR is HIGH.
RCS and REN are both disabled, the output bus is High-Impedance.
c.
Word Wn+1 falls through to the output register, OR goes active, LOW.
RCS is HIGH, therefore the Qn outputs are High-Impedance. EREN goes LOW to indicate that a new word has been placed on the output register.
EREN goes HIGH, no new word has been placed on the output register on this cycle.
No Operation.
RCS is LOW on this cycle, therefore the Qn outputs go to Low-Impedance and the contents of the output register (Wn+1) are made available.
NOTE: In FWFT mode is important to take RCS active LOW at least one cycle ahead of REN, this ensures the word (Wn+1) currently in the output register is made
available for at least one cycle.
d.
e.
f.
g.
h.
i.
REN goes active LOW, this reads out the second word, Wn+2.
EREN goes active LOW to indicate a new word has been placed into the output register.
Word Wn+3 is read out, EREN remains active, LOW indicating a new word has been read out.
NOTE: Wn+3 is the last word in the FIFO.
This is the next enabled read after the last word, Wn+3 has been read out. OR flag goes HIGH and EREN goes HIGH to indicate that there is no new word available.
Figure 29. Echo RCLK and Echo REN Operation (FWFT Mode Only)
49
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
RCLK
tENS
tENH
REN
Qn
tA
W0
W1
tFFA
FF
tFFA
tFFA
tCYC
WR
tCYH
tDS
tDH
Dn
WD
WD+1
5909 drw34
NOTE:
1. OE = LOW, WEN = LOW and RCS = LOW.
Figure 30. Asynchronous Write, Synchronous Read, Full Flag Operation (IDT Standard Mode)
1
2
RCLK
tENS
tENH
REN
tA
tA
Last Word
W1
W0
Qn
tREF
tREF
EF
tCYL
tSKEW
WR
tCYH
tCYC
tDH
tDH
tDS
tDS
W0
W1
Dn
5909 drw35
NOTE:
1. OE = LOW, WEN = LOW and RCS = LOW.
Figure 31. Asynchronous Write, Synchronous Read, Empty Flag Operation (IDT Standard Mode)
50
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
No Write
1
WCLK
WEN
Dn
2
DF+1
DF
tWFF
tWFF
FF
tCYC
tSKEW
tCYL
tCYH
RD
Qn
tAA
t
AA
Last Word
WX
WX+1
5909 drw36
NOTES:
1. OE = LOW, RCS = LOW and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 32. Synchronous Write, Asynchronous Read, Full Flag (IDT Standard Mode)
WCLK
WEN
Dn
t
ENS
t
ENH
t
DS
t
DH
W0
tEFA
EF
tEFA
tRPE
RD
Qn
tCYH
tAA
Last Word in Output Register
W0
5909 drw37
NOTES:
1. OE = LOW, RCS = LOW and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 33. Synchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)
51
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
tCYC
tCYH
tCYL
WR
Dn
tDH
tDH
tDS
W0
W1
RD
Qn
tAA
tAA
W1
W0
Last Word in O/P Register
RPE
t
tEFA
tEFA
EF
5909 drw38
NOTES:
1. OE = LOW, WEN = LOW, REN = LOW and RCS = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 34. Asynchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)
tCYC
tCYH
tCYL
WR
Dn
tDH
tDH
tDS
tDS
W
y+1
Wy
tCYC
tCYH
tCYL
RD
Qn
tAA
tAA
Wx
Wx+1
Wx+2
tFFA
tFFA
FF
5909 drw39
NOTES:
1. OE = LOW, WEN = LOW, REN = LOW and RCS = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
Figure 35. Asynchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)
52
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
avoided by creating composite flags, that is, ANDing EF of every FIFO, and
separatelyANDingFFofeveryFIFO. InFWFTmode,compositeflagscanbe
createdbyORingORofeveryFIFO,andseparatelyORingIRofeveryFIFO.
Figure 36 demonstrates a width expansion using two IDT72T1845/
72T1855/72T1865/72T1875/72T1885/72T1895/72T18105/72T18115/
72T18125devices.D0-D17fromeachdeviceforma36-bitwideinputbusand
Q0-Q17 fromeachdevice forma 36-bitwide outputbus. Anywordwidthcan
beattainedbyaddingadditionalIDT72T1845/72T1855/72T1865/72T1875/
72T1885/72T1895/72T18105/72T18115/72T18125devices.
OPTIONALCONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Wordwidthmaybe increasedsimplybyconnectingtogetherthe control
signalsofmultipledevices. Statusflagscanbedetectedfromanyonedevice.
TheexceptionsaretheEFandFFfunctionsinIDTStandardmodeandtheIR
andORfunctionsinFWFTmode. BecauseofvariationsinskewbetweenRCLK
andWCLK, itis possible forEF/FF deassertionandIR/OR assertiontovary
byonecyclebetweenFIFOs. InIDTStandardmode,suchproblems canbe
SERIAL CLOCK (SCLK)
PARTIAL RESET (PRS)
MASTER RESET (MRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (RT)
Dm+1 - Dn
m + n
m
n
D0 - Dm
DATA IN
READ CLOCK (RCLK)
READ CHIP SELECT (RCS)
IDT
IDT
WRITE CLOCK (WCLK)
WRITE ENABLE (WEN)
LOAD (LD)
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
72T18105
72T18115
72T18125
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
72T18105
72T18115
72T18125
READ ENABLE (REN)
OUTPUT ENABLE (OE)
PROGRAMMABLE (PAE)
#1
FULL FLAG/INPUT READY (FF/IR)
(1)
EMPTY FLAG/OUTPUT READY (EF/OR) #1
EMPTY FLAG/OUTPUT READY (EF/OR) #2
(1)
GATE
FULL FLAG/INPUT READY (FF/IR) #2
GATE
FIFO
#1
FIFO
#2
m + n
PROGRAMMABLE (PAF)
HALF-FULL FLAG (HF)
n
Qm+1 - Qn
DATA OUT
m
5909 drw40
Q0 - Qm
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 36. Block Diagram of Width Expansion
For the x18 Input or x18 Output bus Width: 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 18, 32,768 x 18, 65,536 x 36, 131,072 x 36,
262,144 x 36 and 524,288 x 36
For both x9 Input and x9 Output bus Widths: 4,096 x 18, 8,192 x 18, 16,384 x 18, 32,768 x 18, 65,536 x 18, 131,072 x 18, 262,144 x 18,
524,288 x 18 and 1,048,576 x 18
53
FEBRUARY10,2009
COMMERCIALANDINDUSTRIAL
TEMPERATURERANGES
IDT72T1845/55/65/75/85/95/105/115/125 2.5V TeraSync™ 18-BIT/9-BIT FIFO 2Kx18/4Kx9, 4Kx18/
8Kx9, 8Kx18/16Kx9, 16Kx18/32Kx9, 32Kx18/64Kx9, 64Kx18/128Kx9, 128Kx18/256Kx9, 256Kx18/512Kx9, 512Kx18/1Mx9
FWFT/SI
TRANSFER CLOCK
FWFT/SI
FWFT/SI
WRITE CLOCK
WRITE ENABLE
READ CLOCK
RCLK
WCLK
WEN
IR
RCLK
WCLK
IDT
IDT
READ CHIP SELECT
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
72T18105
72T18115
72T18125
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
72T18105
72T18115
72T18125
RCS
OR
WEN
READ ENABLE
REN
INPUT READY
REN
RCS
OUTPUT READY
IR
OR
OUTPUT ENABLE
OE
OE
GND
n
DATA OUT
n
n
DATA IN
Dn
Qn
Qn
Dn
5909 drw41
Figure 37. Block Diagram of Depth Expansion
For the x18 Input or x18 Output bus Width:
4,096 x 18, 8,192 x 18, 16,384 x 18, 32,768 x 18, 65,536 x 18, 131,072 x 18, 262,144 x 18, 524,288 x 18 and 1,048,576 x 18
For both x9 Input and x9 Output bus Widths:
8,192 x 9, 16,384 x 9, 32,768 x 9, 65,536 x 9, 131,072 x 9, 262,144 x 9, 524,288 x 9, 1,048,576 x 9 and 2,097,152 x 9
outputs)afterawordhasbeenwrittentothefirstFIFOisthesumofthedelays
for each individual FIFO:
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
The IDT72T1845 can easily be adapted to applications requiring depths
greaterthan2,048whenthex18Inputorx18OutputbusWidthisselected,4,096
fortheIDT72T1855,8,192fortheIDT72T1865,16,384fortheIDT72T1875,
32,768 for the IDT72T1885, 65,536 for the IDT72T1895, 131,072 for the
IDT72T18105, 262,144 for the IDT72T18115 and 524,288 for the
IDT72T18125. When both x9 Input and x9 Output bus Widths are selected,
depthsgreaterthan4,096canbeadaptedfortheIDT72T1845,8,192forthe
IDT72T1855, 16,384 for the IDT72T1865, 32,768 for the IDT72T1875,
65,536 for the IDT72T1885, 131,072 for the IDT72T1895, 262,144 for the
IDT72T8105, 524,288 for the IDT72T18115 and 1,048,576 for the
IDT72T18125.InFWFTmode,theFIFOscanbeconnectedinseries(thedata
outputsofoneFIFOconnectedtothedatainputsofthenext)withnoexternal
logicnecessary. Theresultingconfigurationprovidesatotaldepthequivalent
tothesumofthedepthsassociatedwitheachsingleFIFO. Figure37shows
a depth expansion using two IDT72T1845/72T1855/72T1865/72T1875/
72T1885/72T1895/72T18105/72T18115/72T18125devices.
CareshouldbetakentoselectFWFTmodeduringMasterResetforallFIFOs
in the depth expansion configuration. The first word written to an empty
configurationwillpassfromoneFIFOtothenext("rippledown")untilitfinally
appears at the outputs of the last FIFO in the chain – no read operation is
necessarybuttheRCLKofeachFIFOmustbefree-running. Eachtimethedata
word appears at the outputs of one FIFO, that device's OR line goes LOW,
enabling a write to the next FIFO in line.
(N – 1)*(4*transfer clock) + 3*TRCLK
whereNisthenumberofFIFOsintheexpansionandTRCLKistheRCLKperiod.
Note that extra cycles should be added for the possibility that the tSKEW1
specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer
clock,fortheORflag.
The"rippledown"delayisonlynoticeableforthefirstwordwrittentoanempty
depthexpansionconfiguration. Therewillbenodelayevidentforsubsequent
wordswrittentotheconfiguration.
The first free location created by reading from a full depth expansion
configurationwill"bubbleup"fromthelastFIFOtothepreviousoneuntilitfinally
movesintothefirstFIFOofthechain. Eachtimeafreelocationiscreatedinone
FIFOofthechain,thatFIFO'sIRlinegoesLOW,enablingtheprecedingFIFO
towriteawordtofillit.
Forafullexpansionconfiguration,theamountoftimeittakesforIRofthefirst
FIFOinthechaintogoLOWafterawordhasbeenreadfromthelastFIFO is
the sumofthe delays foreachindividualFIFO:
(N – 1)*(3*transfer clock) + 2 TWCLK
where N is the number of FIFOs in the expansion and TWCLK is the WCLK
period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1
specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer
clock,fortheIRflag.
TheTransferClocklineshouldbetiedtoeitherWCLKorRCLK,whichever
isfaster. Boththeseactionsresultindatamoving,asquicklyaspossible,tothe
endofthechainandfreelocations tothebeginningofthechain.
Foranemptyexpansionconfiguration,theamountoftimeittakesforORof
thelastFIFOinthechaintogoLOW(i.e.validdatatoappearonthelastFIFO's
54
FEBRUARY10,2009
ORDERINGINFORMATION
XXXXX
X
XX
X
X
X
Process /
Temperature
Range
Device Type
Power
Speed
Package
BLANK
I(1)
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
G(2)
Green
BB
BB
Plastic Ball Grid Array, PBGA BB144-1 (72T1845/55/65/75/85/95 Only)
Plastic Ball Grid Array, PBGA BB240-1 (72T18105/115/125 Only)
4-4
5
Commercial Only
Commercial and Industrial
Commercial Only
Clock Cycle Time (tCLK
Speed in Nanoseconds
)
6-7
10(3)
Commercial Only
Low Power
L
72T1845
72T1855
72T1865
72T1875
72T1885
72T1895
2,048 x 18/4,096 x 9 ⎯ 2.5V TeraSync™ FIFO
4,096 x 18/8,192 x 9 ⎯ 2.5V TeraSync™ FIFO
8,192 x 18/16,384 x 9 ⎯ 2.5V TeraSync™ FIFO
16,384 x 18/32,768 x 9 ⎯ 2.5V TeraSync™ FIFO
32,768 x 18/65,536 x 9 ⎯ 2.5V TeraSync™ FIFO
65,536 x 18/131,072 x 9 ⎯ 2.5V TeraSync™ FIFO
72T18105 131,072 x 18/262,144 x 9 ⎯ 2.5V TeraSync™ FIFO
72T18115 262,144 x 18/524,288 x 9 ⎯ 2.5V TeraSync™ FIFO
72T18125 524,288 x 18/1,048,576 x 9 ⎯ 2.5V TeraSync™ FIFO
5909 drw42
NOTES:
1. Industrial temperature range product for 5ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Green parts available. For specific speeds and packages contact your sales office.
3. Available for IDT72T18105/72T18115/72T18125 only.
DATASHEETDOCUMENTHISTORY
05/30/2001
07/09/2001
10/17/2001
11/19/2001
11/29/2001
01/15/2002
03/04/2002
06/05/2002
06/27/2002
02/11/2003
03/03/2003
09/02/2003
01/11/2007
02/10/2009
pg. 18.
pgs. 1, 7, 8, 19, and 50.
pgs. 1-6, 8, 10, 11, 13-20, 23, 24, 26, 27, 29, 34, 35, 36, 38-43, 49-51.
pgs. 1, 9, 12, 38, and 39.
pgs. 1, 38, and 39.
pg. 40.
pgs. 9, 10, 17, and 27.
pgs. 9, 10, and 14.
pg. 20.
pgs. 8, 9, and 31.
pgs. 1, 11-13, 29, and 31-33.
pgs. 7, 17, and 25.
pgs. 1, 12, 13, and 55.
pg. 55.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-360-1753
email:FIFOhelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
55
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SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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