72T36125L5BBI_技术文档

2.5 VOLT HIGH-SPEED TeraSync^TMFIFO 36-BIT CONFIGURATIONS

IDT72T36105

IDT72T36115

IDT72T36125

65,536 x 36

131,072 x 36

262,144 x 36

FEATURES:

• User selectable input and output port bus-sizing

• Choose among the following memory organizations:

- x36 in to x36 out

- x36 in to x18 out

- x36 in to x9 out

- x18 in to x36 out

- x9 in to x36 out

• Big-Endian/Little-Endian user selectable byte representation

• Auto power down minimizes standby power consumption

• Master Reset clears entire FIFO

• Partial Reset clears data, but retains programmable settings

• Empty, Full and Half-Full flags signal FIFO status

• Select IDT Standard timing (using EF and FF flags) or First Word

Fall Through timing (using OR and IR flags)

• Output enable puts data outputs into high impedance state

• JTAG port, provided for Boundary Scan function

• Available in 240-pin (19mm x 19mm) Plastic Ball Grid Array (PBGA)

• Easily expandable in depth and width

IDT72T36105

IDT72T36115

IDT72T36125

⎯

65,536 x 36

131,072 x 36

262,144 x 36

• Up to 225 MHz Operation of Clocks

• User selectable HSTL/LVTTL Input and/or Output

• 2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage

• 3.3V Input tolerant

• Read Enable & Read Clock Echo outputs aid high speed operation

• User selectable Asynchronous read and/or write port timing

• Mark & Retransmit, resets read pointer to user marked position

• Write Chip Select (WCS) input enables/disables Write operations

• Read Chip Select (RCS) synchronous to RCLK

• Programmable Almost-Empty and Almost-Full flags, each flag can

default to one of eight preselected offsets

• Independent Read and Write Clocks (permit reading and writing

simultaneously)

• High-performance submicron CMOS technology

• Industrial temperature range (–40°C to +85°C) is available

• Green parts are available, see ordering information

• Program programmable flags by either serial or parallel means

• Selectable synchronous/asynchronous timing modes for Almost-

Empty and Almost-Full flags

• Separate SCLK input for Serial programming of flag offsets

FUNCTIONALBLOCKDIAGRAM

D0 - Dn (x36, x18 or x9)

LD SEN

SCL K

WEN

WCL K / WR

WCS

INPUT REGISTER

OF F SET REGISTER

FF/IR

PAF

EF/OR

PAE

HF

F WF T/SI

PF M

WRI TE CON TROL

LOGIC

ASYW

F LAG

LOGIC

RAM ARRAY

WRITE POINTER

65,536 x 36

131,072 x36

262,144 x 36

F SEL0

F SEL1

BE

CONTROL

LOGIC

REA D P OI N TER

IP

BM

IW

OW

BUS

CONF IGURATION

RT

REA D

CONTROL

LOGIC

MARK

ASYR

MRS

PRS

OUTPUT REGISTER

RESET

LOGIC

TCK

TRST

TMS

TDO

RCL K / RD

REN

JTAGCONTROL

(BOUNDARY SCAN)

RCS

TDI

Vr ef

WHSTL

RHSTL

SHSTL

HSTL I/0

CONTROL

EREN

OE

5907 dr w01

Q0 - Qn (x36, x18 or x9)

ERCL K

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology, Inc. TheTeraSyncFIFOisatrademarkofIntegratedDeviceTechnology, Inc.

JUNE 2017

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

1

©

DSC-5907/21

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PINCONFIGURATION

A1 BALL PAD CORNER

A

B

C

D

E

F

V

CC

V

DDQ

V

DDQ

V

DDQ

VDDQ

V

CC

V

CC

V

CC

V

CC

V

CC

WCLK

WEN

GND

RCLK

V

DDQ

PRS

MRS

LD

FF

PAF

HF

EREN

EF

OE

V

DDQ

VDDQ

CC

REN

RCS

RT

CC

MARK

V

DDQ

V

DDQ

V

DDQ

VDDQ

WCS

PAE

IP

GND

OW

RHSTL

CC

CC FWFT/SI

FS0

SHSTL

FS1

BM

PFM

GND

V

DDQ

V

DDQ

BE

ASYR

CC

GND

V

DDQ

V

CC

G

H

J

DDQ

V

CC

SCLK WHSTL

V

DDQ

V

DDQ

SEN

V

CC

VCC

V

CC

GND

V

DDQ

V

DDQ

V

DDQ

ASYW

GND

V

CC

V

CC

V

CC

VREF

VDDQ

K

L

V

IW

V

DDQ

V

DDQ

D33

D30

D27

D24

D34

D31

D28

D25

D22

D20

D17

D35

D32

GND

V

DDQ

Q35

Q32

Q29

Q26

Q34

Q31

Q28

Q25

M

N

P

R

T

Q33

Q30

Q27

D29

D26

GND

Q2

GND

Q3

GND

Q8

D21

D19

D23

D13

GND

D10

D11

GND

D5

GND

D4

GND

D1

GND

TMS

GND

TDO

TDI

GND

Q0

GND

Q11

Q24

Q14

Q15

Q23

Q21

Q22

Q20

Q19

U

V

D18

D14

D7

D8

D2

Q1

Q6

Q5

Q9

Q12

Q18

TRST

V

CC

D16

D15

D0

ERCLK

Q4

Q7

Q10

Q13

Q17

V

DDQ

D12

D9

D6

D3

TCK

GND

Q16

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

5907 drw02A

PBGA: 1mm pitch, 19mm x 19mm BB240, BBG240 (Order code: BB, BBG)

TOP VIEW

2

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear

onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread

operation,whichconsistsofactivatingRENandenablingarisingRCLKedge,

willshiftthewordfrominternalmemorytothedataoutputlines.

InFWFTmode,thefirstwordwrittentoanemptyFIFOisclockeddirectly

tothedataoutputlinesafterthreetransitionsoftheRCLKsignal.ARENdoes

not have to be asserted for accessing the first word. However, subsequent

wordswrittentotheFIFOdorequireaLOWonRENforaccess. Thestateof

theFWFT/SIinputduringMasterResetdeterminesthetimingmodeinuse.

ForapplicationsrequiringmoredatastoragecapacitythanasingleFIFO

canprovide,theFWFTtimingmodepermitsdepthexpansionbychainingFIFOs

inseries(i.e.thedataoutputsofoneFIFOareconnectedtothecorresponding

data inputs of the next). No external logic is required.

DESCRIPTION:

The IDT72T36105/72T36115/72T36125 are exceptionally deep,

extrememly high speed, CMOS First-In-First-Out (FIFO) memories with

clockedreadandwritecontrolsandaflexibleBus-Matchingx36/x18/x9data

flow. These FIFOs offer several key user benefits:

• Flexible x36/x18/x9 Bus-Matching on both read and write ports

• AuserselectableMARKlocationforretransmit

• User selectable I/O structure for HSTL or LVTTL

• Asynchronous/Synchronoustranslationonthereadorwriteports

• Thefirstworddatalatencyperiod,fromthetimethefirstwordiswrittentoan

empty FIFO to the time it can be read, is fixed and short.

• Highdensityofferingsupto9Mbit

Bus-Matching TeraSync FIFOs are particularly appropriate for network,

video,telecommunications,datacommunicationsandotherapplicationsthat

needtobufferlargeamountsofdataandmatchbussesofunequalsizes.

Each FIFO has a data input port (Dn) and a data output port (Qn), both of

whichcanassumeeithera36-bit, 18-bitora9-bitwidthasdeterminedbythe

stateofexternalcontrolpinsInputWidth(IW), OutputWidth(OW), andBus-

Matching(BM)pinduringtheMasterResetcycle.

TheinputportcanbeselectedaseitheraSynchronous(clocked)interface,

or Asynchronous interface. During Synchronous operation the input port is

controlledbyaWriteClock(WCLK)inputandaWriteEnable(WEN)input. Data

present on the Dn data inputsiswritten into the FIFOon everyrising edge of

WCLKwhenWENisasserted.DuringAsynchronousoperationonlytheWR

inputisusedtowritedataintotheFIFO.DataiswrittenonarisingedgeofWR,

theWENinputshouldbetiedtoitsactivestate,(LOW).

TheoutputportcanbeselectedaseitheraSynchronous(clocked)interface,

orAsynchronousinterface.DuringSynchronousoperationtheoutputportis

controlledbyaReadClock(RCLK)inputandReadEnable(REN)input. Data

is read from the FIFO on every rising edge of RCLK when REN is asserted.

DuringAsynchronousoperationonlytheRDinputisusedtoreaddatafromthe

FIFO. DataisreadonarisingedgeofRD, the RENinputshouldbetiedtoits

activestate,LOW.WhenAsynchronousoperationisselectedontheoutputport

theFIFOmustbeconfiguredforStandardIDTmode,alsotheRCSshouldbe

tiedLOWandtheOEinputusedtoprovidethree-statecontroloftheoutputs,Qn.

Theoutputportcanbeselectedforeither2.5VLVTTLorHSTLoperation,

thisoperationisselectedbythestateoftheRHSTLinputduringamasterreset.

AnOutputEnable(OE)inputisprovidedforthree-statecontroloftheoutputs.

AReadChipSelect(RCS)inputisalsoprovided,theRCSinputissynchronized

tothereadclock,andalsoprovidesthree-statecontroloftheQndataoutputs.

When RCS is disabled, the data outputs will be high impedance. During

Asynchronousoperationoftheoutputport,RCSshouldbeenabled,heldLOW.

Echo Read Enable, EREN and Echo Read Clock, ERCLK outputs are

provided. TheseareoutputsfromthereadportoftheFIFOthatarerequired

forhighspeeddatacommunication,toprovidetightersynchronizationbetween

thedatabeingtransmittedfromtheQnoutputsandthedatabeingreceivedby

theinputdevice.Datareadfromthereadportisavailableontheoutputbuswith

respect to EREN and ERCLK, this is very useful when data is being read at

highspeed.TheERCLKandERENoutputsarenon-functionalwhentheRead

portissetupforAsynchronousmode.

These FIFOs have five flag pins, EF/OR (Empty Flag or Output Ready),

FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable

Almost-Emptyflag)andPAF(ProgrammableAlmost-Fullflag). TheEFandFF

functions are selected in IDT Standard mode. The IR and OR functions are

selected in FWFT mode. HF, PAE and PAF are always available for use,

irrespectiveoftimingmode.

PAEandPAFcanbeprogrammedindependentlytoswitchatanypointin

memory. Programmableoffsetsdeterminetheflagswitchingthresholdandcan

beloadedbytwomethods:parallelorserial. Eightdefaultoffsetsettingsarealso

provided,sothatPAEcanbesettoswitchatapredefinednumberoflocations

from the empty boundary and the PAF threshold can also be set at similar

predefinedvaluesfromthefullboundary. Thedefaultoffsetvaluesaresetduring

Master Reset by the state of the FSEL0, FSEL1, and LD pins.

For serial programming, SEN together with LD on each rising edge of

SCLK,areusedtoloadtheoffsetregistersviatheSerialInput(SI). Forparallel

programming,WENtogetherwithLDoneachrisingedgeofWCLK,areused

toloadtheoffsetregistersviaDn. RENtogetherwithLDoneachrisingedge

ofRCLKcanbeusedtoreadtheoffsetsinparallelfromQnregardlessofwhether

serialorparalleloffsetloadinghasbeenselected.

DuringMasterReset(MRS)thefollowingeventsoccur: thereadandwrite

pointers are set to the first location of the FIFO. The FWFT pin selects IDT

Standard mode or FWFT mode.

The Partial Reset (PRS) also sets the read and write pointers to the first

location of the memory. However, the timing mode, programmable flag

programmingmethod,anddefaultorprogrammedoffsetsettingsexistingbefore

PartialResetremainunchanged.Theflagsareupdatedaccordingtothetiming

modeandoffsetsineffect. PRSisusefulforresettingadeviceinmid-operation,

whenreprogrammingprogrammableflagswouldbeundesirable.

ItisalsopossibletoselectthetimingmodeofthePAE(ProgrammableAlmost-

Empty flag) and PAF (Programmable Almost-Full flag) outputs. The timing

modescanbesettobeeitherasynchronousorsynchronousforthePAEand

PAFflags.

IfasynchronousPAE/PAFconfigurationisselected, thePAEisasserted

LOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGHontheLOW-

to-HIGHtransitionofWCLK.Similarly,thePAFisassertedLOWontheLOW-

to-HIGH transition of WCLK and PAF is reset to HIGH on the LOW-to-HIGH

transitionofRCLK.

IfsynchronousPAE/PAFconfigurationisselected,thePAEisassertedand

updated on the rising edge of RCLK only and not WCLK. Similarly, PAF is

assertedandupdatedontherisingedgeofWCLKonlyandnotRCLK.Themode

desiredisconfiguredduringMasterResetbythestateoftheProgrammableFlag

Mode (PFM) pin.

ThefrequenciesofboththeRCLKandtheWCLKsignalsmayvaryfrom0

tofMAXwithcompleteindependence. Therearenorestrictionsonthefrequency

oftheoneclockinputwithrespecttotheother.

Therearetwopossibletimingmodesofoperationwiththesedevices:IDT

Standard mode and First Word Fall Through (FWFT) mode.

3

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

andD32,D33,D34andD35areignored. IPmodeisselectedduring Master

ResetbythestateoftheIPinputpin.

DESCRIPTION (CONTINUED)

ThisdeviceincludesaRetransmitfromMarkfeaturethatutilizestwocontrol

inputs,MARKand,RT(Retransmit).IftheMARKinputisenabledwithrespect

totheRCLK,thememorylocationbeingreadatthatpointwillbemarked.Any

subsequentretransmitoperation,RTgoesLOW,willresetthereadpointerto

this‘marked’location.

If,atanytime,theFIFOisnotactivelyperforminganoperation,thechipwill

automaticallypowerdown.Onceinthepowerdownstate,thestandbysupply

currentconsumptionisminimized. Initiatinganyoperation(byactivatingcontrol

inputs)willimmediatelytakethedeviceoutofthepowerdownstate.

Both an Asynchronous Output Enable pin (OE) and Synchronous Read

ChipSelectpin(RCS)areprovidedontheFIFO.TheSynchronousReadChip

SelectissynchronizedtotheRCLK.Boththeoutputenableandreadchipselect

control the output buffer of the FIFO, causing the buffer to be either HIGH

impedanceorLOWimpedance.

AJTAGtestportisprovided,heretheFIFOhasfullyfunctionalBoundary

Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and

BoundaryScanArchitecture.

TheTeraSyncFIFOhasthecapabilityofoperatingitsports(writeand/or

read)ineitherLVTTLorHSTLmode,eachportsselectionindependentofthe

other.ThewriteportselectionismadeviaWHSTLandthereadportselection

via RHSTL. An additional input SHSTL is also provided, this allows the user

toselectHSTLoperationforotherpinsonthedevice(notassociatedwiththe

write or read ports).

Thedevicecanbeconfiguredwithdifferentinputandoutputbuswidthsas

shown in Table 1.

ABig-Endian/Little-Endiandatawordformatisprovided. Thisfunctionis

usefulwhendataiswrittenintotheFIFOinlongwordformat(x36/x18)andread

outoftheFIFOinsmallword(x18/x9)format.IfBig-Endianmodeisselected,

thenthemostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwill

bereadoutoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endian

formatisselected,thentheleastsignificantbyteofthelongwordwrittenintothe

FIFOwillbereadoutfirst,followedbythemostsignificantbyte.Themodedesired

isconfiguredduringmasterresetbythestateoftheBig-Endian(BE)pin.See

Figure 5 for Bus-Matching Byte Arrangement.

TheInterspersed/Non-InterspersedParity(IP)bitfunctionallowstheuser

to select the parity bit in the word loaded into the parallel port (D0-Dn) when

programmingtheflagoffsets.IfInterspersedParitymodeisselected,thenthe

FIFOwillassumethattheparitybitislocatedinbitpositionsD8,D17,D26and

D35duringtheparallelprogrammingoftheflagoffsets. IfNon-Interspersed

Parity mode is selected, then D8, D17 and D26 are assumed to be valid bits

TheIDT72T36105/72T36115/72T36125arefabricatedusinghighspeed

submicronCMOStechnology.

4

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PARTIAL RESET (PRS) MASTER RESET (MRS)

WRITE CLOCK (WCLK/WR)

READ CLOCK (RCLK/RD)

WRITE ENABLE (WEN)

READ ENABLE (REN)

OUTPUT ENABLE (OE)

WRITE CHIP SELECT (WCS)

LOAD (LD)

READ CHIP SELECT (RCS)

IDT

72T36105

72T36115

72T36125

(x36, x18, x9) DATA IN (D

0

- D

n

)

(x36, x18, x9) DATA OUT (Q0 - Qn)

RCLK ECHO, ERCLK

REN ECHO, EREN

MARK

SERIAL CLOCK (SCLK)

SERIAL ENABLE(SEN)

FIRST WORD FALL

THROUGH/

RETRANSMIT (RT)

SERIAL INPUT (FWFT/SI)

EMPTY FLAG/OUTPUT READY (EF/OR)

PROGRAMMABLE ALMOST-EMPTY (PAE)

HALF-FULL FLAG (HF)

FULL FLAG/INPUT READY (FF/IR)

PROGRAMMABLE ALMOST-FULL (PAF)

BIG-ENDIAN/LITTLE-ENDIAN (BE)

INTERSPERSED/

NON-INTERSPERSED PARITY (IP)

5907 drw03

OUTPUT WIDTH (OW)

INPUT WIDTH (IW)

BUS-

MATCHING

(BM)

Figure 1. Single Device Configuration Signal Flow Diagram

TABLE 1 — BUS-MATCHING CONFIGURATION MODES

BM

IW

OW

Write Port Width

Read Port Width

L

H

L

x36

x18

x9

x36

x18

x9

L

H

L

H

x36

H

NOTE:

1. Pin status during Master Reset.

5

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PINDESCRIPTION

Symbol

Name

I/O TYPE

Description

(1)

ASYR Asynchronous

LVTTL

INPUT

AHIGHonthisinputduringMasterResetwillselectSynchronousreadoperationfortheoutputport.ALOW

willselectAsynchronousoperation.IfAsynchronousisselectedtheFIFOmustoperateinIDTStandardmode.

Read Port

(1)

ASYW Asynchronous

LVTTL

INPUT

AHIGHonthisinputduringMasterResetwillselectSynchronouswriteoperationfortheinputport.ALOW

willselectAsynchronousoperation.

WritePort

(1)

BE

Big-Endian/

Little-Endian

LVTTL

INPUT

During Master Reset, a LOW on BE will select Big-Endian operation. A HIGH on BE during Master Reset

willselectLittle-Endianformat.

BM⁽¹⁾

Bus-Matching

LVTTL

INPUT

BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size

configuration.

D0–D35 DataInputs

HSTL-LVTTL Datainputsfora36-,18-or9-bitbus.Whenin18-or9-bitmode,theunusedinputpinsshouldbetiedtoGND.

INPUT

EF/OR EmptyFlag/

HSTL-LVTTL IntheIDTStandardmode,theEFfunctionisselected.EFindicateswhetherornottheFIFOmemoryisempty.

OUTPUT InFWFTmode, theORfunctionisselected. ORindicateswhetherornotthereisvaliddataavailableatthe

outputs.

OutputReady

ERCLK RCLK Echo

HSTL-LVTTL Read clock Echo output, only available when the Read is setup for Synchronous mode.

OUTPUT

EREN Read Enable Echo HSTL-LVTTL Read Enable Echo output, only available when the Read is setup for Synchronous mode.

OUTPUT

FF/IR

Full Flag/

Input Ready

HSTL-LVTTL In the IDT Standard mode, the FF function is selected. FF indicates whether or not the FIFO memory is

OUTPUT full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for

writingtotheFIFOmemory.

FSEL0⁽¹⁾FlagSelectBit0

FSEL1⁽¹⁾FlagSelectBit1

FWFT/ FirstWordFall

LVTTL

INPUT

DuringMasterReset,thisinputalongwithFSEL1andtheLDpin,willselectthedefaultoffsetvaluesforthe

programmableflagsPAE andPAF. Thereareuptoeightpossiblesettingsavailable.

DuringMasterReset,thisinputalongwithFSEL0andtheLDpinwillselectthedefaultoffsetvaluesforthe

programmableflagsPAE andPAF. Thereareuptoeightpossiblesettingsavailable.

LVTTL

INPUT

HSTL-LVTTL During MasterReset, selectsFirstWordFallThroughorIDTStandardmode. AfterMasterReset, thispin

SI

Through/Serial In

Half-FullFlag

InterspersedParity

InputWidth

INPUT

functionsasaserialinputforloadingoffsetregisters.IfAsynchronousoperationofthereadporthasbeen

selectedthentheFIFOmustbeset-upinIDTStandardmode.

HF

IP⁽¹⁾

IW⁽¹⁾

LD

HSTL-LVTTL HFindicateswhethertheFIFOmemoryismoreorlessthanhalf-full.

OUTPUT

LVTTL

INPUT

DuringMasterReset,aLOWonIPwillselectNon-InterspersedParitymode.AHIGHwillselectInterspersed

Paritymode.

LVTTL

INPUT

Thispin,alongwithOWandBM,selectsthebuswidthofthewriteport.SeeTable1forbussizeconfiguration.

Load

HSTL-LVTTL This is a dual purpose pin. During Master Reset, the state of the LD input along with FSEL0 and FSEL1,

INPUT

determinesoneofeightdefaultoffsetvaluesforthePAEandPAFflags,alongwiththemethodbywhichthese

offsetregisterscanbeprogrammed,parallelorserial(seeTable2).AfterMasterReset,thispinenableswriting

to and reading from the offset registers.THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE

OR READ DATA TO/FROM THE FIFO MEMORY.

MARK MarkforRetransmit HSTL-LVTTL Whenthispinisassertedthecurrentlocationofthereadpointerwillbemarked.AnysubsequentRetransmit

INPUT operationwillresetthereadpointertothisposition.

MRS

MasterReset

HSTL-LVTTL MRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes. DuringMaster

INPUT

Reset,theFIFOisconfiguredforeitherFWFTorIDTStandardmode,Bus-Matchingconfigurations,

Synchronous/Asynchronousoperationofthereadorwriteport,oneofeightprogrammableflagdefaultsettings,

serialorparallelprogrammingoftheoffsetsettings,Big-Endian/Little-Endianformat,zerolatencytimingmode,

interspersedparity,andsynchronousversusasynchronousprogrammableflagtimingmodes.

OE

OutputEnable

OutputWidth

HSTL-LVTTL OEprovidesAsynchronousthree-statecontrolofthedataoutputs,Qn. DuringaMasterorPartialResetthe

INPUT

OEinputistheonlyinputthatprovideHigh-Impedancecontrolofthedataoutputs.

OW⁽¹⁾

PAE

PAF

LVTTL

INPUT

Thispin,alongwithIWandBM,selectsthebuswidthofthereadport.SeeTable1forbussizeconfiguration.

Programmable

Almost-EmptyFlag

HSTL-LVTTL PAEgoesLOWifthenumberofwordsintheFIFOmemoryislessthanoffsetn,whichisstoredintheEmpty

OUTPUT Offsetregister.PAEgoesHIGHifthenumberofwordsintheFIFOmemoryisgreaterthanorequaltooffsetn.

HSTL-LVTTL PAFgoesHIGHifthenumberoffreelocationsintheFIFOmemoryismorethanoffsetm,whichisstoredinthe

OUTPUT FullOffsetregister.PAFgoesLOWifthenumberoffreelocationsintheFIFOmemoryislessthanorequaltom.

Programmable

Almost-FullFlag

PFM⁽¹⁾Programmable

LVTTL

INPUT

DuringMasterReset,aLOWonPFMwillselectAsynchronousProgrammableflagtimingmode.AHIGHon

PFMwillselectSynchronousProgrammableflagtimingmode.

Flag Mode

6

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PINDESCRIPTION(CONTINUED)

Symbol

Name

I/O TYPE

Description

PRS

PartialReset

HSTL-LVTTL PRSinitializesthereadandwritepointerstozeroandsetstheoutputregistertoallzeroes.DuringPartialReset,

INPUT

theexistingmode(IDTorFWFT),programmingmethod(serialorparallel),andprogrammableflagsettings

are all retained.

Q0–Q35 DataOutputs

RCLK/ ReadClock/

HSTL-LVTTL Data outputs for an 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, any unused output pins should not

OUTPUT be connected.Outputsarenot5VtolerantregardlessofthestateofOEandRCS.

HSTL-LVTTL IfSynchronousoperationofthereadporthasbeenselected,whenenabledbyREN,therisingedgeofRCLK

RD

ReadStobe

INPUT

readsdatafromtheFIFOmemoryandoffsetsfromtheprogrammableregisters.IfLDisLOW,thevalues

loadedintotheoffsetregistersisoutputonarisingedgeofRCLK.IfAsynchronousoperationoftheread

port has been selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner. REN

shouldbetiedLOW.

RCS

REN

ReadChipSelect HSTL-LVTTL RCSprovidessynchronouscontrolofthereadportandoutputimpedanceofQn,synchronoustoRCLK.During

INPUT

aMasterResetorPartialResettheRCSinputisdon’tcare,ifOEisLOWthedataoutputswillbeLow-Impedance

regardless of RCS.

Read Enable

HSTL-LVTTL IfSynchronousoperationofthereadporthasbeenselected, RENenablesRCLKforreadingdatafromthe

INPUT

FIFOmemoryandoffsetregisters. IfAsynchronousoperationofthereadporthasbeenselected, the REN

inputshouldbetiedLOW.

RHSTL⁽¹⁾Read Port HSTL

Select

LVTTL

INPUT

This pin is used to select HSTL or 2.5v LVTTL outputs for the FIFO. If HSTL or eHSTL outputs are

required,thisinputmustbetiedHIGH.OtherwiseitshouldbetiedLOW.

RT

Retransmit

HSTL-LVTTL RTassertedontherisingedgeofRCLKinitializestheREADpointertozero,setstheEFflagtoLOW(ORto

INPUT

HIGHinFWFTmode)anddoesn’tdisturbthewritepointer,programmingmethod,existingtimingmode

orprogrammableflagsettings.IfamarkhasbeensetviatheMARKinputpin,thenthereadpointerwilljump

tothe‘mark’location.

SCLK SerialClock

SEN SerialEnable

HSTL-LVTTL ArisingedgeonSCLKwillclocktheserialdatapresentontheSIinputintotheoffsetregistersprovidingthat

INPUT SEN is enabled.

HSTL-LVTTL SENenablesserialloadingofprogrammableflagoffsets.

INPUT

SHSTL SystemHSTL

Select

LVTTL

INPUT

AllinputsnotassociatedwiththewriteorreadportcanbeselectedforHSTLoperationviatheSHSTLinput.

TCK⁽²⁾JTAGClock

HSTL-LVTTL ClockinputforJTAGfunction.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.Testoperations

INPUT

ofthedevicearesynchronoustoTCK. DatafromTMSandTDIaresampledontherisingedgeofTCKand

outputschangeonthefallingedgeofTCK.IftheJTAGfunctionisnotusedthissignalneedstobetiedtoGND.

TDI⁽²⁾

JTAGTestData

Input

HSTL-LVTTL OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,

INPUT

testdataseriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstructionRegister, IDRegister

andBypassRegister.Aninternalpull-upresistorforcesTDIHIGHifleftunconnected.

TDO⁽²⁾JTAGTestData

Output

HSTL-LVTTL OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.DuringtheJTAGboundaryscanoperation,

OUTPUT testdataseriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeithertheInstructionRegister,ID

RegisterandBypassRegister.Thisoutputishighimpedanceexceptwhenshifting,whileinSHIFT-DRand

SHIFT-IRcontrollerstates.

TMS⁽²⁾JTAGMode

Select

HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the

INPUT

thedevicethroughitsTAPcontrollerstates.Aninternalpull-upresistorforcesTMSHIGHifleftunconnected.

(2)

TRST JTAGReset

HSTL-LVTTL TRSTisanasynchronousresetpinfortheJTAGcontroller.TheJTAGTAPcontrollerdoesnotautomatically

INPUT

resetuponpower-up,thusitmustberesetbyeitherthissignalorbysettingTMS=HIGHforfiveTCKcycles.

IftheTAPcontrollerisnotproperlyresetthentheFIFOoutputswillalwaysbeinhigh-impedance.IftheJTAG

functionisusedbuttheuserdoesnotwanttouseTRST,thenTRSTcanbetiedwithMRStoensureproper

FIFOoperation. IftheJTAGfunctionisnotusedthenthissignalneedstobetiedtoGND.

WEN

WCS

WriteEnable

HSTL-LVTTL WhenSynchronousoperationofthewriteporthasbeenselected,WENenablesWCLKforwritingdatainto

INPUT

theFIFOmemoryandoffsetregisters.IfAsynchronousoperationofthewriteporthasbeenselected,the

WENinputshouldbetiedLOW.

WriteChipSelect

HSTL-LVTTL The WCS pin can be regarded as a second WEN input, enabling/disabling write operations.

INPUT

WCLK/ WriteClock/

WR WriteStrobe

HSTL-LVTTL IfSynchronousoperationofthewriteporthasbeenselected,whenenabledbyWEN,therisingedgeofWCLK

INPUT

writesdataintotheFIFO.IfAsynchronousoperationofthewriteporthasbeenselected,WRwritesdatainto

the FIFO on a rising edge in an Asynchronous manner, (WEN should be tied to its active state).

7

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PINDESCRIPTION(CONTINUED)

Symbol

Name

I/O TYPE

Description

WHSTL⁽¹⁾WritePortHSTL

Select

LVTTL

INPUT

ThispinisusedtoselectHSTLor2.5VLVTTLinputsfortheFIFO.IfHSTLinputsarerequired,thisinputmust

betiedHIGH.OtherwiseitshouldbetiedLOW.

Vcc

GND

Vref

+2.5v Supply

GroundPin

Reference

Voltage

I

These are Vcc supply inputs and must be connected to the 2.5V supply rail.

These are Ground pins an dmust be connected to the GND rail.

ThisisaVoltageReferenceinputandmustbeconnectedtoavoltageleveldeterminedfromthetable,

“RecommendedDCOperatingConditions”. ThisprovidesthereferencevoltagewhenusingHSTLclass

inputs. IfHSTLclassinputsarenotbeingused, thispinshouldbetiedLOW.

VDDQ

O/PRailVoltage

I

This pin should be tied to the desired voltage rail for providing power to the output drivers.

NOTES:

1. Inputs should not change state after Master Reset.

2. These pins are for the JTAG port. Please refer to Figures 6-8.

8

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

ABSOLUTEMAXIMUMRATINGS

CAPACITANCE(TA = +25°C, f = 1.0MHz)

Parameter⁽¹⁾

Conditions

Max.

10⁽³⁾

Unit

Symbol

Rating

Commercial

Unit

Symbol

VTERM

TerminalVoltage

–0.5 to +3.6⁽²⁾

V

CIN^(2,3)

Input

VIN = 0V

pF

with respect to GND

Capacitance

COUT^(1,2)

Output

Capacitance

VOUT = 0V

10

pF

TSTG

IOUT

StorageTemperature

DCOutputCurrent

–55 to +125

–50 to +50

°C

mA

NOTES:

1. With output deselected, (OE ≥ VIH).

2. Characterized values, not currently tested.

3. CIN for Vref is 20pF.

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. Compliant with JEDEC JESD8-5. VCC terminal only.

RECOMMENDED DC OPERATING CONDITIONS

Symbol

VCC

Parameter

Min.

2.375

0

Typ.

2.5

0

Max.

2.625

0

Unit

V

SupplyVoltage

GND

V

VIH

InputHighVoltage

⎯ LVTTL

⎯ eHSTL

⎯ HSTL

1.7

VREF+0.2

—

3.45

VDDQ+0.3

V

VIL

InputLowVoltage

⎯ LVTTL

⎯ eHSTL

⎯ HSTL

-0.3

—

0.7

VREF-0.2

V

VREF⁽¹⁾

TA

VoltageReferenceInput ⎯ eHSTL

⎯ HSTL

0.8

0.68

0.9

0.75

1.0

0.9

V

OperatingTemperatureCommercial

OperatingTemperatureIndustrial

0

—

70

85

°C

TA

-40

NOTE:

1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.

2. Outputs are not 3.3V tolerant.

9

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

DCELECTRICALCHARACTERISTICS

(Commercial: VCC = 2.5V ± 0.125V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)

Symbol

Parameter

Min.

–10

Max.

10

Unit

μA

ILI

InputLeakageCurrent

ILO

VOH⁽⁵⁾

OutputLeakageCurrent

OutputLogic“1”Voltage,

–10

10

μA

IOH = –8 mA @VDDQ = 2.5V 0.125V (LVTTL)

IOH = –8 mA @VDDQ = 1.8V 0.1V (eHSTL)

IOH = –8 mA @VDDQ = 1.5V 0.1V (HSTL)

VDDQ-0.4

—

V

VOL

OutputLogic“0”Voltage,

IOL = 8 mA @VDDQ = 2.5V 0.125V (LVTTL)

IOL = 8 mA @VDDQ = 1.8V 0.1V (eHSTL)

IOL = 8 mA @VDDQ = 1.5V 0.1V (HSTL)

—

0.4V

V

IDT72T36105/72T36115/72T36125

ICC1^(1,2)

ICC2⁽¹⁾

Active VCC Current (VCC = 2.5V)

I/O = LVTTL

I/O = HSTL

I/O = eHSTL

—

60

90

mA

Standby VCC Current (VCC = 2.5V) I/O = LVTTL

—

20

70

mA

I/O = HSTL

I/O = eHSTL

NOTES:

1. Both WCLK and RCLK toggling at 20MHz. Data inputs toggling at 10MHz. WCS = HIGH, REN or RCS = HIGH.

2. For the IDT72T36105/72T36115/72T36125, typical ICC1 calculation (with data outputs in Low-Impedance):

for LVTTL I/O ICC1 (mA) = 1.3 x fs, fs = WCLK = RCLK frequency (in MHz)

for HSTL or eHSTL I/O ICC1 (mA) = 30 + (1.3 x fs), fs = WCLK = RCLK frequency (in MHz)

3. For all devices, typical IDDQ calculation: with data outputs in High-Impedance: IDDQ (mA) = 0.15 x fs, fs = WCLK = RCLK frequency (in MHz)

with data outputs in Low-Impedance: IDDQ (mA) = (CL x VDDQ x fs x N)/2000

fs = WCLK = RCLK frequency (in MHz), VDDQ = 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL, CL = capacitive load (pf), tA = 25°C,

N = Number of outputs switching.

4. Total Power consumed: PT = (VCC x ICC) + VDDQ x IDDQ).

5. Outputs are not 3.3V tolerant.

10

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

ACELECTRICALCHARACTERISTICS⁽¹⁾—SYNCHRONOUSTIMING

(Commercial: VCC = 2.5V 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V 5%, TA = -40°C to +85°C)

Commercial

Com’l & Ind’l

Commercial

IDT72T36105L4-4 IDT72T36105L5 IDT72T36105L6-7 IDT72T36105L10

IDT72T36115L4-4 IDT72T36115L5 IDT72T36115L6-7 IDT72T36115L10

IDT72T36125L4-4 IDT72T36125L5 IDT72T36125L6-7 IDT72T36125L10

Symbol

fC

Parameter

Clock Cycle Frequency (Synchronous)

DataAccessTime

Min.

—

Max.

225

3.4

—

Min.

—

0.6

5

Max.

200

3.6

—

Min.

—

0.6

6.7

2.8

2.0

0.5

2.0

0.5

2.0

0.5

2.0

0.5

—

100

45

15

5

Max.

150

3.8

—

Min.

Max.

100

4.5

—

Unit

MHz

ns

tA

0.6

4.44

2.0

1.2

0.5

1.2

0.5

1.2

0.5

1.2

0.5

—

0.6

10

4.5

3.0

0.5

3.0

0.5

3.0

0.5

3.0

0.5

—

100

45

15

5

tCLK

Clock Cycle Time

ns

tCLKH

tCLKL

tDS

Clock High Time

—

2.3

1.5

0.5

1.5

0.5

1.5

0.5

1.5

0.5

—

100

45

15

5

—

ns

Clock Low Time

—

ns

DataSetupTime

—

ns

tDH

DataHoldTime

—

ns

tENS

EnableSetupTime

—

ns

tENH

EnableHoldTime

—

ns

tLDS

LoadSetupTime

—

ns

tLDH

LoadHoldTime

—

ns

tWCSS

tWCSH

fS

WCSsetuptime

WCSholdtime

Clock Cycle Frequency (SCLK)

Serial Clock Cycle

—

ns

—

ns

10

—

10

—

MHz

ns

tSCLK

tSCKH

tSCKL

tSDS

100

45

15

5

—

Serial Clock High

—

ns

Serial Clock Low

—

ns

SerialDataInSetup

—

ns

tSDH

Serial Data In Hold

—

ns

tSENS

tSENH

tRS

SerialEnableSetup

5

—

5

—

5

—

5

—

ns

SerialEnableHold

ResetPulseWidth⁽²⁾

5

—

5

—

5

—

5

—

ns

30

15

4

—

30

15

4

—

30

15

4

—

30

15

4

—

ns

tRSS

ResetSetupTime

—

ns

tHRSS

tRSR

HSTLResetSetupTime

ResetRecoveryTime

ResettoFlagandOutputTime

Write Clock to FF or IR

Read Clock to EF or OR

WriteClocktoSynchronousProgrammableAlmost-FullFlag

ReadClocktoSynchronousProgrammableAlmost-EmptyFlag

RCLK to Echo RCLK output

RCLK to Echo REN output

RCLK to Active from High-Z⁽³⁾

RCLK to High-Z⁽³⁾

—

μs

ns

10

—

10

—

4

—

10

—

5

—

10

—

7

—

tRSF

10

12

3.6

4

15

4.5

5

ns

tWFF

tREF

—

3.4

3.8

3.4

—

3.8

4.3

3.8

—

ns

—

tPAFS

tPAES

tERCLK

tCLKEN

tRCSLZ

tRCSHZ

—

ns

—

ns

—

3.6

—

4.5

—

ns

—

ns

—

tSKEW1 Skew time between RCLK and WCLK for EF/OR and FF/IR

tSKEW2 Skew time between RCLK and WCLK for PAE and PAF

3.5

4

—

5

—

6

—

8

—

ns

NOTES:

1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.

2. Pulse widths less than minimum values are not allowed.

3. Values guaranteed by design, not currently tested.

4. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.

11

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

ACELECTRICALCHARACTERISTICS—ASYNCHRONOUSTIMING

(Commercial: VCC = 2.5V 5%, TA = 0°C to +70°C;Industrial: VCC = 2.5V 5%, TA = -40°C to +85°C)

Commercial

Com’l & Ind’l

Commercial

IDT72T36105L4-4 IDT72T36105L5 IDT72T36105L6-7 IDT72T36105L10

IDT72T36115L4-4 IDT72T36115L5 IDT72T36115L6-7 IDT72T36115L10

IDT72T36125L4-4 IDT72T36125L5 IDT72T36125L6-7 IDT72T36125L10

Symbol

fA

Parameter

Cycle Frequency (Asynchronous)

DataAccessTime

Min.

—

0.6

10

4.5

8

Max.

100

8

Min.

—

0.6

12

5

Max.

83

Min.

—

0.6

15

7

Max.

66

Min.

—

0.6

20

8

Max. Unit

50

14

—

14

—

4.5

14

MHz

ns

tAA

10

12

tCYC

tCYH

tCYL

tRPE

tFFA

tEFA

tPAFA

tPAEA

tOLZ

tOE

Cycle Time

—

8

—

Cycle HIGH Time

—

Cycle LOW Time

5

—

7

—

8

Read Pulse after EF HIGH

Clock to Asynchronous FF

Clock to Asynchronous EF

ClocktoAsynchronousProgrammableAlmost-FullFlag

ClocktoAsynchronousProgrammableAlmost-EmptyFlag

OutputEnabletoOutputinLowZ⁽¹⁾

OutputEnabletoOutputValid

OutputEnabletoOutputinHighZ⁽¹⁾

Clock to HF

10

—

0

—

12

—

0

—

14

—

0

—

0

10

12

8

10

12

8

10

12

8

10

12

—

3.4

8

—

3.6

10

—

3.8

12

—

tOHZ

tHF

NOTES:

1. Values guaranteed by design, not currently tested.

2. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.

12

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

HSTL

AC TEST LOADS

1.5V AC TEST CONDITIONS

VDDQ/2

InputPulseLevels

0.25to1.25V

0.4ns

50

Ω

InputRise/FallTimes

InputTimingReferenceLevels

OutputReferenceLevels

0.75

Z0 = 50Ω

I/O

VDDQ/2

5907 drw04

NOTE:

1. VDDQ = 1.5V±.

Figure 2a. AC Test Load

EXTENDEDHSTL

1.8V AC TEST CONDITIONS

6

5

4

3

2

1

InputPulseLevels

0.4 to 1.4V

0.4ns

InputRise/FallTimes

InputTimingReferenceLevels

OutputReferenceLevels

0.9

VDDQ/2

NOTE:

1. VDDQ = 1.8V±.

20 30 50 80 100

200

Capacitance (pF)

5907 drw04a

Figure 2b. Lumped Capacitive Load, Typical Derating

2.5VLVTTL

2.5V AC TEST CONDITIONS

InputPulseLevels

GND to 2.5V

1ns

InputRise/FallTimes

InputTimingReferenceLevels

OutputReferenceLevels

VCC/2

VDDQ/2

NOTE:

1. For LVTTL VCC = VDDQ.

13

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

OUTPUT ENABLE & DISABLE TIMING

Output

Enable

Output

Disable

VIH

OE

VIL

tOE &

tOLZ

tOHZ

V

2

CC

Output

Normally

LOW

V

2

CC

100mV

V

OL

V

OH

Output

Normally

HIGH

VCC

100mV

VCC

2

5907 drw04b

NOTES:

1. REN is HIGH.

2. RCS is LOW.

READ CHIP SELECT ENABLE & DISABLE TIMING

VIH

tENH

RCS

VIL

tENS

RCLK

tRCSHZ

tRCSLZ

Output

Normally

LOW

VCC

2

V

2

CC

100mV

VOL

VOH

Output

Normally

HIGH

VCC

100mV

VCC

2

5907 drw04c

NOTES:

1. REN is HIGH.

2. OE is LOW.

14

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

If the FIFO is full, the first read operation will cause FF to go HIGH.

SubsequentreadoperationswillcausePAFandHFtogoHIGHattheconditions

describedinTable3.Iffurtherreadoperationsoccur,withoutwriteoperations,

PAE will go LOW when there are n words in the FIFO, where n is the empty

offsetvalue.ContinuingreadoperationswillcausetheFIFOtobecomeempty.

WhenthelastwordhasbeenreadfromtheFIFO,theEFwillgoLOWinhibiting

further read operations. REN is ignored when the FIFO is empty.

WhenconfiguredinIDTStandardmode,theEFandFFoutputsaredouble

register-bufferedoutputs.

FUNCTIONALDESCRIPTION

TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH

(FWFT) MODE

The IDT72T36105/72T36115/72T36125 support two different timing

modesofoperation:IDTStandardmodeorFirstWordFallThrough(FWFT)

mode.TheselectionofwhichmodewilloperateisdeterminedduringMaster

Reset, bythestateoftheFWFT/SIinput.

If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode

willbeselected.ThismodeusestheEmptyFlag(EF)toindicatewhetherornot

thereareanywordspresentintheFIFO.ItalsousestheFullFlagfunction(FF)

to indicate whether or not the FIFO has any free space for writing. In IDT

Standard mode, every word read from the FIFO, including the first, must be

requested using the Read Enable (REN) and RCLK.

If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe

selected.ThismodeusesOutputReady(OR)toindicatewhetherornotthere

isvaliddataatthedataoutputs(Qn). ItalsousesInputReady(IR)toindicate

whetherornottheFIFOhasanyfreespaceforwriting.IntheFWFTmode,the

firstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLKrising

edges, REN =LOWisnotnecessary. Subsequentwordsmustbeaccessed

using the Read Enable (REN) and RCLK.

RelevanttimingdiagramsforIDTStandardmodecanbefoundinFigure

11, 12, 13 and 18.

FIRST WORD FALL THROUGH MODE (FWFT)

In this mode, the status flags, IR, PAF, HF, PAE, and OR operate in the

manneroutlinedinTable4.TowritedataintototheFIFO,WENmustbeLOW.

DatapresentedtotheDATAINlineswillbeclockedintotheFIFOonsubsequent

transitionsofWCLK.Afterthefirstwriteisperformed,theOutputReady(OR)

flagwillgoLOW.SubsequentwriteswillcontinuetofilluptheFIFO.PAEwillgo

HIGHaftern + 2wordshavebeenloadedintotheFIFO,wherenistheempty

offsetvalue. Thedefaultsettingforthesevaluesarestatedinthefootnoteof

Table2.Thisparameterisalsouserprogrammable.SeesectiononProgram-

mableFlagOffsetLoading.

Varioussignals,bothinputandoutputsignalsoperatedifferentlydepending

onwhichtimingmodeisineffect.

If one continued to write data into the FIFO, and we assumed no read

operationsweretakingplace,theHFwouldtoggletoLOWoncethe32,770th

wordfortheIDT72T36105,65,538thwordfortheIDT72T36115and131,074th

wordfortheIDT72T36125,respectivelywaswrittenintotheFIFO.Continuing

towritedataintotheFIFOwillcausethePAFtogoLOW.Again,ifnoreadsare

performed,thePAFwillgoLOWafter(65,537-m)writesfortheIDT72T36105,

(131,073-m) writes for the IDT72T36115 and (262,145-m) writes for the

IDT72T36125,wheremisthefulloffsetvalue.Thedefaultsettingforthesevalues

arestatedinthefootnoteofTable2.

WhentheFIFOisfull,theInputReady(IR)flagwillgoHIGH,inhibitingfurther

writeoperations.Ifnoreadsareperformedafterareset,IRwillgoHIGHafter

DwritestotheFIFO. D =65,537writesfortheIDT72T36105,131,073writes

fortheIDT72T36115and262,145writesfortheIDT72T36125,respectively.

NotethattheadditionalwordinFWFTmodeisduetothecapacityofthememory

plusoutputregister.

IftheFIFOisfull, thefirstreadoperationwillcausetheIRflagtogoLOW.

Subsequent read operations will cause the PAF and HF to go HIGH at the

conditionsdescribedinTable4.Iffurtherreadoperationsoccur,withoutwrite

operations,thePAEwillgoLOWwhentherearen+1wordsintheFIFO,where

nistheemptyoffsetvalue.ContinuingreadoperationswillcausetheFIFOto

becomeempty.WhenthelastwordhasbeenreadfromtheFIFO, ORwillgo

HIGHinhibitingfurtherreadoperations.RENisignoredwhentheFIFOisempty.

When configured in FWFT mode, the OR flag output is triple register-

buffered,andtheIRflagoutputisdoubleregister-buffered.

IDT STANDARD MODE

In this mode, the status flags, FF, PAF, HF, PAE, and EF operate in the

manneroutlinedinTable3.TowritedataintototheFIFO,WriteEnable(WEN)

mustbeLOW.DatapresentedtotheDATAINlineswillbeclockedintotheFIFO

on subsequent transitions of the Write Clock (WCLK). After the first write is

performed,theEmptyFlag(EF)willgoHIGH.Subsequentwriteswillcontinue

tofilluptheFIFO.TheProgrammableAlmost-Emptyflag(PAE)willgoHIGH

aftern + 1wordshavebeenloadedintotheFIFO,wherenistheemptyoffset

value.ThedefaultsettingforthesevaluesarestatedinthefootnoteofTable2.

Thisparameterisalsouserprogrammable.SeesectiononProgrammableFlag

OffsetLoading.

If one continued to write data into the FIFO, and we assumed no read

operationsweretakingplace,theHalf-Fullflag(HF)wouldtoggletoLOWonce

the32,769thwordfortheIDT72T36105,65,537thwordfortheIDT72T36115

and 131,073rd word for the IDT72T36125, respectively was written into the

FIFO. Continuing to write data into the FIFO will cause the Programmable

Almost-Fullflag(PAF)togoLOW.Again,ifnoreadsareperformed,thePAF

willgoLOWafter(65,536-m)writesfortheIDT72T36105,(131,072-m)writes

fortheIDT72T36115and(262,144-m)writesfortheIDT72T36125.Theoffset

“m”isthefulloffsetvalue.Thedefaultsettingforthesevaluesarestatedinthe

footnoteofTable2.Thisparameterisalsouserprogrammable.Seesectionon

ProgrammableFlagOffsetLoading.

WhentheFIFOisfull,theFullFlag(FF)willgoLOW,inhibitingfurtherwrite

operations.Ifnoreadsareperformedafterareset,FFwillgoLOWafterDwrites

to the FIFO. D = 65,536 writes for the IDT72T36105, 131,072 writes for the

IDT72T36115 and 262,144 writes for the IDT72T36125, respectively.

RelevanttimingdiagramsforFWFTmodecanbefoundinFigure14, 15,

16 and 19.

15

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PROGRAMMING FLAG OFFSETS

TABLE 2 — DEFAULT PROGRAMMABLE

FullandEmptyFlagoffsetvaluesareuserprogrammable.TheIDT72T36105/

72T36115/72T36125haveinternalregistersfortheseoffsets.Thereareeight

defaultoffsetvaluesselectableduringMasterReset.Theseoffsetvaluesare

showninTable2.OffsetvaluescanalsobeprogrammedintotheFIFOinone

of two ways; serial or parallel loading method. The selection of the loading

methodisdoneusingtheLD(Load)pin.DuringMasterReset,thestateofthe

LD input determines whether serial or parallel flag offset programming is

enabled. A HIGH on LD during Master Reset selects serial loading of offset

values. A LOW on LD during Master Reset selects parallel loading of offset

values.

InadditiontoloadingoffsetvaluesintotheFIFO,itisalsopossibletoread

thecurrentoffsetvalues.Offsetvaluescanbereadviatheparalleloutputport

Q0-Qn,regardlessoftheprogrammingmodeselected(serialorparallel).Itis

notpossibletoreadtheoffsetvaluesinserialfashion.

Figure3,ProgrammableFlagOffsetProgrammingSequence,summaries

thecontrolpinsandsequenceforbothserialandparallelprogrammingmodes.

Foramoredetaileddescription,seediscussionthatfollows.

FLAG OFFSETS

IDT72T36105, 72T36115, 72T36125

*LD

H

L

FSEL1

FSEL0

Offsets n,m

L

H

L

H

L

H

L

H

1,023

511

255

127

63

31

15

7

L

H

L

H

*LD

H

L

FSEL1

FSEL0

Program Mode

Serial⁽³⁾

X

Parallel⁽⁴⁾

*THIS PIN MUST BE HIGH AFTER MASTER RESET TO WRITE

OR READ DATA TO/FROM THE FIFO MEMORY.

The offset registers may be programmed (and reprogrammed) any time

afterMasterReset,regardlessofwhetherserialorparallelprogramminghas

been selected. Valid programming ranges are from 0 to D-1.

NOTES:

1. n = empty offset for PAE.

2. m = full offset for PAF.

SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG

TIMING SELECTION

The IDT72T36105/72T36115/72T36125 can be configured during the

MasterResetcyclewitheithersynchronousorasynchronoustimingforPAF

and PAE flags by use of the PFM pin.

3. As well as selecting serial programming mode, one of the default values will also

be loaded depending on the state of FSEL0 & FSEL1.

4. As well as selecting parallel programming mode, one of the default values will

also be loaded depending on the state of FSEL0 & FSEL1.

If synchronous PAF/PAE configuration is selected (PFM, HIGH during

MRS),thePAFisassertedandupdatedontherisingedgeofWCLKonlyand

notRCLK.Similarly,PAEisassertedandupdatedontherisingedgeofRCLK

onlyandnotWCLK.Fordetailtimingdiagrams,seeFigure23forsynchronous

PAFtimingandFigure24forsynchronousPAE timing.

If asynchronous PAF/PAE configuration is selected (PFM, LOW during

MRS),thePAFisassertedLOWontheLOW-to-HIGHtransitionofWCLKand

PAFisresettoHIGHontheLOW-to-HIGHtransitionofRCLK. Similarly,PAE

isassertedLOWontheLOW-to-HIGHtransitionofRCLK.PAEisresettoHIGH

on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see

Figure25forasynchronousPAFtimingandFigure26forasynchronousPAE

timing.

16

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

TABLE 3 ⎯ STATUS FLAGS FOR IDT STANDARD MODE

IDT72T36105

IDT72T36115

IDT72T36125

FF PAF HF PAE EF

0

H

L

H

L

H

L

1 to n⁽¹⁾

Number of

Words in

FIFO

L

H

(n+1) to 32,768

H

(n+1) to 65,536

(n+1) to 131,072

32,769 to (65,536-(m+1))

65,537 to (131,072-(m+1))

131,073 to (262,144-(m+1))

L

(65,536-m) to 65,535

65,536

(131,072-m) to 131,071

131,072

(262,144-m) to 262,143

262,144

L

NOTE:

1. See table 2 for values for n, m.

TABLE 4 ⎯ STATUS FLAGS FOR FWFT MODE

IDT72T36115

IDT72T36105

IR PAF HF PAE OR

IDT72T36125

0

L

H

L

H

L

H

Number of

Words in

FIFO

1 to n+1

L

H

L

(n+2) to 32,769

(n+2) to 131,073

131,074 to (262,145-(m+1))

(262,145-m) to 262,144

262,145

(n+2) to 65,537

L

32,770 to (65,537-(m+1))

65,538 to (131,073-(m+1))

L

(65,537-m) to 65,536

65,537

(131,073-m) to 131,072

131,073

L

NOTE:

1. See table 2 for values for n, m.

5907 drw05

17

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

IDT72T36105, IDT72T36115

IDT72T36125

WCLK RCLK

SCLK

LD

WEN

REN

SEN

Parallel write to registers:

Empty Offset (LSB)

Empty Offset (MSB)

Full Offset (LSB)

X

0

1

Full Offset (MSB)

Parallel read from registers:

Empty Offset (LSB)

Empty Offset (MSB)

Full Offset (LSB)

X

0

1

0

1

0

X

Full Offset (MSB)

Serial shift into registers:

X

32 bits for the IDT72T36105

34 bits for the IDT72T36115

36 bits for the IDT72T36125

1 bit for each rising SCLK edge

Starting with Empty Offset (LSB)

Ending with Full Offset (MSB)

X

1

No Operation

Write Memory

X

1

0

X

1

X

0

1

X

Read Memory

X

No Operation

5907 drw06

NOTES:

1. The programming method can only be selected at Master Reset.

2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.

3. The programming sequence applies to both IDT Standard and FWFT modes.

Figure 3. Programmable Flag Offset Programming Sequence

18

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

1st Parallel Offset Write/Read Cycle

D/Q35

D/Q19

D/Q17

D/Q0

D/Q8

EMPTY OFFSET REGISTER (PAE)

Non-Interspersed

Parity

18

1

17 16 15 14 13 12 11 10

16 15 14 13 1211 10

9

8

7

6

5

4

3

2

# of Bits Used:

Interspersed

Parity

18 17

9

16 bits for the IDT72T36105

17 bits for the IDT72T36115

18 bits for the IDT72T36125

Note: All unused bits of the

LSB & MSB are don't care

# of Bits Used

2nd Parallel Offset Write/Read Cycle

D/Q19

D/Q17

D/Q0

D/Q8

FULL OFFSET REGISTER (PAF)

Non-Interspersed

Parity

18 17 16 15 14 13 12 11 10

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

Interspersed

Parity

17

9

18

16

# of Bits Used

IDT72T36105/72T36115/72T36125 ⎯ x36 Bus Width

1st Parallel Offset Write/Read Cycle

D/Q17

D/Q16

Data Inputs/Outputs

EMPTY OFFSET (LSB) REGISTER (PAE)

D/Q0

1st Parallel Offset Write/Read Cycle

Non-Interspersed

Parity

D/Q17

Data Inputs/Outputs

16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

D/Q0

D/Q16

Interspersed

Parity

9

EMPTY OFFSET (LSB) REGISTER (PAE)

Non-Interspersed

Parity

D/Q8

# of Bits Used

16 15 14 13 1211 10

13 12 10

9

8

7

6

5

4

3

2

1

2nd Parallel Offset Write/Read Cycle

16

Interspersed

Parity

15 14

11

9

D/Q17

D/Q8

D/Q16

# of Bits Used

Data Inputs/Outputs

D/Q0

EMPTY OFFSET (MSB) REGISTER (PAE)

18

17

18

2nd Parallel Offset Write/Read Cycle

D/Q17

3rd Parallel Offset Write/Read Cycle

D/Q17

Data Inputs/Outputs

D/Q16

D/Q

0

Data Inputs/Outputs

D/Q0

D/Q16

FULL OFFSET (LSB) REGISTER (PAF)

16 15 14

12 11

13

10

9

8

7

6

5

4

3

2

1

16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

16 15

14 13 12 11 10

8

3

9

D/Q8

4th Parallel Offset Write/Read Cycle

D/Q17

D/Q16

FULL OFFSET (MSB) REGISTER (PAF)

Data Inputs/Outputs

D/Q0

18 17

IDT72T36105 ⎯ x18 Bus Width

IDT72T36115/72T36125 ⎯ x18 Bus Width

1st Parallel Offset Write/Read Cycle

D/Q8

1st Parallel Offset Write/Read Cycle

D/Q8

D/Q0

1

D/Q0

EMPTY OFFSET REGISTER (PAE)

8

7

6

5

4

3

2

8

7

6

5

4

3

2

10

18

2

1

2nd Parallel Offset Write/Read Cycle

D/Q8

D/Q0

9

EMPTY OFFSET REGISTER (PAE)

2nd Parallel Offset Write/Read Cycle

D/Q8

16

15 14 13 12 11

D/Q0

9

EMPTY OFFSET REGISTER (PAE)

3rd Parallel Offset Write/Read Cycle

D/Q8

16

15 14 13 12 11

10

D/Q0

17

EMPTY OFFSET REGISTER (PAE)

3rd Parallel Offset Write/Read Cycle

D/Q8

4th Parallel Offset Write/Read Cycle

D/Q8

D/Q0

1

D/Q0

1

FULL OFFSET REGISTER (PAF)

8

7

6

5

4

3

2

8

7

6

5

4

3

5th Parallel Offset Write/Read Cycle

D/Q8

D/Q0

9

FULL OFFSET REGISTER (PAF)

4th Parallel Offset Write/Read Cycle

D/Q8

16

15 14 13 12 11

10

D/Q0

9

FULL OFFSET REGISTER (PAF)

6th Parallel Offset Write/Read Cycle

D/Q8

16

15 14 13 12 11

10

D/Q0

17

FULL OFFSET REGISTER (PAF)

18

IDT72T36105 ⎯ x9 Bus Width

IDT72T36115/72T36125 ⎯ x9 Bus Width

5907 drw07

NOTE:

1. Consecutive reads of the offset registers is not permitted. The read operation must be disabled for a minimum of one RCLK cycle in between offset register accesses. (Please

refer to Figure 22, Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for more details).

Figure 3. Programmable Flag Offset Programming Sequence (Continued)

19

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

SERIAL PROGRAMMING MODE

OffsetRegisterMSB.The5^thLOW-to-HIGHtransitionofWCLKdataontheinputs

IfSerialProgrammingmodehasbeenselected,asdescribedabove,then DnareonceagainwrittenintotheEmptyOffsetRegisterLSB.

programmingofPAEandPAFvaluescanbeachievedbyusingacombination

oftheLD,SEN,SCLKandSIinputpins.ProgrammingPAEandPAFproceeds

When a 9 bit input bus width is used:

FortheIDT72T36105,4enabledwritecyclesarerequiredtoloadtheoffset

asfollows:whenLDandSENaresetLOW,dataontheSIinputarewritten,one registers,(2peroffset).DataontheinputsDnarewrittenintotheEmptyOffset

bitforeachSCLKrisingedge,startingwiththeEmptyOffsetLSBandending RegisterLSBonthefirstLOW-to-HIGHtransitionofWCLK.Uponthe2^ndLOW-

withtheFullOffsetMSB.Atotalof32bitsfortheIDT72T36105,34bitsforthe to-HIGHtransitionofWCLKdataontheinputsDnarewrittenintotheEmptyOffset

IDT72T36115and36bitsfortheIDT72T36125.SeeFigure20,SerialLoading RegisterMSB.Uponthe3^rdLOW-to-HIGHtransitionofWCLKdataontheinputs

ofProgrammableFlagRegisters, forthetimingdiagramforthismode.

Dn are written into the Full Offset Register LSB. Upon the 4^thLOW-to-HIGH

Using the serial method, individual registers cannot be programmed transitionofWCLKdataontheinputsDnarewrittenintotheFullOffsetRegister

selectively.PAEandPAFcanshowavalidstatusonlyafterthecompleteset MSB.The5^thLOW-to-HIGHtransitionofWCLKdataontheinputsDnareonce

of bits (for all offset registers) has been entered. The registers can be againwrittenintotheEmptyOffsetRegisterLSB.

reprogrammedaslongasthecompletesetofnewoffsetbitsisentered.When

LD is LOW and SEN is HIGH, no serial write to the registers can occur.

For the IDT72T36115/72T36125, 6 enabled write cycles are required to

loadtheoffsetregisters,(3peroffset).DataontheinputsDnarewrittenintothe

Write operations to the FIFO are allowed before and during the serial EmptyOffsetRegisterLSBonthefirstLOW-to-HIGHtransitionofWCLK.Upon

programmingsequence. Inthiscase,theprogrammingofalloffsetbitsdoesnot the3^rdLOW-to-HIGHtransitionofWCLKdataontheinputsDnarewritteninto

havetooccuratonce. AselectnumberofbitscanbewrittentotheSIinputand theEmptyOffsetRegisterMSB.Uponthe4^thLOW-to-HIGHtransitionofWCLK

then,bybringingLDandSENHIGH,datacanbewrittentoFIFOmemoryvia dataontheinputsDnarewrittenintotheFullOffsetRegisterLSB.Uponthe6^th

Dn bytogglingWEN. WhenWENisbroughtHIGHwithLDandSENrestored LOW-to-HIGHtransitionofWCLKdataontheinputsDnarewrittenintotheFull

toaLOW,thenextoffsetbitinsequenceiswrittentotheregistersviaSI. Ifan OffsetRegisterMSB.The7^thLOW-to-HIGHtransitionofWCLKdataontheinputs

interruptionofserialprogrammingisdesired,itissufficienteithertosetLDLOW DnareonceagainwrittenintotheEmptyOffsetRegisterLSB. SeeFigure3,

anddeactivateSENortosetSENLOWanddeactivateLD. OnceLDandSEN ProgrammableFlagOffsetProgrammingSequence.SeeFigure21,Parallel

arebothrestoredtoaLOWlevel,serialoffsetprogrammingcontinues.

Fromthetimeserialprogramminghasbegun,neitherprogrammableflag

LoadingofProgrammableFlagRegisters,forthetimingdiagramforthismode.

Theactofwritingoffsetsinparallelemploysadedicatedwriteoffsetregister

willbevaliduntilthefullsetofbitsrequiredtofillalltheoffsetregistershasbeen pointer. The act of reading offsets employs a dedicated read offset register

written. MeasuringfromtherisingSCLKedgethatachievestheabovecriteria; pointer.Thetwopointersoperateindependently;however,areadandawrite

PAFwillbevalidafterthreemorerisingWCLKedgesplustPAF,PAEwillbevalid shouldnotbeperformedsimultaneouslytotheoffsetregisters. AMasterReset

after the next three rising RCLK edges plus tPAE.

ItisonlypossibletoreadtheflagoffsetvaluesviatheparalleloutputportQn. noeffectonthepositionofthesepointers.

Write operations to the FIFO are allowed before and during the parallel

programmingsequence.Inthiscase,theprogrammingofalloffsetregistersdoes

initializesbothpointerstotheEmptyOffset(LSB)register.APartialResethas

PARALLELMODE

IfParallelProgrammingmodehasbeenselected,asdescribedabove,then nothavetooccuratonetime. One,twoormoreoffsetregisterscanbewritten

programmingofPAEandPAFvaluescanbeachievedbyusingacombination andthenbybringingLDHIGH,writeoperationscanberedirectedtotheFIFO

of the LD, WCLK , WEN and Dn input pins. Programming PAE and PAF memory.WhenLDissetLOWagain,andWENisLOW,thenextoffsetregister

proceedsasfollows: LDandWENmustbesetLOW.Whenprogrammingthe insequenceiswrittento.AsanalternativetoholdingWENLOWandtoggling

OffsetRegistersoftheTeraSyncFIFO’sthenumberofprogrammingcycleswill LD, parallel programming can also be interrupted by setting LD LOW and

be based on the bus width, the following rules apply:

togglingWEN.

Notethatthestatusofaprogrammableflag(PAEorPAF)outputisinvalid

When a 36 bit input bus width is used:

For the IDT72T36105/72T36115/72T36125, 2 enabled write cycles are during the programming process. From the time parallel programming has

requiredtoprogramtheoffsetregisters,(1peroffset).DataontheinputsDnare begun,aprogrammableflagoutputwillnotbevaliduntiltheappropriateoffset

writtenintotheEmptyOffsetRegisteronthefirstLOW-to-HIGHtransitionof wordhasbeenwrittentotheregister(s)pertainingtothatflag.Measuringfrom

WCLK.UponthesecondLOW-to-HIGHtransitionofWCLK,dataarewritteninto therisingWCLKedgethatachievestheabovecriteria;PAFwillbevalidafter

theFullOffsetRegister.ThethirdtransitionofWCLKwrites,onceagain,tothe twomorerisingWCLKedgesplustPAF,PAEwillbevalidafterthenexttworising

EmptyOffsetRegister.

RCLK edges plus tPAE plus tSKEW2.

When an 18 bit input bus width is used:

The act of reading the offset registers employs a dedicated read offset

FortheIDT72T36105,2enabledwritecyclesarerequiredtoprogramthe registerpointer. ThecontentsoftheoffsetregisterscanbereadontheQ0-Qn

offsetregisters,(1peroffset).DataontheinputsDnarewrittenintotheEmpty pins when LD is set LOW and REN is set LOW. It is important to note that

OffsetRegisteronthefirstLOW-to-HIGHtransitionofWCLK.Uponthesecond consecutivereadsoftheoffsetregistersisnotpermitted.Thereadoperationmust

LOW-to-HIGHtransitionofWCLK,dataarewrittenintotheFullOffsetRegister. be disabled for a minimum of one RCLK cycle in between offset register

ThethirdtransitionofWCLKwrites,onceagain,totheEmptyOffsetRegister. accesses. When reading the Offset Registers of the TeraSync FIFO’s the

For the IDT72T36115/72T36125, 4 enabled write cycles are required to number of reading cycles will be based on the bus width, the following rules

loadtheoffsetregisters,(2peroffset).DataontheinputsDnarewrittenintothe apply:

EmptyOffsetRegisterLSBonthefirstLOW-to-HIGHtransitionofWCLK.Upon

When a 36 bit output bus width is used:

For the IDT72T36105/72T36115/72T36125, 2 enabled read cycles are

the2^ndLOW-to-HIGHtransitionofWCLKdataontheinputsDnarewritteninto

theEmptyOffsetRegisterMSB.Uponthe3^rdLOW-to-HIGHtransitionofWCLK requiredtoreadtheoffsetregisters,(1peroffset).DataontheoutputsQnare

dataontheinputsDnarewrittenintotheFullOffsetRegisterLSB.Uponthe4^threadfromtheEmptyOffsetRegisteronthefirstLOW-to-HIGHtransitionofRCLK.

LOW-to-HIGHtransitionofWCLKdataontheinputsDnarewrittenintotheFull UponthesecondLOW-to-HIGHtransitionofRCLK,dataarereadfromtheFull

20

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

OffsetRegister.ThethirdtransitionofRCLKreads,onceagain,fromtheEmpty betakenoutofretransmitmodeatanytimetoallownormaldeviceoperation.

OffsetRegister.

The‘mark’positioncanbeselectedanynumberoftimes,eachselectionover-

writingthepreviousmarklocation.RetransmitoperationisavailableinbothIDT

When an 18 bit output bus width is used:

FortheIDT72T36105,2enabledreadcyclesarerequiredtoreadtheoffset standardandFWFTmodes.

registers,(1peroffset).DataontheoutputsQnarereadfromtheEmptyOffset

DuringIDTstandardmodetheFIFOisputintoretransmitmodebyaLow-

RegisteronthefirstLOW-to-HIGHtransitionofRCLK.UponthesecondLOW- to-HightransitiononRCLKwhenthe‘MARK’inputisHIGHandEFisHIGH.

to-HIGHtransitionofRCLK,dataarereadfromtheFullOffsetRegister.Thethird TherisingRCLKedge‘marks’thedatapresentintheFIFOoutputregisteras

transitionofRCLKreads,onceagain,fromtheEmptyOffsetRegister.

thefirstretransmitdata.TheFIFOremainsinretransmitmodeuntilarisingedge

For the IDT72T36115/72T36125, 4 enabled read cycles are required to on RCLK occurs while MARK is LOW.

readtheoffsetregisters, (2peroffset). DataontheoutputsQnarereadfrom

Oncea‘marked’locationhasbeenset(andthedeviceisstillinretransmit

theEmptyOffsetRegisterLSBonthefirstLOW-to-HIGHtransitionofRCLK. mode,MARKisHIGH),aretransmitcanbeinitiatedbyarisingedgeonRCLK

Uponthe2^ndLOW-to-HIGHtransitionofRCLKdataontheoutputsQnareread whiletheretransmitinput(RT)isLOW.RENmustbeHIGH(readsdisabled)

fromtheEmptyOffsetRegisterMSB.Uponthe3^rdLOW-to-HIGHtransitionof beforebringingRTLOW.Thedeviceindicatesthestartofretransmitsetupby

RCLKdataontheoutputsQnarereadfromtheFullOffsetRegisterLSB.Upon settingEFLOW,alsopreventingreads.WhenEFgoesHIGH,retransmitsetup

the4^thLOW-to-HIGHtransitionofRCLKdataontheoutputsQnarereadfrom iscompleteandreadoperationsmaybeginstartingwiththefirstdataattheMARK

theFullOffsetRegisterMSB.The5^thLOW-to-HIGHtransitionofRCLKdataon location.SinceIDTstandardmodeisselected,everywordreadincludingthe

theoutputsQnareonceagainreadfromtheEmptyOffsetRegisterLSB.

When a 9 bit output bus width is used:

first‘marked’wordfollowingaretransmitsetuprequiresaLOWonREN(read

enabled).

For the IDT72T36115/72T36125, 4 enabled read cycles are required to

Note, write operations may continue as normal during all retransmit

readtheoffsetregisters, (2peroffset). DataontheoutputsQnarereadfrom functions,howeverwriteoperationstothe‘marked’locationwillbeprevented.

theEmptyOffsetRegisterLSBonthefirstLOW-to-HIGHtransitionofRCLK. See Figure 18, Retransmit from Mark (IDT standard mode), for the relevant

Uponthe2^ndLOW-to-HIGHtransitionofRCLKdataontheoutputsQnareread timingdiagram.

fromtheEmptyOffsetRegisterMSB.Uponthe3^rdLOW-to-HIGHtransitionof

DuringFWFTmodetheFIFOisputintoretransmitmodebyarisingRCLK

RCLKdataontheoutputsQnarereadfromtheFullOffsetRegisterLSB.Upon edgewhenthe‘MARK’inputisHIGHandORisLOW.TherisingRCLKedge

the4^thLOW-to-HIGHtransitionofRCLKdataontheoutputsQnarereadfrom ‘marks’thedatapresentintheFIFOoutputregisterasthefirstretransmitdata.

theFullOffsetRegisterMSB.The5^thLOW-to-HIGHtransitionofRCLKdataon TheFIFOremainsinretransmitmodeuntilarisingRCLKedgeoccurswhile

theoutputsQnareonceagainreadfromtheEmptyOffsetRegisterLSB.

For the IDT72T36115/72T36125, 6 enabled read cycles are required to

MARKisLOW.

Onceamarkedlocationhasbeenset(andthedeviceisstillinretransmit

readtheoffsetregisters, (3peroffset). DataontheoutputsQnarereadfrom mode,MARKisHIGH),aretransmitcanbeinitiatedbyarisingRCLKedgewhile

theEmptyOffsetRegisterLSBonthefirstLOW-to-HIGHtransitionofRCLK. theretransmitinput(RT)isLOW.RENmustbeHIGH(readsdisabled)before

Uponthe3^rdLOW-to-HIGHtransitionofRCLKdataontheoutputsQnareread bringingRTLOW.Thedeviceindicatesthestartofretransmitsetupbysetting

fromtheEmptyOffsetRegisterMSB.Uponthe4^thLOW-to-HIGHtransitionof OR HIGH.

RCLKdataontheoutputsQnarereadfromtheFullOffsetRegisterLSB.Upon

WhenORgoesLOW,retransmitsetupiscompleteandonthenextrising

the6^thLOW-to-HIGHtransitionofRCLKdataontheoutputsQnarereadfrom RCLKedgeafterretransmitsetupiscomplete,(RTgoesHIGH),thecontents

theFullOffsetRegisterMSB.The7^thLOW-to-HIGHtransitionofRCLKdataon ofthefirstretransmitlocationareloadedontotheoutputregister.SinceFWFT

theoutputsQnareonceagainreadfromtheEmptyOffsetRegisterLSB.See modeisselected,thefirstwordappearsontheoutputsregardlessofREN,a

Figure 3, Programmable Flag Offset Programming Sequence. See Figure LOWonRENisnotrequiredforthefirstword.Readingallsubsequentwords

22, ParallelReadofProgrammableFlagRegisters,forthetimingdiagramfor requires a LOW on REN to enable the rising RCLK edge. See Figure 19,

RetransmitfromMarktiming(FWFTmode),fortherelevanttimingdiagram.

Note,theremustbeaminimumof32bytesofdatabetweenthewritepointer

and read pointer when the MARK is asserted. (32 bytes = 16 word = 8 long

words).Also,oncetheMARKisset,thewritepointerwillnotincrementpastthe

“marked”locationuntiltheMARKisdeasserted.Thisprevents“overwriting”

ofretransmitdata.

thismode.

Itispermissibletointerrupttheoffsetregisterreadsequencewithreadsor

writestotheFIFO. TheinterruptionisaccomplishedbydeassertingREN,LD,

orbothtogether. WhenRENand LDarerestoredtoaLOW level, readingof

theoffsetregisterscontinueswhereitleftoff.Itshouldbenoted,andcareshould

betakenfromthefactthatwhenaparallelreadoftheflagoffsetsisperformed,

the data word that was present on the output lines Qn will be overwritten.

Parallel reading of the offset registers is always permitted regardless of

which timing mode (IDT Standard or FWFT modes) has been selected.

HSTL/LVTTL I/O

Both the write port and read port are user selectable between HSTL or

LVTTL I/O, via two select pins, WHSTL and RHSTL respectively. All other

control pins are selectable via SHSTL, see Table 5 for details of groupings.

Note,thatwhenthewriteportisselectedforHSTLmode,theusercanreduce

thepowerconsumption(instand-bymodebyutilizingtheWCSinput).

All“StaticPins”mustbetiedtoVCC orGND. ThesepinsareLVTTLonly,

and are purely device configuration pins.

RETRANSMIT FROM MARK OPERATION

TheRetransmitfromMarkfeatureallowsFIFOdatatobereadrepeatedly

startingatauser-selectedposition.TheFIFOisfirstputintoretransmitmodethat

will‘mark’abeginningwordandalsosetapointerthatwillpreventongoingFIFO

writeoperationsfromover-writingretransmitdata.Theretransmitdatacanbe

readrepeatedlyanynumberoftimesfromthe‘marked’position.TheFIFOcan

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TEMPERATURE RANGES

TABLE 5 — I/O CONFIGURATION

WHSTL SELECT

RHSTL SELECT

SHSTL SELECT

STATIC PINS

WHSTL: HIGH = HSTL

LOW = LVTTL

RHSTL: HIGH = HSTL

LOW = LVTTL

SHSTL: HIGH = HSTL

LOW = LVTTL

LVTTL ONLY

Dn (I/P)

RCLK/RD (I/P)

RCS (I/P)

MARK (I/P)

REN (I/P)

OE (I/P)

EF/OR (O/P)

SCLK (I/P)

LD (I/P)

MRS (I/P)

TCK (I/P)

TMS (I/P)

SEN (I/P)

FWFT/SI (I/P)

PRS (I/P)

IW (I/P)

BM (I/P)

OW (I/P)

ASYW (I/P)

BE (I/P)

FSEL0 (I/P)

PFM (I/P)

WHSTL (I/P)

WCLK/WR (I/P)

WEN (I/P)

WCS (I/P)

PAF (O/P)

EREN (O/P)

PAE (O/P)

FF/IR (O/P)

HF (O/P)

TRST (I/P)

TDI (I/P)

ASYR (I/P)

IP (I/P)

FSEL1 (I/P)

SHSTL (I/P)

RHSTL (I/P)

RT (I/P)

Qn (O/P)

ERCLK (O/P)

TDO (O/P)

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Asynchronous operation of the read port will be selected. During Asynchro-

nousoperationofthereadporttheRCLKinputbecomesRDinput,thisisthe

Asynchronousreadstrobeinput.ArisingedgeonRDwillreaddatafromthe

FIFO via the output register and Qn port. (REN must be tied LOW during

Asynchronous operation of the read port).

The OE input provides three-state control of the Qn output bus, in an

asynchronousmanner.(RCS,providesthree-statecontrolofthereadportin

Synchronousmode).

WhenthereadportisconfiguredforAsynchronousoperationthedevice

mustbeoperatingonIDTstandardmode,FWFTmodeisnotpermissibleifthe

readportisAsynchronous.TheEmptyFlag(EF)operatesinanAsynchronous

manner,thatis,theemptyflagwillbeupdatedbasedonbothareadoperation

andawriteoperation.Refertofigures32,33,34and35forrelevanttimingand

operationalwaveforms.

SIGNALDESCRIPTION

INPUTS:

DATA IN (D0 - Dn)

Datainputsfor36-bitwidedata(D0 -D35),datainputsfor18-bitwidedata

(D0 - D17) or data inputs for 9-bit wide data (D0 - D8).

CONTROLS:

MASTER RESET ( MRS )

AMasterResetisaccomplishedwhenevertheMRSinputistakentoaLOW

state.Thisoperationsetstheinternalreadandwritepointerstothefirstlocation

oftheRAMarray.PAEwill goLOW, PAFwillgoHIGH,and HFwillgoHIGH.

If FWFT/SI is LOW during Master Reset then the IDT Standard mode,

along with EF and FF are selected. EF will go LOW and FF will go HIGH. If

FWFT/SIisHIGH,thentheFirstWordFallThroughmode(FWFT),alongwith

IR and OR, are selected. OR will go HIGH and IR will go LOW.

AllcontrolsettingssuchasOW,IW,BM,BE,RM,PFMandIParedefined

duringtheMasterResetcycle.

RETRANSMIT (RT)

The Retransmit (RT) input is used in conjunction with the MARK input,

togethertheyprovideameansbywhichdatapreviouslyreadoutoftheFIFO

canberereadanynumberoftimes.Ifretransmitoperationhasbeenselected

(i.e.theMARKinputisHIGH),arisingedgeonRCLKwhileRTisLOWwillreset

thereadpointerbacktothememorylocationsetbytheuserviatheMARKinput.

IfIDTstandardmodehasbeenselectedtheEFflagwillgoLOWandremain

LOW for the time that RT is held LOW. RT can be held LOW for any number

ofRCLKcycles,thereadpointerbeingresettothemarkedlocation.Thenext

rising edge of RCLK afterRT has returned HIGH, will cause EF to go HIGH,

allowingreadoperationstobeperformedontheFIFO.Thenextreadoperation

willaccessdatafromthe‘marked’memorylocation.

Subsequentretransmitoperationsmaybeperformed,eachtimetheread

pointerreturningtothe‘marked’location.SeeFigure18,RetransmitfromMark

(IDT Standard mode) for the relevant timing diagram.

IfFWFTmodehasbeenselectedtheORflagwillgoHIGHandremainHIGH

forthetimethatRTisheldLOW.RTcanbeheldLOWforanynumberofRCLK

cycles, thereadpointerbeingresettothe‘marked’location. ThenextRCLK

risingedgeafterRThasreturnedHIGH,willcauseORtogoLOWanddueto

FWFToperation,thecontentsofthemarkedmemorylocationwillbeloadedonto

the output register, a read operation being required for all subsequent data

reads.

DuringaMasterReset,theoutputregisterisinitializedtoallzeroes.AMaster

Resetisrequiredafterpowerup,beforeawriteoperationcantakeplace.MRS

isasynchronous.

See Figure 9, Master Reset Timing, for the relevant timing diagram.

PARTIAL RESET (PRS)

APartialResetisaccomplishedwheneverthePRS inputistakentoaLOW

state.AsinthecaseoftheMasterReset,theinternalreadandwritepointers

aresettothefirstlocationoftheRAMarray,PAEgoesLOW, PAFgoesHIGH,

and HF goes HIGH.

WhichevermodeisactiveatthetimeofPartialReset,IDTStandardmode

orFirstWordFallThrough,thatmodewillremainselected. IftheIDTStandard

mode is active, then FF will go HIGH and EF will go LOW. If the First Word

Fall Through mode is active, then OR will go HIGH, and IR will go LOW.

Following Partial Reset, all values held in the offset registers remain

unchanged. Theprogrammingmethod(parallelorserial)currentlyactiveat

thetimeofPartialResetisalsoretained. Theoutputregisterisinitializedtoall

zeroes. PRS is asynchronous.

A Partial Reset is useful for resetting the device during the course of

operation,whenreprogrammingprogrammableflagoffsetsettingsmaynotbe

convenient.

Subsequentretransmitoperationsmaybeperformedeachtimetheread

pointerreturningtothe‘marked’location.SeeFigure19,RetransmitfromMark

(FWFT mode)for the relevant timing diagram.

See Figure 10, Partial Reset Timing, for the relevant timing diagram.

MARK

ASYNCHRONOUS WRITE (ASYW)

TheMARKinputisusedtoselectRetransmitmodeofoperation.AnRCLK

rising edge while MARK is HIGH will mark the memory location of the data

currently present on the output register, the device will also be placed into

retransmit mode. Note, for the IDT72T36105/72T36115 there must be a

minimum of 128 bytes, for the IDT72T36125 a minimum of 256 bytes.

Remember,4(x9)bytes=2(x18)words=1(x36)word.Also,oncetheMARK

isset, thewritepointerwillnotincrementpastthe“marked”locationuntilthe

MARKisdeasserted.Thisprevents“overwriting”ofretransmitdata.

TheMARKinputmustremainHIGHduringthewholeperiodofretransmit

mode, afallingedgeofRCLKwhileMARKisLOWwilltakethedeviceoutof

retransmitmodeandintonormalmode.AnynumberofMARKlocationscanbe

setduringFIFOoperation,onlythelastmarkedlocationtakingeffect.Oncea

marklocationhasbeensetthewritepointercannotbeincrementedpastthis

markedlocation.Duringretransmitmodewriteoperationstothedevicemay

continuewithouthindrance.

ThewriteportcanbeconfiguredforeitherSynchronousorAsynchronous

mode of operation. If during Master Reset the ASYW input is LOW, then

Asynchronousoperationofthewriteportwillbeselected. DuringAsynchro-

nousoperationofthewriteporttheWCLKinputbecomesWRinput,thisisthe

Asynchronouswritestrobeinput.ArisingedgeonWRwillwritedatapresent

ontheDninputsintotheFIFO.(WENmustbetiedLOWwhenusingthewrite

portinAsynchronousmode).

WhenthewriteportisconfiguredforAsynchronousoperationthefullflag

(FF)operatesinanasynchronousmanner,thatis,thefullflagwillbeupdated

based in both a write operation and read operation. Note, if Asynchronous

modeisselected, FWFTisnotpermissable. RefertoFigures30, 31, 34and

35forrelevanttimingandoperationalwaveforms.

ASYNCHRONOUS READ (ASYR)

ThereadportcanbeconfiguredforeitherSynchronousorAsynchronous

mode of operation. If during a Master Reset the ASYR input is LOW, then

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TEMPERATURE RANGES

FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)

input. Datacanbereadontheoutputs,ontherisingedgeoftheRCLKinput.

This is a dual purpose pin. During Master Reset, the state of the FWFT/ ItispermissibletostoptheRCLK. NotethatwhileRCLKisidle,theEF/OR,PAE

SIinputdetermineswhetherthedevicewilloperateinIDTStandardmodeor andHFflagswillnotbeupdated.(NotethatRCLKisonlycapableofupdating

First Word Fall Through (FWFT) mode.

the HF flag to HIGH). The Write and Read Clocks can be independent or

If,atthetimeofMasterReset,FWFT/SIisLOW,thenIDTStandardmode coincident.

will be selected. This mode uses the Empty Flag (EF) to indicate whether or

If Asynchronous operation has been selected this input is RD (Read

notthereareanywordspresentintheFIFOmemory. ItalsousestheFullFlag Strobe) . Data is Asynchronously read from the FIFO via the output register

function(FF)toindicatewhetherornottheFIFOmemoryhasanyfreespace wheneverthereisarisingedgeonRD.InthismodetheRENandRCSinputs

forwriting. InIDTStandardmode, everywordreadfromtheFIFO, including mustbetiedLOW.TheOEinputisusedtoprovideAsynchronouscontrolofthe

the first, must be requested using the Read Enable (REN) and RCLK.

three-stateQnoutputs.

If,atthetimeofMasterReset,FWFT/SIisHIGH,thenFWFTmodewillbe

selected. ThismodeusesOutputReady(OR)toindicatewhetherornotthere WRITE CHIP SELECT (WCS)

isvaliddataatthedataoutputs(Qn). ItalsousesInputReady(IR)toindicate

The WCS disables all Write Port inputs (data only) if it is held HIGH. To

whetherornottheFIFOmemoryhasanyfreespaceforwriting. IntheFWFT performnormaloperationsonthewriteport,theWCSmustbeenabled,held

mode,thefirstwordwrittentoanemptyFIFOgoesdirectlytoQnafterthreeRCLK LOW.

rising edges, REN = LOW is not necessary. Subsequent words must be

accessed using the Read Enable (REN) and RCLK.

READ ENABLE (REN)

AfterMasterReset,FWFT/SIactsasaserialinputforloadingPAEandPAF

offsetsintotheprogrammableregisters. Theserialinputfunctioncanonlybe outputregisterontherisingedgeofeveryRCLKcycleifthedeviceisnotempty.

When Read Enable is LOW, data is loaded from the RAM array into the

usedwhentheserialloadingmethodhasbeenselectedduringMasterReset.

SerialprogrammingusingtheFWFT/SIpinfunctionsthesamewayinbothIDT and no new data is loaded into the output register. The data outputs Q0-Qn

WhentheRENinputisHIGH,theoutputregisterholdsthepreviousdata

StandardandFWFTmodes.

maintainthepreviousdatavalue.

IntheIDTStandardmode,everywordaccessedatQn,includingthefirst

word written to an empty FIFO, must be requested using REN provided that

WRITE STROBE & WRITE CLOCK (WR/WCLK)

IfSynchronousoperationofthewriteporthasbeenselectedviaASYW,this RCSisLOW. WhenthelastwordhasbeenreadfromtheFIFO,theEmptyFlag

inputbehavesasWCLK.

(EF)willgoLOW,inhibitingfurtherreadoperations. RENisignoredwhenthe

AwritecycleisinitiatedontherisingedgeoftheWCLKinput. Datasetup FIFOisempty.Onceawriteisperformed,EFwillgoHIGHallowingareadto

andholdtimesmustbemetwithrespecttotheLOW-to-HIGHtransitionofthe occur. TheEFflagisupdatedbytwoRCLKcycles+tSKEW afterthevalidWCLK

WCLK.ItispermissibletostoptheWCLK. NotethatwhileWCLKisidle,theFF/ cycle.BothRCSandRENmustbeactive,LOWfordatatobereadoutonthe

IR,PAFandHFflagswillnotbeupdated. (NotethatWCLKisonlycapableof rising edge of RCLK.

updating HF flag to LOW). The Write and Read Clocks can either be

independentorcoincident.

IntheFWFTmode,thefirstwordwrittentoanemptyFIFOautomaticallygoes

totheoutputsQn,onthethirdvalidLOW-to-HIGHtransitionofRCLK+tSKEW

IfAsynchronousoperationhasbeenselectedthisinputisWR(writestrobe). afterthefirstwrite. RENandRCSdonotneedtobeassertedLOW fortheFirst

DataisAsynchronouslywrittenintotheFIFOviatheDninputswheneverthere Wordtofallthroughtotheoutputregister. Inordertoaccessallotherwords,

isarisingedgeonWR. InthismodetheWENinputmustbetiedLOW.

a read must be executed using REN and RCS. The RCLK LOW-to-HIGH

transitionafterthelastword hasbeenreadfromtheFIFO,OutputReady(OR)

willgoHIGHwithatrueread(RCLKwithREN=LOW;RCS=LOW),inhibiting

further read operations. REN is ignored when the FIFO is empty.

IfAsynchronousoperationoftheReadporthasbeenselected,thenREN

mustbeheldactive,(tiedLOW).

WRITE ENABLE (WEN)

WhentheWENinput isLOW,datamaybeloadedintotheFIFORAMarray

ontherisingedgeofeveryWCLKcycleifthedeviceisnotfull. Dataisstored

in the RAM array sequentially and independently of any ongoing read

operation.

WhenWENisHIGH,nonewdataiswrittenintheRAMarrayoneachWCLK

cycle.

To prevent data overflow in the IDT Standard mode, FF will go LOW,

inhibitingfurtherwriteoperations. Uponthecompletionofavalidreadcycle,

FF will go HIGH allowing a write to occur. The FF is updated by two WCLK

cycles + tSKEW after the RCLK cycle.

Topreventdataoverflow intheFWFTmode, IR willgoHIGH, inhibiting

furtherwriteoperations. Uponthecompletionofavalidreadcycle, IRwillgo

LOWallowingawritetooccur. TheIRflagisupdatedbytwoWCLKcycles+

tSKEW after the valid RCLK cycle.

SERIAL ENABLE ( SEN )

TheSENinput isanenableusedonlyforserialprogrammingoftheoffset

registers. The serial programming method must be selected during Master

Reset. SENisalwaysusedinconjunctionwithLD. Whentheselinesareboth

LOW,dataattheSIinputcanbeloadedintotheprogramregisteronebitforeach

LOW-to-HIGHtransitionofSCLK.

When SEN is HIGH, the programmable registers retains the previous

settingsandnooffsetsareloaded. SENfunctionsthesamewayinbothIDT

StandardandFWFTmodes.

WENisignoredwhentheFIFOisfullineitherFWFTorIDTStandardmode.

IfAsynchronousoperationofthewriteporthasbeenselected,thenWEN

mustbeheldactive,(tiedLOW).

OUTPUT ENABLE (OE)

WhenOutputEnableisenabled(LOW),theparalleloutputbuffersreceive

datafromtheoutputregister. WhenOEisHIGH,theoutputdatabus(Qn)goes

intoahighimpedancestate.DuringMasteroraPartialResettheOEistheonly

inputthatcanplacetheoutputbusQn,intoHigh-Impedance.DuringResetthe

RCS input can be HIGH or LOW, it has no effect on the Qn outputs.

READ STROBE & READ CLOCK (RD/RCLK)

IfSynchronousoperationofthereadporthasbeenselectedviaASYR,this

inputbehavesasRCLK.A readcycleisinitiatedontherisingedgeoftheRCLK

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TEMPERATURE RANGES

READ CHIP SELECT ( RCS )

thePAEandPAFflags,alongwiththemethodbywhichtheseoffsetregisters

The Read Chip Select input provides synchronous control of the Read canbeprogrammed,parallelorserial(seeTable2). AfterMasterReset,LD

outputport. WhenRCSgoesLOW,thenextrisingedgeofRCLKcausesthe enableswriteoperationstoandreadoperationsfromtheoffsetregisters.Only

QnoutputstogototheLow-Impedancestate. WhenRCSgoesHIGH,thenext theoffsetloadingmethodcurrentlyselectedcanbeusedtowritetotheregisters.

RCLKrisingedgecausestheQnoutputstoreturntoHIGHZ.DuringaMaster Offsetregisterscanbereadonlyinparallel.

orPartialResettheRCSinputhasnoeffectontheQnoutputbus,OEistheonly

AfterMasterReset,theLDpinisusedtoactivatetheprogrammingprocess

inputthatprovidesHigh-ImpedancecontroloftheQnoutputs.IfOEisLOWthe oftheflagoffsetvaluesPAEandPAF.PullingLDLOWwillbeginaserialloading

QndataoutputswillbeLow-ImpedanceregardlessofRCSuntilthefirstrising or parallel load or read of these offset values. THIS PIN MUST BE HIGH

edgeofRCLKafteraResetiscomplete.ThenifRCSisHIGHthedataoutputs AFTERMASTERRESETTOWRITEORREADDATATO/FROMTHEFIFO

willgotoHigh-Impedance.

MEMORY.

TheRCSinputdoesnoteffecttheoperationoftheflags. Forexample,when

thefirstwordiswrittentoanemptyFIFO,theEFwillstillgofromLOWtoHIGH BUS-MATCHING (BM, IW, OW)

based on a rising edge of RCLK, regardless of the state of the RCS input.

ThepinsBM,IWandOWareusedtodefinetheinputandoutputbuswidths.

Also,whenoperatingtheFIFOinFWFTmodethefirstwordwrittentoan DuringMasterReset,thestateofthesepinsisusedtoconfigurethedevicebus

emptyFIFOwillstillbeclockedthroughtotheoutputregisterbasedonRCLK, sizes. SeeTable1forcontrolsettings. Allflagswilloperateontheword/byte

regardlessofthestateofRCS.Forthisreasontheusermusttakecarewhen sizeboundaryasdefinedbytheselectionofbuswidth.SeeFigure5forBus-

adatawordiswrittentoanemptyFIFOinFWFTmode.IfRCSisdisabledwhen MatchingByteArrangement.

anemptyFIFOiswritteninto,thefirstwordwillfallthroughtotheoutputregister,

butwillnotbeavailableontheQnoutputswhichareinHIGH-Z.Theusermust BIG-ENDIAN/LITTLE-ENDIAN ( BE )

takeRCSactiveLOWtoaccessthisfirstword,placetheoutputbusinLOW-Z.

During Master Reset, a LOW on BE will select Big-Endian operation. A

RENmustremaindisabledHIGHforatleastonecycleafterRCShasgoneLOW. HIGHonBEduringMasterResetwillselectLittle-Endianformat.Thisfunction

ArisingedgeofRCLKwithRCSandRENactiveLOW, willreadoutthenext isusefulwhenthefollowinginputtooutputbuswidthsareimplemented:x36to

word. Care must be taken so as not to lose the first word written to an empty x18,x36tox9,x18tox36andx9tox36.IfBig-Endianmodeisselected,then

FIFOwhenRCSisHIGH.RefertoFigure17,RCSandRENReadOperation themostsignificantbyte(word)ofthelongwordwrittenintotheFIFOwillberead

(FWFT Mode). The RCS pin must also be active (LOW) in order to perform outoftheFIFOfirst,followedbytheleastsignificantbyte.IfLittle-Endianformat

aRetransmit. SeeFigure13forReadCycleandReadChipSelectTiming(IDT isselected,thentheleastsignificantbyteofthelongwordwrittenintotheFIFO

StandardMode). SeeFigure16forReadCycleandReadChipSelectTiming willbereadoutfirst,followedbythemostsignificantbyte.Themodedesired

(First Word Fall Through Mode).

isconfiguredduringmasterresetbythestateoftheBig-Endian(BE)pin.See

IfAsynchronousoperationoftheReadporthasbeenselected,thenRCS Figure 5 for Bus-Matching Byte Arrangement.

mustbeheldactive,(tiedLOW).OEprovidesthree-statecontrolofQn.

PROGRAMMABLEFLAGMODE(PFM)

WRITE PORT HSTL SELECT (WHSTL)

DuringMasterReset,aLOWonPFMwillselectAsynchronousProgram-

Thecontrolinputs,datainputsandflagoutputsassociatedwiththewriteport mable flag timing mode. A HIGH on PFM will select Synchronous Program-

canbesetuptobeeitherHSTLorLVTTL.IfWHSTLisHIGHduringtheMaster mableflagtimingmode.IfasynchronousPAF/PAEconfigurationisselected

Reset,thenHSTLoperationofthewriteportwillbeselected.IfWHSTLisLOW (PFM, LOW during MRS), the PAE is asserted LOW on the LOW-to-HIGH

atMasterReset,thenLVTTLwillbeselected.

transition of RCLK. PAE is reset to HIGH on the LOW-to-HIGH transition of

TheinputsandoutputsassociatedwiththewriteportarelistedinTable5. WCLK.Similarly,thePAFisassertedLOWontheLOW-to-HIGHtransitionof

WCLKandPAFisresettoHIGHontheLOW-to-HIGHtransitionofRCLK.

READ PORT HSTL SELECT (RHSTL)

If synchronous PAE/PAF configuration is selected (PFM, HIGH during

Thecontrolinputs,datainputsandflagoutputsassociatedwiththereadport MRS),thePAEisassertedandupdatedontherisingedgeofRCLKonlyand

canbesetuptobeeitherHSTLorLVTTL.IfRHSTLisHIGHduringtheMaster notWCLK.Similarly,PAFisassertedandupdatedontherisingedgeofWCLK

Reset,thenHSTLoperationofthereadportwillbeselected.IfRHSTLisLOW only and not RCLK. The mode desired is configured during master reset by

atMasterReset,thenLVTTLwillbeselectedforthereadport,thenechoclock thestateoftheProgrammableFlagMode(PFM)pin.

and echo read enable will not be provided.

TheinputsandoutputsassociatedwiththereadportarelistedinTable5. INTERSPERSED PARITY (IP)

During Master Reset, a LOW on IP will select Non-Interspersed Parity

SYSTEM HSTL SELECT (SHSTL)

mode.A HIGHwillselectInterspersedParitymode.TheIPbitfunctionallows

Allinputsnotassociatedwiththewriteandreadportcanbesetuptobeeither theusertoselecttheparitybitinthewordloadedintotheparallelport(D0-Dn)

HSTLorLVTTL.IfSHSTLisHIGHduringMasterReset,thenHSTLoperation whenprogrammingtheflagoffsets.IfInterspersedParitymodeisselected,then

ofalltheinputsnotassociatedwiththewriteandreadportwillbeselected.If theFIFOwillassumethattheparitybitsarelocatedinbitpositionD8,D17,D26

SHSTL is LOW at Master Reset, then LVTTL will be selected. The inputs andD35duringtheparallelprogrammingoftheflagoffsets. IfNon-Interspersed

associated with SHSTL are listed in Table 5.

Paritymodeisselected,thenD8,D17 andD28 areisassumedtobevalidbits

and D32, D33, D34 and D35 are ignored. IP mode is selected during Master

ResetbythestateoftheIPinputpin.

LOAD (LD)

Thisisadualpurposepin. DuringMasterReset,thestateoftheLDinput,

alongwithFSEL0andFSEL1,determinesoneofeightdefaultoffsetvaluesfor

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COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

SeeFigure23,SynchronousProgrammableAlmost-FullFlagTiming(IDT

StandardandFWFTMode), fortherelevanttiminginformation.

IfasynchronousPAFconfigurationisselected,thePAFisassertedLOW

ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK). PAFisresettoHIGH

ontheLOW-to-HIGHtransitionoftheReadClock(RCLK). IfsynchronousPAF

configurationisselected,thePAFisupdatedontherisingedgeofWCLK. See

Figure25,AsynchronousAlmost-FullFlagTiming(IDTStandardandFWFT

Mode).

OUTPUTS:

FULL FLAG ( FF/IR )

Thisisadualpurposepin. InIDTStandardmode,theFullFlag (FF) function

is selected. When the FIFO is full, FF will go LOW, inhibiting further write

operations. WhenFFisHIGH,theFIFOisnotfull. Ifnoreadsareperformed

after a reset (either MRS or PRS), FF will go LOW after D writes to the FIFO

(D = 65,536fortheIDT72T36105,131,072fortheIDT72T36115and262,144

fortheIDT72T36125). SeeFigure11, WriteCycleandFullFlagTiming(IDT

StandardMode),fortherelevanttiminginformation.

In FWFT mode, the Input Ready (IR) function is selected. IRgoesLOW

whenmemoryspaceisavailableforwritingindata. Whenthereisnolonger

anyfreespaceleft,IRgoesHIGH,inhibitingfurtherwriteoperations. Ifnoreads

areperformedafterareset(eitherMRSorPRS),IRwillgoHIGHafterD writes

totheFIFO(D = 65,537fortheIDT72T36105,131,073fortheIDT72T36115

and 262,145 for the IDT72T36125). See Figure 14, Write Timing (FWFT

Mode),fortherelevanttiminginformation.

TheIRstatusnotonlymeasuresthecontentsoftheFIFOmemory,butalso

countsthepresenceofawordintheoutputregister. Thus,inFWFTmode,the

totalnumberofwritesnecessarytodeassertIRisonegreaterthanneededto

assert FF in IDT Standard mode.

FF/IRissynchronousandupdatedontherisingedgeofWCLK.FF/IRare

doubleregister-bufferedoutputs.

Note,whenthedeviceisinRetransmitmode,thisflagisacomparisonofthe

writepointertothe‘marked’location.Thisdiffersfromnormalmodewherethis

flagisacomparisonofthewritepointertothereadpointer.

PROGRAMMABLEALMOST-EMPTYFLAG(PAE)

TheProgrammableAlmost-Emptyflag(PAE)willgoLOWwhentheFIFO

reachesthealmost-emptycondition.InIDTStandardmode,PAEwillgoLOW

when there are n words or less in the FIFO. The offset “n” is the empty offset

value.ThedefaultsettingforthisvalueisstatedinthefootnoteofTable 1.

In FWFT mode, the PAE will go LOW when there are n+1 words or less

in the FIFO. The default setting for this value is stated in Table 2.

See Figure 24, Synchronous Programmable Almost-Empty Flag Timing

(IDT Standard and FWFT Mode), for the relevant timing information.

IfasynchronousPAEconfigurationisselected,thePAEisassertedLOW

ontheLOW-to-HIGHtransitionoftheReadClock(RCLK). PAEisresettoHIGH

ontheLOW-to-HIGHtransitionoftheWriteClock(WCLK). IfsynchronousPAE

configurationisselected,thePAEisupdatedontherisingedgeofRCLK. See

Figure 26, Asynchronous Programmable Almost-Empty Flag Timing (IDT

Standard and FWFT Mode).

Note,whenthedeviceisinRetransmitmode,thisflagisacomparisonofthe

writepointertothe‘marked’location.Thisdiffersfromnormalmodewherethis

flagisacomparisonofthewritepointertothereadpointer.

EMPTY FLAG ( EF/OR )

Thisisadualpurposepin. IntheIDTStandardmode,theEmptyFlag(EF)

functionisselected. WhentheFIFOisempty,EFwillgoLOW,inhibitingfurther

readoperations. WhenEFisHIGH,theFIFOisnotempty.SeeFigure12,Read

Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for

therelevanttiminginformation.

InFWFTmode,theOutputReady(OR)functionisselected.ORgoesLOW

atthesametimethatthefirstwordwrittentoanemptyFIFOappearsvalidon

theoutputs. ORstaysLOWaftertheRCLKLOWtoHIGHtransitionthatshifts

thelastwordfromtheFIFOmemorytotheoutputs. ORgoesHIGHonlywith

atrueread(RCLKwithREN=LOW). Thepreviousdatastaysattheoutputs,

indicatingthelastwordwasread. FurtherdatareadsareinhibiteduntilORgoes

LOWagain.SeeFigure15,ReadTiming(FWFTMode),fortherelevanttiming

information.

HALF-FULL FLAG ( HF )

Thisoutputindicatesahalf-fullFIFO.TherisingWCLKedgethatfillstheFIFO

beyondhalf-fullsetsHFLOW.TheflagremainsLOWuntilthedifferencebetween

thewriteandreadpointersbecomeslessthanorequaltohalfofthetotaldepth

ofthedevice;therisingRCLKedgethataccomplishesthisconditionsetsHF

HIGH.

InIDTStandardmode,ifnoreadsareperformedafterreset(MRSorPRS),

HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 65,536 for the

IDT72T36105,131,072fortheIDT72T36115and262,144fortheIDT72T36125.

In FWFT mode, if no reads are performed after reset (MRS or PRS), HF

will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 65,537 for the

IDT72T36105,131,073fortheIDT72T36115and262,145fortheIDT72T36125.

See Figure 27, Half-Full Flag Timing (IDT Standard and FWFT Modes),

fortherelevanttiminginformation.BecauseHFisupdatedbybothRCLKand

WCLK,itisconsideredasynchronous.

EF/OR is synchronous and updated on the rising edge of RCLK.

In IDT Standard mode, EF is a double register-buffered output. In FWFT

mode,ORisatripleregister-bufferedoutput.

ECHO READ CLOCK (ERCLK)

PROGRAMMABLE ALMOST-FULL FLAG ( PAF )

TheEchoReadClockoutputisprovidedinbothHSTLandLVTTLmode,

selectableviaRHSTL.TheERCLKisafree-runningclockoutput,itwillalways

follow the RCLK input regardless of REN and RCS.

TheERCLKoutputfollowstheRCLKinputwithanassociateddelay. This

delayprovidestheuserwithamoreeffectivereadclocksourcewhenreading

datafromtheQnoutputs.Thisisespeciallyhelpfulathighspeedswhenvariables

withinthedevicemaycausechangesinthedataaccesstimes. Thesevariations

inaccesstimemaybecausedbyambienttemperature,supplyvoltage,device

characteristics. The ERCLK output also compensates for any trace length

delaysbetweentheQndataoutputsandreceivingdevicesinputs.

The Programmable Almost-Full flag (PAF) will go LOW when the FIFO

reaches the almost-full condition. In IDT Standard mode, if no reads are

performedafterreset(MRS),PAFwillgoLOWafter(D - m)wordsarewritten

totheFIFO.ThePAFwillgoLOWafter(65,536-m)writesfortheIDT72T36105,

(131,072-m) writes for the IDT72T36115 and (262,144-m) writes for the

IDT72T36125.Theoffset“m”isthefulloffsetvalue.Thedefaultsettingforthis

valueisstatedinthefootnoteofTable3.

In FWFT mode, the PAF will go LOW after (65,537-m) writes for the

IDT72T36105, (131,073-m) writes for the IDT72T36115 and (262,145-m)

writesfortheIDT72T36125,wheremisthefulloffsetvalue.Thedefaultsetting

for this value is stated in Table 4.

26

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

Anyvariationseffectingthedataaccesstimewillalsohaveacorresponding

effectontheERCLKoutputproducedbytheFIFOdevice,thereforetheERCLK

outputleveltransitionsshouldalwaysbeatthesamepositionintimerelativeto

thedataoutputs.Note,thatERCLKisguaranteedbydesigntobeslowerthan

the slowest Qn, data output. Refer to Figure 4, Echo Read Clock and Data

OutputRelationship,Figure28,EchoReadClock&ReadEnableOperation

and Figure 29, Echo RCLK & Echo REN Operation for timing information.

datafromtheQnoutputportathighspeeds.TheERENoutputiscontrolledby

internallogicthatbehavesasfollows:TheERENoutputisactiveLOWforthe

RCLK cycle that a new word is read out of the FIFO. That is, a rising edge of

RCLKwillcauseERENtogoactive,LOWifbothRENandRCSareactive,LOW

and the FIFO is NOT empty.

SERIAL CLOCK (SCLK)

Duringserialloadingoftheprogrammingflagoffsetregisters,arisingedge

ontheSCLKinputisusedtoloadserialdatapresentontheSIinputprovided

thattheSENinputisLOW.

ECHO READ ENABLE (EREN)

TheEchoReadEnableoutputisprovidedinbothHSTLandLVTTLmode,

selectableviaRHSTL.

DATAOUTPUTS(Q0-Qn)

The EREN output is provided to be used in conjunction with the ERCLK

outputandprovidesthereadingdevicewithamoreeffectiveschemeforreading

(Q0-Q35)aredataoutputsfor36-bitwidedata,(Q0-Q17)aredataoutputs

for 18-bit wide data or (Q0-Q8) are data outputs for 9-bit wide data.

RCLK

tERCLK

ERCLK

tD

tA

Q

SLOWEST⁽³⁾

5907 drw08

NOTES:

1. REN is LOW.

2. tERCLK > tA, guaranteed by design.

3. Qslowest is the data output with the slowest access time, tA.

4. Time, tD is greater than zero, guaranteed by design.

Figure 4. Echo Read Clock and Data Output Relationship

27

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

D35-D27

D26-D18

D17-D9

D8-D0

BYTE ORDER ON INPUT PORT:

Write to FIFO

A

B

C

D

BYTE ORDER ON OUTPUT PORT:

Q17-Q9

Q35-Q27

Q26-Q18

Q8-Q0

BE BM IW

OW

L

A

B

C

D

Read from FIFO

X

L

(a) x36 INPUT to x36 OUTPUT

Q17-Q9

Q35-Q27

Q26-Q18

Q8-Q0

BE BM IW

OW

L

1st: Read from FIFO

2nd: Read from FIFO

A

B

L

H

L

Q17-Q9

Q8-Q0

C

D

(b) x36 INPUT to x18 OUTPUT - BIG-ENDIAN

Q17-Q9

Q35-Q27

Q26-Q18

Q8-Q0

BE BM IW

OW

L

1st: Read from FIFO

2nd: Read from FIFO

C

D

H

L

Q17-Q9

Q35-Q27

Q26-Q18

Q8-Q0

A

B

(c) x36 INPUT to x18 OUTPUT - LITTLE-ENDIAN

Q17-Q9

Q35-Q27

Q26-Q18

Q8-Q0

BE BM IW

OW

H

A

1st: Read from FIFO

2nd: Read from FIFO

L

H

L

Q35-Q27

Q17-Q9

Q26-Q18

Q8-Q0

B

Q8-Q0

C

3rd: Read from FIFO

4th: Read from FIFO

Q35-Q27

Q17-Q9

Q26-Q18

Q8-Q0

D

(d) x36 INPUT to x9 OUTPUT - BIG-ENDIAN

Q35-Q27

Q8-Q0

Q26-Q18

Q17-Q9

BE BM IW

OW

H

D

1st: Read from FIFO

H

L

Q35-Q27

Q17-Q9

Q8-Q0

C

2nd: Read from FIFO

3rd: Read from FIFO

Q8-Q0

B

Q35-Q27

Q8-Q0

A

4th: Read from FIFO

5907 drw09

(e) x36 INPUT to x9 OUTPUT - LITTLE-ENDIAN

Figure 5. Bus-Matching Byte Arrangement

28

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™

36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

BYTE ORDER ON INPUT PORT:

D8-D0

D35-D27

D26-D18

D17-D9

1st: Write to FIFO

2nd: Write to FIFO

A

B

D8-D0

D35-D27

D17-D9

C

D

BYTE ORDER ON OUTPUT PORT:

Q17-Q9

Q35-Q27

Q26-Q18

Q8-Q0

BM IW

OW

L

BE

B

D

Read from FIFO

A

C

L

H

(a) x18 INPUT to x36 OUTPUT - BIG-ENDIAN

Q17-Q9

Q8-Q0

Q35-Q27

Q26-Q18

BM IW

OW

L

BE

D

B

C

A

H

(b) x18 INPUT to x36 OUTPUT - LITTLE-ENDIAN

BYTE ORDER ON INPUT PORT:

D8-D0

D26-D18

D17-D9

D35-D27

A

1st: Write to FIFO

2nd: Write to FIFO

D8-D0

D35-D27

B

D8-D0

3rd: Write to FIFO

4th: Write to FIFO

C

D35-D27

D8-D0

D

Q17-Q9

Q26-Q18

Q8-Q0

BYTE ORDER ON OUTPUT PORT:

Q35-Q27

BE BM IW

OW

H

A

B

C

D

Read from FIFO

L

H

(a) x9 INPUT to x36 OUTPUT - BIG-ENDIAN

Q17-Q9

Q26-Q18

Q35-Q27

Q8-Q0

BM IW

OW

H

BE

C

A

Read from FIFO

D

B

H

(b) x9 INPUT to x36 OUTPUT - LITTLE-ENDIAN

5907 drw10

Figure 5. Bus-Matching Byte Arrangement (Continued)

29

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

JTAGTIMINGSPECIFICATION

tTCK

t4

t1

t2

TCK

t3

TDI/

TMS

tDS

tDH

TDO

tDO

t6

TRST

5907 drw11

Notes to diagram:

t1 = tTCKLOW

t2 = tTCKHIGH

t

5

t3 = tTCKFALL

t4 = tTCKRISE

t5 = tRST (reset pulse width)

t6 = tRSR (reset recovery)

Figure 6. Standard JTAG Timing

JTAG

ACELECTRICALCHARACTERISTICS

(vcc = 2.5V 5%; Tcase = 0°C to +85°C)

Parameter

Symbol

Test

Conditions

Min. Max. Units

SYSTEMINTERFACEPARAMETERS

JTAGClockInputPeriod tTCK

-

100

40

-

ns

IDT72T36105

IDT72T36115

IDT72T36125

JTAGClockHIGH

JTAG Clock Low

tTCKHIGH

tTCKLOW

tTCKRISE

tTCKFALL

tRST

-

Parameter

Symbol Test Conditions Min. Max. Units

JTAGClockRiseTime

JTAGClockFallTime

JTAGReset

5⁽¹⁾

-

DataOutput

tDO⁽¹⁾

-

20

-

ns

-

DataOutputHold tDOH⁽¹⁾

0

50

DataInput

tDS

tDH

trise=3ns

tfall=3ns

10

-

JTAG Reset Recovery

tRSR

-

NOTE:

1. 50pf loading on external output signals.

NOTE:

1. Guaranteed by design.

30

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

TheStandardJTAGinterfaceconsistsoffourbasicelements:

JTAGINTERFACE

•

Test Access Port (TAP)

TAP controller

Instruction Register (IR)

Data Register Port (DR)

Five additional pins (TDI, TDO, TMS, TCK and TRST) are provided to

support the JTAG boundary scan interface. The IDT72T36105/72T36115/

72T36125incorporatesthenecessarytapcontrollerandmodifiedpadcellsto

implementtheJTAG facility.

Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora

completedescriptionrefertotheIEEEStandardTestAccessPortSpecification

(IEEE Std. 1149.1-1990).

NotethatIDTprovidesappropriateBoundaryScanDescriptionLanguage

programfilesforthesedevices.

The Figure below shows the standard Boundary-Scan Architecture

DeviceID Reg.

Mux

Boundary Scan Reg.

Bypass Reg.

TDO

TDI

T

A

clkDR, ShiftDR

UpdateDR

P

TMS

TAP

TCLK

Cont-

roller

TRST

Instruction Decode

clklR, ShiftlR

UpdatelR

Instruction Register

Control Signals

5907 drw12

Figure 7. Boundary Scan Architecture

THETAPCONTROLLER

TEST ACCESS PORT (TAP)

TheTapcontrollerisasynchronousfinitestatemachinethatrespondsto

TMSandTCLKsignalstogenerateclockandcontrolsignalstotheInstruction

andDataRegistersforcaptureandupdateofdata.

The Tap interface is a general-purpose port that provides access to the

internaloftheprocessor. Itconsistsoffourinputports(TCLK,TMS,TDI,TRST)

and one output port (TDO).

31

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

1

0

Test-Logic

Reset

0

1

Select-

IR-Scan

1

Run-Test/

Idle

Select-

DR-Scan

0

1

Capture-DR

Capture-IR

0

Shift-DR

Shift-IR

1

Input = TMS

Exit1-IR

EXit1-DR

0

Pause-DR

Pause-IR

1

Exit2-IR

Exit2-DR

0

1

Update-DR

Update-IR

1

0

1

0

5907 drw13

NOTES:

1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.

2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).

3. TAP controller must be reset before normal FIFO operations can begin.

Figure 8. TAP Controller State Diagram

Capture-IRInthiscontrollerstate,theshiftregisterbankintheInstruction

RegisterparallelloadsapatternoffixedvaluesontherisingedgeofTCK.The

lasttwosignificantbitsarealwaysrequiredtobe“01”.

Shift-IR In this controller state, the instruction register gets connected

betweenTDIandTDO,andthecapturedpatterngetsshiftedoneachrisingedge

ofTCK.TheinstructionavailableontheTDIpinisalsoshiftedintotheinstruction

register.

Exit1-IRThisisacontrollerstatewhereadecisiontoentereitherthePause-

IRstateorUpdate-IRstateismade.

Pause-IR This state is provided in order to allow the shifting of instruction

registertobetemporarilyhalted.

Exit2-DRThisisacontrollerstatewhereadecisiontoentereithertheShift-

IRstateorUpdate-IRstateismade.

Update-IRInthiscontrollerstate,theinstructionintheinstructionregisteris

latchedintothelatchbankoftheInstructionRegisteroneveryfallingedgeof

TCK.Thisinstructionalsobecomesthecurrentinstructiononceitislatched.

Capture-DRInthiscontrollerstate,thedataisparallelloadedintothedata

registersselectedbythecurrentinstructionontherisingedgeofTCK.

Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These

controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and

Update-IRstatesintheInstructionpath.

Refer to the IEEE Standard Test Access Port Specification (IEEE Std.

1149.1)forthefullstatediagram

AllstatetransitionswithintheTAPcontrolleroccurattherisingedgeofthe

TCLKpulse. TheTMSsignallevel(0or1)determinesthestateprogression

thatoccursoneachTCLKrisingedge.TheTAPcontrollertakesprecedence

over the FIFO memory and must be reset after power up of the device. See

TRSTdescriptionformoredetailsonTAPcontrollerreset.

Test-Logic-ResetAlltestlogicisdisabledinthiscontrollerstateenablingthe

normaloperationoftheIC.TheTAPcontrollerstatemachineisdesignedinsuch

awaythat,nomatterwhattheinitialstateofthecontrolleris,theTest-Logic-Reset

statecanbeenteredbyholdingTMSathighandpulsingTCKfivetimes.This

is the reason why the Test Reset (TRST) pin is optional.

Run-Test-IdleInthiscontrollerstate,thetestlogicintheICisactiveonlyif

certaininstructionsarepresent.Forexample,ifaninstructionactivatestheself

test,thenitwillbeexecutedwhenthecontrollerentersthisstate.Thetestlogic

in the IC is idles otherwise.

Select-DR-Scan This is a controller state where the decision to enter the

DataPathortheSelect-IR-Scanstateismade.

Select-IR-Scan This is a controller state where the decision to enter the

InstructionPathismade.TheControllercanreturntotheTest-Logic-Resetstate

otherwise.

32

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

THE INSTRUCTION REGISTER

•

Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween

TDI and TDO during data register scanning.

TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe

processor at the rising edge of TCLK.

TheInstructionisusedtoselectthetesttobeperformed, orthetestdata

registertobeaccessed,orboth. Theinstructionshiftedintotheregisterislatched

atthecompletionoftheshiftingprocesswhentheTAPcontrollerisatUpdate-

IRstate.

Theinstructionregistermustcontain4bitinstructionregister-basedcells

whichcanholdinstructiondata. Thesemandatorycellsarelocatednearestthe

serialoutputstheyaretheleastsignificantbits.

TheInstructionRegisterisa4bitfield(i.e.IR3,IR2,IR1,IR0)todecode16

differentpossibleinstructions. Instructionsaredecodedasfollows.

Hex

Instruction

Function

Value

0x00

0x02

0x01

0x03

0x0F

EXTEST

IDCODE

SAMPLE/PRELOAD

HIGH-IMPEDANCE

BYPASS

SelectBoundaryScanRegister

SelectChipIdentificationdataregister

SelectBoundaryScanRegister

JTAG

SelectBypassRegister

TESTDATAREGISTER

JTAG Instruction Register Decoding

TheTestDataregistercontainsthreetestdataregisters:theBypass,the

Boundary Scan register and Device ID register.

Theseregistersareconnectedinparallelbetweenacommonserialinput

andacommonserialdataoutput.

Thefollowingsectionsprovideabriefdescriptionofeachelement. Fora

completedescription,refertotheIEEEStandardTestAccessPortSpecification

(IEEE Std. 1149.1-1990).

Thefollowingsectionsprovideabriefdescriptionofeachinstruction. For

acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification

(IEEE Std. 1149.1-1990).

EXTEST

TherequiredEXTESTinstructionplacestheICintoanexternalboundary-

testmodeandselectstheboundary-scanregistertobeconnectedbetweenTDI

and TDO. During this instruction, the boundary-scan register is accessed to

drivetestdataoff-chipviatheboundaryoutputsandreceivetestdataoff-chip

viatheboundaryinputs.Assuch,theEXTESTinstructionistheworkhorseof

IEEE.Std1149.1,providingforprobe-lesstestingofsolder-jointopens/shorts

andoflogicclusterfunction.

TEST BYPASS REGISTER

TheregisterisusedtoallowtestdatatoflowthroughthedevicefromTDI

toTDO. Itcontainsasinglestageshiftregisterforaminimumlengthinserialpath.

Whenthebypassregisterisselectedbyaninstruction,theshiftregisterstage

is set to a logic zero on the rising edge of TCLK when the TAP controller is in

theCapture-DRstate.

The operation of the bypass register should not have any effect on the

operationofthedeviceinresponsetotheBYPASSinstruction.

IDCODE

TheoptionalIDCODEinstructionallowstheICtoremaininitsfunctionalmode

andselectstheoptionaldeviceidentificationregistertobeconnectedbetween

TDIandTDO.Thedeviceidentificationregisterisa32-bitshiftregistercontaining

information regarding the IC manufacturer, device type, and version code.

Accessingthedeviceidentificationregisterdoesnotinterferewiththeoperation

oftheIC.Also,accesstothedeviceidentificationregistershouldbeimmediately

available,viaaTAPdata-scanoperation,afterpower-upoftheICorafterthe

TAPhasbeenresetusingtheoptionalTRSTpinorbyotherwisemovingtothe

Test-Logic-Resetstate.

THE BOUNDARY-SCAN REGISTER

TheBoundaryScanRegisterallowsserialdataTDIbeloadedintoorread

outoftheprocessorinput/outputports. TheBoundaryScanRegisterisapart

oftheIEEE1149.1-1990StandardJTAGImplementation.

THE DEVICE IDENTIFICATION REGISTER

The Device Identification Register is a Read Only 32-bit register used to

specify the manufacturer, part number and version of the processor to be

determinedthroughtheTAPinresponsetotheIDCODEinstruction.

IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity

isdroppedinthe11-bitManufacturerIDfield.

SAMPLE/PRELOAD

FortheIDT72T36105/72T36115/72T36125, thePartNumberfieldcon-

tainsthefollowingvalues:

TherequiredSAMPLE/PRELOADinstructionallowstheICtoremainina

normalfunctionalmodeandselectstheboundary-scanregistertobeconnected

betweenTDIandTDO.Duringthisinstruction,theboundary-scanregistercan

beaccessedviaadatescanoperation,totakeasampleofthefunctionaldata

enteringandleavingtheIC.Thisinstructionisalsousedtopreloadtestdatainto

theboundary-scanregisterbeforeloadinganEXTESTinstruction.

Device

Part# Field

0416

IDT72T36105

IDT72T36115

IDT72T36125

0415

0414

HIGH-IMPEDANCE

31(MSB)

Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)

0X0 0X33

28 27

12 11

1 0(LSB)

TheoptionalHigh-Impedanceinstructionsetsalloutputs(includingtwo-state

aswellasthree-statetypes)ofanICtoadisabled(high-impedance)stateand

selects the one-bit bypass register to be connected between TDI and TDO.

Duringthisinstruction,datacanbeshiftedthroughthebypassregisterfromTDI

toTDOwithoutaffectingtheconditionoftheICoutputs.

1

IDT72T36105/72T36115/72T36125JTAGDeviceIdentificationRegister

JTAG INSTRUCTION REGISTER

BYPASS

TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice

whentheTAPcontrollerisintheShift-IRstate. Theinstructionisdecodedto

performthefollowing:

The required BYPASS instruction allows the IC to remain in a normal

functional mode and selects the one-bit bypass register to be connected

between TDI and TDO. The BYPASS instruction allows serial data to be

transferredthroughtheICfromTDItoTDOwithoutaffectingtheoperationof

theIC.

•

Selecttestdataregistersthatmayoperatewhiletheinstructionis

current. Theothertestdataregistersshouldnotinterferewithchip

operationandtheselecteddataregister.

33

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™

36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

tRS

MRS

t

RSR

t

RSS

REN

WEN

t

tRSS

tRSR

FWFT/SI

t

RSS

tRSR

LD

RSS

FSEL0,

FSEL1

OW,

IW, BM

t

HRSS

WHSTL

RHSTL

HRSS

SHSTL

BE

t

RSS

t

PFM

IP

RT

t

RSS

t

SEN

t

RSF

If FWFT = HIGH, OR = HIGH

If FWFT = LOW, EF = LOW

EF/OR

t

RSF

If FWFT = LOW, FF = HIGH

If FWFT = HIGH, IR = LOW

FF/IR

PAE

t

RSF

PAF, HF

t

RSF

OE = HIGH

OE = LOW

Q0 - Qn

5907 drw14

NOTE:

1. During Master Reset the High-Impedance control of the Qn data outputs is provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Master Reset

is complete.

Figure 9. Master Reset Timing

34

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

tRS

PRS

tRSS

tRSR

REN

tRSS

tRSR

WEN

RT

tRSS

SEN

If FWFT = HIGH, OR = HIGH

If FWFT = LOW, EF = LOW

If FWFT = LOW, FF = HIGH

If FWFT = HIGH, IR = LOW

t

RSF

EF/OR

t

RSF

FF/IR

PAE

t

RSF

t

RSF

PAF, HF

t

RSF

OE = HIGH

OE = LOW

Q0 - Qn

5907 drw15

NOTE:

1. During Partial Reset the High-Impedance control of the Qn data outputs is provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Master Reset

is complete.

Figure 10. Partial Reset Timing

35

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

t

CLK

t

CLKH

t

CLKL

NO WRITE

WCLK

2

1

(1)

1

(1)

2

t

SKEW1

t

DH

t

SKEW1

tDS

t

DH

tDS

DX+1

DX

D0 - Dn

tWFF

FF

WEN

RCLK

tENS

t

ENH

tENH

REN

RCS

tENS

tA

Q0

- Qn

NEXT DATA READ

DATA READ

5907 drw16

tRCSLZ

NOTES:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle pus tWFF). If the time between the

rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed one extra WCLK cycle.

2. LD = HIGH, OE = LOW, EF = HIGH.

3. WCS = LOW.

Figure 11. Write Cycle and Full Flag Timing (IDT Standard Mode)

tCLK

tCLKH

tCLKL

1

2

RCLK

REN

tENH

tENS

tENH

tENS

NO OPERATION

tREF

EF

tA

D0

LAST WORD

D1

LAST WORD

Q0 - Qn

tOLZ

tOHZ

t

OLZ

tOE

OE

WCLK

WEN

t

SKEW1⁽¹⁾

tENS

tENH

tENS

tWCSS

tWCSH

WCS

tDS

tDH

tDS

D0

D1

D0 - Dn

5907 drw17

NOTES:

1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the

rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.

2. LD = HIGH.

3. First data word latency = tSKEW1 + 1*TRCLK + tREF.

4. RCS is LOW.

Figure 12. Read Cycle, Output Enable, Empty Flag and First Data Word Latency (IDT Standard Mode)

36

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™

36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

2

1

RCLK

tENS

REN

RCS

tENS

tENH

tREF

EF

tRCSHZ

tA

tRCSLZ

LAST DATA-1

LAST DATA

Q0 - Qn

t

SKEW1⁽¹⁾

WCLK

tENS

tENH

WEN

tDS

tDH

Dn

Dx

5907 drw 18

NOTES:

1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that EF will go HIGH (after one RCLK cycle plus tREF). If the time between the

rising edge of WCLK and the rising edge of RCLK is less than tSKEW1, then EF deassertion may be delayed one extra RCLK cycle.

2. LD = HIGH.

3. First data word latency = tSKEW1 + 1*TRCLK + tREF.

4. OE is LOW.

Figure 13. Read Cycle and Read Chip Select (IDT Standard Mode)

37

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

38

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

39

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

40

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

41

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

42

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

43

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

t

SCLK

tSCKH

t

SCKL

SENS

SCLK

tSENH

t

tENH

SEN

LD

tLDS

tLDH

t

SDH

t

SDS

BIT 1

BIT X⁽¹⁾

BIT 1

SI

5907 drw25

FULL OFFSET

EMPTY OFFSET

NOTE:

1. X = 16 for the IDT72T36105, X = 17 for the IDT72T36115 and X = 18 for the IDT72T36125.

Figure 20. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)

tCLK

tCLKH

tCLKL

WCLK

LD

tLDH

tLDS

tLDH

tENH

t

ENS

tENH

WEN

t

DS

tDH

t

DH

PAF

OFFSET

PAE

OFFSET

D0 - Dn

5907 drw26

NOTE:

1. This timing diagram illustrates programming with an input bus width of 36 bits.

Figure 21. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)

tCLK

tCLKH

tCLKL

RCLK

tLDH

tLDS

LD

tENH

t

ENS

t

ENS

tENS

REN

t

A

t

A

tA

DATA IN OUTPUT REGISTER

PAE OFFSET VALUE

PAF OFFSET VALUE

PAE OFFSET

Q0 - Qn

5907 drw27

NOTES:

1. OE = LOW.

2. The timing diagram illustrates reading of offset registers with an output bus width of 36 bits.

3. The offset registers cannot be read on consecutive RCLK cycles. The read must be disabled (REN = HIGH) for a minimum of one RCLK cycle in between register accesses.

Figure 22. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)

44

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™

36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

tCLKL

WCLK

WEN

PAF

1

2

1

t

ENS

tENH

t

PAFS

tPAFS

D - m words in FIFO⁽²⁾

D-(m+1) words

in FIFO⁽²⁾

D - (m +1) words in FIFO⁽²⁾

t

SKEW2⁽³⁾

RCLK

tENH

t

ENS

5907 drw28

REN

NOTES:

1. m = PAF offset.

2. D = maximum FIFO depth.

In IDT Standard mode: D = 65,536 for the IDT72T36105, 131,072 for the IDT72T36115 and 262,144 for the IDT72T36125.

In FWFT mode: D = 65,537 for the IDT72T36105, 131,073 for the IDT72T36115 and 262,145 for the IDT72T36125.

3. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that PAF will go HIGH (after one WCLK cycle plus tPAFS). If the time between the

rising edge of RCLK and the rising edge of WCLK is less than tSKEW2, then the PAF deassertion time may be delayed one extra WCLK cycle.

4. PAF is asserted and updated on the rising edge of WCLK only.

5. Select this mode by setting PFM HIGH during Master Reset.

Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)

tCLKH

tCLKL

WCLK

t

ENS

tENH

WEN

PAE

n words in FIFO⁽²⁾

n + 1 words in FIFO⁽³⁾

,

n words in FIFO⁽²⁾

n + 1 words in FIFO⁽³⁾

,

n + 1 words in FIFO⁽²⁾

n + 2 words in FIFO⁽³⁾

,

SKEW2⁽⁴⁾

t

PAES

t

PAES

t

1

2

1

2

RCLK

REN

t

ENS

tENH

5907 drw29

NOTES:

1. n = PAE offset.

2. For IDT Standard mode

3. For FWFT mode.

4. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that PAE will go HIGH (after one RCLK cycle plus tPAES). If the time between the

rising edge of WCLK and the rising edge of RCLK is less than tSKEW2, then the PAE deassertion may be delayed one extra RCLK cycle.

5. PAE is asserted and updated on the rising edge of WCLK only.

6. Select this mode by setting PFM HIGH during Master Reset.

7. RCS = LOW.

Figure 24. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)

45

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

tCLKH

tCLKL

WCLK

tENS

tENH

WEN

tPAFA

D - m words

in FIFO

D - (m + 1) words

in FIFO

D - (m + 1) words in FIFO

PAF

RCLK

REN

tPAFA

tENS

5907 drw30

NOTES:

1. m = PAF offset.

2. D = maximum FIFO Depth.

In IDT Standard Mode: D = 65,536 for the IDT72T36105, 131,072 for the IDT72T36115 and 262,144 for the IDT72T36125.

In FWFT Mode: D = 65,537 for the IDT72T36105, 131,073 for the IDT72T36115 and 262,145 for the IDT72T36125.

3. PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.

4. Select this mode by setting PFM LOW during Master Reset.

5. RCS = LOW.

Figure 25. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)

tCLKH

tCLKL

WCLK

tENS

tENH

WEN

tPAEA

(2)

n words in FIFO

,

n words in FIFO

,

(2)

n + 1 words in FIFO

n + 2 words in FIFO

,

(3)

PAE

RCLK

REN

(3)

n + 1 words in FIFO

(3)

tPAEA

tENS

5907 drw31

NOTES:

1. n = PAE offset.

2. For IDT Standard Mode.

3. For FWFT Mode.

4. PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.

5. Select this mode by setting PFM LOW during Master Reset.

6. RCS = LOW.

Figure 26. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)

46

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

tCLKH

tCLKL

WCLK

tENH

tENS

WEN

tHF

D/2 + 1 words in FIFO⁽¹⁾,

D/2 words in FIFO⁽¹⁾

,

D/2 words in FIFO⁽¹⁾

,

D-1

HF

[

+ 2]

words in FIFO⁽²⁾

D-1

2

D-1

[

+ 1

]

words in FIFO⁽²⁾

[

+ 1

words in FIFO⁽²⁾

]

2

tHF

RCLK

tENS

REN

5907 drw32

NOTES:

1. In IDT Standard mode: D = maximum FIFO depth. D = 65,536 for the IDT72T36105, 131,072 for the IDT72T36115 and 262,144 for the IDT72T36125.

2. In FWFT mode: D = maximum FIFO depth. D = 65,537 for the IDT72T36105, 131,073 for the IDT72T36115 and 262,145 for the IDT72T36125.

3. RCS = LOW.

Figure 27. Half-Full Flag Timing (IDT Standard and FWFT Modes)

47

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

48

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

WCLK

tENS

tENH

WEN

tDS

t

DH

tDS

t

DH

tDS

tDH

Wn+1

Wn+2

Wn+3

D0 - Dn

tSKEW1

1

2

RCLK

b

e

h

a

d

g

c

i

f

tERCLK

ERCLK

tENS

tENH

REN

RCS

tENS

tCLKEN

EREN

Qn

tA

t

RCSLZ

HIGH-Z

Wn+1

Wn+2

Wn+3

tREF

OR

tA

O/P

Reg.

Wn

Last Word

Wn+1

Wn+2

Wn+3

5907 drw34

NOTE:

1. The O/P Register is the internal output register. Its contents are available on the Qn output bus only when RCS and OE are both active, LOW, that is the bus is not in High-

Impedance state.

2. OE is LOW.

Cycle:

a&b. At this point the FIFO is empty, OR is HIGH.

RCS and REN are both disabled, the output bus is High-Impedance.

c.

Word Wn+1 falls through to the output register, OR goes active, LOW.

RCS is HIGH, therefore the Qn outputs are High-Impedance. EREN goes LOW to indicate that a new word has been placed on the output register.

EREN goes HIGH, no new word has been placed on the output register on this cycle.

No Operation.

RCS is LOW on this cycle, therefore the Qn outputs go to Low-Impedance and the contents of the output register (Wn+1) are made available.

NOTE: In FWFT mode is important to take RCS active LOW at least one cycle ahead of REN, this ensures the word (Wn+1) currently in the output register is made

available for at least one cycle.

d.

e.

f.

g.

h.

i.

REN goes active LOW, this reads out the second word, Wn+2.

EREN goes active LOW to indicate a new word has been placed into the output register.

Word Wn+3 is read out, EREN remains active, LOW indicating a new word has been read out.

NOTE: Wn+3 is the last word in the FIFO.

This is the next enabled read after the last word, Wn+3 has been read out. OR flag goes HIGH and EREN goes HIGH to indicate that there is no new word available.

Figure 29. Echo RCLK and Echo REN Operation (FWFT Mode Only)

49

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

RCLK

tENS

tENH

REN

tA

Qn

W0

W1

tFFA

FF

tFFA

tCYC

WR

Dn

tCYH

tDS

t

DH

W

D

WD+1

5907 drw35

NOTE:

1. OE = LOW, WEN = LOW and RCS = LOW.

Figure 30. Asynchronous Write, Synchronous Read, Full Flag Operation (IDT Standard Mode)

1

2

RCLK

tENS

tENH

REN

tA

Last Word

W1

W0

Qn

tREF

EF

tCYL

tSKEW

WR

tCYH

tCYC

tDH

tDS

W0

W1

Dn

5907 drw36

NOTE:

1. OE = LOW, WEN = LOW and RCS = LOW.

Figure 31. Asynchronous Write, Synchronous Read, Empty Flag Operation (IDT Standard Mode)

50

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™

36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

No Write

1

WCLK

WEN

Dn

2

DF+1

tWFF

DF

tWFF

FF

tCYC

tSKEW

tAA

tCYL

tCYH

RD

Qn

tAA

Last Word

WX

WX+1

5907 drw37

NOTE:

1. OE = LOW, RCS = LOW and REN = LOW.

2. Asynchronous Read is available in IDT Standard Mode only.

Figure 32. Synchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)

WCLK

WEN

Dn

tENS

tDS

tENH

tDH

W0

tEFA

EF

tEFA

tRPE

RD

tCYH

tAA

Qn

Last Word in Output Register

W0

5907 drw38

NOTE:

1. OE = LOW, REN = LOW and RCS = LOW.

2. Asynchronous Read is available in IDT Standard Mode only.

Figure 33. Synchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)

51

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

tCYC

tCYH

tCYL

WR

Dn

tDH

tDS

W0

W1

RD

Qn

tAA

W1

W0

Last Word in O/P Register

tRPE

tEFA

EF

5907 drw39

NOTES:

1. OE = LOW, WEN = LOW, REN = LOW and RCS = LOW

2. Asynchronous Read is available in IDT Standard Mode only.

Figure 34. Asynchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)

tCYC

tCYH

tCYL

WR

Dn

tDH

tDS

Wy+1

Wy

tCYC

tCYH

tCYL

RD

Qn

tAA

Wx

Wx+1

Wx+2

tFFA

FF

5907 drw40

NOTES:

1. OE = LOW, WEN = LOW, REN = LOW and RCS = LOW.

2. Asynchronous Read is available in IDT Standard Mode only.

Figure 35. Asynchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)

52

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

avoided by creating composite flags, that is, ANDing EF of every FIFO, and

separately ANDing FF of every FIFO. In FWFT mode, composite flags can

be created by ORing OR of every FIFO, and separately ORing IR of every

FIFO.

Figure 36 demonstrates a width expansion using two IDT72T36105/

72T36115/72T36125 devices. D0 - D35 fromeachdeviceforma72-bitwide

inputbusandQ0-Q35fromeachdeviceforma72-bitwideoutputbus.Anyword

widthcanbeattainedbyaddingadditionalIDT72T36105/72T36115/72T36125

devices.

OPTIONALCONFIGURATIONS

WIDTH EXPANSION CONFIGURATION

Word width may be increased simply by connecting together the control

signalsofmultipledevices. Statusflagscanbedetectedfromanyonedevice.

TheexceptionsaretheEFandFFfunctionsinIDTStandardmodeandtheIR

andORfunctionsinFWFTmode. BecauseofvariationsinskewbetweenRCLK

and WCLK, it is possible for EF/FF deassertion and IR/OR assertion to vary

byonecyclebetweenFIFOs. InIDTStandardmode, suchproblemscanbe

SERIAL CLOCK

(SCLK)

PARTIAL RESET (PRS)

MASTER RESET (MRS)

FIRST WORD FALL THROUGH/

SERIAL INPUT (FWFT/SI)

RETRANSMIT (RT)

D

m+1 - D

n

m + n

m

n

D0 - Dm

DATA IN

READ CLOCK (RCLK)

READ CHIP SELECT (RCS)

WRITE CLOCK (WCLK)

WRITE ENABLE (WEN)

LOAD (LD)

READ ENABLE (REN)

IDT

OUTPUT ENABLE (OE)

PROGRAMMABLE (PAE)

IDT

72T36105

72T36115

72T36125

72T36105

72T36115

72T36125

#1

FULL FLAG/INPUT READY (FF/IR)

(1)

EMPTY FLAG/OUTPUT READY (EF/OR) #1

EMPTY FLAG/OUTPUT READY (EF/OR) #2

(1)

GATE

FULL FLAG/INPUT READY (FF/IR) #2

GATE

FIFO

#2

m + n

PROGRAMMABLE (PAF)

HALF-FULL FLAG (HF)

n

FIFO

#1

Qm+1 - Qn

DATA OUT

m

5907 drw41

Q0 - Qm

NOTES:

1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.

2. Do not connect any output control signals directly together.

3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.

Figure 36. Block Diagram of 65,536 x 72, 131,072 x 72 and 262,144 x 72 Width Expansion

53

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™

36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

FWFT/SI

TRANSFER CLOCK

FWFT/SI

WRITE CLOCK

WRITE ENABLE

READ CLOCK

READ CHIP SELECT

READ ENABLE

WCLK

WEN

IR

RCLK

WCLK

RCLK

RCS

REN

IDT

OR

WEN

72T36105

72T36115

72T36125

72T36105

72T36115

72T36125

INPUT READY

REN

RCS

OE

OUTPUT READY

IR

OR

OE

OUTPUT ENABLE

GND

n

DATA OUT

n

DATA IN

Dn

Qn

Dn

5907 drw42

Figure 37. Block Diagram of 131,072 x 36, 262,144 x 36 and 524,288 x 36 Depth Expansion

DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)

TheIDT72T36105caneasilybeadaptedtoapplicationsrequiringdepths

65,536,131,072fortheIDT72T36115and262,144fortheIDT72T36125with

an18-bitbuswidth.InFWFTmode,theFIFOscanbeconnectedinseries(the

data outputs of one FIFO connected to the data inputs of the next) with no

externallogicnecessary. Theresultingconfigurationprovidesatotaldepth

equivalenttothesumofthedepthsassociatedwitheachsingleFIFO. Figure

37showsadepthexpansionusingtwoIDT72T36105/72T36115/72T36125

devices.

CareshouldbetakentoselectFWFTmodeduringMasterResetforallFIFOs

in the depth expansion configuration. The first word written to an empty

configurationwillpassfromoneFIFOtothenext("rippledown")untilitfinally

appears at the outputs of the last FIFO in the chain – no read operation is

necessarybuttheRCLKofeachFIFOmustbefree-running. Eachtimethe

datawordappearsattheoutputsofoneFIFO,thatdevice'sORlinegoesLOW,

enabling a write to the next FIFO in line.

period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1

specificationisnotmetbetweenWCLKandtransferclock,orRCLKandtransfer

clock,fortheORflag.

The"rippledown"delayisonlynoticeableforthefirstwordwrittentoanempty

depthexpansionconfiguration. Therewillbenodelayevidentforsubsequent

wordswrittentotheconfiguration.

The first free location created by reading from a full depth expansion

configurationwill"bubbleup"fromthelastFIFOtothepreviousoneuntilitfinally

movesintothefirstFIFOofthechain. Eachtimeafreelocationiscreatedinone

FIFOofthechain,thatFIFO'sIRlinegoesLOW,enablingtheprecedingFIFO

to write a word to fill it.

Forafullexpansionconfiguration,theamountoftimeittakesforIRofthefirst

FIFOinthechaintogoLOWafterawordhasbeenreadfromthelastFIFO is

the sum of the delays for each individual FIFO:

(N – 1)*(3*transfer clock) + 2 TWCLK

where N is the number of FIFOs in the expansion and TWCLK is the WCLK

period. NotethatextracyclesshouldbeaddedforthepossibilitythatthetSKEW1

specificationisnotmetbetweenRCLKandtransferclock,orWCLKandtransfer

clock,fortheIRflag.

TheTransferClocklineshouldbetiedtoeitherWCLKorRCLK,whichever

isfaster. Boththeseactionsresultindatamoving,asquicklyaspossible,tothe

endofthechainandfreelocationstothebeginningofthechain.

Foranemptyexpansionconfiguration,theamountoftimeittakesforORof

thelastFIFOinthechaintogoLOW(i.e.validdatatoappearonthelastFIFO's

outputs)afterawordhasbeenwrittentothefirstFIFOisthesumofthedelays

for each individual FIFO:

(N – 1)*(4*transfer clock) + 3*TRCLK

where N is the number of FIFOs in the expansion and TRCLK is the RCLK

54

IDT72T36105/115/125 2.5V TeraSync

64K x 36, 128K x 36 and 256K x 36

™ 36-BIT FIFO

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

ORDERINGINFORMATION

XXXXX

X

XX

X

Process /

Temperature

Range

Device Type

Power

Speed Package

BLANK

I⁽¹⁾

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

G⁽²⁾

BB

Green

Plastic Ball Grid Array (BB240, BBG240)

Commercial Only

Commercial and Industrial

4-4

5

Clock Cycle Time (tCLK

Speed in Nanoseconds

)

Commercial Only

6-7

10

Low Power

L

72T36105 65,536 x 36 ⎯ 2.5V TeraSync™ FIFO

72T36115 131,072 x 36 ⎯ 2.5V TeraSync™ FIFO

72T36125 262,144 x 36 ⎯ 2.5V TeraSync™ FIFO

5907 drw43

NOTES:

1. Industrial temperature range product for 5ns speed is available as a standard device. All other speed grades are available by special order.

2. Green parts available. For specific speeds and packages contact your sales office.

ORDERABLEPARTINFORMATION

Speed

(ns)

Pkg.

Code

Pkg.

Temp.

Grade

Speed

(ns)

Pkg.

Code

Pkg.

Type

Temp.

Grade

Orderable Part ID

Type

PBGA

4-4

5

72T36105L4-4BB

72T36105L4-4BBG

72T36105L5BB

BB240

PBGA

C

I

4-4

5

72T36125L4-4BB

72T36125L4-4BBG

72T36125L5BB

BB240

BBG240

BB240

C

I

5

72T36105L5BBI

72T36105L6-7BB

72T36105L10BB

5

72T36125L5BBI

72T36125L5BBG

72T36125L5BBGI

72T36125L6-7BB

72T36125L10BB

BB240

6-7

10

C

5

BBG240

BB240

C

I

5

6-7

10

C

Speed

(ns)

Pkg.

Code

Pkg.

Type

Temp.

Grade

BB240

Orderable Part ID

4-4

5

72T36115L4-4BB

72T36115L4-4BBG

72T36115L5BB

BB240

BBG240

BB240

PBGA

C

I

5

72T36115L5BBI

72T36115L6-7BB

72T36115L10BB

6-7

10

C

55

DATASHEETDOCUMENTHISTORY

05/30/2001

07/09/2001

09/07/2001

09/11/2001

11/19/2001

11/29/2001

01/15/2002

03/04/2002

06/05/2002

02/11/2003

03/03/2003

09/02/2003

01/11/2007

02/04/2009

06/06/2017

pgs. 17, and 18.

pgs. 1, 7, 8, 19, and 51.

pgs. 1-53.

pg. 8.

pgs. 1, 9, 12, 40, and 41.

pgs. 1, 40, and 41.

pg. 42.

pgs. 9, 10, and 29.

pgs. 9, 10, and 14.

pgs. 8, 9, and 33.

pgs. 1, 11-13, 31, and 33-35.

pgs. 7, 17, and 26.

pgs. 1, 12, 13, and 57.

pg. 57.

pgs 1-56.

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

for Tech Support:

408-360-1753

email:FIFOhelp@idt.com

800-345-7015 or 408-284-8200

fax: 408-284-2775

www.idt.com

56


型号：	72T36125L5BBI
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	2.5 VOLT HIGH-SPEED TeraSyncTM FIFO 36-BIT CONFIGURATIONS 时钟 PC 先进先出芯片内存集成电路
文件：	总56页 (文件大小：359K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

72T36125L5BBI [IDT]

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