72T54262L6-7BB_技术文档

2.5VQUAD/DUALTeraSync™DDR/SDRFIFO

x10QUADFIFOorx10/x20DUALFIFOCONFIGURATIONS

32,768 x 10 x 4/16,384 x 20 x 2

65,536 x 10 x 4/32,768 x 20 x 2

131,072 x 10 x 4/65,536 x 20 x 2

IDT72T54242

IDT72T54252

IDT72T54262

•

Up to 200MHz operating frequency or 2Gbps throughput in SDR mode

Up to 100MHz operating frequency or 2Gbps throughput in DDR mode

Double Data Rate, DDR is selectable, providing up to 400Mbps

bandwidth per data pin

User selectable Single or Double Data Rate modes on both the

write port(s) and read port(s)

FEATURES

•

Choose from among the following memory organizations:

IDT72T54242

IDT72T54252

IDT72T54262

-

32,768 x 10 x 4/32,768 x 10 x 2

65,536 x 10 x 4/65,536 x 10 x 2

131,072 x 10 x 4/131,072 x 10 x 2

•

User Selectable Quad / Dual Mode - Choose between two or

four independent FIFOs

Quad Mode offers

•

All I/Os are LVTTL/ HSTL/ eHSTL user selectable

3.3V tolerant inputs in LVTTL mode

ERCLK and EREN Echo outputs on all read ports

Write enable WEN and Chip Select WCS input for each write port

Read enable REN and Chip Select RCS input for each read port

User Selectable IDT Standard mode (using EF and FF) or FWFT

mode (using IR and OR)

Programmable Almost Empty and Almost Full flags per FIFO

Dedicated Serial Port for flag offset programming

Power Down pin minimizes power consumption

2.5V Supply Voltage

- Eight discrete clock domain, (four write clocks & four read clocks)

- Four separate write ports, write data to four independent FIFOs

- 10-bit wide write ports

- Four separate read ports, read data from any of four independent FIFOs

- Independent set of status flags and control signals for each FIFO

Dual Mode offers

•

- Four discrete clock domain, (two write clocks & two read clocks)

- Two separate write ports, write data to two independent FIFOs

- 10-bit/20-bit wide write ports

- Two separate read ports, read data from any of two independent FIFOs

- Independent set of status flags and control signals for each FIFO

- Bus-Matching on read and write port x10/x20

Available in a 324-pin PBGA, 1mm pitch, 19mm x 19mm

IEEE 1149.1 compliant JTAG port provides boundary scan function

Low Power, High Performance CMOS technology

•

Industrial temperature range (-40°C to +85°C)

- Maximum depth of each FIFO is the same as in Quad Mode

• Green parts available, see ordering information

FUNCTIONALBLOCKDIAGRAMS

Quad Mode

RCLK0

REN0

RCS0

OE0

ERCLK0

EREN0

WCLK0

WEN0

WCS0

Data In D[9:0]

FIFO 0

Data Out

32,768 x 10

65,536 x 10

131,072 x 10

Q[9:0]

RCLK1

REN1

RCS1

OE1

x10

FIFO 0

WCLK1

WEN1

WCS1

ERCLK1

EREN1

FIFO 1

32,768 x 10

65,536 x 10

131,072 x 10

FIFO 1

Data Out

Data In D[19:10]

Q[19:10]

RCLK2

REN2

RCS2

OE2

x10

FIFO 1

WCLK2

WEN2

WCS2

ERCLK2

EREN2

FIFO 2

Data Out

32,768 x 10

65,536 x 10

131,072 x 10

Data In D[29:20]

Q[29:20]

RCLK3

REN3

RCS3

OE3

ERCLK3

EREN3

x10

FIFO 2

WCLK3

WEN3

WCS3

FIFO 3

Data In

FIFO 3

Data Out

32,768 x 10

65,536 x 10

131,072 x 10

D[39:30]

Q[39:30]

FIFO 3

EF0/OR0

PAE0

FF0/IR0

PAF0

FF1/IR1

PAF1

FF2/ IR2

PAF2

EF1/OR1

PAE1

EF2/OR2

PAE2

EF3/OR3

PAE3

FF3/IR3

PAF3

6158 drw01

(See next page for Dual Mode)

C^IDTO^andM^theM^IDTE^logR^oaC^rereI^gA^isteL^redtrA^adeN^maD^rksofIIⁿN^tegrD^ateU^dDS^evicT^eTR^ecI^hnA^oloL^gy,InT^c.TE^heM^TeraP^SyE^ncR^isaA^tradT^emU^arkR^ofE^IntegrR^atedA^DeN^vicG^eTeE^chS^nology,Inc.

FEBRUARY 2009

1

©

DSC-6158/4

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

FUNCTIONALBLOCKDIAGRAMS(CONTINUED)

Dual Mode

RCLK0

REN0

RCS0

OE0

ERCLK0

EREN0

WCLK0

WEN0

WCS0

Data In D[19:0]

FIFO 0

Data Out

32,768 x 10/16,384 x 20

65,536 x 10/32,768 x 20

131,072 x 10/65,536 x 20

x10 or

x20

x10 or

x20

Q[19:0]

FIFO 0

RCLK2

REN2

RCS2

OE2

ERCLK2

EREN2

WCLK2

WEN2

WCS2

Data In D[39:20]

FIFO 2

Data Out

32,768 x 10/16,384 x 20

65,536 x 10/32,768 x 20

131,072 x 10/65,536 x 20

Q[39:20]

x10 or

x20

x10 or

x20

FIFO 2

FF0/IR0

PAF0

EF0/OR0

PAE0

FF2/IR2

PAF2

EF2/OR2

PAE2

6158 drw02

2

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

Table of Contents

Features ......................................................................................................................................................................................................................... 1

Description ...................................................................................................................................................................................................................... 4

Pin Configuration ............................................................................................................................................................................................................. 6

Pin Descriptions............................................................................................................................................................................................................... 7

Device Characteristics ................................................................................................................................................................................................... 11

DC Electrical Characteristics .......................................................................................................................................................................................... 12

AC Electrical Characteristics ........................................................................................................................................................................................... 14

ACTest Conditions ........................................................................................................................................................................................................ 15

Functional Description ................................................................................................................................................................................................... 17

Signal Descriptions ........................................................................................................................................................................................................ 23

JTAGTiming Specifications ............................................................................................................................................................................................ 29

List of Tables

Table 1 — Device Configuration .................................................................................................................................................................................... 17

Table 2 — Default Programmable Flag Offsets................................................................................................................................................................ 17

Table 3 — Status Flags for IDT Standard mode ............................................................................................................................................................. 20

Table 4 — Status Flags for FWFT mode ........................................................................................................................................................................ 20

Table 5 — I/O Voltage LevelAssociations ....................................................................................................................................................................... 21

Table 6 — TSKEW Measurement ................................................................................................................................................................................... 27

List of Figures

Figure 1. Quad/Dual Block Diagram ................................................................................................................................................................................ 5

Figure 2a. AC Test Load................................................................................................................................................................................................ 15

Figure 2b. Lumped Capacitive Load, Typical Derating ................................................................................................................................................... 15

Figure 3. Programmable Flag Offset Programming Methods ........................................................................................................................................... 18

Figure 4. Offset Registers Serial Bit Sequence................................................................................................................................................................ 19

Figure 5. Bus-Matching in Dual mode ............................................................................................................................................................................ 22

Figure 6. Echo Read Clock and Data Output Relationship .............................................................................................................................................. 27

Figure 7. Standard JTAG Timing ................................................................................................................................................................................... 28

Figure 8. JTAGArchitecture ........................................................................................................................................................................................... 29

Figure 9. TAP Controller State Diagram ......................................................................................................................................................................... 30

Figure 10. Master Reset Timing ..................................................................................................................................................................................... 33

Figure 11. Partial Reset Timing ...................................................................................................................................................................................... 34

Figure 12. Write Cycle and Full Flag Timing (Quad mode, IDT Standard mode, SDR to SDR) ....................................................................................... 35

Figure 13. Write Cycle and Full Flag Timing (Quad mode, IDT Standard mode, DDR to DDR)....................................................................................... 36

Figure 14. Write Cycle and Full Flag Timing (Dual mode, IDT Standard mode, DDR to SDR, x10 In to x20 Out) ............................................................ 37

Figure 15. Write Cycle and Full Flag (Dual mode, IDT Standard mode, SDR to DDR, x20 In to x10 Out) ....................................................................... 38

Figure 16. Write Cycle and Output Ready Timing (Quad mode, FWFT mode, SDR to SDR) .......................................................................................... 39

Figure 17. Write Cycle and Output Ready Timing (Quad mode, FWFT mode, DDR to DDR) .......................................................................................... 40

Figure 18. Read Cycle, Output Enable and Empty Flag Timing (Quad mode, IDT Standard mode, SDR to SDR) ........................................................... 41

Figure 19. Read Cycle, Output Enable and Empty Flag Timing (Quad mode, IDT Standard mode, DDR to DDR) .......................................................... 42

Figure 20. Read Cycle and Empty Flag Timing (Dual mode, IDT Standard mode, DDR to SDR, x20 In to x10 Out) ....................................................... 43

Figure 21. Read Cycle and Empty Flag Timing (Dual mode, IDT Standard mode, SDR to DDR, x10 In to x20 Out) ....................................................... 44

Figure 22. Read Timing and Output Ready Flag (Quad mode, FWFT mode, SDR to SDR) ........................................................................................... 45

Figure 23. Read Timing and Output Ready Timing (Quad mode, FWFT mode, DDR to DDR)........................................................................................ 46

Figure 24. Read Cycle and Read Chip Select (Quad mode, IDT Standard mode, SDR to SDR) .................................................................................... 47

Figure 25. Read Cycle and Read Chip Select Timing (Quad mode, FWFT mode, SDR to SDR) .................................................................................... 48

Figure 26. Echo Read Clock and Read Enable Operation (Quad mode, IDT Standard mode, DDR to DDR) ................................................................. 49

Figure 27. Echo RCLK and Echo Read Enable Operation (Quad mode, FWFT mode, SDR to SDR) ............................................................................. 50

Figure 28. Echo Read Clock and Read Enable Operation (Quad mode, IDT Standard mode, SDR to SDR) .................................................................. 51

Figure 29. Loading of Programmable Flag Registers (IDT Standard and FWFT modes) ................................................................................................ 52

Figure 30. Reading of Programmable Flag Registers (IDT Standard and FWFT modes)................................................................................................ 52

Figure 32. Synchronous ProgrammableAlmost-Empty Flag Timing (Quad mode, IDTStandard and FWFT mode, SDR to SDR) ................................... 53

Figure 31. Synchronous ProgrammableAlmost-Full Flag Timing (Quad mode, IDTStandard and FWFT mode, SDR to SDR) ....................................... 53

Figure 33.Asynchronous ProgrammableAlmost-Full FlagTiming (Quad mode, IDT Standard and FWFT mode, SDR to SDR)...................................... 54

Figure 34.Asynchronous ProgrammableAlmost-Empty Flag Timing (Quad mode, IDTStandard and FWFT mode, SDR to SDR) .................................. 54

Figure 35. Power Down Operation ................................................................................................................................................................................ 55

3

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

mode,theinputclockcanoperateupto200MHz.Datawilltransition/latchon

therisingedgeoftheclock.InDDRmode,theinputclockcanoperateupto100

MHz,withdatatransitioning/latchedonbothrisingandfallingedgesoftheclock.

TheadvantageofDDRisthatitcanachievethesamethroughputasSDRwith

onlyhalfthenumberofbits,assumingthefrequencyisconstant.Forexample,

a4Gbps throughputinSDRis 100MHzx40bits.InDDRmode,itis 100MHz

x20bits,becausetwobitstransitionperclockcycle.

AllReadportsprovidetheuserwithadedicatedEchoReadEnable,EREN

and Echo Read Clock, ERCLK output. These outputs aid in high speed

applications where synchronization of the input clock and data of receiving

device is critical. Otherwise known as “Source Synchronous Clocking,” the

echooutputsprovidetightersynchronizationofthedatatransmittedfromthe

FIFOandthereadclockinterfacingtheFIFOoutputs.

A Master Reset input is provided and all setup and configuration pins are

latched with respect to a Master Reset pulse. For example, the mode of

operation,bus-matching,anddatarateareselectedatMasterReset. APartial

ResetisprovidedforeachinternalFIFO. WhenaPartialResetisperformed

onaFIFOthereadandwritepointersofthatFIFOareresettothefirstmemory

location. The flag offset values, timing modes, and initial configurations are

retained.

TheQuad/DualdevicehasthecapabilityofoperatingitsI/Oateither2.5V

LVTTL, 1.5V HSTL or 1.8V eHSTL levels. A Voltage Reference, Vref input

isprovidedforHSTLandeHSTLinterfaces. ThetypeofI/Oisselectedviathe

IOSELpin. Thecoresupplyvoltageofthedevice,VCCisalways2.5V,however

theoutputpinshaveaseparatesupply,VDDQwhichcanbe2.5V,1.8V,or1.5V.

Theinputsofthisdeviceare3.3VtolerantwhenVDDQissetto2.5V. Thedevice

alsoofferssignificantpowersavings,mostnotablyachievedbythepresence

of a Power Down input, PD.

DESCRIPTION

The IDT72T54242/72T54252/72T54262 Quad/Dual TeraSync FIFO

devicesareidealformanyapplicationswheredatastreamconvergenceand

parallelbufferingofmultipledatapathsarerequired.Theseapplicationsmay

include communication systems such as data bandwidth aggregation, data

acquisitionsystemsandmedicalequipment,etc.TheQuad/DualFIFOallows

theusertoselecteithertwoorfourindividualinternalFIFOsforoperation.Each

internalFIFOhasitsowndiscretereadandwriteclock,independentreadand

writeenables,andseparatestatus flags.ThedensityofeachFIFOis fixed.

IfQuadmodeisselected,therewillbeatotalofeightclockdomains,fourread

andfourwriteclocks.Datacanbewrittenintoanyofthefourwriteportstotally

independentofanyotherport,andcanbereadoutofanyofthefourreadports

corresponding to their respective write port. Each port has its own control

enables and status flags and is 10 bits wide. The device functions as four

separate10-bitwideFIFOs.

IfDualmodeisselected,therewillbeatotaloffourclockdomains,tworead

andtwowriteclocks.Datacanbewrittenintoanyofthetwowriteportstotally

independentofanyotherport,andcanbereadoutofanyofthetworeadports

corresponding to their respective write port. Each port has its own control

enables and status flags. All input and output ports have bus-matching

capabilities ofx10orx20bits wide.

AstypicalwithmostIDTFIFOs,twotypesofdatatransferareavailable,IDT

StandardmodeandFirstWordFallThrough(FWFT)mode.This affects the

deviceoperationandalsotheflagoutputs.Thedeviceprovideseightflagoutputs

perinputandoutputport.AdedicatedSerialClockisusedforprogrammingthe

flagoffsets.Thisclockisalsousedforreadingtheoffsetvalues. Theserialread

andwriteoperations areperformedviatheSCLK,FWFT/SI,SWEN,SREN,

andSDOpins.TheflagoffsetscanalsobeprogrammedusingtheJTAGport.

Ifthisoptionisselected,theSCLK,SWEN,andSRENpinsmustbedisabled.

TheQuad/Dualdeviceoffersamaximumthroughputof2Gbpsperport,with

selectableSDRorDDRdatatransfermodesfortheinputsandoutputs.InSDR

AJTAGtestportis provided. The Quad/Dualdevice has a fullyfunctional

BoundaryScanfeature,compliantwithIEEE1149.1StandardTestAccessPort

andBoundaryScanArchitecture.

4

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

D

- D (x10, x20, or x40)

39

0

INPUT

DEMUX

IW[1:0]

WDDR

*WEN0

*WSC0

*WCLK0

RDDR

REN0*

RSC0*

RCLK0*

10

Write Control

Read Control

Logic

Write Pointer

Read Pointer

RAM

ARRAY

*PAF0

*FF0

CFF

PAE0*

EF0*

CEF

Status Flag

Logic

Status Flag

Logic

8,192 x 40

16,384 x 40

32,768 x 40

SCLK

SWEN

SREN

Programmable

Flag Control

ERCLK0*

Echo Outputs

SDI

EREN0*

SDO

FSEL[1:0]

PFM

HSTL I/O

Control

IOSEL

MRS

PRS

Reset

Logic

TCK

TRST

TMS

TDI

JTAG Control

(Boundary Scan)

10

TDO

OUTPUT

MUX

OW[1:0]

OE0*

6158 drw03A

Q

- Q (x10, x20, or x40)

39

0

NOTES:

1. This block diagram only shows the architecture for FIFO 0. There are a total of four FIFOs inside this device all with the identical architecture.

2. *Denotes dedicated signal for each internal FIFO inside the device.

Figure 1. Quad/Dual Block Diagram

5

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PINCONFIGURATION

A1 BALL PAD CORNER

A

MRS

D0

D3

D6

D2

D5

D8

V

REF

PRS0

PRS1

PRS2

V

CC

GND

V

DDQ

PRS3

PD

OE1

SCLK

TMS

OE2

OE3

Q0

Q1

Q2

Q3

D1

D4

D7

OE0

TDI

B

C

D

E

F

SREN

GND

D9

MD

FSEL0 RDDR

VCC

VDDQ

FWFT/SI TDO

SDO

GND

IW

FSEL1

OW

WDDR

GND

VCC

V

DDQ

GND

TCK

TRST SWEN

D10

D13

D11

D14

D12

D15

PFM

GND

IOSEL

GND

V

DDQ

VDDQ

Q6

Q9

Q5

Q8

Q4

Q7

VCC

VDDQ

VCC

V

CC

GND

VCC

D16

D18

V

CC

V

CC

GND

VDDQ

Q11

Q14

WCLK0

WCLK1

D17

D19

Q12

Q15

Q10

Q13

G

H

J

VDDQ

V

CC

VCC

VDDQ

WCLK2 D20

WCLK3 D22

D21

D23

D24

VCC

GND

V

DDQ

VDDQ

Q18

Q17

Q16

V

DDQ

VDDQ EREN1 EREN0 Q19

VCC

K

L

D26

D25

VCC

V

DDQ

VDDQ

EREN3

VCC

EREN2

Q20

D29

D32

D35

D28

D31

D34

D27

D30

D33

V

CC

V

CC

GND

V

DDQ

V

DDQ

Q21

Q24

Q27

Q22

Q25

Q28

Q23

Q26

Q29

M

N

P

R

T

VCC

V

DDQ

VDDQ

VCC

V

DDQ

VDDQ

VCC

D38

D37

VCC

GND GND

VDDQ

V

DDQ

V

DDQ Q30

Q31

Q34

Q32

D36

D39

VCC

VDDQ

GND

FF2

VDDQ

V

DDQ

VDDQ

Q33

Q36

ERCLK0

WEN2 WEN3

VDDQ

VCC

WCS3 WEN0 WEN1

WCS0 WCS1 WCS2

FF0

PAF1

EF1

NC

PAF2

EF2

VCC

PAF3

FF3

GND

RCS1 REN2

Q35

Q37 ERCLK1

Q39 ERCLK2

U

V

PAF0

VCC

PAE3

RCS3 RCS0 REN1

RCS2 REN3 RCLK3

REN0

Q38

ERCLK3

RCLK1 RCLK0

RCLK2

GND

PAE0

EF0

PAE1

FF1

PAE2

VCC

GND

EF3

GND

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

6158 drw03B

NOTE:

1. NC = No Connection.

PBGA (BB324-1, order code: BB)

TOP VIEW

6

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

PINDESCRIPTIONS

Symbol

Name

I/O Type

Description

D[39:0]

DataInputBus

HSTL-LVTTL Thesearethedatainputsforthedevice.Dataiswrittenintothepartviatheseinputsusingtherespective

INPUT

writeportclocksandenables.InQuadmode,theseinputsprovidefourseparatebussestothefour

separate FIFOs. D[9:0] is FIFO[0], D[19:10] is FIFO[1], D[29:20] is FIFO[2], D[39:30] is FIFO[3].

InDualmode,theseinputsprovidetwoseparatebussestothetwoseparateFIFOs.D[19:0]isFIFO[0],

D[39:20] is FIFO[2]. Any unused inputs should be tied to GND.

EF0/1/2/3,

OR0/1/2/3

EmptyFlag0/1/2/3 HSTL-LVTTL ThesearetheEmptyFlags(IDTStandardmode)orOutputReadyFlag(FWFTmode)corresponding

(1)

orOutputReady

Flags 0/1/2/3

OUTPUT

to each of the four FIFOs on the read port. If Dual mode is selected EF1/OR1 and EF3/OR3 are

notusedandcanbeleftfloating.

ERCLK0/1/2/3 EchoReadClock

0/1/2/3

HSTL-LVTTL These are the echo clock outputs corresponding to each of the four FIFOs on the read port. The

(1)

OUTPUT

echoreadclockisguaranteedtotransitionaftertheslowestoutputdataswitching.IfDualmodeis

selectedERCLK1andERCLK3are notusedandcanbe leftfloating

EREN0/1/2/3 Echo Read Enable HSTL-LVTTL ThesearetheechoreadenableoutputscorrespondingtoeachofthefourFIFOsonthereadport.

(1)

0/1/2/3

OUTPUT

The echoreadenable is synchronous tothe RCLKinputandis active whena readoperationhas

occurredandanewwordhasbeenplacedontothedataoutputbus.IfDualmodeisselectedEREN1

and EREN3 are not used and can be left floating.

FF0/1/2/3,

IR0/1/2/3

Full Flags 0/1/2/3 or HSTL-LVTTL ThesearetheFullFlags(IDTStandardmode)andInputReadyFlags(FWFTmode)corresponding

(1)

Input Ready Flags

0/1/2/3

OUTPUT

toeachofthe fourFIFOs onthe readport. IfDualmode is selectedFF1/IR1andFF3/IR3are not

usedandcanbeleftfloating.

FSEL

[1:0]

FlagSelect

HSTL-LVTTL Flagselectdefaultoffsetpins.Duringmasterreset,theFSELpinsareusedtoselectoneoffourdefault

INPUT

PAEandPAFoffsets.BoththePAEandthePAFoffsetsareprogrammedtothesamevalue.Values

are:00=7;01=63;10=127;11=1023.TheoffsetvalueselectedissuppliedtoallinternalFIFOs.

FWFT/SI

IOSEL

FirstWordFall

Through/ Serial

Input

HSTL-LVTTL DuringMasterReset,FWFT=1selectsFirstWordFallThroughmode,FWFT=0selectsIDTStandard

INPUT

mode.AfterMasterResetthispinisusedfortheSerialDatainputfortheprogrammingofthePAEand

PAFflag'soffsetregisters.

I/OSelect

CMOS⁽²⁾

INPUT

This inputdetermines whetherthe inputs willoperate inLVTTLorHSTL/eHSTLmode. IfIOSEL

pinisHIGH,thenallinputsandoutputsthataredesignated"LVTTLorHSTL"inthissectionwillbe

settoHSTL.IfIOSELisLOWthenLVTTLisselected.ThissignalmustbetiedtoeitherVCCorGND

forproperoperation.

IW

InputWidth

CMOS⁽²⁾

INPUT

IfDualmodeisselected,thispinisusedduringmasterresettoselecttheinputwordwidthbussize

forthedevice.0=x10;1=x20.IfQuadmodeisselectedtheinputwordwidthwillbex10regardless

ofIW.IWmustbetiedtoVCC orGNDandcannotbeleftfloating.

MD

Mode

CMOS⁽²⁾

INPUT

ThismodeselectionpinisusedduringmasterresettoselecteitherQuadorDualmodeoperation.

AHIGHonthispinselectsQuadmode,aLOWselectsDualmode.

MRS

MasterReset

HSTL-LVTTL Thisinputprovidesafulldevicereset.Allset-uppinsarelatchedbasedonamasterresetoperation.

INPUT

Readandwritepointerswillberesettothefirstlocationmemory.Allflagoffsetsareclearedand

resettodefaultvaluesdeterminedbyFSEL[1:0].

OE0/1/2/3

OutputEnable

0/1/2/3

HSTL-LVTTL ThesearetheoutputenablescorrespondingtoeachindividualFIFOonthereadport.Alldataoutputs

INPUT

willbeplacedintoHighImpedanceifthispinisHigh.Theseinputsareasynchronous.IfDualmode

is selected OE1 and OE3 are not used and should be tied to VCC.

IfDualmodeisselected,thispinisusedduringmasterresettoselecttheoutputwordwidthbussize

for thedevice.0=x10;1=x20.IfQuadmodeisselectedtheoutputwordwidthwillbex10regardless

ofOW.OWmustbetiedtoVCC orGNDandcannotbeleftfloating.

OW

OutputWidth

CMOS⁽²⁾

INPUT

PAE0/1/2/3

Programmable

Almost-Empty

Flags 0/1/2/3

HSTL-LVTTL Thesearetheprogrammablealmostemptyflagsthatcanbeusedasanearlyindicatorfortheempty

(1)

OUTPUT

boundaryofeachFIFO.ThePAEflags canbesettooneoffourdefaultoffsets determinedbythe

stateofFSEL0andFSEL1duringmasterreset.ThePAEoffsetvaluecanalsobewrittenandread

fromseriallybyeithertheJTAGportortheserialprogrammingpins(SCLK,SI,SDO,SWEN,SREN).

ThisflagcanoperateinsynchronousorasynchronousmodedependingonthesateofthePFMpin

duringmasterreset.IfDualmodeisselectedPAE1andPAE3arenotusedandcanbeleftfloating.

PAF0/1/2/3

Programmable

Almost-FullFlags

0/1/2/3

HSTL-LVTTL These are the programmable almostfullflags thatcanbe usedas anearlyindicatorforthe full

(1)

OUTPUT

boundaryofeachFIFO.ThePAFflags canbesettooneoffourdefaultoffsets determinedbythe

stateofFSEL0andFSEL1duringmasterreset.ThePAFoffsetvaluecanalsobewrittenandread

fromseriallybyeithertheJTAGportortheserialprogrammingpins(SCLK,SI,SDO,SWEN,SREN).

7

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PINDESCRIPTIONS(CONTINUED)

Symbol

Name

I/O Type

Description

PAF0/1/2/3

(Continued)

Programmable

Almost-FullFlags0-3 OUTPUT

HSTL-LVTTL ThisflagcanoperateinsynchronousorasynchronousmodedependingonthesateofthePFMpin

(1)

duringmasterreset.IfDualmodeisselectedPAF1andPAF3arenotusedandcanbeleftfloating.

PD

Power Down

HSTL-LVTTL This input provides considerable power saving in HSTL/eHSTL mode. If this pin is low, the input

INPUT

leveltranslatorsforallthedatainputpins,clocksandnon-essentialcontrolpinsareturnedoff.

When PD is broughthigh, power-upsequence timingwillhave tobe adheredtobefore the inputs

willberecognized.Itisessentialthattheuserrespecttheseconditionswhenpoweringdownthe

partandpoweringupthepart,soastonotproduceruntpulsesorglitchesontheclocksiftheclocks

are free running. PD does not provide any power consumption savings when the inputs are

configuredforLVTTL.

PFM

Programmable

Flag Mode

CMOS⁽²⁾

INPUT

Duringmasterreset, a HIGHonPFMselects synchronous PAE/PAF flagtiming, a Lowduring

masterresetselectsasynchronousPAE/PAFflagtiming.ThispincontrolsallPAE/PAFflagoutputs.

PRS0/1/2/3

PartialReset

HSTL-LVTTL ThesearethepartialresetinputsforeachinternalFIFO.Theread,write,flagpointers,andoutput

INPUT

registerswillallbesettozerowhenpartialresetisactivated.Duringpartialreset,theexistingmode

(IDTorFWFT),input/outputbus widthandratemode,andtheprogrammableflagsettings areall

retained. If Dual mode is selected, PRS1 and PRS3 are not used and should be tied to VCC.

Q[39:0]

DataOutputBus

HSTL-LVTTL These aretheDataOutputs forthedevice.Datais readfromthepartviatheseoutputs usingthe

(1)

OUTPUT

respectivereadportclocksandenables.InQuadmode,theseoutputsprovidefourseparatebusses

fromthefourseparateFIFO's.Q[9:0]isFIFO[0],Q[19:10]isFIFO[1],Q[29:20]isFIFO[2],Q[39:30]

isFIFO[3].InDualmodetheseoutputsprovidetwoseparatebussesfromthetwoseparateFIFO's.

Q[19:0] is FIFO[0] and Q[39:20] is FIFO[2].

RCLK0/1/2/3 Read Clock 0/1/2/3 HSTL-LVTTL ThesearetheclockinputscorrespondingtoeachofthefourFIFOsonthereadport.IfDualmode

INPUT

is selected then RCLK1 and RCLK3 are not used and should be tied to GND. In SDR mode data

willbeaccessedontherisingedgeofRCLKwhenRENandRCSareLOWattherisingedgeofRCLK.

In DDR mode data will be accessed on both rising and falling edge of RCLK when REN is LOW.

RCS0/1/2/3

REN0/1/2/3

ReadChipSelect

ReadEnable

HSTL-LVTTL ThesearethereadchipselectinputscorrespondingtoeachofthefourFIFOsonthereadport.This

INPUT

pinprovidessynchronouscontrolofthereadportandhighimpedancecontroloftheoutputdatabus.

RCSisonlysampledontherisingedgeofRCLK.Duringmasterorpartialresetthisinputisadon’t

care,ifOEisLOWthedatainputswillbeinLow-ImpedanceregardlessofthestateofRCS. IfDual

mode is selected then RCS1 and RCS3 are not used and should be tied to VCC.

HSTL-LVTTL ThesearethereadenableinputscorrespondingtoeachofthefourFIFOsonthereadport.InSDR,

INPUT

whenthissignal(andRCS)areLOWdatawillbesentfromtheFIFOmemorytotheoutputbuson

every rising edge of RCLK. In DDR mode, data will be accessed on both rising and falling edges

ofRCLK.NoteinDDRmodetheRENandRCSareonlysampledontherisingedgeofRCLK.New

data willalways beginfromthe risingedge notthe fallingedge ofRCLK. IfDualmode is selected

then REN1 and REN3 are not used and should be tied to VCC.

RDDR

SCLK

Read Port DDR

SerialClock

CMOS⁽²⁾

INPUT

Duringmasterreset,thispinselectstheoutputporttooperateinDDRorSDRformat.IfRDDRisHIGH,

thenawordisreadontherisingandfallingedgeoftheappropriateRCLK0,1,2and3input.IfRDDR

is LOW, then a word is read only on the rising edge of the appropriate RCLK0, 1, 2 and 3 inputs.

HSTL-LVTTL Serialclockforwritingandreadingthe PAE andPAF offsetregisters. Onthe risingedge ofeach

INPUT

SCLK,whenSWENislow,onebitofdataisshiftedintothePAEandPAFregisters.Ontherisingedge

ofeachSCLK,whenSRENislow,onebitofdataisshiftedoutofthePAEandPAFoffsetregisters.

ThereadingofthePAEandPAFregistersisnon-destructive.IfprogrammingofthePAE/PAFoffset

registers are done via the JTAGport, this inputmustbe tiedtoVCC.

SDO

SerialData

LVTTL

OUTPUT

Thisoutputisusedtoreaddatafromtheprogrammableflagoffsetregisters.Itisusedinconjunction

withthe SREN andSCLKsignals.

(1)

SREN

Serial Read Enable HSTL-LVTTL WhenSREN is broughtLOWbefore the risingedge ofSCLK, the contents ofthe PAE andPAF

INPUT

offsetregistersarecopiedtoaserialshiftregister.WhileSRENismaintainedLOW,oneachrising

edgeofSCLK,onebitofdataisshiftedoutofthisserialshiftregisterthroughtheSDOoutputpin.

IfprogrammingofthePAE/PAFoffsetregistersisdoneviatheJTAGport,thisinputmustbetiedHIGH.

SWEN

SerialWriteEnable HSTL-LVTTL On each rising edge of SCLK when SWEN is LOW, data from the FWFT/SI pin is serially loaded

INPUT

intothePAEandPAFregisters.IfprogrammingofthePAE/PAFoffsetregistersisdoneviathe

JTAGport,thisinputmustbetiedHIGH.

8

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

PINDESCRIPTIONS(CONTINUED)

Symbol

Name

I/O Type

Description

(3)

TCK

JTAGClock

HSTL-LVTTL ClockinputforJTAGfunction.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.Test

INPUT

operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the

risingedgeofTCKandoutputschangeonthefallingedgeofTCK.IftheJTAGfunctionisnotused

this signalneeds tobetiedtoGND.

(3)

TDI

JTAGTestData

Input

HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan

INPUT

operation, testdata seriallyloadedvia the TDIonthe risingedge ofTCKtoeitherthe Instruction

Register,IDRegisterandBypass Register.Aninternalpull-upresistorforces TDIHIGHifleft

unconnected.

(3)

TDO

JTAGTestData

Output

HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan

OUTPUT

operation,testdataseriallyloadedoutputviatheTDOonthefallingedgeofTCKfromeitherthe

InstructionRegister,IDRegisterandBypassRegister.Thisoutputishighimpedanceexcept

whenshifting, while inSHIFT-DRandSHIFT-IRcontrollerstates.

TMS⁽³⁾

JTAGModeSelect HSTL-LVTTL TMSisaserialinputpin.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.TMSdirects

INPUT

thedevicethroughitsTAPcontrollerstates.Aninternalpull-upresistorforcesTMSHIGHifleft

unconnected.

(3)

TRST

JTAGReset

HSTL-LVTTL TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not

INPUT

automaticallyresetuponpower-up,thusitmustberesetbyeitherthissignalorbysettingTMS=HIGH

forfive TCKcycles. Ifthe TAPcontrolleris notproperlyresetthenthe FIFOoutputs willalways be

inhigh-impedance.IftheJTAGfunctionisusedbuttheuserdoesnotwanttouseTRST,thenTRST

canbetiedwithMRStoensureproperFIFOoperation.IftheJTAGfunctionisnotusedthenthissignal

needs tobetiedtoGND.Aninternalpull-upresistorforces TRST HIGHifleftunconnected.

WCLK0/1/2/3 WriteClock0/1/2/3 HSTL-LVTTL ThesearetheclockinputscorrespondingtoeachofthefourFIFOsonthewriteport.IfDualmode

INPUT

is selectedthenWCLK1andWCLK3arenotusedandshouldbetiedtoGND.InSDRmodedata

willbewrittenontherisingedgeofWCLKwhenWENandWCSareLOWattherisingedgeofWCLK.

InDDRmodedatawillbewrittenonbothrisingandfallingedgeofWCLKwhenWENandWCSare

LOWattherisingedgeofWCLK.

WCS0/1/2/3

WDDR

WriteChipSelect

WritePortDDR

HSTL-LVTTL ThesearethewritechipselectinputscorrespondingtoeachofthefourFIFOsonthewriteport.This

INPUT

pincanbe regardedas a secondwrite enable input,enabling/disablingwrite operations. WCS is

onlysampledontherisingedgeofWCLK.IfDualmodeisselectedthenWCS1andWCS3arenot

used and should be tied to VCC.

CMOS⁽²⁾

INPUT

Duringmasterreset,thispinselectstheinputporttooperateinDDRorSDRformat.IfWDDRisHIGH,

then a word is written on the rising and falling edge of the appropriate WCLK0, 1, 2 and 3 input.

IfWDDRisLOW,thenawordiswrittenonlyontherisingedgeoftheappropriateWCLK0,1,2and

3inputs.

WEN0/1/2/3

WriteEnable0/1/2/3 HSTL-LVTTL ThesearethewriteenableinputscorrespondingtoeachofthefourFIFOsonthewriteport.InSDR,

INPUT

whenthissignal(andWCS)areLOWdataonthedatabuswillbewrittenintotheFIFOmemoryon

every rising edge of WCLK. In DDR mode, data will be written on both rising and falling edges of

WCLK.NoteinDDRmodetheWENandWCSareonlysampledontherisingedgeofWCLK.New

datawillalways beginwritingfromtherisingedge,notthefallingedgeofWCLK.IfDualmodeis

selected then WEN1 and WEN3 are not used and should be tied to VCC.

VCC

+2.5VSupply

Power

These are VCC core power supply pins and must all be connected to a +2.5V supply rail.

VDDQ

OutputRailVoltage

Thispinshouldbetiedtothedesiredvoltagerailforprovidingtotheoutputdrivers.Nominally1.5V

or 1.8V for HSTL, 2.5V for LVTTL.

GND

Vref

GroundPin

Ground

Power

These ground pins are for the core device and must be connected to the GND rail.

Referencevoltage

ThisisaVoltageReferenceinputandmustbeconnectedtoavoltageleveldeterminedintheVoltage

RecommendedDCOperatingConditionssection.Thisprovidesthereferencevoltagewhenusing

HSTLclass inputs.IfHSTLclass inputs arenotbeingused,this pinmustbeconnectedtoGND.

NOTES:

1. All unused outputs may be left floating.

2. All CMOS pins should remain unchanged. CMOS format means that the pin is intended to be tied directly to VCC or GND and these particular pins are not tested for VIH or VIL.

3. These pins are for the JTAG port. Please refer to pages 27-31 and Figures 7-9.

9

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

QUAD/DUALI/OUSAGESUMMARY

SERIAL PORT

SET-UP, CONFIGURATION & RESET PINS

Regardlessofthemodeofoperation,(QuadorDual),thefollowinginputs

mustbealwaysbeused.Theseinputsmustbeset-upwithrespecttomaster

resetastheyarelatchedduringthistime.

WDDR–WritePortDDR/SDRselection

RDDR – Read Port DDR/SDR selection

MD–Mode Selection

ThefollowingpinsareusedwhenuserprogrammingoftheProgrammable

Flagoffsetsisrequired:

SCLK – Serial Clock

SWEN–SerialWriteEnable

SREN – Serial Read Enable

FWFT/SI – Serial Data In

SDO–SerialData Out

OW–Outputwidth

IW–InputWidth

FSEL[1:0]–Flagoffsetdefaultvalues

IOSEL–I/OLevelSelection

PFM – Programmable Flag Mode

FWFT/SI – First word Fall Through or IDT Standard mode

QUADMODE

DUALMODE

Thefollowinginputs/outputsshouldbeusedwhenMuxmodeisselected

by the user:

Thefollowinginputs/outputsshouldbeusedwhenMuxmodeisselected

by the user:

INPUTS:

WCLK0,WCLK1,WCLK2,WCLK3–Fourwriteportclocks

WEN0, WEN1, WEN2, WEN3 – Four write port enables

WCS0, WCS1, WCS2, WCS3 – Four write port chip selects

RCLK0, RCLK1, RCLK2, RCLK3 – Four read port clocks

REN0, REN1, REN2, REN3 – Four read port enables

RCS0, RCS1, RCS2, RCS3, – Four read port chip selects

OE0, OE1, OE2, OE3 – Four read port output enables

WCLK0,WCLK2–Twowriteportclocks

WEN0, WEN2 – Two write port enables

WCS0, WCS2 – Two write port chip selects

RCLK0, RCLK2 – Two read port clocks

REN0, REN2 – Two read port enables

RCS0, RCS2 – Two read port chip selects

OE0, OE2 – Two read port output enables

OUTPUTS:

ERCLK0, ERCLK1, ERCLK2, ERCLK3 – Four read port echo read clocks

EREN0, EREN1, EREN2, EREN3 – Four read port echo read enables

EF0/OR0, EF1/OR1, EF2/OR2, EF3/OR3 – Four read port Empty/Output

Ready Flags

FF0/IR0,FF1/IR1,FF2/IR2,FF3/IR3–Fourwriteportfull/inputreadyflags

PAE0,PAE1,PAE2, PAE3–Fourreadportprogrammablealmostemptyflags

PAF0,PAF1,PAF2,PAF3–Fourwriteportprogrammablealmostemptyflags

ERCLK0, ERCLK2 – Two read port echo read clock outputs

EREN0, EREN2 – Two read port echo read enable outputs

EF0/OR0, EF2/OR2 – Two read port empty/output ready flags

FF0/IR0, FF2/IR2 – Two write port Full/ Input Ready Flags

PAE0,PAE2–Tworeadportprogrammablealmostemptyflags

PAF0,PAF2–Twowriteportprogrammablealmostfullflags

10

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

CAPACITANCE(TA = +25°C, f = 1.0MHz)

Symbol

Rating

Com'l & Ind'l

Unit

Symbol

Parameter

Conditions

Max.

Unit

VTERM

TerminalVoltage

–0.5 to +3.6⁽²⁾

V

(2,3)

CIN

Input

VIN = 0V

10⁽³⁾

pF

with respect to GND

Capacitance

TSTG

IOUT

TJ

StorageTemperature

–55to+125

–50to+50

+150

°C

mA

°C

(1,2)

COUT

Output

Capacitance

VOUT = 0V

10

pF

DCOutputCurrent

NOTES:

MaximumJunctionTemperature

1. With output deselected, (OE ≥ VIH).

2. Characterized values, not currently tested.

3. CIN for Vref is 20pF.

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. Compliant with JEDEC JESD8-5. VCC terminal only.

RECOMMENDEDDCOPERATINGCONDITIONS

Symbol

VCC

Parameter

Min.

Typ.

Max.

Unit

Supply voltage relative to GND

2.375

2.5

2.625

V

VDDQ

Outputsupplyvoltage

⎯LVTTL

⎯ eHSTL

⎯ HSTL

2.375

1.7

1.4

2.5

1.8

1.5

2.625

1.9

1.6

V

VREF⁽¹⁾

VIH

Voltagereferenceinput

Inputhighvoltage

⎯ eHSTL

⎯ HSTL

0.8

0.68

0.9

0.75

1.0

0.9

V

⎯LVTTL

⎯ eHSTL

⎯ HSTL

1.7

VREF+0.2

—

3.45

VDDQ+0.3

V

VIL

Inputlowvoltage

⎯LVTTL

⎯ eHSTL

⎯ HSTL

-0.3

—

0.7

VREF-0.2

V

TA

Operatingtemperature(Commercial)

Operatingtemperature(Industrial)

0

—

+70

+85

°C

-40

NOTES:

1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.

2. GND = Ground.

11

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

DCELECTRICALCHARACTERISTICS

(Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)

Symbol

ILI

Parameter

Min.

–10

—

Max.

+10

-16

Unit

µA

mA

InputLeakageCurrent

OutputLeakageCurrent

ILO

ICC3^(2,3)

JTAGInputLeakageCurrent

OutputLogic“1”Voltage,

(1)

VOH

IOH = –8 mA @LVTTL

IOH = –8 mA @eHSTL

IOH = –8 mA @HSTL

VDDQ-0.4

—

V

VOL

OutputLogic“0”Voltage,

IOL = 8 mA @LVTTL

IOL = 8 mA @eHSTL

IOL = 8 mA @HSTL

—

0.4

V

(7)

ICC1^(2,3,4)

ICC2^(2,3,4)

IDDQ1^(2,3,5)

IDDQ2^(2,3,5)

ISB1^(2,3,4)

ISB2^(2,3,4)

ISB3^(2,3,5)

ISB4^(2,3,5)

IPD1^(3,4)

ActiveVCC Current(Quadmode)

(SeeNote7fortestconditions)

--LVTTL

-- eHSTL

-- HSTL

—

250

mA

(7)

350

(7)

350

(7)

ActiveVCC Current(Dualmode)

(SeeNote8fortestconditions)

--LVTTL

-- eHSTL

-- HSTL

—

180

mA

(7)

295

(7)

295

ActiveVDDQ Current(Quadmode)

(SeeNote7fortestconditions)

--LVTTL

-- eHSTL

-- HSTL

—

50

40

mA

ActiveVDDQCurrent(Dualmode)

(SeeNote8fortestconditions)

--LVTTL

-- eHSTL

-- HSTL

—

35

20

mA

(7)

StandbyVCC Current(Quadmode)

(SeeNote9fortestconditions)

--LVTTL

-- eHSTL

-- HSTL

—

110

mA

(7)

240

(7)

240

(7)

StandbyVCC Current(Dualmode)

(SeeNote10fortestconditions)

--LVTTL

-- eHSTL

-- HSTL

—

100

mA

(7)

185

(7)

185

StandbyVDDQCurrent(Quadmode)

(SeeNote9fortestconditions)

--LVTTL

-- eHSTL

-- HSTL

—

40

35

mA

StandbyVDDQCurrent(Dualmode)

(SeeNote10fortestconditions)

--LVTTL

-- eHSTL

-- HSTL

—

30

15

15⁽⁷⁾

(7)

mA

Power Down VCC Current (Quad mode)

(SeeNote11fortestconditions)

--LVTTL

-- eHSTL

-- HSTL

—

mA

30

30⁽⁷⁾

15⁽⁷⁾

IPD2^(3,4)

Power Down VCC Current (Dual mode)

(SeeNote12fortestconditions)

--LVTTL

-- eHSTL

-- HSTL

—

mA

(7)

30

30⁽⁷⁾

IPD3^(3,5)

PowerDownVDDQ Current(Quadmode)

(SeeNote11fortestconditions)

--LVTTL

-- eHSTL

-- HSTL

—

0.5

mA

IPD4^(3,5)

PowerDownVDDQ Current(Dualmode)

(SeeNote12fortestconditions)

--LVTTL

-- eHSTL

-- HSTL

—

0.2

mA

NOTES:

1. Outputs are not 3.3V tolerant.

2. All WCLKs and RCLKs toggling at 20MHz. Data inputs toggling at 10MHz.

3. VCC = 2.5V, OE0-3 = HIGH.

4. Typical ICC1 calculation: for LVTTL I/O: ICC1 (Quad mode) = 11.25 x fs

ICC1 (Dual mode) = 7.74 x fs

for HSTL I/O: ICC1 (Quad mode) = 158 + (11.25 x fs)

ICC1 (Dual mode) = 115 + (7.74 x fs)

where fs = WCLK = RCLK frequency (in MHz)

NOTES CONTINUED ON PAGE 13.

12

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

5. Typical IDDQ calculation: With data outputs in High-Impedance: IDDQ (Quad mode) = 0.8 x fs

IDDQ (Dual mode) = 0.3 x fs

With data outputs in Low-Impedance: IDDQ (Quad mode and Dual mode) = CL x VDDQ x fs x N

2000

where fs = WCLK = RCLK frequency (in MHz). CL = capacitance load (pF), N= Number of outputs switching.

6. Total Power consumed: PT = [(VCC x ICC) + (VDDQ x IDDQ)].

7. Maximum value tested wtih RCLK = WCLK = 20MHz at 85°C. Maximum value may differ depending on VCC and temperature.

8. WEN0-3 = REN0-3 = LOW, WCS0-3 = RCS0-3 = LOW, PD = HIGH.

9. WEN0,2 = REN0,2 = LOW, WCS0,2 = RCS0,2 = LOW, PD = HIGH.

10. WEN0-3 = REN0-3 = HIGH, WCS0-3 = RCS0-3 = HIGH, PD = HIGH.

11. WEN0,2 = REN0,2 = HIGH, WCS0,2 = RCS0,2 = HIGH, PD = HIGH.

12. WEN0-3 = REN0-3 = HIGH, WCS0-3 = RCS0-3 = HIGH, PD = LOW.

13. WEN0,2 = REN0,2 = HIGH, WCS0,2 = RCS0,2 = HIGH, PD = LOW.

13

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

ACELECTRICALCHARACTERISTICS⁽¹⁾

(Commercial: VCC = 2.5V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)

Commerical

IDT72T54242L5

IDT72T54252L5

IDT72T54262L5

Com'l & Ind'l

IDT72T54242L6-7

IDT72T54252L6-7

IDT72T54262L6-7

Symbol

Parameter

Clock Cycle Frequency (WCLK & RCLK) SDR

Clock Cycle Frequency (WCLK & RCLK) DDR

Data Access Time

Min.

—

0.6

5

Max.

200

100

3.6

—

Min.

—

0.6

6.7

13

2.8

6.0

2.8

6.0

2.0

0.5

2.0

0.5

—

100

45

15

5

Max.

150

75

Unit

MHz

ns

MHz

ns

µs

ns

fS1

fS2

tA

3.8

—

tCLK1

tCLK2

tCLKH1

tCLKH2

tCLKL1

tCLKL2

tDS

Clock Cycle Time SDR

Clock Cycle Time DDR

Clock High Time SDR

Clock High Time DDR

Clock Low Time SDR

Clock Low Time DDR

Data Setup Time

10

2.3

4.5

2.3

4.5

1.5

0.5

1.5

0.5

—

100

45

15

5

—

tDH

Data Hold Time

—

tENS

Enable Setup Time

—

tENH

fC

Enable Hold Time

—

Clock Cycle Frequency (SCLK)

Serial Output Data Access Time

Serial Clock Cycle

10

tASO

tSCLK

tSCKH

tSCKL

tSDS

20

—

Serial Clock High

—

Serial Clock Low

—

Serial Data In Setup

—

tSDH

tSENS

tSENH

tRS⁽³⁾

tRSS

Serial Data In Hold

—

Serial Enable Setup

5

—

5

—

Serial Enable Hold

5

—

5

—

Reset Pulse Width

200

15

10

—

0.6

—

1

—

200

15

10

—

0.8

—

1

—

Reset Setup Time

—

tRSR

tRSF

Reset Recovery Time

Reset to Flag and Output Time

—

12

15

tOLZ (OE - Qn) Output Enable to Output in Low-Impedance

3.6

19.4

13.5

19.4

—

3.8

19.6

13.7

19.6

—

tOHZ

Output Enable to Output in High-Impedance

Output Enable to Data Output Valid

tOE

tRCSLZ

tRCSHZ

tPDLZ

tPDHZ

tPDL

RCLK to Active from High-Impedance

RCLK to High-Impedance

Power Down to Output Low-Impedance

Power Down to Output High-Impedance

Power Down LOW

tPDH

Power Down HIGH

tWFF

Write Clock to FF or IR

—

4

3.6

10

—

5

3.8

12

tREF

Read Clock to EF or OR

tPAFS

Write Clock to Synchronous Programmable Almost-Full Flag

Read Clock to Synchronous Programmable Almost-Empty Flag

Write Clock to Asynchronous Programmable Almost-Full Flag

Read Clock to Asynchronous Programmable Almost-Empty Flag

RCLK to Echo RCLK Output

tPAES

tPAFA

tPAEA

tERCLK

tCLKEN

tSKEW1

tSKEW2

10

12

4.0

3.6

—

4.3

3.8

—

RCLK to Echo REN Output

SKEW time between RCLK and WCLK for EF/OR and FF/IR for SDR inputs and outputs

SKEW time between RCLK and WCLK for EF/OR and FF/IR in for DDR inputs and outputs

SKEW time between RCLK and WCLK for PAE and PAF

5

—

6

—

tSKEW3

5

—

6

—

NOTES:

1. With exception to clock cycle frequency, these parameters apply to both DDR and SDR modes of operation.

2. All AC timings apply to both IDT Standard mode and FWFT mode in both Quad and Dual mode.

3. Pulse width less than the minimum value is not allowed.

4. Values guaranteed by design, not currently tested.

5. Industrial temperature range product for the 6-7ns speed grade is available as a standard device. All other speed grades available by special order.

14

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

HSTL

AC TEST LOADS

1.5V AC TEST CONDITIONS

VDDQ/2

InputPulseLevels

0.25to1.25V

0.4ns

50

Ω

InputRise/FallTimes

InputTimingReferenceLevels

OutputReferenceLevels

0.75V

Z0 = 50Ω

I/O

0.75V

10pF

NOTES:

1. VDDQ = 1.5V.

2. VREF = 0.75V.

6158 drw04

Figure 2a. AC Test Load

EXTENDEDHSTL

1.8V AC TEST CONDITIONS

InputPulseLevels

0.4 to 1.4V

0.4ns

6

5

4

3

2

1

InputRise/FallTimes

InputTimingReferenceLevels

OutputReferenceLevels

0.9V

NOTES:

1. VDDQ = 1.8V.

2. VREF = 0.9V.

20 30 50 80 100

Capacitance (pF)

200

6158 drw04a

LVTTL

Figure 2b. Lumped Capacitive Load, Typical Derating

2.5V AC TEST CONDITIONS

InputPulseLevels

GND to 2.5V

1ns

InputRise/FallTimes

InputTimingReferenceLevels

OutputReferenceLevels

1.25V

NOTE:

1. For LVTTL, VCC = VDDQ = 2.5V.

15

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

OUTPUT ENABLE & DISABLE TIMING

Output

Enable

Output

Disable

VIH

OE

VIL

tOE &

tOLZ

tOHZ

Single Output

Normally

LOW

V

CC/2

OL

V

CC/2

100mV

V

OH

Single Output

Normally

HIGH

100mV

VCC/2

tOE

tOHZ

tOLZ

VCC/2

Output Bus

VCC/2

Current data in output register

NOTES:

1. REN is HIGH.

2. RCS is LOW.

6158 drw05

READ CHIP SELECT ENABLE & DISABLE TIMING

VIH

tENH

RCS

VIL

tENS

RCLK

tRCSHZ

tRCSLZ

Single Output

Normally

LOW

VCC

2

V

2

CC

100mV

VOL

VOH

Single Output

Normally

HIGH

VCC

100mV

VCC

2

t

OLZ

RCSLZ

tOHZ

t

V

2

CC

V

2

CC

Output Bus

Current data in output register

6158 drw06

NOTES:

1. REN is HIGH.

2. OE is LOW.

16

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

FIFOswillfunctioninSDRmode;ifitishighthenthereadportwillbeDDRmode.

ThisfeatureisdescribedintheSignalDescriptionssection.

FUNCTIONALDESCRIPTION

Programmable Almost Empty/Full Flags. These flags can operate in

eithersynchronous orasynchronous timingmode.Iftheprogrammableflag

input,PFMisHIGHduringmasterresetthenallprogrammableflagswilloperate

in a synchronous manner, meaning the PAE flags are double buffered and

updatedbasedontherisingedgeofitsrespectivereadclocks.ThePAFflags

arealsodoublebufferedandupdatedbasedontherisingedgeofitsrespective

write clocks. If it is LOW then all programmable flags will operate in an

asynchronousmanner,meaningthePAEandPAFflagsarenotdoublebuffered

andwillupdatethroughtheinternalcounterafteranominaldelay.Thisfeature

isdescribedintheSignalDescriptionssection.

MASTER RESET & DEVICE CONFIGURATION

DuringMasterResetthedeviceconfigurationandsettingsaredetermined,

thisincludesthefollowing:

1. Quad or Dual mode

2. IDT Standard or First Word Fall Through (FWFT) flag timing mode

3. Single or Double Data Rates on both the Write and Read ports

4. Programmableflagmode,synchronousorasynchronoustiming

5. Write and Read Port Bus Widths, x10 or x20 (in Dual mode only)

6. DefaultOffsets fortheprogrammableflags,7,63,127,or1023

7. LVTTL or HSTL I/O selection

Selectable Bus Width. In Dual mode, the bus width can be selected on

thereadandwriteportsusingtheIWandOWinputs.IfIWisLOWthenthewrite

portswillbe10bitswide,ifIWisHIGHthenthewriteportswillbe20bitswide.

IfOWisLOWthenthereadportswillbe10bitswide,ifOWisHIGHthentheread

portswillbe20bitswide.NoteinQuadmodetheinputsandoutputsarealways

10bitswideregardlessofthestateofthesepins.Thisfeatureisdescribedinthe

SignalDescriptionssection.

Programmable Flag Offset Values. These offset values can be user

programmedortheycanbesettooneoffourdefaultvalues duringamaster

reset.Fordefaultprogramming,thestateoftheFSEL[1:0]inputsduringmaster

resetwilldeterminethevalue.Table2,DefaultProgrammableoffsetsliststhe

fouroffsetvaluesandhowtoselectthem.Forprogrammingtheoffsetvaluesto

aspecificnumber,usetheserialprogrammingsignals(SCLK,SWEN,SREN,

FWFT/SI)toloadthevalueintotheoffsetregister.YoumayalsousetheJTAG

portonthisdevicetoloadtheoffsetvalue.Keepinmindthatyoumustdisable

theserialprogrammingsignalsifyouplantousetheJTAGportforloadingthe

offset values. To disable the serial programming signals, tie SCLK, SWEN,

SREN,andFWFT/SItoVCC. AthoroughexplanationoftheserialandJTAG

programmingoftheflagoffsetvaluesisprovidedinthe"SerialWriteandReading

ofOffsetRegisters”section.

Thestateoftheconfigurationinputsduringmasterresetwilldeterminewhich

oftheabovemodesareselected.AmasterresetcomprisesofpulsingtheMRS

inputpinfromhightolowforaperiodoftime(tRS)withtheconfigurationinputs

heldintheirrespectivestates.Table1summarizestheconfigurationmodes

available duringmasterreset. Theyare describedas follows:

Quad or Dual mode. This mode is selected using the MD input. If during

masterreset,MDisHIGHthenQuadmodeisselected,ifMDisLOWthenDual

modeisselected.InQuadmodefourindependentFIFOsareavailable,while

in Dual mode two independent FIFOs are available.

IDT Standard or FWFT mode. The two available flag timing modes are

selectedusingtheFWFT/SIinput.IfFWFT/SIisLOWduringmasterresetthen

IDTStandardmodeisselected,ifitishighthenFWFTmodeisselected.The

timingmodesaredescribedlaterinthissection.

Single Data Rate (SDR) or Double Data Rate (DDR). The input/output

dataratesareportselectable.Thisisaversatilefeaturethatallowstheuserto

selecteitherSDRorDDRonthewriteportsand/orreadportsofallFIFOsusing

theWDDRandRDDRinputs.IfWDDRisLOWduringmasterresetthenthewrite

portsofallFIFOswillfunctioninSDRmode;ifitishighthenthewriteportswill

beDDRmode.IfRDDRisLOWduringmasterresetthenthereadportsofall

I/OLevelSelection.TheI/Oscanbeselectedforeither2.5VLVTTLlevels

or1.5VHSTL/1.8VeHSTLlevels.ThestateoftheIOSELinputwilldetermine

whichI/Olevelwillbeselected.IfIOSELisHIGHthentheapplicableI/Oswill

be1.5VHSTLor1.8VeHSTL,dependingonthevoltagelevelappliedtoVDDQ

andVREF.ForHSTL,VDDQandVREF=1.5VandforeHSTLVDDQandVREF

=1.8V.IfIOSELisLOWthentheapplicableI/Oswillbe2.5VLVTTL.Asnoted

inthePinDescriptionsection,IOSELisaCMOSinputandmustbetiedtoeither

VCC or GND for proper operation.

TABLE 1 — DEVICE CONFIGURATION

PINS

VALUES

CONFIGURATION

MD

0

1

Dualmode

Quadmode

FWFT/SI

WDDR

RDDR

PFM

0

1

IDTStandardmode

FWFTmode

0

1

SingleDataRatewriteport

DoubleDataRatewriteport

0

1

SingleDataRatereadport

DoubleDataRatereadport

TABLE 2 — DEFAULT PROGRAMMABLE

FLAG OFFSETS

0

1

AsynchronousoperationofPAEandPAFoutputs

SynchronousoperationofPAEandPAFoutputs

IDT72T54242

IDT72T54252

IDT72T54262

IW

0

1

Write portis 10bits wide

Write port is 20 bits wide in dual mode, 10 bits wider

inDualmode

FSEL1

FSEL0

Offsets n,m

OW

0

1

Readportis 10bits wide

Read port is 20 bits wide in dual mode, 10 bits wider

inDualmode

0

1

0

1

0

1

7

63

127

1023

FSEL[1:0]

00

01

10

11

Programmableflagregistersoffsetvalue=7

Programmableflagregistersoffsetvalue=63

Programmableflagregistersoffsetvalue=127

Programmableflagregistersoffsetvalue=1023

NOTES:

1. In default programming, the offset value selected applies to all internal FIFOs.

2. To program different offset values for each FIFO, serial programming must be used.

3. n is the offset value for PAE, m is the offset value for PAF.

IOSEL

0

1

All applicable I/Os (except CMOS) are LVTTL

All applicable I/Os (except CMOS) are HSTL/eHSTL

17

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

SERIAL WRITING AND READING OF OFFSET REGISTERS

theoffsetregisters,astheoffsetregisterdataforeachFIFOistemporarilystored

Theoffsetregisterscanbeloadedwithadefaultvalueortheycanbeuser inascanchain.Whendatahasbeencompletelyreadoutoftheoffsetregisters,

programmedwithaspecificvalue.Oneoffourdefaultvaluesareloadedbased anyadditionalreadoperations totheoffsetregisterwillresultinzeros as the

onthestateoftheFSEL[1:0]inputs.Theflagoffsetvaluescanbeprogrammed outputdata.

eitherthroughthe dedicatedserialprogrammingportorthe JTAGport. The

Readingandwritingtheoffsetregisterscanalsobeaccomplishedusingthe

dedicated serial port can be used to load or read the contents of the offset JTAGport.TowritetotheoffsetregistersusingJTAG,settheinstructionalregister

registers.Theoffsetregistersareprogrammedandreadsequentiallythrough totheoffsetwritecommand(HexValue=0x0008).TheJTAGportwillloaddata

aseriesofshiftregisters.Eachbitintheserialinputwillshiftthroughtheoffset intoeachoftheoffsetregistersinasimilarfashionastheserialprogramming

registersandprogrameachFIFOsoffsetregisters.

describedabove.Toreadthevaluesfromtheoffsetregisters,settheinstructional

TheserialreadandwriteoperationsareperformedbythededicatedSCLK, registertotheoffsetreadcommand(HexValue=0x0007).TheTDOoftheJTAG

FWFT/SI,SWEN,SRENandSDOpins.Thetotalnumberofbitsrequiredper portwilloutputdatainasimilarfashionastheserialprogrammingdescribed

device are listed in Figure 3, Programmable Flag Offset Programming above.

Methods.ThesebitsaccountforallfourPAE/PAFoffsetregistersinthedevice.

Thenumberofbitsrequiredtoloadtheoffsetregistersisdependentonthe

Towritetotheoffsetregisters,settheserialwriteenablesignalactive(LOW), sizeofthedeviceselectedandthewidthoftheI/Osselected.Eachoffsetregister

andoneachrisingedgeofSCLKonebitfromtheFWFT/SIpinisseriallyshifted requires15bits,16bitsor17bitsfortheIDT72T54242/72T54252/72T54262

intotheflagoffsetregisterchain.Oncethecompletenumberofbitshasbeen devicesrespectively.Soatotalof120bits,128bitsor136bitswillneedtobe

programmedintoallfourregisters,theprogrammingsequenceiscomplete.The loadedintoeachoffsetregisterchainfortheIDT72T54242/72T54252/72T54262

programmingsequenceislistedinFigure3.Toreadthevaluesfromtheoffset devicesrespectively.IfDualmodeisselected,onlytwoofthefouroffsetregister

registers,settheserialreadenableactive(LOW).Thenoneachrisingedge will need to be programmed (PAE/PAF2, PAE/PAF0). Therefore, the total

ofSCLK,onebitisshiftedouttotheserialdataoutput.Theserialreadenable numberofbitsrequiredwillbehalfofitsQuadmodeoperation.SeeFigure4,

mustbekeptLOWthroughouttheentirereadoperation.Tostopreadingtheoffset OffsetRegisterSerialBitSequenceforamappingoftheserialbitstoeachoffset

register,disabletheserialreadenable(HIGH).Thereisasetuptimeforreading registers.

Dual Mode⁽⁴⁾

(IW/OW = x10)

JTAG Programming Serial Programming IDT Part Number

Instruction Code

Quad Mode

Dual Mode

(IW/OW = x20)

SWEN

SREN

0008 (Hex)

0007 (Hex)

IDT72T54242

IDT72T54252

IDT72T54262

120

128

136

60

64

68

56

60

64

0

1

IDT72T54242

IDT72T54252

IDT72T54262

120

128

136

60

64

68

56

60

64

1

0

6158 drw07

PROGRAMMING INSTRUCTIONS:

JTAG Programming

1. Load JTAG Instruction code in "JTAG Timing Specifications" section.

2. Use rising edge of TCK to clock in the required bits from the TD2 input or to clock out from the TDO output pin.

Serial Programming

1. Set SWEN and SREN as shown above.

2. If reading, SREN LOW will clock data out of the SDO pin on every rising TCK edge. If writing, SWEN LOW will clock in data from the FWFT/SI pin.

NOTES:

1. The programming methods apply to both IDT Standard mode and FWFT mode.

2. The number of bits indicated are for all four PAE/PAF offset registers.

3. SWEN = 0, and SREN = 0 simultaneously are not allowed.

4. In Dual mode (IW/OW = x10), the total number of bits required will be half since only two FIFOs are active.

5. Parallel programming is not available.

Figure 3. Programmable Flag Offset Programming Methods

18

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH settings for these values are listed in Table 2. This parameter is also user

(FWFT) MODE programmableasdescribedintheSerialWritingandReadingofOffsetRegisters

TheIDT72T54242/72T54252/72T54262supporttwodifferenttimingmodes section.

ofoperation:IDTStandardmodeandFirstWordFallThrough(FWFT)mode.

ContinuingtowritedataintotheFIFOwithoutperformingreadoperationswill

Theselectionofwhichmodewillbeusedisdeterminedduringmasterreset,by causetheProgrammableAlmost-Fullflag(PAF)togoLOW.Again,ifnoreads

thestateoftheFWFTinput.

areperformed,thePAFwillgoLOWafter(32,768-m)writesfortheIDT72T54242,

Duringmasterreset,iftheFWFTpinisLOW,thenIDTStandardmodewill (65,536-m) writes for the IDT72T54252, and (131,072-m) writes for the

beselected.ThismodeusestheEmptyFlag(EF)toindicatewhetherornotthere IDT72T54262.Inx20dualmode,PAFwillgoLOWafter(16,384-m)writesfor

are any words present in the FIFO. It also uses the Full Flag (FF) to indicate the IDT72T54242, (32,768-m)writes forthe IDT72T54252, and(65,536-m)

whetherornottheFIFOhasanyfreespaceforwriting.InIDTStandardmode, writesfortheIDT72T54262.Theoffset“m”isthefulloffsetvalue.Thedefault

everywordreadfromtheFIFO,includingthefirst,mustberequestedusingthe setting for these values are listed in Table 3, Status Flags for IDT Standard

Read Enable (REN), Read Chip Select (RCS), and RCLK.

Mode.This parameteris alsouserprogrammable.SeethesectiononSerial

If the FWFT pin is HIGH during master reset, then FWFT mode will be WritingandReadingofOffsetRegistersfordetails.

selected.ThismodeusesOutputReady(OR)toindicatewhetherornotthere

WhentheFIFOisfull,theFullFlag(FF)willgoLOW,inhibitingfurtherwrite

isvaliddataatthedataoutputs.ItalsousesInputReady(IR)toindicatewhether operations.Ifnoreadsareperformedafterareset,FFwillgoLOWafterDwrites

ornottheFIFOhasanyfreespaceforwriting.IntheFWFTmode,thefirstword totheFIFO,whereD=32,768writesfortheIDT72T54242,65,536writesfor

written to an empty FIFO goes directly to output bus after three RCLK rising theIDT72T54252,and131,072writesfortheIDT72T54262.Inx20dualmode,

edges.ApplyingREN=LOWisnotnecessary,althoughhavingRCS=0atthe FFwillgoLOWafter16,384writesfortheIDT72T54242,32,768writesforthe

previous rising RCLK is necessary to keep the output from being in high- IDT72T54252, and 65,536 writes for the IDT72T54262.

impedance. However, subsequent words must be accessed using Read

IftheFIFOisfull,thefirstreadoperationwillcauseFFtogoHIGH.Subsequent

Enable (REN), ReadChipSelect(RCS), andRCLK. Various signals inboth readoperationswillcausePAFtogoHIGHattheconditionsdescribedinTable

inputsandoutputsoperatedifferentlydependingonwhichtimingmodeisineffect. 3,StatusFlagsforIDTStandardMode.Iffurtherreadoperationsoccurwithout

ThetimingmodeselectedaffectsallinternalFIFOsandarenotprogrammed writeoperations,PAEwillgoLOWwhentherearenwordsintheFIFO,where

individually.

nistheemptyoffsetvalue.ContinuingreadoperationswillcausetheFIFOto

becomeempty.WhenthelastwordhasbeenreadfromtheFIFO,theEFwill

goLOWinhibitingfurtherreadoperations. REN is ignoredwhenthe FIFOis

IDT STANDARD MODE

Inthismode,thestatusflagsFF,PAF,PAE,andEFoperateinthemanner empty,butRCSwillcontinuetodeterminewhetherornottheoutputisinhigh-

outlinedinTable3,StatusFlagsforIDTStandardMode.Towritedataintothe impedance.

FIFO,WriteEnable(WEN),andWriteChipSelect(WCS)mustbeLOW.Data

WhenconfiguredinIDTStandardmode,theEFandFFoutputsaredouble

presentedtothe DATAINlines willbe clockedintothe FIFOonsubsequent register-bufferedoutputs.IDTStandardmodeisavailablewhenthedeviceis

transitionsoftheWriteClock(WCLK).Afterthefirstwriteisperformed,theEmpty configured in either Single Data Rate or Double Data Rate mode. Relevant

Flag(EF)willgoHIGH.SubsequentwriteswillcontinuetofilluptheFIFO.The timingdiagramsforIDTStandardmodecanbefoundinFigure10,11,12,13,

ProgrammableAlmost-Emptyflag(PAE)willgoHIGHaftern+1wordshave 14, 15, 16, 17, 18 and 23.

been loaded into the FIFO, where "n" is the empty offset value. The default

IDT72T54242

Quad mode

IDT72T54252

Quad mode

IDT72T54262

Quad mode

IDT72T54242

Dual mode

IW/OW = x20

IDT72T54242

Dual mode

IW/OW = x10

or

IDT72T54252

Dual mode

IW/OW = x10

or

IDT72T54262

Dual mode

IW/OW = x10

Offset

Register

IDT72T54252

IW/OW = x20

IDT72T54262

IW/OW = x20

PAE3⁽¹⁾

PAF3⁽¹⁾

PAE2

1 - 15

1 - 16

1 - 17

⎯

16 - 30

31 - 45

46 - 60

61 - 75

76 - 90

91 - 105

106 - 120

17 - 32

33 - 48

49 - 64

65 - 80

81 - 96

97 - 112

113 - 128

18 - 34

35 - 51

52 - 68

69 - 85

86 - 102

103 - 119

120 - 136

⎯

1 - 14

15 - 28

⎯

1 - 15

16 - 30

⎯

1 - 16

17 - 32

⎯

1 - 17

18 - 34

⎯

Serial Bits

PAF2

PAE1⁽¹⁾

PAF1⁽¹⁾

PAE0

⎯

29 - 42

43 - 56

31 - 45

46 - 60

33 - 48

49 - 64

35 - 51

52 - 68

PAF0

6158 drw08

NOTES:

1. These registers are not used in Dual mode. They are not programmed or read in the serial chain.

2. In all modes, the higher numbered bit is the MSB. For example, in the IDT72T54242 in Quad mode, the first bit is the LSB for PAE3.

Figure 4. Offset Registers Serial Bit Sequence

19

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

FIRST WORD FALL THROUGH MODE (FWFT)

WhentheFIFOisfull,theInputReady(IR)willgoLOW,inhibitingfurtherwrite

Inthismode,thestatusflagsOR,IR,PAE,andPAFoperateinthemanner operations.Ifnoreadsareperformedafterareset,IRwillgoLOWafterDwrites

outlinedinTable4,StatusFlagsforFWFTMode.TowritedataintototheFIFO, totheFIFO,whereD=32,769writesfortheIDT72T54242,65,537writesfor

WEN, and WCS must be LOW. Data presented to the DATA IN lines will be theIDT72T54252,and131,073writesfortheIDT72T54262.Inx20dualmode,

clockedintotheFIFOonsubsequenttransitionsofWCLK.Afterthefirstwriteis FFwillgoLOWafter16,385writesfortheIDT72T54242,32,769writesforthe

performed, the OutputReady(OR)flagwillgoLOW. Subsequentwrites will IDT72T54252, and 65,537 writes for the IDT72T54262.

continuetofilluptheFIFO.PAEwillgoHIGHaftern+2wordshavebeenloaded

IftheFIFOisfull,thefirstreadoperationwillcauseIRtogoHIGH.Subsequent

intotheFIFO,wherenistheemptyoffsetvalue.Thedefaultsettingforthese readoperationswillcausePAFtogoHIGHattheconditionsdescribedinTable

values are listedinTable 4, Status Flags forFWFTMode. This parameteris 4,StatusFlagsforFWFTMode.Iffurtherreadoperationsoccurwithoutwrite

alsouserprogrammableasdescribedintheSerialWritingandReadingofOffset operations,PAE willgoLOWwhentherearenwords intheFIFO,wherenis

Registerssection.

the empty offset value. Continuing read operations will cause the FIFO to

ContinuingtowritedataintotheFIFOwithoutperformingreadoperationswill becomeempty.WhenthelastwordhasbeenreadfromtheFIFO,theORwill

causetheProgrammableAlmost-Fullflag(PAF)togoLOW.Again,ifnoreads goHIGHinhibitingfurtherreadoperations.RENisignoredwhentheFIFOis

areperformed,thePAFwillgoLOWafter(32,769-m)writesfortheIDT72T54242, empty,butRCSwillcontinuetodeterminewhetherornottheoutputisinhigh-

(65,537-m) writes for the IDT72T54252, and (131,073-m) writes for the impedance.

IDT72T54262.Inx20dualmode,PAFwillgoLOWafter(16,385-m)writesfor

WhenconfiguredinFWFTmode,theORflagoutputistripleregister-buffered

the IDT72T54242, (32,769-m)writes forthe IDT72T54252, and(65,537-m) andtheIRflagoutputisdoubleregister-buffered.Relevanttimingdiagramsfor

writesfortheIDT72T54262.Theoffset“m”isthefulloffsetvalue.Thedefault FWFT mode can be found in Figure 19, 20, 21, 22 and 24.

settingforthesevaluesarelistedinTable4,StatusFlagsforFWFTMode.This

parameter is also user programmable. See the section on serial writing and

readingofoffsetregistersfordetails.

TABLE 3 — STATUS FLAGS FOR IDT STANDARD MODE

IDT72T54242

Dual mode

IDT72T54242

IDT72T54252

IDT72T54262

Quad mode or Dual mode Quad mode or Dual mode Quad mode or Dual mode

IW/OW = x20

IW/OW = x10

or

IW/OW = x10

or

IW/OW = x10

IDT72T54252

Dual mode IW/OW = x20

IDT72T54262

Dual mode IW/OW = x20

Number of

Words in

FIFO

PAE

FF PAF

EF

H

L

0

1 to n

H

L

H

16,384 - (m) to 16,383

16,384

32,768 - (m) to 32,767

32,768

65,536 - (m) to 65,535

65,536

131,072 - (m) to 131,071

131,072

L

H

NOTE:

1. See Table 2 for values for n, m. Values n,m may be different for each FIFO.

TABLE 4 — STATUS FLAGS FOR FWFT MODE

IDT72T54242

Dual mode

IDT72T54242

IDT72T54252

IDT72T54262

Quad mode or Dual mode Quad mode or Dual mode Quad mode or Dual mode

IW/OW = x20

IW/OW = x10

or

IW/OW = x10

or

IW/OW = x10

IDT72T54252

Dual mode IW/OW = x20

IDT72T54262

Dual mode IW/OW = x20

Number of

Words in

FIFO

PAE

IR PAF

OR

L

H

L

H

0

1 to n+1

L

H

16,385 - (m) to 16,384

16,385

32,769 - (m) to 32,768

32,769

65,537 - (m) to 65,536

65,537

131,073 - (m) to 131,072

131,073

L

6158 drw09

NOTE:

1. See Table 2 for values for n, m. Values n,m may be different for each FIFO.

20

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

SELECTABLE MODES

arenotassociatedwiththisfeature.Notethatall“StaticPins”mustbetiedtoVCC

Thisdeviceiscapableofoperatingintwodifferentmodes:QuadmodeorDual orGND.ThesepinsareLVTTLonlyandarepurelydeviceconfigurationpins.

mode.IntheQuadmodetherearefourindependentFIFOsavailable,withthe NotetheIOSELpinshouldbetiedHIGHorLOWandcannottogglebeforeand

inputandoutputbus widths setto10bits wide foreachFIFO.Atotalofeight aftermasterreset.

independentclockinputs areavailable–fourRCLKs andfourWCLKs.Each

FIFOhasindependentreadandwritecontrols,outputenablecontrols,aswell BUS MATCHING

asindividualstatusflagsEF/OR,FF/IR,PAE,andPAF.Alsoavailableareecho

outputsERCLKandERENforeachindividualFIFOtoaidhigh-speedoperation capabilitysuchthattheinputandoutputbussescaneachbeeither10bitsor

wheresynchronizingdataiscritical. 20bitswide.Thebuswidthofboththeinputandoutputportisdeterminedduring

In the Dual mode operation, the write and read port have bus-matching

IntheDualmodetherearetwoindependentFIFOsavailable,withtheinput masterresetusingtheinput(IW)andoutput(OW)widthssetuppins.Theselected

andoutputbuswidthseachselectablebetweenx10orx20.Bus-matchingis portwidthisappliedtobothFIFOports,suchthatbothFIFOswillbeconfigured

availableinthismode,allowingformoreflexibility.Atotaloffourindependent foreitherx10orx20buswidths.WhenwritingorreadingdatafromaFIFOthe

clock inputs are available, two RCLKs and two WCLKs. Each FIFO has numberofmemorylocationsavailabletobereadwilldependonthebuswidth

independent read and write controls– output enable controls, as well as selectedandthedensityofthedevice.

individualstatusflagsEF/OR,FF/IR,PAE,andPAF.Alsoavailableareecho

Ifthewrite/readportsare10bitswide,thisprovidestheuserwithaFIFOdepth

outputsERCLKandERENforeachindividualFIFOtoaidhigh-speedoperation of 32,768 x 10 for the IDT72T54242, 65,536 x 10 for the IDT72T54252, or

wheresynchronizingdataiscritical.

131,072x10fortheIDT72T54262.Ifthewrite/readportsare20bitswide,this

provides the user with a FIFO depth of 16,384 x 20 for the IDT72T54242,

32,768x20forthe IDT72T54252, or65,536x20forthe IDT72T54262. The

HSTL/LVTTL I/O

TheinputsandoutputsofthisdevicecanbeconfiguredforeitherLVTTLor FIFOdepthswillalwayshaveafixeddensityof327,680bitsfortheIDT72T54242,

HSTL/eHSTLoperation.IftheIOSELpinisHIGHduringmasterreset,thenall 655,360 bits for the IDT72T54252 and 1,310,072 bits for the IDT72T54262

applicable LVTTL or HSTL signals will be configured for HSTL/eHSTL regardlessofbus-widthconfigurationonthewrite/readport.Whenthedevice

operating voltage levels. To select between HSTL or eHSTL VREF must be isoperatingindoubledatarate,thewordistwiceaslargeasinsingledatarate

drivento1.5Vor1.8Vrespectively.TypicallyalogicHIGHinHSTLwouldbe sinceonewordconsistsofboththerisingandfallingedgeofclock.Therefore

VREF + 0.2V and a logic LOW would be VREF – 0.2V.

inDDR,theFIFOdepthswillbehalfofwhatitismentionedabove.Forinstance,

Ifthe IOSELpinis LOWduringmasterreset, thenallapplicable LVTTLor ifthewrite/readportis 10bits wide,thedepthofeachFIFOis 16,384x10for

HSTL signals will be configured for LVTTL operating voltage levels. In this the IDT72T54242, 32,768 x 10 for the IDT72T54252, or 65,536 x 10 for the

configurationVREFmustbesettoGND.Table5illustrateswhichpinsareand IDT72T54262.SeeFigure5,Bus-MatchinginDualmodeformoreinformation.

TABLE 5 — I/O VOLTAGE LEVEL ASSOCIATIONS

LVTTL/HSTL/eHSTL SELECT

JTAG Signal Pins

TCK

STATIC CMOS SIGNALS

Static Pins

Write Port

D[39:0]

WCLK0/1/2/3

WEN0/1/2/3

WCS0/1/2/3

FF/IR0/1/2/3

PAF0/1/2/3

Read Port

Serial Clock Port

Q[39:0]

FSEL[1:0]

PD

SCLK

SREN

SWEN

FWFT/SI

SDO

IOSEL

IW

OW

RCLK0/1/2/3

REN0/1/2/3

RCS0/1/2/3

EF/OR0/1/2/3

OE0/1/2/3

TRST

TMS

TDI

MRS

PRS0/1/2/3

FWFT/SI

MD

TDO

PFM

RDDR

WDDR

PAE0/1/2/3

ERCLK0/1/2/3

EREN0/1/2/3

NOTE:

1. In Dual mode, not all available signals will be used. Signals with a designation of 1 and 3 are not used.

21

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

D39-D30

D29-D20

D19-D10

D9-D0

D

C

B

A

Write to

FIFO 0 and FIFO 2

FIFO 2

FIFO 0

D39-D30

D29-D20

D19-D10

D9-D0

INPUT PORT BUS-WIDTH x20

OUTPUT PORT BUS-WIDTH x20

Read from

FIFO 0 and FIFO 2

D

C

B

A

IW

H

OW

H

FIFO 2

FIFO 0

(a) x20 INPUT to x20 OUTPUT

D39-D30

D29-D20

C

D19-D10

D9-D0

A

INPUT PORT BUS-WIDTH x20

OUTPUT PORT BUS-WIDTH x10

1st Read from

FIFO 0 and FIFO 2

IW

H

OW

L

FIFO 2

FIFO 0

D39-D30

D29-D20

D

D19-D10

D9-D0

B

2nd Read from

FIFO 0 and FIFO 2

FIFO 2

FIFO 0

(b) x20 INPUT to x10 OUTPUT

D39-D30

D29-D20

B

D19-D10

D9-D0

A

1st Write to

FIFO 0 and FIFO 2

FIFO 2

FIFO 0

D39-D30

D29-D20

D19-D10

D9-D0

2nd Write to

FIFO 0 and FIFO 2

D

C

FIFO 2

FIFO 0

INPUT PORT BUS-WIDTH x10

OUTPUT PORT BUS-WIDTH x10

D39-D30

D29-D20

D19-D10

D9-D0

1st Read from

B

A

FIFO 0 and FIFO 2

IW

L

OW

L

FIFO 2

FIFO 0

D39-D30

D29-D20

D19-D10

D9-D0

2nd Read from

FIFO 0 and FIFO 2

D

C

FIFO 2

FIFO 0

(c) x10 INPUT to x10 OUTPUT

D39-D30

D

D29-D20

B

D19-D10

C

D9-D0

A

INPUT PORT BUS-WIDTH x10

OUTPUT PORT BUS-WIDTH x20

Read from

FIFO 0 and FIFO 2

IW

L

OW

H

FIFO 2

FIFO 0

(d) x10 INPUT to x20 OUTPUT

6158 drw10

Figure 5. Bus-Matching in Dual mode

22

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)

SIGNALDESCRIPTIONS

Thisisadualpurposepin.Duringmasterreset,thestateoftheFWFT/SIinput

determineswhetherthedevicewilloperateinIDTStandardmodeorFirstWord

Fall Through (FWFT) mode.

INPUTS:

DATA INPUT BUS (D[39:0])

IfFWFT/SIisLOWbeforethefallingedgeofmasterreset,thenIDTStandard

modewillbeselected.ThismodeusestheEmptyFlag(EF)toindicatewhether

ornotthereareanywordspresentintheFIFOs’memory.ItalsousestheFull

Flag(FF)toindicatewhetherornottheFIFOs’memoryhasanyfreespacefor

writing.InIDTStandardmode,everywordreadfromtheFIFOs,includingthe

first,mustberequestedusingtheReadEnable(REN),ReadChipSelect(RCS)

and RCLK.

Thedatainputbussesare10bitswideinQuadmodeand20or10-bitswide

inDualmode. InQuadmode, D[9:0]are data inputs forFIFO0, D[19:10]are

forFIFO1,D[29:20]areforFIFO2,andD[39:30]areforFIFO3.InDualmode,

D[19:0]aredatainputsforFIFO0andD[39:20]areforFIFO2forthe20-bitwide

data bus. D[9:0] are data inputs for FIFO0 and D[29:20] are data inputs for

FIFO2 for the 10-bit wide data bus.

IfFWFT/SIisHIGHbeforethefallingedgeofmasterreset,thenFWFTmode

willbeselected.ThismodeusesOutputReady(OR)toindicatewhetherornot

thereisvaliddataintheoutputregister.ItalsousesInputReady(IR)toindicate

whetherornottheFIFO'smemoryhasanyfreespaceforwriting.Inotherwords,

theyaretheinverseoftheemptyandfullflags.IntheFWFTmode,thefirstword

writtentoanemptyFIFOgoesdirectlytodataoutputsafterthreeRCLKrising

edges,providedthatthefirstRCLKmeetsthetSKEWparameter.Theremaybe

a one RCLKcycle delayiftSKEW is notmet. REN andRCS donotneedtobe

enabled. Subsequent words must be accessed using the REN, RCS, and

RCLK.

MASTER RESET (MRS)

ThereisasinglemasterresetavailableforallinternalFIFOsinthisdevice.

AmasterresetisinitiatedwhenevertheMRSinputistakentoaLOWstate.This

operationsetstheinternalreadandwritepointersofallFIFOstothefirstlocation

inmemory.TheprogrammablealmostemptyflagwillgoLOWandthealmost

fullflagswillgoHIGH.

IfFWFT/SIsignalis LOWduringmasterresetthenIDTStandardmode is

selected.ThismodeutilizestheemptyandfullstatusflagsfromtheEF/ORand

FF/IRdual-purposepin.Duringmasterreset,allemptyflagswillbesettoLOW

andallfullflags willbesettoHIGH.

ThestateoftheFWFT/SIinputmustbekeptatthepresentstatefortheminimum

oftheresetrecoverytime(tRSR)aftermasterreset.Afterthistime,theFWFT/

SIactsasaserialinputforloadingPAEandPAFoffsetsintotheprogrammable

offsetregisters.TheserialinputisusedinconjunctionwithSCLK,SWEN,SREN,

andSDOtoaccesstheoffsetregisters.SerialprogrammingusingtheFWFT/

SIpinfunctions the same wayinbothIDTStandardandFWFTmodes.

If FWFT/SI signal is HIGH during master reset, then the First Word Fall

Throughmodeisselected.Thismodeutilizestheinputreadandoutputready

statusflagsfromtheEF/ORandFF/IRdual-purposepin.Duringmasterreset,

allinputreadyflags willbesettoLOWandalloutputreadyflags willbesetto

HIGH.

AlldeviceconfigurationpinssuchasMD,OW,IW,WDDR,RDDR,IOSEL,

PFM,FSEL[1:0]andFWFT/SIneedtobedefinedbeforethemasterresetcycle.

Duringamasterresettheoutputregistersareinitializedtoallzeros.Iftheoutput

enablesareLOWduringmasterreset,thentheoutputbuswillbeLOW.Ifthe

outputenable(s)areHIGHduringmasterreset,thentheoutputbuswillbein

high-impedance.RCShasnoaffectonthedataoutputsduringmasterreset.If

theoutputwidthOWisconfiguredtox10inDualmode,thentheunusedoutputs

Q[19:10]andQ[39:30]willbeinhigh-impedance.Amasterresetis required

afterpowerupbeforeawriteoperationtoanyFIFOcantakeplace.Masterreset

is an asynchronous signal and thus the read and write clocks can be free-

runningoridleduringmasterreset.SeeFigure10,MasterResetTiming,for

theassociatedtimingdiagram.

WRITE CLOCK (WCLK0/1/2/3)

Thereareapossibletotaloffourwriteclocks(ortwoinDualmode)available

in this device depending on the mode selected, each corresponding to the

individualFIFOsinmemory.Awritecanbeinitiatedontherising(orfalling)edge

oftheWCLKinput.Ifthewritedoubledatarate(WDDR)modepinistiedHIGH,

datawillbewrittenonboththerisingandfallingedgeofWCLK0/1/2/3,provided

thatWEN0/1/2/3andWCS0/1/2/3areenabledontherisingedgeofWCLK0/

1/2/3.IfWDDRistiedLOW,datawillbewrittenonlyontherisingedgeofWCLK0/

1/2/3 provided that WEN0/1/2/3 and WCS 0/1/2/3 are enabled. Each write

clockiscompletelyindependentfromtheothers.

DatasetupandholdtimesmustbemetwithrespecttotheLOW-to-HIGH(and

HIGH-to-LOWinDDR)transitionofthewriteclock.Itispermissibletostopthe

writeclocks,forasynchronousoperations.Notethatwhilethewriteclocksare

idle,theFF0/1/2/3andPAF0/1/2/3flagswillnotbeupdatedunlesstheportis

operating in asynchronous timing mode (PFM=0). The write clocks can be

independentorcoincidentwithoneanother.InDualmode,theunusedclocks

(WCLK1andWCLK3)shouldbe tiedtoGND.

PARTIAL RESET (PRS0/1/2/3)

Apartialresetisameansbywhichtheusercanresetboththereadandwrite

pointersofeachindividualFIFOinsidethedevicewithoutchangingtheFIFO's

configuration.Therearefourdedicatedpartialresetsignals(twoinDualmode)

thateachcorrespondtoanindividualFIFO.Therearenorestrictionsastowhen

partialresetcanbeperformedineitheroperatingmodes.

Duringpartialreset, the internalreadandwrite pointers are settothe first

locationinmemory,PAE goesLOWandPAFgoesHIGH.Whichevertiming

modewasactiveatthetimeofPartialResetwillremainactiveafterPartialReset.

If IDT Standard Mode is active, then FF will go HIGH and EF will go LOW. If

the FirstWordFallThroughmode is active, thenOR willgoHIGHandIRwill

goLOW.

Following Partial Reset, all values held in the offset registers remain

unchanged. The output registers are initialized to all zeros. All other

configurations set up during master reset remain unchanged. PRS is an

asynchronoussignal.SeeFigure11,PartialResetTiming,fortheassociated

timingdiagram.

WRITE ENABLE (WEN0/1/2/3)

Thereareatotaloffourwriteenables(ortwoinDualmode)availableinthis

devicedependingonthemodeselected,oneforeachindividualFIFO.When

thewriteenableinputisLOWontherisingedgeofWCLKinsingledataratemode,

data is loaded on the rising edge of every WCLK cycle, provided the device

isnotfullandthewritechipselect(WCS)isenabled.Thesetupandholdtimes

arereferencedwithrespecttotherisingedgeofWCLKonly.Whenthewrite

enable input is LOW on the rising edge of WCLK in double data rate, data is

loadedintoanyoftheFIFOsontherisingandfallingedgeofeveryWCLKcycle,

providedthedeviceisnotfullandthewritechipselect(WCS)isenabledonthe

23

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

risingedgeofWCLK.Inthismode,thedatasetupandholdtimesarereferenced areidle,theEF/0/1/2/3andPAE0/1/2/3flagswillnotbeupdatedunlessthepart

withrespecttotherisingandfallingedgeofWCLK.NotethatWENandWCS isoperatinginasynchronoustimingmode(PFM=0).Thewriteandreadclocks

are sampledonlyonthe risingedge ofWCLKineitherdata rates.

canbeindependentorcoincident.InDualmode,theunusedclocks(RCLK1

DataisstoredintheFIFOs’memorysequentiallyandindependentlyofany and RCLK3) should be tied to GND.

ongoingreadoperation.WhenthewriteenablesorwritechipselectsareHIGH,

nonewdataiswrittenintothecorrespondingFIFOoneachWCLKcycle.Each READ ENABLE (REN0/1/2/3)

writeenableoperatesindependentlyoftheothers.InDualmode,theunused

Thereareatotaloffourreadenables(ortwoinDualmode)availableinthis

write enables (WEN1 and WEN3) should be tied to VCC.

devicedependingonthemodeselected,oneforeachindividualFIFOs.When

thereadenableinputisLOWontherisingedgeofRCLKinsingledataratemode,

datawillbereadontherisingedgeofeveryRCLKcycle,providedthedevice

WRITE CHIP SELECT (WCS0/1/2/3)

There are a total of four write chip selects (or two in Dual mode) available is notemptyandthereadchipselect(RCS)is enabled.Theassociateddata

inthisdevicedependingonthemodeselected,oneforeachindividualFIFO. accesstime(tA)isreferencedwithrespecttotherisingedgeofRCLK.When

ThewritechipselectsdisablesalldatabusinputsifitisheldHIGH.Toperform thereadenableinputisLOWontherisingedgeofWCLKindoubledatarate

normalwriteoperations,thewritechipselectmustbeenabled,(heldLOW).The mode, data will be read on the rising and falling edge of every RCLK cycle,

fourwritechipselectsarecompletelyindependentofoneanother.Whenthe providedthe device is notemptyandRCS is enabled. Inthis mode, the data

writechipselectisLOWontherisingedgeofWCLKinsingledataratemode, accesstimesarereferencedwithrespecttotherisingandfallingedgesofRCLK.

data is loaded on the rising edge of every WCLK cycle, provided the device NotethatREN, andRCSaresampledonlyontherisingedgeofRCLKineither

is notfullandthe write enable (WEN)ofthe correspondingFIFOis LOW.

WhenthewritechipselectisLOWontherisingedgeofWCLKindoubledata

datarate.

DatareadfromtheFIFO'smemorysequentiallyandindependentlyofany

ratemode,datais loadedintoanyoftheFIFOs ontherisingandfallingedge ongoingwriteoperation.WhenthereadenablesorreadchipselectsareHIGH,

ofeveryWCLKcycle,providedthedeviceisnotfullandthewriteenable(WEN) no new data is read on each RCLK cycle. Each read enable operates

ofthe correspondingFIFOis LOWonthe risingclockedge.

independentlyoftheothers.

WhenthewritechipselectisHIGHontherisingedgeofWCLKinsingledata

TopreventreadingfromanemptyFIFOintheIDTStandardmode,theempty

rate mode, the write port is disabled and no words are written into the FIFO flagofeachFIFOwillgoLOWwithrespecttoRCLK,whenthetotalnumberof

memory,ontherisingedgeofWCLK, evenifWENisLOW.Ifthewritechipselect wordsintheFIFOhasbeenread,thusinhibitingfurtherreadoperations.Upon

is HIGHonthe risingedge ofWCLKindouble data rate mode, the write port thecompletionofavalidwritecycle,theemptyflagwillgoHIGHwithrespect

isdisabled andnowordsarewrittenintotheFIFOmemoryontherisingorfalling toRCLKtwocycleslater,thusallowinganotherreadtooccursimilarly,forFWFT

edgeofWCLK,evenifWENisLOW.NotethatWCSissampledontherising mode,theoutputreadyflagofeachFIFOwillgoHIGHwithrespecttoRCLK

edge of WCLK only in either data rate. In Dual mode, the unused write chip whenthetotalnumberofwordsintheFIFOhasbeenreadout.InDualmode,

selects (WCS1 and WCS3) should be tied to VCC.

the unused read enables (REN1 and REN3) should be tied to VCC.

WRITE DOUBLE DATA RATE (WDDR)

READ CHIP SELECT (RCS0/1/2/3)

Whenthewritedoubledatarate(WDDR)pinisHIGH,thewriteportwillbe

There are a total of four read chip selects (or two in Dual mode) available

settodoubledataratemode.Inthis mode,allwriteoperations arebasedon inthisdevice,eachcorrespondingtoanindividualFIFO.Thereadchipselect

therisingandfallingedgeofthewriteclocks,providedthatwriteenablesand inputsprovidesynchronouscontrolofthereadport.Whenthereadchipselect

writechipselectsareLOWfortherisingclockedges.Indoubledataratethewrite is heldLOW,thenextrisingedgeofthecorrespondingRCLKwillenablethe

enablesignalsaresampledwithrespecttotherisingedgeofwriteclockonly, outputbus.WhenthereadchipselectgoesHIGH,thenextrisingedgeofRCLK

and a word will be written to both the rising and falling edge of write clock will send the output bus into high-impedance and prevent that RCLK from

regardlessofwhetherornotwriteenableisactiveonthefallingedgeofwrite initiatingaread,regardlessofthestateofREN.Duringamasterorpartialreset

clock.

thereadchipselectinputhasnoeffectontheoutputbus–outputenableisthe

WhenWDDRisLOW,thewriteportwillbesettosingledataratemode.In onlyinputthatprovideshigh-impedancecontroloftheoutputbus.Ifoutputenable

this mode, all write operations are based on only the rising edge of the write isLOW,thedataoutputswillbeactiveregardlessofreadchipselectuntilthefirst

clocks,providedthatwriteenablesandwritechipselectsareLOWduringthe risingedgeofRCLKafteraresetiscomplete.Afterwardsifreadchipselectis

rising edge of write clock. This pin should be tied HIGH or LOW and cannot HIGH the data outputs will go to high-impedance. Each read chip select is

toggle.

completelyindependentoftheothers.

Thereadchipselectinputsdonotaffecttheupdatingoftheflags.Forexample,

whenthefirstwordiswrittentoany/allemptyFIFOs,theemptyflagswillstillgo

READ CLOCK (RCLK0/1/2/3)

There are a totaloffourreadclocks (ortwoinDualmode)available inthis fromLOWtoHIGHbasedonarisingedgeoftheRCLK,regardlessofthestate

devicedependingonthemodeselected,eachcorrespondingtotheindividual ofthereadchipselectinputs.Also,whenoperatingtheFIFOinFWFTmode

FIFOs inmemory.Areadcanbeinitiatedontherising(orfalling)edgeofthe thefirstwordwrittentoany/allemptyFIFOswillstillbeclockedthroughtothe

RCLKinput.Ifthereaddoubledatarate(RDDR)modepinistiedHIGH,data outputbusonthethirdrisingedgeofRCLK,regardlessofthestateofreadchip

willbereadonboththerisingandfallingedgeofRCLK0/1/2/3,providedthat selectinputs,assumingthatthetSKEWparameterismet.Forthisreasontheuser

REN0/1/2/3 and RCS0/1/2/3 are enabled on the rising edge of RCLK0/1/2/ shouldpayextraattentiontothereadchipselectswhenadatawordiswritten

3.IfRDDRistiedLOW,datawillbereadonlyontherisingedgeofRCLK0/1/ toany/allemptyFIFOsinFWFTmode.IfthereadchipselectinputsareHIGH

2/3providedthatREN0/1/2/3andRCS0/1/2/3areenabled.Eachreadclock whenanemptyFIFOiswritteninto,thefirstwordwillfallthroughtotheoutput

iscompletelyindependentfromtheothers.

register but will not be available on the outputs because they are in high-

Thereisanassociateddataaccesstime(tA)forthedatatobereadoutofthe impedance.TheusermustenablereadchipselectontherisingedgeofRCLK

FIFOs.Itispermissibletostopthereadclocks.Notethatwhilethereadclocks whiledisablingRENtoaccessthisfirstword.InDualmode,theunusedread

24

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

chipselects(RCS1andRCS3)shouldbetiedtoVCC.RefertoFigures23and

24,ReadCycleandReadChipSelectfortheassociatedtimingdiagrams.

• Alldataoutputsbecomeinactiveandenterhigh-impedancestate.

• Allflagoutputswillmaintaintheircurrentstatesbeforepowerdown.

• Allprogrammableflagoffsetsmaintaintheirvalues.

READ DOUBLE DATA RATE (RDDR)

• Allechoclocks andenables willbecomeinactiveandenterhigh-

impedancestate.

• TheserialprogrammingandJTAGportwillbecomeinactiveandenter

high-impedancestate.

• AllsetupandconfigurationCMOSstaticinputsarenotaffected,asthese

pins are tied to a known value and do not toggle during operation.

Allinternalcounters,registers,andflagswillremainunchangedandmaintain

Whenthereaddoubledatarate(RDDR)pintiedHIGH,thereadportwillbe

settodouble data rate mode. Inthis mode, allreadoperations are basedon

therisingandfallingedgeofthereadclocks,providedthatreadenablesand

read chip selects are LOW. In double data rate the read enable signals are

sampledwithrespecttotherisingedgeofreadclockonly,andawordwillbe

readfromboththerisingandfallingedgeofreadclockregardlessofwhether

ornotreadenable andreadchipselectare active onthe fallingedge ofread theircurrentstatepriortopowerdown.Clockinputscanbecontinuousandfree-

clock. runningduringpowerdown,butwillhavenoaffectonthepart.However,itis

WhenRDDRistiedLOW,thereadportwillbesettosingledataratemode. recommendedthattheclockinputsbelowwhenthepowerdownisactive.To

Inthismode,allreadoperationsarebasedononlytherisingedgeoftheread exitpowerdownstateandresumenormaloperations,disablethepowerdown

clocks,providedthatreadenablesandreadchipselectsareLOWduringthe signalbybringingitHIGH.Theremustbeaminimumof1µswaitingperiodbefore

risingedgeofreadclock.ThispinshouldbetiedHIGHorLOWandcannottoggle readandwriteoperationscanresume.Thedevicewillcontinuefromwhereit

beforeoraftermasterreset.

hadstoppedandnoformofresetisrequiredafterexitingpowerdownstate.The

powerdownfeaturedoesnotprovideanypowersavingswhentheinputsare

configuredforLVTTLoperation.However,itwillreducethecurrentforI/Osthat

OUTPUTENABLE(OE0/1/2/3)

There are total of four asynchronous output enables (two in Dual mode) are not tied directly to VCC or GND. See Figure 35, Power Down Operation,

availableinthisdevice,eachcorrespondingtoanindividualFIFOinmemory. fortheassociatedtimingdiagram.

WhentheoutputenableinputsareLOW,theoutputbusofeachindividualFIFO

becomesactiveanddrivesthedatacurrentlyintheoutputregister.Whenthe SERIAL CLOCK (SCLK)

outputenableinputsareHIGH,theoutputbusofeachindividualFIFOgoesinto

The serial clock is used to load and read data in the programmable offset

high-impedance.Duringmasterorpartialresettheoutputenableistheonlyinput registers.Datafromtheserialinputsignal(FWFT/SI)canbeloadedintotheoffset

thatcanplacetheoutputdatabusintohigh-impedance.Duringresettheread registers on the rising edge of SCLK provided that the serial write enable

chipselectinputhasnoeffectontheoutputdatabus.Eachoutputenableinput (SWEN)signalisLOW.Datacanbereadfromtheoffsetregistersviatheserial

iscompletelyindependentfromtheothers.InDualmode,theunusedoutput dataoutput(SDO)signalontherisingedgeofSCLKprovidedthatSRENisLOW.

enables (OE1 and OE3) should be tied to VCC.

Theserialclockcanoperateatamaximumfrequencyof10MHz.

I/O SELECT (IOSEL)

SERIAL WRITE ENABLE (SWEN)

TheinputsandoutputsofthisdevicecanbeconfiguredforeitherLVTTLor

Theserialwriteenableinputisanenableusedforserialprogrammingofthe

HSTL/eHSTLoperation.IftheIOSELpinisHIGHduringmasterreset,thenall programmable offset registers. It is used in conjunction with the serial input

applicable LVTTL or HSTL signals will be configured for HSTL/eHSTL (FWFT/SI) and serial clock (SCLK) when programming the offset registers.

operating voltage levels. To select between HSTL or eHSTL VREF must be WhentheserialwriteenableisLOW,dataattheserialinputisloadedintothe

drivento1.5Vor1.8Vrespectively.IftheIOSELpinisLOWduringmasterreset, offsetregister,onebitforeachLOW-to-HIGHtransitionofSCLK.Whenserial

thenallapplicableLVTTLorHSTLprogrammablepinswillbeconfiguredfor writeenableis HIGH,theoffsetregisters retaintheprevious settings andno

LVTTL operating voltage levels. In this configuration VREF should be set to offsetsareloaded.SerialwriteenablefunctionsthesamewayinbothStandard

GND.ThispinshouldbetiedHIGHorLOWandcannottogglebeforeorafter IDT and FWFT modes. See Figure 29, Loading of Programmable Flag

masterreset.Pleaserefertotable5foralistofLVTTL/HSTL/eHSTLprogram- Registers,forthetimingdiagram.

mablepins.

SERIAL READ ENABLE (SREN)

POWER DOWN (PD)

Theserialreadenableinputis anenableusedforreadingthevalueofthe

This device has a power down feature intended for reducing power programmableoffsetregisters.Itisusedinconjunctionwiththeserialdataoutput

consumptionforHSTL/eHSTLconfiguredinputswhenthedeviceisidlefora (SDO) and serial clock (SCLK) when reading the offset registers. When the

long period of time. By entering the power down state certain inputs can be serialreadenableisLOW,dataattheserialdataoutputcanbereadfromthe

disabled,therebysignificantlyreducingthepowerconsumptionofthepart.All offsetregister,onebitforeachLOW-to-HIGHtransitionofSCLK.Whenserial

WENandRENsignalsmustbedisabledforaminimumoffourWCLKandRCLK readenableisHIGH,thereadingoftheoffsetregisterswillstop.Wheneverserial

cycles before activating the power down signal. The power down signal is readenable(SREN)isactivated(LOW)valuesintheoffsetregistersarecopied

asynchronousandneedstobeheldLOWthroughoutthedesiredpowerdown directlyintoaserialscanoutregister.SRENmustbekeptLOWinordertoread

time.Duringpowerdown,thefollowingconditionsfortheinputs/outputssignals theentirecontentsofthescanoutregister.IfatanypointSRENistoggledHIGH,

are:

• All data in FIFO(s) memory are retained.

• Alldatainputsbecomeinactive.

anothercopyfunctionfromtheoffsetregistertotheserialscanoutregisterwill

occurthenexttimeSRENisenabled(LOW).Serialreadenablefunctionsthe

same wayinbothIDTStandardandFWFTmodes. See Figure 30, Reading

• Allwrite andreadpointers maintaintheirlastvalue before powerdown. ofProgrammableFlagRegisters,forthetimingdiagram.

• Allenables,chipselects,andclockinputpinsbecomeinactive.

25

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

andOutputReadyTiming,fortheassociatedtiminginformation.AlsoseeTable

4,StatusFlagsforFWFTModeforthetruthtableofthefullflags.Theinputready

statusnotonlymeasuresthecontentsoftheFIFOsmemory,butalsocountsthe

presenceofawordintheoutputregister.Thus,inFWFTmode,thetotalnumber

ofwritesnecessarytomakeIRLOWisonegreaterthanneededtoassertFF

in IDT Standard mode.

FF/IRissynchronousandupdatedontherisingedgeofWCLK.FF/IRare

double register-buffered outputs. Each flag operates independently of the

others.TopreventdataoverflowintheIDTStandardmode,thefullflagofeach

FIFOwillgoLOWwithrespecttoWCLK,whenthemaximumnumberofwords

hasbeenwrittenintotheFIFO,thusinhibitingfurtherwriteoperations.Uponthe

completionofavalidreadcycle,thefullflagwillgoHIGHwithrespecttoWCLK

twocycleslater,thusallowinganotherwritetooccur.

OUTPUTS:

DATA OUTPUT BUS (Q[39:0])

Thedataoutputbussesare10bitswideinQuadmodeand20or10-bitswide

inDualmode.InQuadmode,Q[9:0]aredataoutputsforFIFO0,Q[19:10]are

forFIFO1,Q[29:20]areforFIFO2,andQ[39:30]areforFIFO3.InDualmode,

Q[19:0]are data outputs forFIFO0andQ[39:20]are forFIFO2forthe 20-bit

widedatabus.Q[9:0]aredataoutputsforFIFO0andQ[29:20]aredataoutputs

for FIFO2 for the 10-bit wide data bus.

EMPTY/OUTPUTREADYFLAG(EF/0/1/2/3)

Therearefourempty/outputreadyflags(twoinDualmode)availableinthis

device,eachcorrespondingtotheindividualFIFOsinmemory.Thisisadual-

purposepinwhosefunctionisdeterminedbasedonthestateoftheFWFT/SI

pinduringmasterreset.IntheIDTStandardmode,theemptyflagsareselected.

WhenanindividualFIFOisempty,itsemptyflagwillgoLOW,inhibitingfurther

readoperations fromthatFIFO.Whentheemptyflagis HIGH,theindividual

FIFOisnotemptyandvalidreadoperationscanbeperformed.SeeFigure18,

Read Cycle, Output Enable and Empty Flag Timing, for the relevant timing

information.AlsoseeTable3,StatusFlagsforIDTStandardModeforthetruth

tableoftheemptyflags.

InFWFTmode,theoutputreadyflagsareselected.Outputreadyflags(OR)

goLOWatthesametimethatthefirstwordwrittentoanemptyFIFOappears

ontheoutputs,whichisaminimumoftworeadclockcyclesprovidedtheRCLK

andWCLKmeetsthetSKEWparameter(SeeTable6-TSKEWMeasurement).

ORstaysLOWaftertheRCLKLOW-to-HIGHtransitionsthatshiftsthelastword

from the FIFO memory to the outputs. OR goes HIGH when another read

operationisperformed,indicatingthelastwordwasread.Thepreviousdata

staysattheoutputs,furtherdatareadsareinhibiteduntilORgoesLOWagain

andanewwordappearsonthebus.SeeFigure22,ReadTimingandOutput

ReadyFlag,fortherelevanttiminginformation.AlsoseeTable4,StatusFlags

forFWFTModeforthetruthtableoftheemptyflags.Topreventreadinginthe

FWFTmode,theoutputreadyflagofeachFIFOwillgoHIGHwithrespectto

RCLK, when the total number of words has been read out of the FIFO, thus

inhibitingfurtherreadoperations.Uponthecompletionofavalidwritecycle,the

output ready flag will go LOW with respect to RCLK three cycles later, thus

indicatinganotherreadhasoccurred.

TopreventdataoverflowintheFWFTmode,theinputreadyflagofeachFIFO

willgoHIGHwithrespecttoWCLK,whenthemaximumnumberofwordshas

beenwrittenintothe FIFO, thus inhibitingfurtherwrite operations. Uponthe

completionofavalidreadcycle,theinputreadyflagwillgoLOWwithrespect

toWCLKtwocycleslater,thusallowinganotherwritetooccur.

PROGRAMMABLEALMOSTEMPTYFLAG(PAE0/1/2/3)

There are four programmable almost empty flags (two in Dual mode)

availableinthisdevice,eachcorrespondingtoanindividualFIFOinmemory.

Theprogrammablealmostemptyflagisanadditionalstatusflagthatnotifiesthe

userwhentheFIFOmemoryis nearempty.Theusermayutilizethis feature

asanearlyindicatorastowhentheFIFOwillbecomeempty.InIDTStandard

mode,PAEwillgoLOWwhentherearenwordsorlessintheFIFO.InFWFT

mode,thePAEwillgoLOWwhentherearen-1wordsorlessintheFIFO.The

offset“n”istheemptyoffsetvalue.Thedefaultsettingforthisvalueisstatedin

Table2.TherearefourinternalFIFOshencefourPAEoffsetvalues,(n0,n1,

n2, and n3).

TherearetwotimingmodesavailableforthePAEflags,selectablebythestate

of the Programmable Flag Mode (PFM) pin. If PFM is tied HIGH, then

synchronoustimingmodeisselected.IfPFMistiedLOW,thenasynchronous

timingmodeisselected.Insynchronousconfiguration,thePAEflagisupdated

ontherisingedgeofRCLK.InasynchronousPAEconfiguration,thePAEflag

isassertedLOWontheLOW-to-HIGHtransitionsoftheReadClock(RCLK).

PAEisresettoHIGHontheLOW-to-HIGHtransitionsoftheWriteClock(WCLK).

See Figures 31 and 33, Synchronous and Asynchronous Programmable

Almost-EmptyFlagTiming,fortherelevanttiminginformation.

The empty/outputreadyflags are synchronous andupdatedonthe rising

edgeofRCLK.InIDTStandardmode,theflagsaredoubleregister-buffered

outputs. In FWFT mode, the flags are triple register-buffered outputs. Each

empty flag operates independently of the others and always indicates the

respectiveFIFO’sstatus.

Eachprogrammablealmostemptyflagoperatesindependentlyoftheothers.

PROGRAMMABLE ALMOST FULL FLAG (PAF0/1/2/3)

Therearefourprogrammablealmostfullflags(twoinDualmode)available

in this device, each corresponding to the individual FIFOs in memory. The

programmablealmostfullflagisanadditionalstatusflagthatnotifiestheuserwhen

the FIFO memory is nearly full. The user may utilize this feature as an early

indicatorastowhentheFIFOwillnotbeabletoacceptanymoredataandthus

prevent data from being dropped. In IDT Standard mode, if no reads are

performed after master reset, PAF will go LOW after (D-m) (D meaning the

densityoftheparticulardevice)wordsarewrittentotheFIFO.InFWFTmode,

PAFwillgoLOWafter(D+1-m)words arewrittentotheFIFO.Theoffset“m”

isthefulloffsetvalue.ThedefaultsettingforthisvalueisstatedinTable2.There

arefourinternalFIFOshencefourPAFoffsetvalues,(m0,m1,m2,andm3).

TherearetwotimingmodesavailableforthePAFflags,selectablebythestate

of the Programmable Flag Mode (PFM) pin. If PFM is tied HIGH, then

synchronoustimingmodeisselected.IfPFMistiedLOW,thenasynchronous

timingmodeisselected.Insynchronousconfiguration,thePAFflagisupdated

ontherisingedgeofWCLK.InasynchronousPAFconfiguration,thePAFflag

FULL/INPUT READY FLAG (FF/IR/0/1/2/3)

There are four full/input ready flags (two in Dual mode) available in this

device,eachcorrespondingtotheindividualFIFOsinmemory.Thisisadual-

purposepinwhosefunctionisdeterminedbasedonthestateoftheFWFT/SI

pinduringmasterreset.IntheIDTStandardmode,thefullflagsareselected.

WhenanindividualFIFOisfull,itsfullflagswillgoLOWaftertherisingedgeof

WCLKthatwrotethelastword,thusinhibitingfurtherwriteoperationstotheFIFO.

WhenthefullflagisHIGH,theindividualFIFOisnotfullandvalidwriteoperations

can be performed. See Figure 11, Write Cycle and Full Flag Timing for the

associatedtimingdiagram.AlsoseeTable4,StatusFlagsforFWFTModefor

thetruthtableofthefullflags.

InFWFTmode,theinputreadyflagsareselected.InputreadyflagsgoLOW

whenthereisadequatememoryspaceintheFIFOsforwritingindata.Theinput

readyflagsgoHIGHaftertherisingedgeofWCLKthatwrotethelastword,when

therearenofreespacesavailableforwritingindata.SeeFigure16,WriteCycle

26

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

isassertedLOWontheLOW-to-HIGHtransitionsoftheWriteClock(WCLK).

TABLE 6 — TSKEW MEASUREMENT

PAFisresettoHIGHontheLOW-to-HIGHtransitionsoftheReadClock(RCLK).

See Figure 31 and 33, Synchronous and Asynchronous Programmable

Almost-FullFlagTiming(IDTStandardandFWFTmode),fortherelevanttiming

information.

Data Port

Status Flags

TSKEW Measurement

Datasheet

Parameter

Configuration

DDR Input

to

EF/OR

FF/IR

PAE

Negative Edge WCLK to

Positive Edge RCLK

tSKEW2

tSKEW3

Eachprogrammablealmostfullflagoperatesindependentlyoftheothers.

DDR Output

Negative Edge RCLK to

Positive Edge WCLK

ECHO READ CLOCK (ERCLK0/1/2/3)

Negative Edge WCLK to

Positive Edge RCLK

Therearefourechoreadclockoutputs(twoinDualmode)availableinthis

device,eachcorrespondingtotheirrespectiveinputreadclocksintheFIFO.

Theechoreadclockisafree-runningclockoutput,thatwillalwaysfollowthe

RCLKinputregardlessofthereadenablesandreadchipselects.TheERCLK

outputfollowstheRCLKinputwithanassociateddelay.Thisdelayprovidesthe

userwithamoreeffectivereadclocksourcewhenreadingdatafromtheoutput

bus.Thisisespeciallyhelpfulathighspeedswhenvariableswithinthedevice

maycausechangesinthedataaccesstimes.Thesevariationsinaccesstime

maybecausedbyambienttemperature,supplyvoltage,ordevicecharacteristics.

Anyvariationseffectingthedataaccesstimewillalsohaveacorresponding

effectontheechoreadclockoutputproducedbytheFIFO,thereforetheecho

readclockoutputleveltransitionsshouldalwaysbeatthesamepositionintime

relativetothedataoutputs.Note,thatechoreadclockisguaranteedbydesign

tobeslowerthantheslowestdataoutputs.RefertoFigure6,EchoReadClock

andDataOutputRelationship,Figures 25,26,and27EchoReadClockand

ReadEnable Operationfortiminginformation. Eachechoreadclockoutput

operate independently of the others and transitions with respect to the data

outputsofitsFIFO.

PAF

Negative Edge RCLK to

Positive Edge WCLK

DDR Input

to

EF/OR

FF/IR

PAE

Negative Edge WCLK to

Positive Edge RCLK

tSKEW2

tSKEW1

tSKEW3

SDR Output

Positive Edge RCLK to

Positive Edge WCLK

Negative Edge WCLK to

Positive Edge RCLK

PAF

Positive Edge RCLK to

Positive Edge WCLK

SDR Input

to

EF/OR

FF/IR

PAE

Positive Edge WCLK to

Positive Edge RCLK

tSKEW1

tSKEW2

tSKEW3

DDR Output

Negative Edge RCLK to

Positive Edge WCLK

Positive Edge WCLK to

Positive Edge RCLK

PAF

Negative Edge RCLK to

Positive Edge WCLK

RCLK

SDR Input

to

EF/OR

FF/IR

PAE

Positive Edge WCLK to

Positive Edge RCLK

tSKEW1

tSKEW3

SDR Output

Positive Edge RCLK to

Positive Edge WCLK

t

ERCLK

Positive Edge WCLK to

Positive Edge RCLK

PAF

Positive Edge RCLK to

Positive Edge WCLK

tD

t

A

Q

SLOWEST⁽³⁾

6158 drw11

NOTES:

1. REN is LOW.

2. tERCLK > tA, guaranteed by design.

3. Qslowest is the data output with the slowest access time, tA.

4. Time, tD is greater than zero, guaranteed by design.

Figure 6. Echo Read Clock and Data Output Relationship

27

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

tTCK

t1

t

2

TCK

TDI/

TMS

tDS

tDH

tDO

TDO

tDOH

t

4

TRST

6158 drw12

Notes to diagram:

t1 = tTCKLOW

t3

t2 = tTCKHIGH

t3 = tRST (reset pulse width)

t4 = tRSR (reset recovery)

Figure 7. Standard JTAG Timing

JTAG

ACELECTRICALCHARACTERISTICS

(vcc = 2.5V 5%; Tcase = 0°C to +85°C)

SYSTEMINTERFACEPARAMETERS

IDT72T54242

IDT72T54252

IDT72T54262

Parameter

Symbol

Test

Conditions Min. Max. Units

JTAGClockInputPeriod tTCK

-

100

40

50

-

ns

Parameter

Symbol Test Conditions Min. Max. Units

JTAGClockHIGH

JTAGClockLow

JTAGReset

tTCKHIGH

(1)

DataOutput

tDO

-

20

-

ns

tTCKLOW

tRST

(1)

DataOutputHold tDOH

0

DataInput

tDS

tDH

trise=3ns

tfall=3ns

10

-

JTAG Reset Recovery

tRSR

NOTE:

1. 50pf loading on external output signals.

28

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

TheStandardJTAGinterfaceconsistsoffivebasicelements:

JTAGTIMINGSPECIFICATIONS

(IEEE1149.1COMPLIANT)

TheJTAGtestportinthisdeviceisfullycompliantwiththeIEEEStandard

TestAccessPort(IEEE1149.1)specifications.Fiveadditionalpins(TDI,TDO,

TMS, TCK and TRST) are provided to support the JTAG boundary scan

interface. Note that IDT provides appropriate Boundary Scan Description

Languageprogramfilesforthesedevices.

•

Test Access Port (TAP)

TAPcontroller

Instruction Register (IR)

Data Register Port (DR)

Bypass Register(BYR)

Thefollowingsections provideabriefdescriptionofeachelement.Fora

completedescriptionrefertotheIEEEStandardTestAccessPortSpecification

(IEEEStd. 1149.1-1990).

The Figure belowshows the standardBoundary-ScanArchitecture

Incell

In Pad

Outcell

Out Pad

All inputs

Eg: Dins, Clks

(BSDL file

describes the

chain order)

Core

Logic

All outputs

TDI

ID

Bypass

TDO

Instruction

Register

TMS

TCK

Instruction

Select

Enable

TAP

TRST

6158 drw13

Figure 8. JTAG Architecture

THETAPCONTROLLER

TEST ACCESS PORT (TAP)

TheTAPcontrollerisasynchronousfinitestatemachinethatrespondsto

TMSandTCLKsignalstogenerateclockandcontrolsignalstotheInstruction

andDataRegistersforcaptureandupdatingofdatapassedthroughtheTDI

serialinput.

The TAPinterface is a general-purpose portthatprovides access tothe

internalJTAGstatemachine.Itconsistsoffourinputports(TCLK,TMS,TDI,

TRST) and one output port (TDO).

29

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

1

Test-Logic

Reset

0

Input is

TMS

1

0

1

Run-Test/

Idle

Select-

DR-Scan

Select-

IR-Scan

0

1

Capture-DR

Capture-IR

0

Shift-IR

Shift-DR

1

Exit1-IR

EXit1-DR

0

Pause-IR

Pause-DR

1

Exit2-IR

Exit2-DR

0

1

Update-IR

Update-DR

1

0

1

0

6158 drw14

NOTES:

1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.

2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by TRST or TMS).

3. TAP controller must be reset before normal FIFO operations can begin.

Figure 9. TAP Controller State Diagram

Refer to the IEEE Standard Test Access Port Specification (IEEE Std.

1149.1)forthefullstatediagram

Capture-IRInthiscontrollerstate,theshiftregisterbankintheInstruction

RegisterparallelloadsapatternoffixedvaluesontherisingedgeofTCK.The

AllstatetransitionswithintheTAPcontrolleroccurattherisingedgeofthe lasttwosignificantbits arealways requiredtobe“01”.

TCLKpulse. The TMSsignallevel(0or1)determines the state progression

Shift-IR In this controller state, the instruction register gets connected

thatoccursoneachTCLKrisingedge.TheTAPcontrollertakesprecedence betweenTDIandTDO,andthecapturedpatterngetsshiftedoneachrisingedge

over the FIFO memory and must be reset after power up of the device. See ofTCK.TheinstructionavailableontheTDIpinisalsoshiftedintotheinstruction

TRSTdescriptionformoredetailsonTAPcontrollerreset.

Test-Logic-ResetAlltestlogicisdisabledinthiscontrollerstateenablingthe

register.

Exit1-IRThisisacontrollerstatewhereadecisiontoentereitherthePause-

normaloperationoftheIC.TheTAPcontrollerstatemachineisdesignedinsuch IRstateorUpdate-IRstateismade.

awaythat,nomatterwhattheinitialstateofthecontrolleris,theTest-Logic-Reset

Pause-IRThis state is providedinordertoallowthe shiftingofinstruction

statecanbeenteredbyholdingTMSathighandpulsingTCKfivetimes.This registertobetemporarilyhalted.

is the reason why the Test Reset (TRST) pin is optional.

Exit2-DRThisisacontrollerstatewhereadecisiontoentereithertheShift-

Run-Test-IdleInthiscontrollerstate,thetestlogicintheICisactiveonlyif IRstateorUpdate-IRstateismade.

certaininstructionsarepresent.Forexample,ifaninstructionactivatestheself

Update-IRInthiscontrollerstate,theinstructionintheinstructionregisteris

test,thenitwillbeexecutedwhenthecontrollerentersthisstate.Thetestlogic latchedintothelatchbankoftheInstructionRegisteroneveryfallingedgeof

intheICis idles otherwise.

Select-DR-ScanThis is a controllerstate where the decisiontoenterthe

DataPathortheSelect-IR-Scanstateismade.

TCK.Thisinstructionalsobecomesthecurrentinstructiononceitislatched.

Capture-DRInthiscontrollerstate,thedataisparallelloadedintothedata

registersselectedbythecurrentinstructionontherisingedgeofTCK.

Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These

Select-IR-Scan This is a controller state where the decision to enter the

InstructionPathismade.TheControllercanreturntotheTest-Logic-Resetstate controllerstates are similartothe Shift-IR, Exit1-IR, Pause-IR, Exit2-IRand

otherwise. Update-IRstatesintheInstructionpath.

30

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

THE INSTRUCTION REGISTER

JTAG INSTRUCTION REGISTER

TheInstructionregisterallowsinstructiontobeseriallyinputintothedevice

whentheTAPcontrollerisintheShift-IRstate.Theinstructionisdecodedto

performthefollowing:

TheInstructionregisterallowsaninstructiontobeshiftedinseriallyintothe

processor at the rising edge of TCLK.

TheInstructionis usedtoselectthetesttobeperformed,orthetestdata

registertobeaccessed,orboth.Theinstructionshiftedintotheregisterislatched

atthecompletionoftheshiftingprocesswhentheTAPcontrollerisatUpdate-

IRstate.

Theinstructionregistermustcontain4bitinstructionregister-basedcells

whichcanholdinstructiondata.Thesemandatorycellsarelocatednearestthe

serialoutputstheyaretheleastsignificantbits.

•

Selecttestdataregistersthatmayoperatewhiletheinstructionis

current.Theothertestdataregistersshouldnotinterferewithchip

operationandtheselecteddataregister.

Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween

TDI and TDO during data register scanning.

•

The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode

16differentpossibleinstructions.Instructionsaredecodedasfollows.

TESTDATAREGISTER

Hex

Instruction

Function

TheTestDataregistercontainsthreetestdataregisters:theTestBypass

register, the Boundary Scan register and Device ID register.

Theseregistersareconnectedinparallelbetweenacommonserialinput

andacommonserialdataoutput.

Thefollowingsections provideabriefdescriptionofeachelement.Fora

completedescription,refertotheIEEEStandardTestAccessPortSpecification

(IEEEStd. 1149.1-1990).

Value

0000 EXTEST

0001 SAMPLE/PRELOAD Selectboundaryscanregister

0002 IDCODE

0003 CLAMP

0004 HI-IMPEDANCE

0007 OFFSET READ

0008 OFFSETWRITE

000F BYPASS

Private

Testexternalpins

Selectschipidentificationregister

Fixtheoutputchains toscanchainvalues

Putsalloutputsinhigh-impedancestate

ReadPAE/PAFoffsetregistervalues

WritePAE/PAFoffsetregistervalues

Selectbypassregister

Severalcombinations are private (forIDT

internaluse). Donotuse codes otherthan

thoseidentifiedabove.

Test Bypass Register

TheregisterisusedtoallowtestdatatoflowthroughthedevicefromTDI

toTDO.Itcontainsasinglestageshiftregisterforaminimumlengthinserialpath.

Whenthebypassregisterisselectedbyaninstruction,theshiftregisterstage

is settoa logiczeroonthe risingedge ofTCLKwhenthe TAPcontrolleris in

theCapture-DRstate.

JTAG Instruction Register Decoding

Thefollowingsectionsprovideabriefdescriptionofeachinstruction.For

acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification

(IEEEStd. 1149.1-1990).

The operation of the bypass register should not have any effect on the

operationofthedeviceinresponsetotheBYPASSinstruction.

The Boundary-Scan Register

EXTEST

TheBoundaryScanRegisterallowsserialdataTDIbeloadedintoorread

outoftheprocessorinput/outputports.TheBoundaryScanRegisterisapart

oftheIEEE1149.1-1990StandardJTAGImplementation.

TherequiredEXTESTinstructionplacestheICintoanexternalboundary-

testmodeandselectstheboundary-scanregistertobeconnectedbetweenTDI

andTDO. Duringthis instruction, theboundary-scanregisteris accessedto

drivetestdataoff-chipviatheboundaryoutputsandreceivetestdataoff-chip

viatheboundaryinputs.Assuch,theEXTESTinstructionistheworkhorseof

IEEE.Std1149.1,providingforprobe-lesstestingofsolder-jointopens/shorts

andoflogicclusterfunction.

The Device Identification Register

The Device IdentificationRegisteris a ReadOnly32-bitregisterusedto

specify the manufacturer, part number and version of the processor to be

determinedthroughtheTAPinresponsetotheIDCODEinstruction.

IDTJEDECIDnumberis0xB3.Thistranslatesto0x33whentheparityis

droppedinthe11-bitManufacturerIDfield.

SAMPLE/PRELOAD

TherequiredSAMPLE/PRELOADinstructionallows theICtoremainina

normalfunctionalmodeandselectstheboundary-scanregistertobeconnected

betweenTDIandTDO.Duringthisinstruction,theboundary-scanregistercan

beaccessedviaadatescanoperation,totakeasampleofthefunctionaldata

enteringandleavingtheIC.Thisinstructionisalsousedtopreloadtestdatainto

theboundary-scanregisterbeforeloadinganEXTESTinstruction.

FortheIDT72T54242/72T54252/72T54262,thePartNumberfieldcon-

tainsthefollowingvalues:

Device

Part# Field

4C5 (hex)

4C6 (hex)

4C7 (hex)

IDT72T54242

IDT72T54252

IDT72T54262

IDCODE

TheoptionalIDCODEinstructionallowstheICtoremaininitsfunctionalmode

andselectstheoptionaldeviceidentificationregistertobeconnectedbetween

TDIandTDO.Thedeviceidentificationregisterisa32-bitshiftregistercontaining

information regarding the IC manufacturer, device type, and version code.

Accessingthedeviceidentificationregisterdoesnotinterferewiththeoperation

oftheIC.Also,accesstothedeviceidentificationregistershouldbeimmediately

available,viaaTAPdata-scanoperation,afterpower-upoftheICorafterthe

TAPhasbeenresetusingtheoptionalTRSTpinorbyotherwisemovingtothe

Test-Logic-Resetstate.

31(MSB)

28 27

12 11

1 0(LSB)

Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)

0X0

00B3 (hex)

1

IDT72T54242/252/262 JTAG Device Identification Register

31

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

CLAMP

The optional CLAMP instruction sets the outputs of an IC to logic levels

OFFSET READ

Thisinstructionisanalternativetoserialreadingtheoffsetregistersforthe

determinedbythecontentsoftheboundary-scanregisterandselectstheone- PAE/PAFflags.Whenreadingtheoffsetregistersthroughthisinstruction,the

bitbypassregistertobeconnectedbetweenTDIandTDO.Beforeloadingthis dedicatedserialprogrammingsignalsmustbedisabled.

instruction,thecontentsoftheboundary-scanregistercanbepresetwiththe

SAMPLE/PRELOADinstruction.Duringthis instruction,datacanbeshifted OFFSET WRITE

throughthebypassregisterfromTDItoTDOwithoutaffectingtheconditionof

theoutputs.

Thisinstructionisanalternativetoserialprogrammingtheoffsetregistersfor

thePAE/PAFflags.Whenwritingtheoffsetregistersthroughthisinstruction,the

dedicatedserialprogrammingsignalsmustbedisabled.

HIGH-IMPEDANCE

TheoptionalHigh-Impedanceinstructionsetsalloutputs(includingtwo-state BYPASS

aswellasthree-statetypes)ofanICtoadisabled(high-impedance)stateand

The required BYPASS instruction allows the IC to remain in a normal

selects the one-bit bypass register to be connected between TDI and TDO. functional mode and selects the one-bit bypass register to be connected

Duringthisinstruction,datacanbeshiftedthroughthebypassregisterfromTDI between TDI and TDO. The BYPASS instruction allows serial data to be

toTDOwithoutaffectingtheconditionoftheICoutputs.

transferredthroughtheICfromTDItoTDOwithoutaffectingtheoperationof

theIC.

32

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

tRS

MRS

t

RSR

t

RSS

WEN0/1/2/3⁽⁶⁾

REN0/1/2/3⁽⁶⁾

t

SWEN,

SREN

t

RSS

HIGH = Quad mode

LOW = Dual mode

MD⁽³⁾

t

OW⁽³⁾

,

IW⁽³⁾

HIGH = Synchronous PAE/PAF Timing

LOW = Asynchronous PAE/PAF Timing

PFM⁽³⁾

tRSS

HIGH = Read/Write Double Data Rate

LOW = Read/Write Single Data Rate

RDDR⁽³⁾

,

WDDR⁽³⁾

tRSS

HIGH = FWFT Mode

FWFT/SI⁽³⁾

LOW = IDT Standard Mode

t

RSS

HIGH = HSTL I/Os

LOW = LVTTL I/Os

IOSEL⁽³⁾

t

FSEL[1:0]⁽³⁾

tRSF

If FWFT = HIGH, OR = HIGH

If FWFT = LOW, EF = LOW

EF/OR⁽⁶⁾

0/1/2/3

If FWFT = LOW, FF = HIGH

If FWFT = HIGH, IR = LOW

FF/IR⁽⁶⁾

0/1/2/3

PAF⁽⁶⁾

0/1/2/3

PAE⁽⁶⁾

0/1/2/3

tRSF

OE = HIGH

OE = LOW

Q[39:0]⁽⁷⁾

6158 drw15

NOTES:

1. OE can be toggled during master reset. During master reset, the high-impedance control of the Qn data outputs are provided by OE only.

2. RCLK(s), WCLK(s) and SCLK(s) can be free running or idle.

3. The state of these pins are latched when the master reset pulse is LOW.

4. JTAG flag should not toggle during master reset.

5. RCS and WCS can be HIGH or LOW until the first rising edge of RCLK after master reset is complete.

6. If Dual mode is selected, only the signals designated with a "0" or "2" are used.

7. If Dual mode is selected, outputs Q[19:10] and Q[39:30] are not used if outputs are configured to x10.

Figure 10 . Master Reset Timing

33

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

tRS

PRS

t

RSR

t

RSS

WEN

REN

t

SWEN,

SREN

t

RSF

If FWFT = HIGH, OR = HIGH

If FWFT = LOW, EF = LOW

EF/OR

FF/IR

PAF

t

If FWFT = LOW, EF = HIGH

If FWFT = HIGH, IR = LOW

t

RSF

t

PAE

tRSF

OE = HIGH

OE = LOW

Q[39:0]⁽³⁾

6158 drw16

NOTES:

1. This timing diagram shows the partial reset timing for a single FIFO. Each PRS is independent of the others.

2. During partial reset the high-impedance control of the Qn data outputs are provided by OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after master reset.

3. If Dual mode is selected, outputs Q[19:10] and Q[39:30] are not used if outputs are configured to x10.

Figure 11. Partial Reset Timing

34

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

t

CLK

tCLKH

t

CLKL

NO WRITE

2

WCLK0

D[9:0]

1

(2)

2

(2)

t

SKEW1

tDH

t

SKEW1

tDS

tDH

tDS

WX+1

WX

tWFF

FF0

WEN0

RCLK0

tENS

tENH

REN0

RCS0

tENS

t

A

tA

Q[9:0]

NEXT DATA READ

DATA READ

6158 drw17

tRCSLZ

NOTES:

1. The timing diagram shown is for FIFO0. FIFO1-3 exhibits the same behavior.

2. tSKEW1 is the minimum time between a rising RCLK0 edge and a rising WCLK0 edge to guarantee that FF0 will go HIGH (after one WCLK0 cycle plus tWFF). If the time between

the rising edge of the RCLK0 and the rising edge of the WCLK0 is less than tSKEW1, then the FF0 deassertion may be delayed one extra WCLK0 cycle. (See Table 6 - TSKEW

measurement).

3. OE0 = LOW, and WCS0 = LOW.

4. WCLK0 must be free running for FF0 to update.

5.

MD

1

IW

OW

D/C

WDDR RDDR FWFT/SI

D/C

0

Figure 12. Write Cycle and Full Flag Timing (Quad mode, IDT Standard mode, SDR to SDR)

35

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

36

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

37

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

38

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

39

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

40

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

tCLK

tCLKH

tCLKL

RCLK0

REN0

EF0

1

2

tENS

tENH

tENS

t

ENH

tENS

t

ENH

NO OPERATION

tREF

tA

Q[9:0]

W

X+1

WX-1

WX

tOLZ

tOHZ

tOE

OE0

(2)

tSKEW1

WCLK0

tENS

tENH

tENS

WEN0

tENS

tENH

WCS0

tDS

tDH

tDS

WX+1

D[9:0]

WX

6158 drw23

NOTES:

1. The timing diagram shown is for FIFO0. FIFO1-3 exhibits the same behavior.

2. tSKEW1 is the minimum time between a rising WCLK0 edge and a rising RCLK0 edge to guarantee that EF0 will go HIGH (after one RCLK0 cycle plus tREF). If the time between

the rising edge of WCLK0 and the rising edge of RCLK0 is less than tSKEW1, then EF0 deassertion may be delayed one extra RCLK0 cycle. (See Table 6 - TSKEW measurement)..

3. First data word latency = tSKEW1 + 1*TRCLK + tREF.

4. RCS0 = LOW.

5. RCLK0 must be free running for EF0 to update.

6.

MD

1

IW

OW

D/C

WDDR RDDR FWFT/SI

D/C

0

Figure 18. Read Cycle, Output Enable and Empty Flag Timing (Quad mode, IDT Standard mode, SDR to SDR)

41

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

42

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

43

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

44

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

45

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

46

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

tCLK

tCLKH

tCLKL

2

1

RCLK0

REN0

RCS0

t

ENS

tENS

tENH

t

ENS

tENH

tREF

EF0

tRCSHZ

t

A

tA

tRCSLZ

LAST DATA-1

LAST DATA

Q[9:0]

t

SKEW1⁽²⁾

WCLK0

tENS

tENH

WEN0

tDS

tDH

D[9:0]

Dx

6158 drw29

NOTES:

1. The timing diagram shown is for FIFO0. FIFO1-3 exhibit the same behavior.

2. tSKEW1 is the minimum time between a rising WCLK0 edge and a rising RCLK0 edge to guarantee that EF0 will go HIGH (after one RCLK0 cycle plus tREF). If the time between

the rising edge of WCLK0 and the rising edge of RCLK0 is less than tSKEW1, then EF0 deassertion may be delayed one extra RCLK0 cycle.

3. First data word latency = tSKEW1 + 1*TRCLK + tREF.

4. OE0 = LOW.

5. RCLK0 must be free running for EF0 to update.

6.

MD

1

IW

OW

D/C

WDDR RDDR FWFT/SI

D/C

0

Figure 24. Read Cycle and Read Chip Select (Quad mode, IDT Standard mode, SDR to SDR)

47

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

48

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

49

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

WCLK0

tENS

tENH

WEN0

tDS

tDH

tDS

tDH

tDS

tDH

Wn+1

Wn+2

Wn+3

D[9:0]

tSKEW1

1

2

RCLK0

b

e

h

a

d

g

c

i

f

tERCLK

ERCLK0

tENS

tENH

REN0

RCS0

tENS

tCLKEN

EREN0

Q[9:0]

OR0

t

A

tA

t

RCSLZ

HIGH-Z

W

n+1

Wn+2

Wn+3

tREF

t

REF

t

A

tA

O/P

Reg.

Wn

Last Word

Wn+1

W

n+2

Wn+3

6158 drw32

NOTE:

1. The timing diagram shown is for FIFO0. FIFO1-3 exhibit the same behavior.

2. The O/P Register is the internal output register. Its contents are available on the Qn output bus only when RCS0 and OE0 are both active, LOW, that is the bus is not in High-

Impedance state.

3. OE0 is LOW.

Cycle:

a&b. At this point the FIFO is empty, OR0 is HIGH.

RCS0 and REN0 are both disabled, the output bus is High-Impedance.

c.

Word Wn+1 falls through to the output register, OR0 goes active, LOW.

RCS0 is HIGH, therefore the Qn outputs are High-Impedance. EREN0 goes LOW to indicate that a new word has been placed on the output register.

EREN0 goes HIGH, no new word has been placed on the output register on this cycle.

No Operation.

RCS0 is LOW on this cycle, therefore the Qn outputs go to Low-Impedance and the contents of the output register (Wn+1) are made available.

NOTE: In FWFT mode is important to take RCS0 active LOW at least one cycle ahead of REN0, this ensures the word (Wn+1) currently in the output register is made

available for at least one cycle.

d.

e.

f.

g.

h.

i.

REN0 goes active LOW, this reads out the second word, Wn+2.

EREN0 goes active LOW to indicate a new word has been placed into the output register.

Word Wn+3 is read out, EREN0 remains active, LOW indicating a new word has been read out.

NOTE: Wn+3 is the last word in the FIFO.

This is the next enabled read after the last word, Wn+3 has been read out. OR0 flag goes HIGH and EREN0 goes HIGH to indicate that there is no new word available.

4. OE0 is LOW, WDDR = LOW, and RDDR = LOW.

Figure 27. Echo RCLK and Echo Read Enable Operation (Quad mode, FWFT mode, SDR to SDR)

50

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

RCLK0

tERCLK

ERCLK0

tENS

tENH

REN0

tENS

RCS0

tCLKEN

EREN0

tREF

EF0

t

A

OLZ

tA

t

A

t

Q[9:0]

WD-1

W

D Last Word

6158 drw33

NOTES:

1. The timing diagram shown is for FIFO0. FIFO1-3 exhibit the same behavior.

2. The EREN0 output is LOW if RCS0 and REN0 are LOW on the rising RCLK0 edge provided that the FIFO is not empty. If the FIFO is empty, EREN0 will go HIGH to indicate that

there is no new word available.

3. The EREN0 output is synchronous to RCLK0.

4. OE0 = LOW.

5.

MD

1

IW

OW

D/C

WDDR RDDR FWFT/SI

D/C

0

Figure 28. Echo Read Clock and Read Enable Operation (Quad mode, IDT Standard mode, SDR to SDR)

51

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

52

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

tCLKL

WCLK0

1

2

1

tENS

tENH

WEN0

PAF0

tPAFS

D - m0 words in FIFO⁽²⁾

D-(m0+1) words

in FIFO⁽²⁾

D - (m0 +1) words in FIFO⁽²⁾

t

SKEW3⁽⁴⁾

RCLK0

tENH

tENS

6158 drw36

REN0

NOTES:

1. The timing diagram shown is for FIFO0. FIFO1-3 exhibit the same behavior.

2. m0 = PAF0 offset .

2. D = maximum FIFO depth. For density of FIFO with bus-matching, refer to the bus-matching section on page 19.

4. tSKEW3 is the minimum time between a rising RCLK0 edge and a rising WCLK0 edge to guarantee that PAF0 will go HIGH (after one WCLK0 cycle plus tPAFS). If the time

between the rising edge of RCLK0 and the rising edge of WCLK0 is less than tSKEW2, then the PAF0 deassertion time may be delayed one extra WCLK0 cycle.

5. PAF0 is asserted and updated on the rising edge of WCLK0 only.

6. RCS0 = LOW, and WCS0 = LOW.

7.

MD

1

IW

OW

D/C

WDDR RDDR

PFM

1

D/C

0

Figure 31. Synchronous Programmable Almost-Full Flag Timing (Quad mode, IDT Standard and FWFT mode, SDR to SDR)

tCLKH

tCLKL

WCLK0

tENS

tENH

WEN0

PAE0

n0 words in FIFO⁽³⁾

n0 + 1 words in FIFO⁽⁴⁾

,

n0 words in FIFO⁽³⁾

n0 + 1 words in FIFO⁽⁴⁾

,

n0 + 1 words in FIFO⁽³⁾

n0 + 2 words in FIFO⁽⁴⁾

,

SKEW3⁽⁵⁾

tPAES

t

1

2

1

2

RCLK0

tENS

tENH

6158 drw37

REN0

NOTES:

1. The timing diagram shown is for FIFO0. FIFO1-3 exhibit the same behavior.

2. n0 = PAE0 offset.

3. For IDT Standard mode

4. For FWFT mode.

5. tSKEW3 is the minimum time between a rising WCLK0 edge and a rising RCLK0 edge to guarantee that PAE

0

will go HIGH (after one RCLK0 cycle plus tPAES). If the time between

the rising edge of WCLK0 and the rising edge of RCLK0 is less than tSKEW3, then the PAE

6. PAE0 is asserted and updated on the rising edge of RCLK0 only.

7. RCS0 = LOW, and WCS0 = LOW.

0 deassertion may be delayed one extra RCLK0 cycle.

8.

MD

1

IW

OW

D/C

WDDR RDDR

PFM

1

D/C

0

Figure 32. Synchronous Programmable Almost-Empty Flag Timing (Quad mode, IDT Standard and FWFT mode, SDR to SDR)

53

FEBRUARY11,2009

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

tCLKH

tCLKL

WCLK0

tENS

tENH

WEN0

PAF0

tPAFA

D - m0 words

in FIFO

D - (m0 + 1) words

in FIFO

D - (m0 + 1) words in FIFO

tPAFA

RCLK0

tENS

REN0

6158 drw38

NOTES:

1. The timing diagram shown is for FIFO0. FIFO1-3 exhibit the same behavior.

2. m0 = PAF0 offset.

3. D = maximum FIFO depth. For density of FIFO with bus-matching, refer to the bus-matching section on page 19.

4. PAF0 is asserted to LOW on WCLK0 transition and reset to HIGH on RCLK0 transition.

5. RCS0 = LOW, and WCS0 = LOW.

6.

MD

1

IW

OW

D/C

WDDR RDDR

PFM

0

D/C

0

Figure 33. Asynchronous Programmable Almost-Full Flag Timing (Quad mode, IDT Standard and FWFT mode, SDR to SDR)

tCLKH

tCLKL

WCLK0

tENS

tENH

WEN0

(3)

tPAEA

(3)

n0 words in FIFO

,

n0 words in FIFO

,

(3)

n0 + 1 words in FIFO

n 0+ 2 words in FIFO

,

(4)

PAE0

(4)

n0 + 1 words in FIFO

(4)

tPAEA

RCLK0

tENS

REN0

6158 drw39

NOTES:

1. The timing diagram shown is for FIFO0. FIFO1-3 exhibit the same behavior.

2. n0 = PAE0 offset.

3. For IDT Standard Mode.

4. For FWFT Mode.

5. PAE0 is asserted LOW on RCLK0 transition and reset to HIGH on WCLK0 transition.

6. RCS0 = LOW, and WCS0 = LOW.

7.

MD

1

IW

OW

D/C

WDDR RDDR

PFM

0

D/C

0

Figure 34. Asynchronous Programmable Almost-Empty Flag Timing (Quad mode, IDT Standard and FWFT mode, SDR to SDR)

54

FEBRUARY11,2009

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IDT72T54242/72T54252/72T542622.5VQUAD/DUALTeraSync™DDR/SDRFIFO

32K x 10 x 4/16K x 20 x 2, 64K x 10 x 4/32K x 20 x 2 and 128K x 10 x 4/64K x 20 x 2

WCLK

WEN

tDH

tDS

tDH

tDS

tDH

tDS

WD10

WD11

WD12

WD13

D[39:0]

1ns

(1)

3

1

2

4

RCLK

REN

(7)

PDHZ

(2)

t

tPDLZ

tA

Hi-Z

WD1

WD2

WD3

WD4

WDH

WDS

Q[39:0]

(2)

PDH

t

(2)

PDH

t

tPDL

PD

tERCLK

Hi-Z

ERCLK

tEREN

EREN

6158 drw40

NOTES:

1. All read and write operations must have ceased a minimum of 4 WCLK and 4 RCLK cycles before power down is asserted. REN and WEN must be held HIGH during this interval.

2. When the PD input becomes deasserted, there will be a 1µs waiting period before read and write operations can resume.

All input and output signals will also resume after this time period.

3. Setup and configuration static inputs are not affected during power down.

4. Serial programming and JTAG programming port are inactive during power down.

5. RCS = 0, WCS = 0 and OE = 0. These signals can toggle during and after power down.

6. All flags remain active and maintain their current states.

7. During power down, all outputs will be in high-impedance.

Figure 35. Power Down Operation

55

FEBRUARY11,2009

ORDERINGINFORMATION

XXXXX

X

XX

X

Process /

Temperature

Range

Device Type

Power

Speed

Package

BLANK

I⁽¹⁾

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

Green

G

Plastic Ball Grid Array (PBGA, BB324-1)

BB

Clock Cycle Time (tCLK

Speed in Nanoseconds

)

5

6-7

Commercial Only

Commercial and Industrial

L

Low Power

72T54242

72T54252

72T54262

32,768 x 10 x 4/32,768 x 10 x 2 ⎯ 2.5V Quad/Dual TeraSync^TMDDR/SDR FIFO

65,536 x 10 x 4/65,536 x 10 x 2 ⎯ 2.5V Quad/Dual TeraSync^TMDDR/SDR FIFO

131,072 x 10 x 4/131,072 x 10 x 2 ⎯ 2.5V Quad/Dual TeraSync^TMDDR/SDR FIFO

6158 drw41

NOTES:

1. Industrial temperature range product for the 6-7 speed grade is available as a standard device. All other speed grades available by special order.

2. Green parts available. For specific speeds contact your sales office.

DATASHEETDOCUMENTHISTORY

12/01/2003

03/22/2005

02/11/2009

pgs. 1, 6, 13, 27, and 30.

pgs. 1, 4, 7, 12-15 and 56.

pgs. 1 and 56.

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

for Tech Support:

408-360-1753

email:FIFOhelp@idt.com

800-345-7015 or 408-284-8200

fax: 408-284-2775

www.idt.com

56


型号：	72T54262L6-7BB
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	PBGA-324, Tray
文件：	总56页 (文件大小：535K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

72T54262L6-7BB [IDT]

相关型号：

72T54262L6-7BBG

72T54262L6-7BBGI

72T55248L5BB

72T55248L5BBI

72T55248L6-7BBI

72T55258L5BBI

72T55258L6-7BB

72T55258L6-7BBI

72T55268L5BB

72T55268L5BBI

72T55268L6-7BBI

72T631S12BCG