72T55268L5BB_技术文档

2.5VQUADMUXDDRFLOW-CONTROLDEVICE

WITHMUX/DEMUX/BROADCASTFUNCTIONS

8,192 x 40 x 4

IDT72T55248

IDT72T55258

IDT72T55268

16,384 x 40 x 4

32,768 x 40 x 4

•

Demux Mode offers 1:4 architecture

- Five discrete clock domains, one write clock and four read clocks

FEATURES

•

Choose from among the following memory organizations:

IDT72T55248 - 8,192 words, 40-bits/word maximum, 4 Sequential

Queues total

- Four separate read ports, read data from four independent Queues

- One single write port, capable of writing to any four Queues

- Selectable single or double data rate on read and write ports

- 10-bit wide read ports in single data rate, doubles internally in double

data rate

- 40-bit wide write port, doubles internally in double data rate,

selectable between the four independent Queues

- Bus Matching on the Write Port x10/x20/x40 (SDR/DDR)

- Fully independent status flags for every Queue

- Composite Full/Input Ready Flag monitors currently selected Queue

- Dedicated partial reset for every Queue

Broadcast Write Mode offers, 1:4 architecture (with simultaneous

writes to all Queues)

- Five discrete clock domains, one write clock and four read clocks

- Four separate read ports, read data from four independent Queues

- One single write port, writes to all four independent Queues

simultaneously

IDT72T55258 - 16,384 words, 40-bits/word maximum, 4 Sequential

Queues total

IDT72T55268 - 32,768 words, 40-bits/word maximum, 4 Sequential

Queues total

•

User Selectable Mux / Demux / Broadcast Write Modes

Mux Mode offers 4:1 architecture

- Five discrete clock domains, four write clocks and one read clock

- Four separate write ports, writes data to four independent Queues

- One single read port, capable of reading from any four Queues

- Selectable single or double data rate (SDR/DDR) on read and write

ports

•

- 10-bit wide write ports in single data rate, doubles internally in double

data rate

- 40-bit wide read port, doubles internally in double data rate,

selectable between the four independent Queues

- Bus Matching on the Read Port x10/x20/x40 (SDR/DDR)

- Fully independent status flags for every Queue

- Composite Empty/OutputReadyFlagmonitors currentlyselected

Queue

- 10-bit wide read ports in single data rate, doubles internally in double

data rate

- 40-bit wide write port, doubles internally in double data rate

- Selectable single or double data rate on read and write ports

- Bus-Matching on the write port x10/x20/x40 (SDR/DDR)

- Dedicated partial reset for every Queue

FUNCTIONALBLOCKDIAGRAMS

Mux Mode

WCLK0

RCLK0

REN0

RCS0

WEN0

WCS0

D[9:0]

Queue 0

Data In

8,192 x 40

16,384 x40

32,768 x 40

10

OE0

Queue 0

Queue 1

WCLK1

WEN1

WCS1

OS[1:0]

2

Queue 1

8,192 x 40

16,384 x40

32,768 x 40

Data In D[19:10]

x10,x20,x40

WCLK2

WEN2

WCS2

Data Out

Q[39:0]

Queue 2

8,192 x 40

16,384 x40

32,768 x 40

Data In D[29:20]

Queue 2

Queue 3

WCLK3

WEN3

WCS3

Queue 3

Data In

8,192 x 40

16,384 x40

32,768 x 40

D[39:30]

10

EF0/OR0

PAE0

EF1/OR1

FF0/IR0

PAF0

FF1/IR1

PAE1

PAF1

FF2/ IR2

PAF2

FF3/IR3

PAF3

EF2/OR2

PAE2

EF3/OR3

PAE3

CEF/COR

6157 drw01

(See next pages for Demux and Broadcast modes)

IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

FEBRUARY 2009

1

©

DSC-6157/5

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

Table of Contents

Features ...................................................................................................................................................................................................................... 1,4

Description ...................................................................................................................................................................................................................... 6

Pin Configuration ............................................................................................................................................................................................................. 8

Pin Descriptions.......................................................................................................................................................................................................... 9-13

Device Characteristics ................................................................................................................................................................................................... 15

DC Electrical Characteristics .......................................................................................................................................................................................... 16

AC Electrical Characteristics ........................................................................................................................................................................................... 17

ACTest Conditions ........................................................................................................................................................................................................ 18

Functional Description .............................................................................................................................................................................................. 20-29

Signal Descriptions ................................................................................................................................................................................................... 30-33

JTAGTiming Specifications ....................................................................................................................................................................................... 36-40

List of Tables

Table 1 — Device Configuration .................................................................................................................................................................................... 20

Table 2 — Default Programmable Flag Offsets................................................................................................................................................................ 20

Table 3 — Status Flags for IDT Standard mode ............................................................................................................................................................. 23

Table 4 — Status Flags for FWFT mode ........................................................................................................................................................................ 23

Table 5 — I/O Voltage LevelAssociations ....................................................................................................................................................................... 24

Table 6 —TSKEW Measurement .................................................................................................................................................................................. 34

FEBRUARY01,2009

2

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

List of Figures

Figure 1. QuadMux Block Diagram.................................................................................................................................................................................. 7

Figure 2a. AC Test Load................................................................................................................................................................................................ 18

Figure 2b. Lumped Capacitive Load, Typical Derating ................................................................................................................................................... 18

Figure 3. Programmable Flag Offset Programming Methods ........................................................................................................................................... 21

Figure 4. Offset Registers Serial Bit Sequence................................................................................................................................................................ 22

Figure 5. Bus-Matching ByteArrangement (Mux, DeMux and Broadcast Mode) ....................................................................................................... 25-27

Figure 6. Echo Read Clock and Data Output Relationship .............................................................................................................................................. 35

Figure 7. Standard JTAG Timing ................................................................................................................................................................................... 36

Figure 8. JTAGArchitecture ........................................................................................................................................................................................... 37

Figure 9. TAP Controller State Diagram ......................................................................................................................................................................... 38

Figure 10. Master Reset ................................................................................................................................................................................................ 41

Figure 11. Partial Reset for Mux mode ........................................................................................................................................................................... 42

Figure 12. Partial Reset for Demux mode ...................................................................................................................................................................... 43

Figure 13. Partial Reset for Broadcast mode .................................................................................................................................................................. 44

Figure 14. Write Cycle and Full Flag Timing (Mux mode, IDT Standard mode, SDR to SDR) x10 In to x40 Out ............................................................. 45

Figure 15. Write Cycle and Full Flag Timing (Broadcast Write mode, IDT Standard mode, SDR to SDR) x10 In to x10 Out ............................................ 46

Figure 16. Write Cycle and Full Flag Timing (Demux mode, IDT Standard mode, SDR to SDR) x10 In to x10 Out ......................................................... 47

Figure 17. Write Timing (Mux mode, FWFT mode, SDR to SDR) x10 In to x10 Out........................................................................................................ 48

Figure 18. Write Timing (Broadcast Write mode, FWFT mode, SDR to SDR) x10 In to x10 Out....................................................................................... 49

Figure 19. Write Timing (Demux mode, FWFT mode, SDR to SDR) x10 In to x10 Out ................................................................................................... 50

Figure 20. Read Cycle, Empty Flag and First Word Latency (Mux mode, IDT Standard mode, SDR to SDR) x10 In to x40 Out ..................................... 51

Figure 21. Read Timing (Broadcast Write mode, FWFT mode, SDR to SDR) x10 In to x10 Out...................................................................................... 52

Figure 22. Read Timing (Mux mode, FWFT mode, SDR to SDR) x10 In to x10 Out....................................................................................................... 53

Figure 23. Read Timing (Demux mode, FWFT mode, SDR to SDR) x20 In to x10 Out .................................................................................................. 53

Figure 24. Read Cycle, Empty Flag and First Word Latency (Demux mode, IDT Standard mode, SDR to SDR) x20 In to x10 Out ................................. 54

Figure 25. Read Cycle, Empty Flag and First Word Latency (Broadcast Write mode, IDT Standard mode, SDR to SDR) x40 In to x10 Out .................... 55

Figure 26. Composite Empty Flag (Mux mode, IDT Standard mode, SDR to SDR) x10 In to x40 Out ............................................................................. 56

Figure 27. Composite Output Ready Flag (Mux mode, FWFT mode, SDR to SDR) x10 In to x40 Out ............................................................................ 56

Figure 28. Composite Full Flag (Demux mode, IDT Standard mode, SDR to SDR) x20 In to x10 Out ............................................................................ 57

Figure 29. Composite Input Ready Flag (Demux mode, FWFT mode, SDR to SDR) x20 In to x10 Out .......................................................................... 57

Figure 30. Echo Read Clock and Read Enable Operation (Mux/Demux/Broadcast mode, IDT Standard mode, DDR to DDR) x10 In to x10 Out ........... 58

Figure 31. Echo RCLK and Echo Read Enable Operation (Mux/Demux/Broadcast mode, FWFT mode, SDR to SDR) .................................................. 59

Figure 32. Echo Read Clock and Read Enable Operation (Mux/Demux/Broadcast mode, IDT Standard mode, SDR to SDR) x10 In to x10 Out ........... 60

Figure 33. Loading of Programmable Flag Registers (IDT Standard and FWFT modes) ................................................................................................ 61

Figure 34. Reading of Programmable Flag Registers (IDT Standard and FWFT modes)................................................................................................ 61

Figure 35. Synchronous ProgrammableAlmost-Full FlagTiming (see page for details)................................................................................................... 62

Figure 36. Synchronous ProgrammableAlmost-Empty Flag Timing (see page for details) ............................................................................................... 62

Figure 37. Asynchronous ProgrammableAlmost-Full Flag Timing (see page for details) ................................................................................................ 63

Figure 38. Asynchronous ProgrammableAlmost-Empty FlagTiming (see page for details) ............................................................................................ 63

Figure 39. Power Down Operation ................................................................................................................................................................................ 64

FEBRUARY01,2009

3

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

•

Composite Full/ Input Ready Flag in Demux and Broadcast

mode

Composite Empty/ Output Ready flag in Mux mode

Independent Programmable Almost Empty and Almost Full flags

per Queue

Dedicated Serial Port for flag programming

Dedicated Partial Reset for each individual Queue

Power Down pin minimizes power consumption

2.5V Supply Voltage

Available in a 324-pin Plastic Ball Grid Array (PBGA)

19mmx19mm,1mmPitch

FEATURES(CONTINUED)

- Fully independent status flags for every Queue

- Composite Full/Input Ready Flag monitors currently selected Queue

- Dedicated partial reset for every Queue

•

Up to 200MHz operating frequency or 8Gbps throughput in SDR mode

Up to 100MHz operating frequency or 8Gbps throughput in DDR mode

User selectable Single Data Rate (SDR) or Double Data Rate

(DDR) modes on both the write port(s) and read port(s)

All I/O are LVTTL/ HSTL/ eHSTL user selectable

•

3.3V tolerant inputs in LVTTL mode

ERCLK and EREN Echo outputs on all read ports

Write Chip Select WCS input for each write port

Read Chip Select RCS input for each read port

•

IEEE 1149.1 compliant JTAG port provides boundary scan

function, or flag programming

Low Power, High Performance CMOS technology

Industrial temperature range (-40°C to +85°C)

•

User Selectable IDT Standard mode (using EF and FF flags) or

FWFT mode (using IR and OR flags)

FUNCTIONALBLOCKDIAGRAMS(CONTINUED)

Demux Mode

RCLK0

REN0

RCS0

OE0

WCLK0

WEN0

WCS0

Queue 0

Data Out

8,192 x 40

16,384 x40

32,768 x 40

Q[9:0]

10

IS[1:0]

2

Queue 0

Queue 1

RCLK1

REN1

RCS1

OE1

Queue 1

Data Out

8,192 x 40

16,384 x40

32,768 x 40

Q[19:10]

D[39:0]

RCLK2

REN2

RCS2

OE2

Data In

x10,x20,x40

Queue 2

Data Out

8,192 x 40

16,384 x40

32,768 x 40

Q[29:20]

10

RCLK3

REN3

RCS3

OE3

Queue 2

Queue 3

Data Out

8,192 x 40

16,384 x40

32,768 x 40

Q[39:30]

EF0/ OR0

PAE0

FF0/ IR0

PAF0

FF1/ IR1

PAF1

FF2/ IR2

PAF2

EF1/ OR1

PAE1

EF2/ OR2

PAE2

EF3/ OR3

PAE3

FF3/ IR3

PAF3

CFF/ CIR

6157 drw02

FEBRUARY01,2009

4

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

FUNCTIONALBLOCKDIAGRAMS(CONTINUED)

Broadcast Mode

RCLK0

REN0

RCS0

Queue 0

Data Out

OE0

8,192 x 40

16,384 x40

32,768 x 40

Q[9:0]

10

WCLK0

WEN0

WCS0

Queue 0

Queue 1

Queue 2

Queue 3

RCLK1

REN1

RCS1

OE1

Queue 1

Data Out

8,192 x 40

16,384 x40

32,768 x 40

Q[19:10]

RCLK2

REN2

RCS2

OE2

D[39:0]

Data In

x10,x20,x40

8,192 x 40

16,384 x40

32,768 x 40

Queue 2

Data Out

Q[29:20]

10

RCLK3

REN3

RCS3

OE3

8,192 x 40

16,384 x40

32,768 x 40

Queue 3

Data Out

Q[39:30]

EF0/ OR0

PAE0

EF1/ OR1

PAE1

EF2/ OR2

PAE2

FF0/ IR0

PAF0

FF1/ IR1

PAF1

FF2/ IR2

PAF2

EF3/ OR3

PAE3

FF3/ IR3

PAF3

CFF/ CIR

6157 drw03

FEBRUARY01,2009

5

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

Queue.DatacanbereadoutofthefourQueuesthroughthereadporttotally

independentofanyotherport.Eachporthasitsownreadclockinputandcontrol

enables.TheinputporthasaselectableBusMatchingx10,x20orx40buswidth

and all the output ports are 10-bits. A full set of flag outputs per Queue are

availableinthismodeprovidingtheuserwithcontinuousstatusofeachindividual

Queuelevels.

IntheBroadcastWritemodethearchitectureissimilartotheDemuxmode,

1:4 (one input port to four output ports). However, there is no Queue select

operationinBroadcastmode.Insteaddatawrittenintothewriteportiswritten

toallfourinternalQueuessimultaneously.Againtherearefourindependent

read ports, one port per Queue. In Broadcast mode write operations to all

Queues will be prevented when any one or more of the four Queues are full

orbeingpartiallyreset.Afullsetofflagoutputsisavailableinthismodeproviding

theuserwithcontinuousstatusofeachindividualQueuelevels.

As is typical with most IDT Queues, two types of data timing modes are

available,IDTStandardmodeandFirstWordFallThrough(FWFT)mode.This

affectsthedevice’soperationandalsotheflagoutputs.Thedeviceprovidesfour

flagoutputs,foreachinternalQueue.Thedevicealsoprovidescompositeflags

thatrepresentthefullandemptystatusofthecurrentlyselectedQueue.

AllreadportsprovidetheuserwithadedicatedEchoReadEnable,EREN

and an Echo Read Clock, ERCLK output. These outputs aid in high-speed

applicationswheresynchronizationoftheinputclockanddataofareceiving

deviceiscritical.Otherwiseknownas“SourceSynchronousclocking”theecho

outputsprovidetightersynchronizationofthedatatransmittedfromtheQueue

tothereadclockinterfacingtheQueueoutputs.

A master reset input is provided and all setup and configuration pins are

latched with respect to a Master Reset. A Partial Reset is provided for each

internalQueue.WhenaPartialResetisperformedonaQueuethereadand

writepointersofthatQueueonlyareresettothefirstmemorylocation.Theflag

offsetvalues,timingmodes,andinitialconfigurationsareretained.

DESCRIPTION

The IDT72T55248/72T55258/72T55268 QuadMux flow-control devices

areidealformanyapplicationswheredatastreamconvergenceandparallel

bufferingofmultipledatapathsarerequired.Theseapplicationsmayinclude

communication and networking systems such as terabit routers, quality of

service (QOS) and packet prioritization routing systems, data bandwidth

aggregation, data acquisition systems, WCDMA baseband systems, and

medicalequipments.TheQuadMuxreplacestraditionalmethodsofmuxing

multipledatapathsatdifferentdatarates,inessencereducingexternalglue

logic. The QuadMux offers three modes of operation, Mux, Demux and

Broadcast. Regardless of the mode of operation there are four internal

Sequential Queues built using IDT FIFO technology and five discrete clock

domains.AllfourQueueshavethesamedensity,andthereadandwriteports

can operate independently in Single Data Rate (SDR) or Double Data Rate

(DDR).SeeFigure1,QuadMuxBlockDiagramoranoutlineofthefunctional

blockswithinthedevice.

TheQuadMuxdeviceoffersamaximumthroughputof8Gbps,withselectable

SDRorDDRdata transfermodes forthe inputs andoutputs. InSDRmode,

theinputclockcanoperateupto200MHz.Datawilltransition/latchontherising

edgeoftheclock.InDDRmode,theinputclockcanoperateupto100MHz,

withdatatransitioning/latchedonbothrisingandfallingedgesoftheclock.The

advantageofDDRisthatitcanachievethesamethroughputasSDRwithonly

halfthe numberofbits, assumingthe frequencyis constant. Forexample, a

4GbpsthroughputinSDRis100MHzx40bits.InDDRmode,itis100MHzx

20bits,becausetwobitstransitionperclockcycle.

InMuxmodeoperationa4:1architectureissetup,(fourinputportstoone

output port). Here there are four internal Sequential Queues each with a

dedicatedwriteport.Datacanbewrittenintoeachofthededicatedwriteports

totallyindependentofanyotherport,eachporthasitsownwriteclockinputand

controlenables.Thereisasinglereadportthatcanaccessanyoneofthefour

Queues. Data is readoutofa specificQueue basedonthe address present

onthe outputselectpins. Onlyone Queue canbe selectedandreadfromat

atime.Allinputportsare10bitswideandtheoutputporthasaselectableBus

Matchingx10,x20orx40bus widths.Afullsetofflagoutputs perQueueare

available in this mode providing the user with continuous status of each

individualQueuelevels.

TheQuadMuxdevicehasthecapabilityofoperatingitsI/Osateither2.5V

LVTTL, 1.5V HSTL or 1.8V eHSTL levels. A Voltage Reference, VREF input

isprovidedforHSTLandeHSTLinterfaces.ThetypeofI/Oisselectedbythe

IOSELpin.TherearecertaininputsthatareCMOSbasedandmustbetiedto

eitherVCCorGND.Thecoresupplyvoltageofthedevice,VCCisalways2.5V,

howevertheoutputpinshaveaseparatesupply,VDDQwhichcanbe2.5V,1.8V

or1.5V.Thedevicealsoofferssignificantpowersavings,achievedthroughthe

use of the Power Down input, PD in HSTL/eHSTL mode.

InDemuxmodeoperationa1:4architectureissetup,(oneinputporttofour

outputports).Herethereisasinglewriteportthatcanwritedataintoanyone

of four internal Queues. Data is written into a specific Queue based on the

addresspresentontheinputselectpins.OnlyoneQueuecanbeselectedand

written into at a time. There are four dedicated read ports, one port for each

AJTAGtestportisprovidedontheQuadMuxdevice.TheBoundaryScan

isfullycompliantwithIEEE1149.1StandardTestAccessPortandBoundary

ScanArchitecture.TheJTAGportcanalsobeusedtoprogramtheflagoffsets.

FEBRUARY01,2009

6

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

D[39:0] (x10, x20, x40)

Input Mux

Input

IW[1:0]

WDDR

WEN0

WCS0

WCLK0

WDDR

WEN2

Write Control

Logic

Write Control

WCS2

Logic

WCLK2

RAM

ARRAY 0

ARRAY 2

RDDR

REN0

RDDR

REN2

RCS2

RCLK2

Read Control

Logic

Read Control

Logic

8,192 x 40

16,384 x 40

32,768 x 40

8,192 x 40

16,384 x 40

32,768 x 40

RCS0

80

RCLK0

PAF0

FF0/IR0

PAE0

PAF2

Status Flag

Logic

Status Flag

Logic

FF2/IR2

PAE2

80

EF0/OR0

EF2/OR2

80

WDDR

WEN1

WCS1

WCLK1

WDDR

WEN3

WCS3

WCLK3

Write Control

Logic

Write Control

Logic

RAM

ARRAY 1

RAM

ARRAY 3

8,192 x 40

16,384 x 40

32,768 x 40

8,192 x 40

16,384 x 40

32,768 x 40

RDDR

REN1

RDDR

REN3

RCS3

RCLK3

Read Control

Logic

Read Control

Logic

RCS1

RCLK1

PAF1

FF1/IR1

PAE1

PAF3

Composite

Flags

FF3/IR3

PAE3

Status Flag

Logic

Status Flag

Logic

EF1/OR1

EF3/OR3

Reset

Logic

Output Mux

CEF/ CFF/

COR CIR

OW[1:0]

SCLK

SWEN

SREN

FWFT/SI

SDO

TCK

TRST

TMS

TDI

JTAG Control

(Boundary Scan)

Programmable

Flag Control

4

FSEL[1:0]

PFM

TDO

PRS0/1/2/3

MRS

OE0/1/2/3

RCS0/1/2/3

4

6157 drw04

Q[39:0] (x10, x20, x40)

NOTES:

1. This block diagram only shows the architecture for Queue 0. There are a total of four Queues inside this device all with the identical architecture.

2. *Denotes dedicated signal for each internal Queue inside the device.

Figure 1. QuadMux Block Diagram

FEBRUARY01,2009

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PINCONFIGURATION

A1 BALL PAD CORNER

A

MRS

D0

D3

D6

D2

D5

D8

VREF

MD0

D9

PRS0

PRS1

PRS2

V

CC

GND

V

DDQ

PRS3

PD

OE0

TDI

OE1

SCLK

TMS

OE2

OE3

Q0

Q1

Q2

Q3

D1

D4

D7

B

C

D

E

F

SREN

FWFT/SI TDO

MD1

FSEL0 RDDR

OW0 WDDR

VCC

VDDQ

OW1

IW0

TRST SWEN

FSEL1

VCC

V

DDQ

IW1

TCK

SDO

V

CC

GND

VCC

D10

D13

D11

D14

D12

D15

PFM

IOSEL

GND

V

DDQ

V

DDQ

V

DDQ

V

DDQ

V

DDQ

Q6

Q9

Q5

Q8

Q4

Q7

VCC

VDDQ

V

DDQ

VDDQ

VCC

V

CC

VCC

V

CC

V

CC

GND

V

DDQ

V

DDQ

Q12

Q15

Q11

Q14

Q10

Q13

WCLK0 D16

D17

D19

G

H

J

WCLK1

D18

VDDQ

VCC

VDDQ

D21

D23

D24

VCC

GND

V

DDQ

VDDQ

Q18

Q17

Q16

WCLK2 D20

WCLK3 D22

V

DDQ

VDDQ EREN1 EREN0 Q19

VCC

K

L

D26

D25

VCC

V

DDQ

V

DDQ

EREN3

VCC

EREN2

Q20

D29

D32

D35

D28

D31

D34

D27

D30

D33

V

CC

V

CC

GND

V

DDQ

V

DDQ

Q21

Q24

Q27

Q22

Q25

Q28

Q23

Q26

Q29

M

N

P

R

T

VCC

V

DDQ

VDDQ

VCC

GND GND

V

DDQ

VDDQ

VCC

D38

D37

VCC

GND GND

VDDQ

V

DDQ

V

DDQ Q30

Q31

Q34

Q32

D36

D39

VCC

VDDQ

GND

FF2/IR2

PAE3

VDDQ

V

DDQ

VDDQ

Q33

Q36

Q38

ERCLK0

WEN2 WEN3

VDDQ

VCC

WCS3 WEN0 WEN1

WCS0 WCS1 WCS2

PAF1 CFF/CIR PAF2

CEF/

VCC

PAF3

OS0

RCS1 REN2

Q35

Q37 ERCLK1

FF0/IR0

U

V

VCC

FF3/IR3

RCS3 RCS0 REN1

REN0

Q39 ERCLK2

RCLK0 ERCLK3

PAF0 EF1/OR1

EF2/OR2

COR

RCLK3 RCLK2 RCLK1

FF1/IR1

VCC

GND

IS1

IS0

PAE0 EF0/OR0 PAE1

PAE2

OS1

RCS2 REN3

EF3/OR3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

6157 drw05

PBGA (BB324-1, order code: BB)

TOP VIEW

FEBRUARY01,2009

8

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PINDESCRIPTIONS

Symbol &

Pin No.

Name

I/OTYPE

Description

CEF/COR

(U6)

CompositeEmpty/ HSTL-LVTTL IfMuxmodeisselectedthisflagwillrepresenttheexactstatusofthecurrentQueuebeingread

(2)

CompositeOutput

Ready Flag

OUTPUT

withouttheuserhavingtoobservetheemptyflagcorrespondingtothecurrentQueue.

IfDemuxorBroadcastmodeisselectedthisoutputisnotusedandcanbeleftfloating.

CFF/CIR

(T6)

CompositeFull/

CompositeInput

Ready flag

HSTL-LVTTL IfMuxmodeisselectedthisoutputisnotusedandcanbeleftfloating.

(2)

OUTPUT

IfDemuxmodeisselectedthisflagwillrepresenttheexactstatusofthecurrentQueuebeingwritten

withouttheuserhavingtoobservethefullflagcorrespondingtothecurrentQueue.

IfBroadcastmodeis selectedthis flaggoes activewhenanyoneofthefourQueues goes fulland

inactivewhenallfourQueues arenotfull.

D[39:0]

DataInputBus

HSTL-LVTTL Thesearethedatainputsforthedevice.Dataiswrittenintothepartusingtherespectivewriteport

(See Pin No.

tablefordetails)

INPUT

clock(s)andenable(s).IfDemuxorBroadcastmodeisselectedthisisasingledatainputbusproviding

Bus-Matchingofx10,x20orx40bits.IfMuxmodeis selectedtheseinputs becomefourseparate

bussestothefourseparateQueues.D[9:0]isQueue[0],D[19:10]isQueue[1],D[29:20]isQueue[2],

D[39:30]is Queue[3]. Anyunusedinputs shouldbe tiedtoGND. Note the inputs are 3.3Vtolerant

in LVTTL mode.

EF0/1/2/3/-

OR0/1/2/3

(See Pin No. Flags 0/1/2/3

tablefordetails)

EmptyFlags0/1/2/3 HSTL-LVTTL This is the Empty Flag (Standard IDT mode) or Output Ready Flag (FWFT mode) corresponding

(2)

orOutputReady

OUTPUT

toeachofthe fourQueues onthe readport. EF indicates whetherornotthe Queue is empty.

ORindicateswhetherornotthereisvaliddataavailableattheoutputs.Theseflagsalwaysrepresent

thestatusofthecorrespondingQueueatalltimesineverymode.

ERCLK0

(R18)

Echo Read Clock 0 HSTL-LVTTL IfMuxmodeis selectedthis is theonlyechoclockoutputavailableforthereadport.

(2)

OUTPUT

IfDemuxorBroadcastmodeis selectedthis is theechoreadclockoutputforQueue0.

Echoreadclockalways follows RCLK0withanassociateddelay.

ERCLK1/2/3 EchoReadClock

(ERCLK1-T18 1/2/3

ERCLK2-U18

HSTL-LVTTL IfMuxmodeisselectedtheseclockoutputsareinactiveandcanbeleftfloating.

(2)

OUTPUT

IfDemuxorBroadcastmodeisselectedthesearetheechoreadclockoutputsforQueues1,2,and

3respectively.

ERCLK3-V18)

ERCLK1, ERCLK2 and ERCLK3 always follow RCLK1, RCLK2 and RCLK3 respectively.

EREN0

(J17)

Echo Read Enable 0 HSTL-LVTTL IfMuxmode is selectedthis is the echoreadenable outputforthe readport.

(2)

OUTPUT

IfDemuxorBroadcastmode is selectedthis is the echoreadenable inputforQueue 0.

EchoReadEnableissynchronoustotheRCLKinputandisactivewhenareadoperationhasoccurred

and a new word has been placed onto the data output bus.

EREN1/2/3

Echo Read Enable HSTL-LVTTL IfMuxmodeisselectedtheseoutputsareinactiveandcanbeleftfloating.

(2)

(EREN1-J16 1/2/3

EREN2-K16

OUTPUT

IfDemuxorBroadcastmodeisselectedthesearetheechoreadenableoutputsforQueues1,2and

3respectively.

EREN3-K17)

EchoReadEnableissynchronoustotheRCLKinputandisactivewhenareadoperationhasoccurred

and a new word has been placed onto the data output bus.

FF0/1/2/3-

IR0/1/2/3

Full Flags 0/1/2/3 or HSTL-LVTTL This is the Full Flag (Standard IDT mode) or Input Ready Flag (FWFT mode) corresponding to

(2)

Input Ready Flags

OUTPUT

eachofthe fourQueues onthe write port. FF indicates whetherornotthe Queue is full.

IR indicates whetherornotthere is validspace forwritingdata ontothe Queue.

(See Pintable) 0/1/2/3

FSEL [1:0]

(FSEL1-C5

FSEL0-B6)

FlagSelect

HSTL-LVTTL Duringmasterreset,theFSELpins areusedtoselectoneoffourdefaultPAE andPAFoffsets.

INPUT

AllfourinternalQueues are programmedtothe same PAE/PAFoffsetvalue. Values are:00=7;

01 = 63; 10 = 127; 11 = 1023

FWFT/SI

(B16)

FirstWordFall

Through/ Serial

Input

HSTL-LVTTL Duringmasterreset, FWFTis HIGHthenthe FirstWordFallThroughmode is selected. IfFWFT

INPUT

isLOWtheIDTStandardmodeisselected.Aftermasterresetthispinisusedfortheserialdata

inputfortheprogrammingofthePAEandPAFflagsoffsetregisters.

IOSEL

(D5)

I/OSelect

CMOS⁽¹⁾

INPUT

This inputdetermines whetherthe inputs willoperate inLVTTLorHSTL/eHSTLmode. IfIOSEL

pinisHIGH,thenallinputsandoutputsthataredesignated"LVTTLorHSTL"inthissectionwillbe

settoHSTL. IfIOSELis LOWthenLVTTLis selected. This signalmustbe tiedtoeitherVCC or

GND for proper operation.

IS[1:0]

InputSelect

HSTL-LVTTL IfMuxorBroadcastmode is selectedthese inputs are notusedandshouldbe tiedtoGND.

(IS1-V1

IS0-V2)

INPUT

IfDemuxmodeisselectedtheseinputsselectoneofthefourQueuestobewrittenintoonthewrite

port.Theaddress ontheinputselectpins is setupwithrespecttotherisingedgeofWCLK0.

FEBRUARY01,2009

9

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PINDESCRIPTIONS(CONTINUED)

Symbol &

Pin No.

Name

I/OTYPE

Description

IW[1:0]

InputWidth

CMOS⁽¹⁾

INPUT

InDemuxorBroadcast,thesepinsareusedduringmasterresettoselecttheinputbussizeforthe

device.Thevaluesare:00=x10;01=x20;10=x40.11=Restricted.InMuxmodethesepinsmust

betiedtoGND.

(IW1-C12

IW0-C8)

MD[1:0]

(MD1-B5

MD0-B4)

Mode Pin

CMOS⁽¹⁾

INPUT

ThismodeselectionpinusedduringMasterResettoselectthemodeoftheQueue.Thevaluesare:

00 = Demux; 10 = Mux; 01 = Broadcast Write; 11 = Restricted.

MRS

MasterReset

OutputEnable0

HSTL-LVTTL Thisinputprovidesafulldevicereset.Allset-uppinsaresampledbasedonamasterresetoperation.

(A5)

INPUT

Readandwritepointerswillberesettothefirstlocationmemory.Allflagoffsetsareclearedand

resettodefaultvaluesdeterminedbyFSEL[1:0].

OE0

(A13)

HSTL-LVTTL IfMuxmodeisselectedthisistheOutputEnableforthereadport.Alldataoutputpinswillbeplaced

INPUT

intoHighImpedanceifthispinisHIGH.

IfDemuxorBroadcastmodeisselectedthisistheoutputenablepinforQueue0.Alldataoutput

pins ofQueue0willbeplacedintoHighImpedanceifthis pinis HIGH.This inputis asynchronous.

OE1-(A14)

OE2-(A15)

OE3-(A16)

OutputEnable1/2/3 HSTL-LVTTL IfMux mode is selected these inputs are ignored and can be tied HIGH.

INPUT

IfDemuxorBroadcastmode is selectedthese are the outputenable pins Queues 1, 2and3

respectively. All data outputs on Queue 1, Queue 2 and Queue 3 will be in High-Impedance if the

respective outputenable pinis High. These inputs are asynchronous.

OS[1:0]

(OS1-V11

OS0-T12)

OutputSelect

OutputWidth

HSTL-LVTTL IfMuxmodeisselectedtheseinputsselectoneofthefourQueuestobereadfromonthereadport.

INPUT

Theaddress ontheoutputselectpins is setupwithrespecttotherisingedgeofRCLK0.

IfDemuxorBroadcastmode is selectedthese inputs are notusedandshouldbe tiedtoGND.

OW[1:0]

HSTL-LVTTL IfMuxmodeisselected,thispinisusedduringmasterresettoselecttheoutputwordwidthbus

(OW1-B8

OW0-C6)

INPUT

size for the device. The values are: 00 = x10; 01 = x20; 10 = x40; 11 = Restricted.

IfDemuxorBroadcastmodeisselectedtheoutputwordwidthwillbex10.Thesepinsarenotused

andmustbetiedtoGND.

PAE0-(V3)

PAE1-(V5)

PAE2-(V7)

PAE3-(U10)

Programmable

AlmostEmptyFlag

0/1/2/3

HSTL-LVTTL Thisistheprogrammablealmostemptyflagthatcanbeusedtopre-indicatetheemptyboundary

(2)

OUTPUT

ofeachQueue.ThePAEflagscanbesettooneoffourdefaultoffsetsdeterminedbythestateof

FSEL0andFSEL1 during master reset. The PAE offsetvalues canalsobe writtenandreadfrom

serially by either the JTAG port or the serial programming pins (SCLK, FWFT/SI, SDO, SWEN,

SREN).Thisflagcanoperateinsynchronousorasynchronousmodedependingonthestateofthe

PFMpinduringmasterreset.

PAF0-(U4)

PAF1-(T5)

PAF2-(T7)

PAF3-(T11)

Programmable

AlmostFullFlag

0/1/2/3

HSTL-LVTTL Thisistheprogrammablealmostfullflagthatcanbeusedtopre-indicatethefullboundaryofeach

(2)

OUTPUT

Queue.ThePAFflagscanbesettooneoffourdefaultoffsetsdeterminedbythestateofFSEL0and

FSEL1 during master reset. The PAF offset values can also be written and read from serially by

eithertheJTAGportortheserialprogrammingpins (SCLK,FWFT/SI,SDO,SWEN,SREN).This

flagcanoperate insynchronous orasynchronous mode dependingonthe state ofthe PFMpin

duringmasterreset.

PD

(B12)

Power Down

HSTL-LVTTL This input provides considerable power saving in HSTL/eHSTL mode. If this pin is low, the input

INPUT

leveltranslatorsforallthedatainputpins,clocksandnon-essentialcontrolpinsareturnedoff.

WhenPD is broughthigh, power-upsequence timingwillhave tobe followedtobefore the inputs

willberecognized.Itisessentialthattheuserrespecttheseconditionswhenpoweringdownthe

partandpoweringupthepart,soastonotproduceruntpulsesorglitchesontheclocksiftheclocks

are free running. PD does not provide any power consumption savings when the inputs are

configuredforLVTTL

PFM

(D4)

ProgrammableFlag

Mode

CMOS⁽¹⁾

INPUT

Duringmasterreset, a HIGHonPFMselects synchronous PAE/PAF flagtiming, a Lowduring

masterresetselectsasynchronousPAE/PAFflagtiming.ThispincontrolsallPAE/PAFflagoutputs.

PRS0-(A6)

PRS1-(A7)

PRS2-(A8)

PRS3-(A12)

PartialReset

0/1/2/3

HSTL-LVTTL ThesearethepartialresetinputsforeachinternalQueue.Theread,write,flagpointers,andoutput

registerswillallbesettozerowhenpartialresetisactivated.Duringpartialreset,theexistingmode

(IDTorFWFT),input/outputbus widthandratemode,andtheprogrammableflagsettings areall

retained.

FEBRUARY01,2009

10

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PINDESCRIPTIONS(CONTINUED)

Symbol &

Pin No.

Name

I/OTYPE

Description

Q[39:0]

See Pin No.

tablefordetails)

DataOutputBus

HSTL-LVTTL These are the data outputs forthe device. Data is readfromthe partusingthe respective read

(2)

OUTPUT

portclock(s)andenable(s).IfMuxmodeis selectedthis is asingledataoutputbus providingBus-

Matchingofx10,x20orx40bits.IfDemuxorBroadcastmodeisselectedtheseoutputsbecomefour

separatebussesfromthefourseparateQueues.Q[9:0]isQueue[0],Q[19:10]isQueue[1],Q[29:20]

isQueue[2],Q[39:30]isQueue[3].Anyunusedoutputsshouldbeleftfloating.Note,thattheoutputs

are NOT 3.3V tolerant.

RCLK0

(V17)

Read Clock 0

HSTL-LVTTL IfMuxmode is selectedthis is the clockinputforthe readport. Allreadportoperations willbe

INPUT

synchronoustothisclockinput.

IfDemuxorBroadcastmodeisselectedthisisthereadclockinputforQueue0.Allreadportoperations

onQueue 0willbe synchronous tothis clockinput.

RCLK1-(V16) Read Clock 1/2/3

RCLK2-(V15)

RCLK3-(V14)

HSTL-LVTTL IfMuxmode is selectedthese clockinputs are ignoredandifunusedcanbe tiedtoGND.

INPUT

IfDemuxorBroadcastmode is selectedthese are the readclockinputs forQueues 1, 2, and3

respectively.AllreadportoperationsonQueue1,Queue2andQueue3willbesynchronoustoclock

inputs RCLK1, RCLK2 and RCLK3 respectively.

RCS0

(U13)

Read Chip Select 0 HSTL-LVTTL IfMuxmodeisselectedthisisthereadchipselectinputforthereadport.Allreadoperationswilloccur

INPUT

synchronous to the RCLK0 input provided that REN0 and RCS0 are LOW.

IfDemuxorBroadcastmodeisselectedthisisthereadchipselectinputforQueue0.Allreadoperations

on Queue 0 will occur synchronous to the RCLK0 input provided that REN0 and RCS0 are LOW.

RCS1-(T13) ReadChipSelect

RCS2-(V12) 1/2/3

RCS3-(U12)

HSTL-LVTTL IfMux mode is selected these inputs are ignored and can be tied HIGH.

INPUT

IfDemuxorBroadcastmode is selectedthese are the readchipselectinputs forQueues 1, 2and

3respectively.AllreadoperationsonQueue1,Queue2andQueue3willoccursynchronoustothe

RCLK1, 2 and 3 input respectively, provided that the corresponding read enable and read chip

selectinputsareLOW.

RDDR

(B7)

Read Port DDR

Read Enable 0

CMOS⁽¹⁾

INPUT

Duringmasterreset,thispinselectstheoutputporttooperateinDDRorSDRformat.IfRDDRisHIGH,

thenawordisreadontherisingandfallingedgeoftheappropriateRCLK0,1,2and3input.IfRDDR

is LOW, then a word is read only on the rising edge of the appropriate RCLK0, 1, 2 and 3 inputs.

REN0

(U15)

HSTL-LVTTL IfMuxmodeisselectedthisisthereadenableinputforthereadport.Allreadoperationswilloccur

INPUT

synchronous to the RCLK0 clock input provided that REN0 and RCS0 are LOW.

IfDemuxorBroadcastmodeisselectedthisisthereadenableinputforQueue0.Allreadoperations

on Queue 0 will occur synchronous to the RCLK0 input provided that REN0 and RCS0 are LOW.

REN1-(U14) Read Enable 1/2/3 HSTL-LVTTL IfMux mode is selected these inputs are ignored and can be tied HIGH.

REN2-(T14)

REN3-(V13)

INPUT

If Demux or Broadcast mode is selected these are the read enable inputs for Queues 1, 2 and 3

respectively.Allreadoperations onQueue1,Queue2andQueue3willoccursynchronous tothe

RCLK0,1,2and3inputsrespectively,providedthatthecorrespondingreadenableandreadchip

selectinputsareLOW.

SCLK

(B14)

SerialClock

HSTL-LVTTL SerialclockforwritingandreadingthePAE andPAF offsetregisters. Onthe risingedge ofeach

INPUT

SCLK,whenSWENisLOW,onebitofdataisshiftedfromtheFWFT/SIpinintothePAEandPAFoffset

registers.OntherisingedgeofeachSCLK,whenSRENisLOW,onebitofdataisshiftedoutofthe

PAEandPAFoffsetregisters.ThereadingofthePAEandPAFoffsetregistersarenon-destructive.

IfprogrammingofthePAE/PAFoffsetregistersisdoneviatheJTAGport,thisinputmustbetiedtoVCC.

SDO

(C17)

SerialDataOutput

LVTTL

OUTPUT

Thisoutputisusedtoreaddatafromtheprogrammableflagoffsetregisters.Itisusedinconjunction

withthe SREN andSCLKsignals.

(2)

SREN

(B15)

Serial Read Enable HSTL-LVTTL WhenSREN is broughtLOWbefore the risingedge ofSCLK, the contents ofthe PAE andPAF

INPUT

offsetregistersarecopiedtoaserialshiftregister.WhileSRENismaintainedLOW,oneachrising

edgeofSCLK,onebitofdataisshiftedoutofthisserialshiftregisterthroughtheSDOoutputpin.

IfprogrammingofthePAE/PAFoffsetregistersisdoneviatheJTAGport,thisinputmustbetiedtoVCC.

SWEN

(C16)

SerialWriteEnable HSTL-LVTTL On each rising edge of SCLK when SWEN is LOW, data from the FWFT/SI pin is serially loaded

INPUT

intothePAEandPAFregisters.IfprogrammingofthePAE/PAFoffsetregistersisdoneviathe

JTAGport,thisinputmustbetiedtoVCC.Oneachclock,dataisshiftedintoandthroughtheactual

PAE and PAF registers, sothe value ofthe registers is changedoneachclock

FEBRUARY01,2009

11

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PINDESCRIPTIONS(CONTINUED)

Symbol &

Pin No.

(3)

Name

I/OTYPE

Description

TCK

JTAGClock

HSTL-LVTTL ClockinputforJTAGfunction.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.Test

(C13)

INPUT

operations of the device are synchronous to TCK. Data from TMS and TDI are sampled on the

risingedgeofTCKandoutputTDOchangeonthefallingedgeofTCK.IftheJTAGfunctionisnotused

this signalneeds tobetiedtoGND.

(3)

TDI

JTAGTestData

Input

HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan

(B13)

INPUT

operation,testdatais seriallyloadedviatheTDIontherisingedgeofTCKtoeithertheInstruction

Register,IDRegister,BypassRegisterorBoundaryScanchain.Aninternalpull-upresistorforces

TDIHIGHifleftunconnected.

(3)

TDO

JTAGTestData

Output

HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan

(B17)

OUTPUT

operation,testdataisscannedtotheTDOoutputonthefallingedgeofTCKfromeithertheInstruction

Register, IDRegister, Bypass RegisterandBoundaryScanchain. This outputis highimpedance

exceptwhenshifting, while inSHIFT-DRandSHIFT-IRcontrollerstates.

TMS⁽³⁾

(C14)

JTAGModeSelect HSTL-LVTTL TMSisaserialinputpin.OneoffourterminalsrequiredbyIEEEStandard1149.1-1990.TMSdirects

INPUT

thedevicethroughitsTAPcontrollerstatessampledontherisingedgeofTCK.Aninternalpull-up

resistorforcesTMSHIGHifleftunconnected.

(3)

TRST

JTAGReset

WriteClock0

HSTL-LVTTL TRSTisanasynchronousresetpinfortheJTAGcontroller.TheJTAGTAPcontrollerisautomatically

(C15)

INPUT

resetuponpower-up.IftheTAPcontrollerisnotproperlyresetthentheQueueoutputswillalways

beinhigh-impedance.IftheJTAGfunctionisusedbuttheuserdoesnotwanttouseTRST,thenTRST

canbetiedwithMRStoensureproperQueueoperation.IftheJTAGfunctionis notusedthenthis

signalneeds tobetiedtoGND.Aninternalpull-upresistorforces TRST HIGHifleftunconnected.

WCLK0

(F1)

HSTL-LVTTL IfMuxmodeis selectedthis is theclockinputforQueue0.Allwriteportoperations toQueue0will

INPUT

besynchronoustothisclockinput.

IfDemuxorBroadcastmodeisselectedthisistheclockinputforthewriteport.Allwriteport operations

willbesynchronoustothisclockinput.SampledontherisingedgeofWCLKandindependentofWDDR.

WCLK1-(G1) WriteClock1/2/3

WCLK2-(H1)

WCLK3-(J1)

HSTL-LVTTL IfMuxmode is selectedthese are the clockinputs forQueues 1, 2, and3respectively. Allwrite

INPUT

portoperations on Queue1, Queue 2 and Queue 3 will be synchronous to clock inputs WCLK1,

WCLK2andWCLK3respectively.

IfDemuxorBroadcastmode is selectedthese clockinputs are ignoredandcanbe tiedtoGND.

WCS0

(U1)

WriteChipSelect0 HSTL-LVTTL IfMuxmodeisselectedthisisthewritechipselectinputforQueue0.AllwriteoperationsonQueue0

INPUT

willoccursynchronous tothe WCLK0inputprovidedthatWEN0andWCS0are LOW.

IfDemuxorBroadcastmodeisselectedthisisthewritechipselectinputforthewriteport.Allwrite

operations willoccursynchronous tothe WCLK0inputprovidedthatWEN0andWCS0are LOW.

SampledontherisingedgeofWCLKandindependentofWDDR.

WCS1-(U2)

WCS2-(U3)

WCS3-(T1)

WriteChipSelect

1, 2, 3

HSTL-LVTTL IfMuxmodeisselectedthesearethewritechipselectinputsforQueues1,2and3respectively.All

INPUT

writeoperationsonQueue1,Queue2andQueue3willoccursynchronoustotheWCLK1,2and3

respectively,providedthatthecorrespondingwriteenableandwritechipselectinputsareLOW.

SampledontherisingedgeofWCLKandindependentofWDDR.

IfDemuxorBroadcastmode is selectedthese inputs are ignoredandcanbe tiedHIGH.

WDDR

(C7)

WritePortDDR

WriteEnable0

CMOS⁽¹⁾

INPUT

Duringmasterreset,thispinselectstheinputporttooperateinDDRorSDRformat.IfWDDRisHIGH,

then a word is written on the rising and falling edge of the appropriate WCLK0, 1, 2 and 3 input.

IfWDDRisLOW,thenawordiswrittenonlyontherisingedgeoftheappropriateWCLK1,1,2and

3inputs.

WEN0

(T2)

HSTL-LVTTL IfMuxmodeisselectedthisisthewriteenableinputforQueue0.AllwriteoperationsonQueue0will

INPUT

occursynchronous tothe WCLK0inputprovidedthatWEN0and WCS0are LOW.

IfDemuxorBroadcastmodeis selectedthis is thewriteenableinputforthewriteport.Allwrite

operationswilloccursynchronoustotheWCLK0clockinputprovidedthatWEN0andWCS0areLOW.

WEN1-(T3)

WEN2-(R1)

WEN3-(R2)

WriteEnable1/2/3

LVTTL

IfMuxmodeisselectedthesearethewriteenableinputsforQueues1,2and3respectively.Allwrite

operationsonQueue1,Queue2andQueue3willoccursynchronoustotheWCLK1,2and3inputs

respectively,providedthatthecorrespondingwriteenableandwritechipselectinputsareLOW.

IfDemuxorBroadcastmode is selectedthese inputs are ignoredandcanbe tiedHIGH.

FEBRUARY01,2009

12

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

PINDESCRIPTIONS(CONTINUED)

Symbol &

Pin No.

Name

I/OTYPE

Description

VCC

+2.5VSupply

Power

These are VCC core power supply pins and must all be connected to a +2.5V supply rail.

(See Pin table)

VDDQ

(See Pin table)

OutputRailVoltage

GroundPin

Power

Ground

Analog

Thispinshouldbetiedtothedesiredvoltagerailforprovidingtotheoutputdrivers.Nominally1.5V

or 1.8V for HSTL, 2.5V for LVTTL.

GND

(See Pintable)

These ground pins are for the core device and must be connected to the GND rail.

Vref

(A4)

Referencevoltage

ThisisaVoltageReferenceinputandmustbeconnectedtoavoltageleveldeterminedintheVoltage

RecommendedDCOperatingConditionssection.Thisprovidesthereferencevoltagewhenusing

HSTLclass inputs.IfHSTLclass inputs arenotbeingused,this pinmustbeconnectedtoGND.

NOTES:

1. AllCMOSpins shouldremainunchanged. CMOSformatmeans thatthe pinis intendedtobe tieddirectlytoVCC orGNDandthese particularpins are nottestedforVIH

or VIL.

2. Allunusedoutputsmaybeleftfloating.

3. ThesepinsarefortheJTAGport.Pleaserefertopages36-40,Figure7-9forJTAGinformation.

PIN NUMBER TABLE

Symbol

Name

I/OTYPE

Pin Number

D[39:0]

DataInputBus

HSTL-LVTTL D39-R3, D(38-36)-P(1-3), D(35-33)-N(1-3), D(32-30)-M(1-3), D(29-27)-L(1-3), D(26-24)-K(1-3),

INPUT

D(23,22)-J(3,2), D(21,20)-H(3,2), D(19,18)-G(3,2), D(17,16)-F(3,2), D(15-13)-E(3-1),

D(12-10)-D(3-1), D(9-6)-C(4-1), D(5-3)-B(3-1), D(2-0)-A(3-1)

EF0/1/2/3- EmptyFlags0-3or

OR0/1/2/3 Output Ready Flags 0-3 OUTPUT

HSTL-LVTTL EF0/OR0-V4, EF1/OR1-U5, EF2/OR2-U7, EF3/OR3-V10

(2)

FF0/1/2/3- Full Flags0-3 or

IR0/1/2/3 Input Ready Flags 0-3

HSTL-LVTTL FF0/IR0-T4, FF1/IR1-V6, FF2/IR2-T10, FF3/IR3-U11

(2)

OUTPUT

Q[39:0]

DataOutputBus

HSTL-LVTTL Q(39,38)-U(17,16),Q(37-35)-T(17-15),Q(34,33)-R(17,16),Q(32-30)-P(18-16),Q(29-27)-N(18-16),

(2)

OUTPUT

Q(26-24)-M(18-16),Q(23-21)-L(18-16),Q20-K18,Q19-J18,Q(18-16)-H(16-18),Q(15-13)-G(16-18),

Q(12-10)-F(16-18), Q(9-7)-E(16-18), Q(6-4)-D(16-18), Q3-C18, Q2-B18, Q(1-0)-A(18-17)

VCC

+2.5VSupply

O/PRailVoltage

GroundPin

Power

A9, B9, C9, D(6,9), E(4-9), F(4,5), G(4,5), H(4,5), J(4,5), K(4,5), L(4,5), M(4,5), N(4,5), P(4-8),

R(4-8), T8, U8, V8

VDDQ

GND

Power

A11, B11, C11, D(11-15), E(11-15), F(14,15), G(14,15), H(14,15), J(14,15), K(14,15), L(14,15),

M(14,15), N(14,15), P(11-15), R(11-15)

Ground

A10, B10, C10, D(7,8,10), E10, F(6-13), G(6-13), H(6-13), J(6-13), K(6-13), L(6-13), M(6-13),

N(6-13), P(9,10), R(9,10), T9, U9, V9

FEBRUARY01,2009

13

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

QUADMUXI/OUSAGESUMMARY

SERIAL PORT

SET-UP, CONFIGURATION & RESET PINS

ThefollowingpinsareusedforwritingandreadingtheProgrammableFlag

Offsetsvalues:

Regardless of the mode of operation, (Mux, Demux or Broadcast), the

followinginputsmustalwaysbeused.Theseinputsmustbeset-upwithrespect

tomasterresetastheyarelatchedduringmasterreset.

SCLK – Serial Clock

SWEN–SerialWriteEnable

SREN – Serial Read Enable

FWFT/SI – Serial Data In

SDO–SerialData Out

WDDR–WritePortDDR/SDRselection

RDDR – Read Port DDR/SDR selection

MD[1:0]–ModeSelection

OW[1:0]–Outputwidth

IW[1:0]–InputWidth

FSEL[1:0]–Flagoffsetdefaultvalues

IOSEL–I/OLevelSelection

PFM – Programmable Flag Mode

FWFT/SI–FirstwordFallThroughorStandardIDTmodeflagtimingselection

MUXMODE

DEMUXORBROADCASTMODE

Thefollowinginputs/outputsshouldbeusedwhenMuxmodeisselected

by the user:

The following inputs/outputs should be used when Demux or Broadcast

Writemodeisselectedbytheuser:

INPUTS:

WCLK0,WCLK1,WCLK2,WCLK3–Fourwriteportclocks

WEN0, WEN1, WEN2, WEN3 – Four write port enables

WCS0, WCS1, WCS2, WCS3 – Four write port chip selects

OS[1:0]-OutputSelect

IS[1:0]-InputSelect, Demuxmode only, notusedinbroadcastmode.

WCLK0–Writeportclock

WEN0–Writeportenable

WCS0–Writeportchipselect

RCLK0, RCLK1, RCLK2, RCLK3 – Four read port clocks

REN0, REN1, REN2, REN3 – Four read port enables

RCS0, RCS1, RCS2, RCS3 – Four read port chip selects

OE0, OE1, OE2, OE3 – Four read port output enables

RCLK0 – Read port clock

REN0 – Read port enable

RCS0 – Read port chip select

OE0–Readportoutputenable

OUTPUTS:

ERCLK0 – Read port echo read clock

EREN0 – Read port echo read enable

ERCLK0, ERCLK1, ERCLK2, ERCLK3 – Four read port echo read clock

outputs

EF0/OR0, EF1/OR1, EF2/OR2, EF3/OR3 – Four read port empty/output

readyflags

PAE0,PAE1,PAE2,PAE3–Fourreadportprogrammablealmostemptyflags

PAF0,PAF1,PAF2,PAF3–Fourwriteportprogrammablealmostfullflags

FF0/IR0,FF1/IR1,FF2/IR2,FF3/IR3–Fourwriteportfull/inputreadyflags

CEF/COR–Compositeempty/outputreadyflagonreadport

EREN0,EREN1,EREN2,EREN3–Fourreadportechoreadenableoutputs

EF0/OR0, EF1/OR1, EF2/OR2, EF3/OR3 – Four read port empty/output

readyflags

FF0/IR0, FF1/IR1, FF2/IR2, FF3/IR3–Fourwrite portfull/inputreadyflags

PAF0, PAF1, PAF2, PAF3–Fourwriteportprogrammablealmostfullflags

PAE0,PAE1,PAE2,PAE3–Fourreadportprogrammablealmostemptyflags

CFF/CIR –Composite full/inputreadyflagonwrite port

FEBRUARY01,2009

14

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

ABSOLUTEMAXIMUMRATINGS

CAPACITANCE(TA = +25°C, f = 1.0MHz)

Parameter⁽¹⁾

Conditions

Max.

Unit

Symbol

Rating

Com'l & Ind'l

Unit

Symbol

VTERM

TerminalVoltage

–0.5 to +3.6⁽²⁾

V

(2,3)

CIN

Input

VIN = 0V

10⁽³⁾

pF

with respect to GND

Capacitance

TSTG

IOUT

StorageTemperature

DCOutputCurrent

–55 to +125

–50to+50

°C

mA

(1,2)

COUT

Output

Capacitance

VOUT = 0V

10

pF

NOTES:

1. With output deselected, (OE ≥ VIH).

2. Characterized values, not currently tested.

3. CIN for Vref is 20pF.

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

2. Compliant with JEDEC JESD8-5. VCC terminal only.

RECOMMENDEDDCOPERATINGCONDITIONS

Symbol

VCC

Parameter

Min.

Typ.

Max.

Unit

SupplyVoltage

OutputSupplyVoltage

2.375

2.5

2.625

V

VDDQ

⎯LVTTL

⎯ eHSTL

2.375

1.7

2.5

1.8

1.5

2.625

1.9

1.6

V

(2)

⎯ HSTL

1.4

VREF

VoltageReferenceInput ⎯ eHSTL

0.8

0.68

0.9

0.75

1.0

0.9

V

(2)

⎯ HSTL

GND

VIH

SupplyVoltage

0

V

InputHighVoltage

⎯LVTTL

⎯ eHSTL

1.7

VREF+0.1

—

3.45

VDDQ+0.3

V

(2)

⎯ HSTL

VIL

InputLowVoltage

⎯LVTTL

⎯ eHSTL

—

VREF-0.3

—

0.7

VREF-0.1

V

(2)

⎯ HSTL

TA

OperatingTemperatureCommercial

OperatingTemperatureIndustrial

0

—

+70

+85

°C

-40

NOTES:

1. VREF is only required for HSTL or eHSTL inputs. VREF should be tied LOW for LVTTL operation.

2. Compliant with JEDEC JESD8-6.

FEBRUARY01,2009

15

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

DCELECTRICALCHARACTERISTICS

(Industrial: VCC = 2.5V ± 0.125V, TA = -40°C to +85°C)

Symbol

ILI

Parameter

Min.

–10

Max.

+10

Unit

µA

V

InputLeakageCurrent

OutputLeakageCurrent

OutputLogic“1”Voltage,

ILO

(7)

VOH

IOH = –8 mA @LVTTL

IOH = –8 mA @eHSTL

IOH = –8 mA @HSTL

VDDQ-0.4

—

VOL

OutputLogic“0”Voltage,

IOL = 8 mA @LVTTL

IOL = 8 mA @eHSTL

IOL = 8 mA @HSTL

—

0.4

V

(6)

ICC1^(1,2,3)

Active VCC Current

(SeeNote8and9fortestconditions)

--LVTTL

-- eHSTL

-- HSTL

—

240

mA

(6)

330

(6)

330

(1,2,3)

IDDQ

ActiveVDDQ Current

(SeeNote8and9fortestconditions)

--LVTTL

-- eHSTL

-- HSTL

—

50

30

mA

(6)

ISB1^(1,2,3)

ISB2^(1,2,3)

IPD1^(1,2,3)

IPD2^(1,2,3)

Standby VCC Current (Mux mode)

(SeeNote10and11fortestconditions)

--LVTTL

-- eHSTL

-- HSTL

—

110

mA

(6)

190

(6)

190

StandbyVDDQCurrent

(SeeNote10and11fortestconditions)

--LVTTL

-- eHSTL

-- HSTL

—

40

30

15⁽⁶⁾

30⁽⁶⁾

mA

Power Down VCC Current (Mux mode)

(SeeNote12and13fortestconditions)

--LVTTL

-- eHSTL

-- HSTL

—

mA

Power Down VDDQ Current

(SeeNote12and13fortestconditions)

--LVTTL

-- eHSTL

-- HSTL

—

0.5

mA

NOTES:

1. Both WCLK and RCLK toggling at 20MHz.

2. Data inputs toggling at 10MHz.

3. Typical ICC1 calculation: for LVTTL I/O ICC1 (mA) = 10 x fS, fS = WCLK frequency = RCLK frequency (in MHz)

for HSTL or eHSTL I/O ICC1 (mA) = 72+ (10 x fS), fS = WCLK frequency = RCLK frequency (in MHz)

4. Typical IDDQ calculation: With Data Outputs in High-Impedance: IDDQ (mA) = 0.78 x fS

With Data Outputs in Low-Impedance: IDDQ (mA) = CL x VDDQ x fS x N /2000

fs = WCLK frequency = RCLK frequency (in MHz), VDDQ = 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL

tA = 25°C, CL = capacitive load (pF), N = Number of bits switching

5. Total Power consumed: PT = [(VCC x ICC) + (VDDQ x IDDQ)]. IOH = -8mA for all voltage levels.

6. Maximum value tested wtih RCLK = WCLK = 20MHz at 85°C. Maximum value may differ depending on VCC and temperature.

7. Outputs are not 3.3V tolerant.

8. VCC = 2.5V, WCLK0-3 = RCLK0 = 20MHz, WEN0-3 = REN0 = LOW, WCS0-3 = RCS0 = LOW, OE = LOW, PD = HIGH.

9. VCC = 2.5V, WCLK0 = RCLK0-3 = 20MHz, WEN0 = REN0-3 = LOW, WCS0 = RCS0-3 = LOW, OE0-3 = LOW, PD = HIGH.

10. VCC = 2.5V, WCLK0-3 = RCLK0 = 20MHz, WEN0-3 = REN0 = HIGH, WCS0-3 = RCS0 = HIGH, OE = LOW, PD = HIGH.

11. VCC = 2.5V, WCLK0 = RCLK0-3 = 20MHz, WEN0 = REN0-3 = HIGH, WCS0 = RCS0-3 = HIGH, OE0-3 = LOW, PD = HIGH.

12. VCC = 2.5V, WCLK0-3 = RCLK0 = 20MHz, WEN0-3 = REN0 = HIGH, WCS0-3 = RCS0 = HIGH, OE = LOW, PD = LOW.

13. VCC = 2.5V, WCLK0 = RCLK0-3 = 20MHz, WEN0 = REN0-3 = HIGH, WCS0 = RCS0-3 = HIGH, OE0-3 = LOW, PD = LOW.

FEBRUARY01,2009

16

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

ACELECTRICALCHARACTERISTICS⁽¹⁾

(Commercial: VCC = 2.5V ± 0.15V, TA = 0°C to +70°C;Industrial: VCC = 2.5V ± 0.15V, TA = -40°C to +85°C; JEDEC JESD8-A compliant)

Commercial

Commercial & Industrial

IDT72T55248L5

IDT72T55258L5

IDT72T55268L5

IDT72T55248L6-7

IDT72T55258L6-7

IDT72T55268L6-7

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

fS1

Clock Cycle Frequency (WCLK & RCLK) SDR

Clock Cycle Frequency (WCLK & RCLK) DDR

Data Access Time

—

0.6

5

200

100

3.6

—

10

—

0.6

6.7

13

2.8

6.0

2.8

6.0

2.0

0.5

2.0

0.5

—

100

45

15

5

150

75

MHz

ns

MHz

ns

fS2

tA

3.8

—

10

tCLK1

tCLK2

tCLKH1

tCLKH2

tCLKL1

tCLKL2

tDS

Clock Cycle Time SDR

Clock Cycle Time DDR

Clock High Time SDR

Clock High Time DDR

Clock Low Time SDR

Clock Low Time DDR

Data Setup Time

10

2.3

4.5

2.3

4.5

1.5

0.5

1.5

0.5

—

100

45

15

5

tDH

Data Hold Time

tENS

Enable Setup Time

tENH

fC

Enable Hold Time

Clock Cycle Frequency (SCLK)

Serial Output Data Access Time

Serial Clock Cycle

tASO

tSCLK

tSCKH

tSCKL

tSDS

20

—

12

—

15

Serial Clock High

Serial Clock Low

Serial Data In Setup

tSDH

tSENS

tSENH

tRS

Serial Data In Hold

Serial Enable Setup

5

Serial Enable Hold

5

Reset Pulse Width

200

15

10

—

0.6

—

0.4

—

4

200

15

10

—

0.8

—

0.5

—

5

tRSS

Reset Setup Time

tRSR

tRSF

Reset Recovery Time

Reset to Flag and Output Time

tOLZ (OE - Qn) Output Enable to Output in Low-Impedance

3.6

10

3.8

12

tOHZ

Output Enable to Output in High-Impedance

Output Enable to Data Output Valid

tOE

tWFF

Write Clock to FF or IR

tREF

Read Clock to EF or OR

tCEF

Read Clock to Composite EF or OR

tCFF

Write Clock to Composite FF or IR

tPAFS

tPAES

tPAFA

tPAEA

tERCLK

tCLKEN

tD

Write Clock to Synchronous Programmable Almost-Full Flag

Read Clock to Synchronous Programmable Almost-Empty Flag

Write Clock to Asynchronous Programmable Almost-Full Flag

Read Clock to Asynchronous Programmable Almost-Empty Flag

RCLK to Echo RCLK Output

10

12

4.0

3.6

—

3.6

—

4.3

3.8

—

3.8

—

RCLK to Echo REN Output

Time Between Data Switching and ERCLK edge

RCLK to Active from High-Impedance

tRCSLZ

tRCSHZ

tSKEW1

tSKEW2

tSKEW3

RCLK to High-Impedance

SKEW time between RCLK and WCLK for EF/OR and FF/IR

SKEW time between RCLK and WCLK for EF/OR and FF/IR in DDR mode

SKEW time between RCLK and WCLK for PAE and PAF

5

7

5

7

NOTES:

1. With exception to clock cycle frequency, these parameters apply to both DDR and SDR modes of operation.

2. Values guaranteed by design, not currently tested.

3. Industrial temperature range product for the 6-7ns speed grade is available as a standard device. All other speed grades available by special order.

FEBRUARY01,2009

17

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

HSTL

AC TEST LOADS

1.5V AC TEST CONDITIONS

VDDQ/2

InputPulseLevels

0.25to1.25V

0.4ns

InputRise/FallTimes

50

Ω

InputTimingReferenceLevels

OutputReferenceLevels

0.75V

Z0 = 50Ω

I/O

0.75V

10pF

NOTE:

1. VDDQ = 1.5V.

6157 drw06

Figure 2a. AC Test Load

EXTENDEDHSTL

1.8V AC TEST CONDITIONS

InputPulseLevels

0.4 to 1.4V

0.4ns

6

5

4

3

2

1

InputRise/FallTimes

InputTimingReferenceLevels

OutputReferenceLevels

0.9V

NOTE:

1. VDDQ = 1.8V.

20 30 50 80 100

Capacitance (pF)

200

6157 drw06a

LVTTL

Figure 2b. Lumped Capacitive Load, Typical Derating

2.5V AC TEST CONDITIONS

InputPulseLevels

GND to 2.5V

1ns

InputRise/FallTimes

InputTimingReferenceLevels

OutputReferenceLevels

1.25V

NOTE:

1. For LVTTL, VCC = VDDQ = 2.5V.

FEBRUARY01,2009

18

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

OUTPUT ENABLE & DISABLE TIMING

Output

Enable

Output

Disable

VIH

OE

VIL

tOE &

tOLZ

tOHZ

Single Output

Normally

LOW

V

DDQ/2

V

DDQ/2

100mV

V

OL

V

OH

Single Output

Normally

HIGH

100mV

V

DDQ/2

VDDQ/2

tOE

tOHZ

tOLZ

VDDQ/2

Output Bus

V

Current data in output register

6157 drw07

NOTES:

1. REN is HIGH.

2. RCS is LOW.

READ CHIP SELECT ENABLE & DISABLE TIMING

VIH

tENH

RCS

VIL

tENS

RCLK

tRCSHZ

tRCSLZ

Output

Normally

LOW

V

DDQ

V

DDQ

100mV

2

100mV

V

OL

V

OH

Output

Normally

HIGH

VDDQ

100mV

VDDQ

2

6157 drw08

NOTES:

1. REN is HIGH.

2. OE is LOW.

FEBRUARY01,2009

19

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

Mux/Demux/Broadcast.ThismodeisselectedusingtheMD[1:0]inputs.

Ifduringmasterreset,MD1isHIGHandMD0isLOWthenMuxmodeisselected.

IfMD1andMD2are LOWthenDemuxis selected. IfMD1is LOWandMD0

isHIGHthenBroadcastmodeisselected.

FUNCTIONALDESCRIPTION

MASTER RESET & DEVICE CONFIGURATION - MRS

DuringMasterResetthedeviceoperationisdetermined,thisincludesthe

following:

IDT Standard or FWFT Mode. The two available flag timing modes are

selectedusingtheFWFT/SIinput.IfFWFT/SIisLOWduringMasterResetthen

IDTStandardmodeisselected,ifitishighthenFWFTmodeisselected.

Single Data Rate (SDR) or Double Data Rate (DDR). The input/output

dataratesareportselectable.Thisisaversatilefeaturethatallowstheuserto

select either SDR or DDR on the write port(s) and/or read(s) port using the

WDDRand/orRDDRinputs.IfWDDRisLOWduringmasterresetthenthewrite

port(s)willfunctioninSDRmode,ifitishighthenthewriteportwillbeDDRmode.

IfRDDRisLOWduringmasterresetthenthereadport(s)willfunctioninSDR

mode,ifitishighthenthereadportwillbeDDRmode.NotethatWDDRwillselect

thedataratemodeforthesinglewriteportinDemuxandBroadcastmodeand

allfourwriteportsinMuxmode.Likewise,RDDRwillselectthedataratemode

for the single read port in Mux mode and all four read ports in Demux and

Broadcastmode.

1. Mux, Demux or Broadcast mode

2. IDT Standard or First Word Fall Through (FWFT) flag timing mode

3. Single orDouble Data Rates onboththe Write andReadports

4. Programmableflagmode,synchronousorasynchronoustiming

5. Write and read port bus widths, x10, x20 or x40

6. Defaultoffsetsfortheprogrammableflags,7,63,127or1023

7. LVTTL or HSTL I/O level selection

8. InputandoutputQueueselection

Thestateoftheconfigurationinputsduringamasterresetwilldeterminewhich

oftheabovemodesareselected.AMasterResetcomprisesofpulsingtheMRS

inputpingfromhightolowforaperiodoftime(tRS)withtheconfigurationinputs

heldintheirrespectivestates.Table1summarizestheconfigurationmodes

available doingmasterreset. The are describedas follows:

Programmable Almost Empty/Full Flags. These flags can operate in

eithersynchronous orasynchronous timingmode.Iftheprogrammableflag

input,PFMisHIGHduringmasterresetthenallprogrammableflagswilloperate

in a synchronous manner, meaning the PAE flags are double buffered and

updatedbasedontherisingedgeofitsrespectivereadclocks.ThePAFflags

arealsodoublebufferedandupdatedbasedontherisingedgeofitsrespective

write clocks. If it is LOW then all programmable flags will operate in an

asynchronousmanner,meaningthePAEandPAFflagsarenotdoublebuffered

andwillupdatethroughtheinternalcounterafteranominaldelay.

SelectableBus Width.Thebus widthcanbeselectedonthewriteportin

DemuxandBroadcastmodeandonthereadportinMuxmode.InDemuxand

BroadcastmodethewriteportwidthisselectedusingtheIW[1:0]inputs.IfIW0

andIW1areLOWthenthewriteportwillbe10bitswide,ifIW0isLOWandIW1

isHIGHthenthewriteportwillbe20bitswide,ifIW0isHIGHandIW1isLOW

thenthewriteportwillbe40bitswide.Note,inDemuxandBroadcastmodeall

readportsare10bitswide.InMuxmodethereadportwidthisselectedusing

theOW[1:0]inputs.IfOW0and0W1areLOWthenthereadportwillbe10bits

wide,ifOW0isLOWandOW1areHIGHthenthereadportwillbe20bitswide,

ifOW0isHIGHandOW1areLOWthenthereadportwillbe40bitswide.Note,

in Mux mode all write ports are 10 bits wide.

TABLE 1 — DEVICE CONFIGURATION

PINS

VALUES

CONFIGURATION

MD[1:0]

00

10

01

11

Demux

Mux

BroadcastWrite

Restricted

FWFT/SI

WDDR

RDDR

PFM

0

1

IDTStandard

FWFT

0

1

SingleDataRatewriteport

DoubleDataRatewriteport

0

1

SingleDataRatereadport

DoubleDataRatereadport

0

1

AsynchronousoperationofPAEandPAFoutputs

SynchronousoperationofPAEandPAFoutputs

IW[1:0]

00

01

10

11

Write portis 10bits wide

Write portis 20bits wide

Write portis 40bits wide

Restricted

Programmable Flag Offset Values. These offset values can be user

programmedortheycanbesettooneoffourdefaultvalues duringamaster

reset.Fordefaultprogramming,thestateoftheFSEL[1:0]inputsduringmaster

OW[1:0]

00

01

10

11

Readportis 10bits wide

Readportis 20bits wide

Readportis 40bits wide

Restricted

FSEL[1:0]

00

01

10

11

Programmableflagoffsetregistersvalue=7

Programmableflagoffsetregistersvalue=63

Programmableflagoffsetregistersvalue=127

Programmableflagoffsetregistersvalue=1023

TABLE 2 — DEFAULT PROGRAMMABLE

FLAG OFFSETS

IDT72T55248

IDT72T55258

IDT72T55268

IOSEL

IS[1:0]

0

1

All applicable I/Os (except CMOS) are LVTTL

All applicable I/Os (except CMOS) are HSTL/eHSTL

Mux/BroadcastMode

notused

Demux Mode

Queue0

00

01

10

11

FSEL1

FSEL0

Offsets n,m

notused

Queue1

0

1

0

1

0

1

7

63

127

1,023

notused

Queue2

notused

Queue3

OS[1:0]

Mux Mode

Queue0

Queue1

Queue2

Queue3

Demux/BroadcastMode

notused

00

01

10

11

notused

NOTES:

1. In default programming, the offset value selected applies to all internal Queues.

2. To program different offset values for each Queue, serial programming must be used.

FEBRUARY01,2009

20

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

resetwilldeterminethevalue.Table1liststhefouroffsetvaluesandhowtoselect section earlier. User programming of the offset values can be performed by

them.Forprogrammingtheoffsetvaluestoaspecificnumber,usetheserial eitherthededicatedserialprogrammingportortheJTAGport.Thededicated

programmingsignals(SCLK,SWEN,SREN,FWFT/SI)toloadthevalueinto serialportcanbeusedtoloadorreadthecontentsoftheoffsetregisters.The

theoffsetregister.YoumayalsousetheJTAGportonthisdevicetoloadthe offsetregistersareprogrammedandreadsequentiallyandbehavesimilarto

offsetvalue.Keepinmindthatyoumustdisabletheserialprogrammingsignals ashiftregister.

ifyouplantousetheJTAGportforloadingtheoffsetvalues.Todisabletheserial

TheserialreadandwriteoperationsareperformedbythededicatedSCLK,

programming signals, tie SCLK, SWEN, SREN, and SI to VCC. A thorough FWFT/SI,SWEN,SREN,andSDOpins.Thetotalnumberofbits perdevice

explanation of the serial and JTAG programming of the flag offset values is islistedinFigure4,ProgrammableFlagOffsetProgrammingMethods.These

providedinthenextsection.

bitsaccountforallfourPAE/PAFoffsetregistersinthedevice.Towritetothe

I/OLevelSelection.TheI/Oscanbeselectedforeither2.5VLVTTLlevels offsetregisters,settheserialwriteenablesignalactive(LOW),andoneachrising

or1.5VHSTL/1.8VeHSTLlevels.ThestateoftheIOSELinputwilldetermine edgeofSCLKonebitfromtheFWFT/SIpinisseriallyshiftedintotheflagoffset

whichI/Olevelwillbeselected.IfIOSELisHIGHthentheapplicableI/Oswill registerchain.Oncethecompletenumberofbitshasbeenprogrammedintoall

be1.5VHSTLor1.8VeHSTL,dependingonthevoltagelevelappliedtoVDDQ fourregisters,theprogrammingsequenceiscomplete.Toreadvaluesfromthe

andVREF.ForHSTL,VDDQandVREF=0.75VandforeHSTLVDDQandVREF offsetsregisters,settheserialreadenableactive(LOW).Thenoneachrising

=0.9V. IfIOSELis LOWthenthe applicable I/Os willbe 2.5VLVTTLVREF = edge ofSCLK, one bitis shiftedouttothe serialdata output. The serialread

0.AsnotedinthePinDescriptionsection,IOSELisaCMOSinputandmustbe enablemustbekeptLOWthroughouttheentirereadoperation.Tostopreading

tied to either VCC or GND for proper operation.

theoffsetregister,disabletheserialreadenable(HIGH).Thereisserialread

InputandOutputSelection.Duringmasterreset,thevalueofIS[1:0]and enabletoSCLKtimeforreadingtheoffsetregisters,astheoffsetregisterdata

OS[1:0]willbeheldconstantandindicateswhichinternalQueuethereadand for each Queue is temporarily stored in a scan chain. When data has been

writeportwillselectforinitialoperation.Datawillbewrittentoorreadfromthis completelyreadoutoftheoffsetregisters,anyadditionalreadoperationstothe

internalQueueonthefirstvalidwriteandreadoperationaftermasterreset. offsetregisterwillresultinzerosastheoutputdata.

Readingandwritingoftheoffsetregisterscanalsobeaccomplishedusing

SERIAL WRITING AND READING OF OFFSET REGISTERS

theJTAGport.TowritetotheoffsetregistersusingJTAG,settheinstructional

Theseoffsetregisterscanbeloadedwithadefaultvalueortheycanbeuser registertotheoffsetwritecommand(HexValue=0x0008).TheJTAGportwill

programmedwithanothervalue.Oneoffourdefaultvaluesaredetectedbased load data into each of the offset registers in a similar fashion as the serial

onthestateoftheFSEL[1:0]inputs,discussedintheFunctionalDescription programmingdescribedabove.Toreadthevaluesfromtheoffsetregisters,set

IDT72T55258

IDT72T55268

IDT72T55278

SWEN SREN

IW/OW = x40

IW/OW = x20

IW/OW = x10

TDI*

TCK*

SCLK

Serial write into register:

0008

0

1

104 bits for the IDT72T55248

112 bits for the IDT72T55258

120 bits for the IDT72T55268

1 bit for each rising SCLK edge

112 bits for the IDT72T55248

120 bits for the IDT72T55258

128 bits for the IDT72T55268

120 bits for the IDT72T55248

128 bits for the IDT72T55258

136 bits for the IDT72T55268

1 bit for each rising SCLK edge 1 bit for each rising SCLK edge

starting with empty offset (LSB) starting with empty offset (LSB) starting with empty offset (LSB)

ending with full offset (MSB)

Serial read from registers:

112 bits for the IDT72T55248

120 bits for the IDT72T55258

128 bits for the IDT72T55268

1 bit for each rising SCLK edge 1 bit for each rising SCLK edge

starting with empty offset (LSB) starting with empty offset (LSB)

Serial read from registers:

120 bits for the IDT72T55248

128 bits for the IDT72T55258

136 bits for the IDT72T55268

0007

1

0

1

104 bits for the IDT72T55248

112 bits for the IDT72T55258

120 bits for the IDT72T55268

1 bit for each rising SCLK edge

starting with empty offset (LSB)

ending with full offset (MSB)

Don’t

care

No Operation

X

except

0008 &

0007

6157 drwAA

NOTES:

* Programming done using the JTAG port.

1. The programming methods apply to both IDT Standard mode and FWFT mode.

2. Parallel programming is not featured in this device.

3. The number of bits includes programming to all four dedicated PAE/PAF offset registers.

Figure 3. Programmable Flag Offset Programming Methods

FEBRUARY01,2009

21

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

theinstructionalregistertotheoffsetreadcommand(HexValue=0x0007).The IDT STANDARD MODE

TDO of the JTAG port will output data in a similar fashion as the serial

programmingdescribedabove.

Inthismode,thestatusflagsFF,PAF,PAE,andEFoperateinthemanner

outlinedinTable3.TowritedataintotheQueue,WriteEnable(WEN)andWCS

Thenumberofbitsrequiredtoloadtheoffsetregistersisdependentonthe mustbeLOW.DatapresentedtotheDATAINlineswillbeclockedintotheQueue

sizeofthedeviceselected.Eachoffsetregisterrequiresdifferenttotalnumber on subsequent transitions of the Write Clock (WCLK). After the first write is

ofbitsdependingoninputandoutputbuswidthconfiguration.Thistotalmustbe performed, the Empty Flag (EF) will go HIGH after three clock latency.

programmedintothedeviceinorderforalltheflagstobeprogrammedcorrectly. SubsequentwriteswillcontinuetofilluptheQueue.TheProgrammableAlmost-

To change values of one or more offset register, all of the registers must be Empty flag (PAE) will go HIGH after n + 1 words have been loaded into the

reprogrammedseriallyagain.

Queue,wherenistheemptyoffsetvalue.Thedefaultsettingforthesevalues

arelistedinTable3.Thisparameterisalsouserprogrammableasdescribed

TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH intheserialwritingandreadingofoffsetregisterssection.

(FWFT) MODE

ContinuingtowritedataintotheQueuewithoutperformingreadoperations

TheIDT72T55248/72T55258/72T55268supporttwodifferenttimingmodes willcausetheProgrammableAlmost-Fullflag(PAF)togoLOW. Again, ifno

ofoperation:IDTStandardmode orFirstWordFallThrough(FWFT)mode. reads are performed, the PAF will go LOW after (8,192-m) writes for the

Theselectionofwhichmodewilloperateisdeterminedduringmasterreset,by IDT72T55248,(16,384-m)writesfortheIDT72T55258,and(32,768-m)writes

thestateoftheFWFTinput.

fortheIDT72T55268.ThisisassumingtheI/Obuswidthisconfiguredtox40.

Duringmasterreset,iftheFWFTpinisLOW,thenIDTStandardmodewill If the I/O is x20, then PAF will go LOW after (16,384-m) writes for the

beselected.ThismodeusestheEmptyFlag(EF)toindicatewhetherornotthere IDT72T55248,(32,768-m)writesfortheIDT72T55258,and(65,536-m)writes

areanywordspresentintheQueue.ItalsousestheFullFlag(FF)toindicate fortheIDT72T55268.IftheI/Oisx10,thenPAFwillgoLOWafter(32,768-m)

whetherornottheQueuehasanyfreespaceforwriting.InIDTStandardmode, writes for the IDT72T55248, (65,536-m) writes for the IDT72T55258, and

everywordreadfromtheQueue,includingthefirst,mustberequestedusing (131,072-m)writesfortheIDT72T55268.Theoffset“m”isthefulloffsetvalue.

the Read Enable (REN) and RCLK.

ThedefaultsettingforthesevaluesarelistedinTable3.Thisparameterisalso

If the FWFT pin is HIGH during master reset, then FWFT mode will be user programmable. See the section on serial writing and reading of offset

selected.ThismodeusesOutputReady(OR)toindicatewhetherornotthere registersfordetails.

isvaliddataatthedataoutputs.ItalsousesInputReady(IR)toindicatewhether

WhentheQueueisfull,theFullFlag(FF)willgoLOW,inhibitingfurtherwrite

ornottheQueuehasanyfreespaceforwriting.IntheFWFTmode,thefirstword operations.Ifnoreadsareperformedafterareset,FFwillgoLOWafterDwrites

writtentoanemptyQueuegoesdirectlytooutputbusafterthreeRCLKrising totheQueue.IftheI/Obuswidthisconfiguredtox40,thenD=8,192writesfor

edges,applyingRCS=LOWisnotnecessary.However,subsequentwords theIDT72T55248,16,384writesfortheIDT72T55258,and32,768writesfor

mustbeaccessedusingthe(RCS)andRCLK.Varioussignals,inbothinputs theIDT72T55268.IftheI/Oisx20,thenD=16,384writesfortheIDT72T55248,

andoutputsoperatedifferentlydependingonwhichtimingmodeisineffect.The 32,768writesfortheIDT72T55258,and65,536writesfortheIDT72T55268.

timingmodeselectedaffectsallinternalQueuesequally.

If the I/O is x10, then D = 32,768 writes for the IDT72T55248, 65,536 writes

for the IDT72T55258, and 131,072 writes for the IDT72T55268.

IDT72T55248

IW/OW = x40

IDT72T55248 IDT72T55248

IDT72T55258

IW/OW = x10

IDT72T55268

IW/OW = x10

Offset

Register

IW/OW = x20

or

IW/OW = x20

or IDT72T55258 or

IDT72T55268

IDT72T55258 IW/OW = x20

IW/OW = x40

or IDT72T55268 IW/OW = x20

IW/OW = x40

1 - 13

1 - 14

1 - 15

1 - 16

1 - 17

PAE3

PAF3

PAE2

14 - 26

27 - 39

40 - 52

53 - 65

66 - 78

79 - 91

92 - 104

15 - 28

29 - 42

43 - 56

57 - 70

71 - 84

85 - 98

99 - 112

16 - 30

31 - 45

46 - 60

61 - 75

76 - 90

91 - 105

106 - 120

17 - 32

33 - 48

49 - 64

65 - 80

81 - 96

97 - 112

113 - 128

18 - 34

35 - 51

52 - 68

69 - 85

86 - 102

103 - 119

120 - 136

Serial Bits

PAF2

PAE1

PAF1

PAE0

PAF0

6157 drwAB

Figure 4. Offset Registers Serial Bit Sequence

FEBRUARY01,2009

22

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

IftheQueueisfull,thefirstreadoperationwillcauseFFtogoHIGHaftertwo If the I/O is x20, then PAF will go LOW after (16,385-m) writes for the

WCLKS. Subsequent read operations will cause PAF to go HIGH at the IDT72T55248,(32,769-m)writesfortheIDT72T55258,and(65,537-m)writes

conditionsdescribedinTable3.Iffurtherreadoperationsoccur,withoutwrite fortheIDT72T55268.IftheI/Oisx10,thenPAFwillgoLOWafter(32,769-m)

operations, PAE willgoLOWwhenthere are nwords inthe Queue, where n writes for the IDT72T55248, (65,537-m) writes for the IDT72T55258, and

istheemptyoffsetvalue.ContinuingreadoperationswillcausetheQueueto (131,073-m)writesfortheIDT72T55268.Theoffset“m”isthefulloffsetvalue.

becomeempty.ThenthelastwordhasbeenreadfromtheQueue,theEFwill ThedefaultsettingforthesevaluesarelistedinTable4.Thisparameterisalso

goLOWinhibitingfurtherreadoperations.RENisignoredwhentheQueueis user programmable. See the section on serial writing and reading of offset

empty.

WhenconfiguredinIDTStandardmode,theEFandFFoutputsaredouble

registersfordetails.

WhentheQueueisfull,theInputReady(IR)willgoLOW,inhibitingfurther

register-bufferedoutputs.IDTStandardmodeisavailablewhenthedeviceis writeoperations.Ifnoreadsareperformedafterareset,IRwillgoLOWafter

configured in both Single Data Rate and Double Data Rate mode. Relevant DwritestotheQueue.IftheI/Obuswidthisconfiguredtox40,thenD=8,193

timing diagrams for IDT Standard mode can be found in Figures 14, 15, 16. writesfortheIDT72T55248,16,385writesfortheIDT72T55258,and32,769

writes for the IDT72T55268. If the I/O is x20, then D = 16,385 writes for the

FIRST WORD FALL THROUGH MODE (FWFT)

IDT72T55248,32,769writesfortheIDT72T55258,and65,537writesforthe

Inthismode,thestatusflagsOR,IR,PAE,andPAFoperateinthemanner IDT72T55268.IftheI/Oisx10,thenD=32,769writesfortheIDT72T55248,

outlinedinTable4.TowritedataintototheQueue,WCSmustbeLOW.Data 65,537writesfortheIDT72T55258,and131,073writesfortheIDT72T55268.

presentedtotheDATAINlineswillbeclockedintotheQueueonsubsequent

IftheQueueisfull,thefirstreadoperationwillcauseIRtogoHIGHaftertwo

transitionsofWCLK.Afterthefirstwriteisperformed,theOutputReady(OR) WCLKsafterRCLK.SubsequentreadoperationswillcausePAFtogoHIGH

flagwillgoLOWafter3rdrisingedgeofRCLK.Subsequentwriteswillcontinue attheconditionsdescribedinTable4.Iffurtherreadoperationsoccur,without

tofilluptheQueue.PAEwillgoHIGHaftern+2wordshavebeenloadedinto writeoperations,PAEwillgoLOWwhentherearenwordsintheQueue,where

theQueue,wherenistheemptyoffsetvalue.Thedefaultsettingforthesevalues nistheemptyoffsetvalue.ContinuingreadoperationswillcausetheQueueto

arelistedinTable4.Thisparameterisalsouserprogrammableasdescribed becomeempty.ThenthelastwordhasbeenreadfromtheQueue,theORwill

intheserialwritingandreadingofoffsetregisterssection.

ContinuingtowritedataintotheQueuewithoutperformingreadoperations isempty.

goHIGHinhibitingfurtherreadoperations. RCS is ignoredwhentheQueue

willcausetheProgrammableAlmost-Fullflag(PAF)togoLOW.Again,ifno

WhenconfiguredinFWFTmode,theORflagoutputistripleregister-buffered

reads are performed, the PAF will go LOW after (8,193-m) writes for the andtheIRflagoutputisdoubleregister-buffered.Relevanttimingdiagramsfor

IDT72T55248,(16,385-m)writesfortheIDT72T55258,and(32,769-m)writes FWFT mode can be found in Figures 17, 18, 19.

fortheIDT72T55268.ThisisassumingtheI/Obuswidthisconfiguredtox40.

TABLE 3 — STATUS FLAGS FOR IDT STANDARD MODE

IDT72T55248

OW = x40

IDT72T55258

IDT72T55268

IDT72T55248

OW = x20

OW = x10

IDT72T55258

IDT72T55268

IDT72T55248

IDT72T55258

IDT72T55268

PAE

FF PAF

EF

0

H

L

H

L

Number of

Words in

Queue

1 to n⁽¹⁾

(n+1) to (8,192 - m)

8,192

1 to n⁽¹⁾

(n+1) to (16,384 - m)

16,384

1 to n⁽¹⁾

(n+1) to (32,768 - m)

32,768

1 to n⁽¹⁾

(n+1) to (65,536 - m)

65,536

1 to n⁽¹⁾

(n+1) to (131,072 - m)

131,072

L

H

L

NOTE:

1. n, m = 7 if FSEL[1:0] = 00, n, m = 63 if FSEL[1:0] = 01, n, m = 127 if FSEL[1:0] = 10, n, m = 1023 if FSEL[1:0] = 11.

TABLE 4 — STATUS FLAGS FOR FWFT MODE

IDT72T55248

OW = x40

IDT72T55258

IDT72T55268

IDT72T55248

OW = x20

OW = x10

IDT72T55258

IDT72T55268

IDT72T55248

IDT72T55258

IDT72T55268

PAE

FF PAF

EF

0

H

L

H

L

Number of

Words in

Queue

1 to n+1⁽¹⁾

(n+2) to (8,193 - m)

8,193

1 to n+1⁽¹⁾

(n+2) to (16,385 - m)

16,385

1 to n+1⁽¹⁾

(n+2) to (32,769 - m)

32,769

1 to n+1⁽¹⁾

(n+2) to (65,537 - m)

65,537

1 to n+1⁽¹⁾

(n+2) to (131,073 - m)

131,073

L

H

L

6157 drwSFT

NOTE:

1. n, m = 7 if FSEL[1:0] = 00, n, m = 63 if FSEL[1:0] = 01, n, m = 127 if FSEL[1:0] = 10, n, m = 1023 if FSEL[1:0] = 11.

FEBRUARY01,2009

23

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

HSTL/LVTTL I/O

widths. When writing or reading data from a Queue the number of memory

TheinputsandoutputsofthisdevicecanbeconfiguredforeitherLVTTLor locationsavailabletobewrittenorreadwilldependonthebuswidthselected

HSTL/eHSTLoperation.IftheIOSELpinisHIGHduringmasterreset,thenall andthedensityofthedevice.

applicable LVTTL or HSTL signals will be configured for HSTL/eHSTL

Ifthewrite/readportis10bitswide,thisprovidestheuserwithaQueuedepth

operating voltage levels. To select between HSTL or eHSTL VREF must be of 32,768 x 10 for the IDT72T55248, 65,536 x 10 for the IDT72T55258, or

driven to 0.75V or 0.9V respectively. Typically a logic HIGH in HSTL would 131,072 x 10 for the IDT72T55268. If the write/read port is 20 bits wide, this

beVREF ±300mVandalogicLOWwouldbeVREF ±300mV.IftheIOSELpin provides the user with a Queue depth of 16,384 x 20 for the IDT72T55248,

isLOWduringmasterreset,thenallapplicableLVTTLorHSTLsignalswillbe 32,768x20fortheIDT72T55258,or65,536x20fortheIDT72T55268.Ifthe

configuredforLVTTLoperatingvoltagelevels.InthisconfigurationVREFmust write/readportis40bitswide,thisprovidestheuserwithaQueuedepthof8,192

besettothestaticcorevoltageof2.5V.Table5illustrateswhichpinsareand x40forthe IDT72T55248, 16,384x40forthe IDT72T55258, or32,768x40

arenotassociatedwiththisfeature.Notethatall“StaticPins”mustbetiedtoVCC for the IDT72T55268. The Queue depths will always have a fixed density of

orGND.ThesepinsareCMOSonlyandarepurelydeviceconfigurationpins. 327,680 bits for the IDT72T55248, 655,360 bits for the IDT72T55258 and

NotetheIOSELpinshouldbetiedHIGHorLOWandcannottogglebeforeand 1,310,072bitsfortheIDT72T55268regardlessofbus-widthconfigurationon

aftermasterreset.

thewrite/readport.

Whenthedeviceisoperatingindoubledatarate,thewordistwiceaslarge

asinsingledataratesinceonewordwrittenorreadonboththerisingandfalling

BUS MATCHING

Thewriteandreadporthasbus-matchingcapabilitysuchthattheinputand edge of clock. Therefore in DDR, the Queue depths will be half of what it is

outputbus canbe either10bits, 20bits or40bits wide, dependingonwhich mentionedabove.Forinstance,ifthewrite/readportis10bitswide,thedepth

operatingmodethedeviceisconfiguredto.Thebuswidthofboththeinputand of each Queue is 16,384 x 10 for the IDT72T55248, 32,768 x 10 for the

outputportisdeterminedduringmasterresetusingtheinputandoutputwidth IDT72T55258, or 65,536 x 10 for the IDT72T55268.

setuppins(IW[1:0],OW[1:0]).TheselectedportwidthisappliedtoallfourQueue

ports,suchthatallfourQueueswillbeconfiguredforeitherx10,x20orx40bus

SeeFigure5, Bus-MatchingByteArrangementformoreinformation.

TABLE 5 — I/O VOLTAGE LEVEL ASSOCIATIONS

LVTTL/HSTL/eHSTL

STATIC CMOS SIGNALS

Static Pins

Write Port

D[39:0]

WCLK0/1/2/3

WEN0/1/2/3

FF0/1/2/3

WCS0/1/2/3

CFF/CIR

PAF0/1/2/3

Read Port

JTAG

TCK

TRST

TMS

TDI

Control Pins

Serial Port

SCLK

SREN

SWEN

FWFT/SI

SDO

CEF/COR

EF0/1/2/3

OR0/1/2/3

ERCLK0/1/2/3

OE0/1/2/3

PAE0/1/2/3

Q[39:0]

FSEL[1:0]

IS[1:0]

OS[1:0]

PD

MRS

IOSEL

IW[1:0]

MD[1:0]

OW[1:0]

PFM

TDO

PRS0/1/2/3

FWFT/SI

RDDR

WDDR

RCLK0/1/2/3

RCS0/1/2/3

REN0/1/2/3

EREN[3:0]

FEBRUARY01,2009

24

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

D39-D30

D29-D20

D19-D10

D9-D0

MUX MODE

BYTE ORDER ON INPUT PORT:

1st: Write to Queues

A

B

C

2nd: Write to Queues

3rd: Write to Queues

D

4th: Write to Queues

Queue3

Queue2

Queue1

Queue0

BYTE ORDER ON OUTPUT PORT:

OS1 OS0 OW1 OW0

Q39-Q30

Q29-Q20

Q19-Q10

Q9-Q0

1st: Read from Queues

D

C

B

A

L

H

L

x10 INPUT to x40 OUTPUT for Queue0

Q39-Q30

Q29-Q20

Q19-Q10

Q9-Q0

BYTE ORDER ON OUTPUT PORT:

OS1 OS0 OW1 OW0

B

A

1st: Read from Queues

2nd: Read from Queues

L

H

D

C

x10 INPUT to x20 OUTPUT for Queue0

BYTE ORDER ON OUTPUT PORT:

OS1 OS0 OW1 OW0

Q39-Q30

Q29-Q20

Q19-Q10

Q9-Q0

1st: Read from Queues

A

L

B

C

D

2nd: Read from Queues

3rd: Read from Queues

4th: Read from Queues

x10 INPUT to x10 OUTPUT for Queue0

NOTES:

= High-Z outputs.

= Inputs set to GND.

6157 drw09

Figure 5. Bus-Matching Byte Arrangement (Mux Mode)

FEBRUARY01,2009

25

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

D39-D30

D29-D20

D19-D10

D9-D0

DEMUX MODE

1st: Write to Queues

D

C

B

A

BYTE ORDER ON INPUT PORT:

IS1

L

IS0 IW1 IW0

H

L

Q39-Q30

Q29-Q20

Q19-Q10

Q9-Q0

X

A

1st: Read from Queues

2nd: Read from Queues

B

C

X

3rd: Read from Queues

4th: Read from Queues

X

D

Note:

X is data in the output register.

Queue3

Queue2

Queue1

Queue0

x40 INPUT to x10 OUTPUT for Queue1

BYTE ORDER ON INPUT PORT:

D39-D30

D29-D20

D19-D10

D9-D0

IS1

L

IS0 IW1 IW0

B

A

1st: Write to Queues

H

L

H

Q39-Q30

Q29-Q20

Q19-Q10

Q9-Q0

X

A

1st: Read from Queues

2nd: Read from Queues

X

B

x20 INPUT to x10 OUTPUT for Queue1

D39-D30

D29-D20

D19-D10

D9-D0

BYTE ORDER ON INPUT PORT:

IS1

L

IS0 IW1 IW0

A

1st: Write to Queues

H

L

Q39-Q30

Q29-Q20

Q19-Q10

Qn-Q0

X

1st: Read from Queues

A

x10 INPUT to x10 OUTPUT for Queue1

6157 drw10

Figure 5. Bus-Matching Byte Arrangement (Demux Mode) (Continued)

FEBRUARY01,2009

26

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

D39-D30

D29-D20

D19-D10

D9-D0

BROADCAST MODE

BYTE ORDER ON INPUT PORT:

IW1 IW0

D

C

B

A

1st: Write to Queues

H

L

Q39-Q30

Q29-Q20

Q19-Q10

Q9-Q0

A

1st: Read from Queues

2nd: Read from Queues

B

C

D

C

D

C

D

C

D

3rd: Read from Queues

4th: Read from Queues

x40 INPUT to x10 OUTPUT for Every Queue

BYTE ORDER ON INPUT PORT:

IW1 IW0

D39-D30

D29-D20

D19-D10

D9-D0

B

A

1st: Write to Queues

L

H

Q39-Q30

Q29-Q20

Q19-Q10

Q9-Q0

1st: Read from Queues

2nd: Read from Queues

A

B

x20 INPUT to x10 OUTPUT for Every Queue

BYTE ORDER ON INPUT PORT:

IW1 IW0

D39-D30

D29-D20

D19-D10

D9-D0

A

1st: Write to Queues

L

Q39-Q30

Q29-Q20

Q19-Q10

Q9-Q0

A

1st: Read from Queues

x10 INPUT to x10 OUTPUT to Every Queue

6157 drw11

Figure 5. Bus-Matching Byte Arrangement (Broadcast Mode) (Continued)

FEBRUARY01,2009

27

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

SELECTABLE MODES

thenextclockedgeafterthenewQueueisselected.Forexample,ifOS[1:0]

Thedeviceiscapableofoperatinginthreedifferentmodes,Mux,Demux, issetto01(Queue1)onRCLKedge0,thenonRCLKedge1(nextreadclock

andBroadcastWrite.Eachofthesethreemodescanbeselectedbasedonthe edge) data can be read from Queue1 if REN0 and RCS0 are enabled.

MD[1:0]bits.ThesebitsshouldbetieddirectlytoVCCorGNDastheyarelatched

InFWFTmode,thefirstwordwrittentoaselectedQueuewillautomatically

induringmasterreset.ThestateoftheMDpinsforeachmodeissummarized beplacedontotheoutputbusofthatrespectiveQueueregardlessofthestate

in Table 1 – Device Configuration. ofthecorrespondingreadenable,providedthattheselectedQueuewasempty

EachmodehasaccesstofourdedicatedQueuesinternally,witheachQueue andits correspondingoutputreadyflagwas inactive. This occurs due tothe

having densities of 327,680 bits for the IDT72T55248, 655,360 bits for the natureoftheFWFTflagtiming.Thereisatwocycleinputpipelineandatwocycle

IDT72T55258and1,310,072bitsfortheIDT72T55268.Thedensityofeach outputpipeline.ItwilltaketwocyclesorthreerisingedgesoftheWCLKtomove

Queueisfixedandcannotbeprogrammed.Also,thedensitydoesnotchange datafromthewriteporttothequeueandtwocyclesorthoserisingedgesofRCLK

whenthedeviceisoperatinginsingleordoubledatarate,orwhenthedevice tomovedatafromthequeuetothedataoutlines.SubsequentwritestotheQueue

isutilizingthebus-matchingfeature.

thatisnotemptywillnotfallthroughtotheoutputbus.NoteinFWFTmode,during

TheQuadMuxflow-controldeviceaccommodatesforallofthetimingissues aQueueselectionthenextwordavailableintheQueuewillautomaticallyfall

associated with converging multiple data rates onto one path. Such issues throughtotheoutputbusregardlessofthereadenableandreadchipselect.

includeclockskew,raceconditions,andmeetingsetupandholdtimes.These

InIDTStandardmode,everywordincludingthefirstwordmustbeaccessed

issuesaredifficulttoaddresswhenperformingmuxoperationsfromexternal bythereadenableandreadchipselect.UnlikeFWFTmode,duringaQueue

logicorwithinanFPGA,especiallyathigherfrequencies.Thecomplexityofthe selectionthenextwordavailableintheQueuewillnotautomaticallyfallthrough

designmakesitdifficulttoimplementwithinanFPGA,wherespeeddegradations totheoutputbus.Thepreviouswordthatwasreadoutofthereadportwillremain

occurasthecircuitbecomesmorecomplicated.

on the output bus if the REN and RCS select are HIGH.

MUXMODE

DEMUXMODE

In Mux mode the device is configured as shown in the Mux mode block

InDemuxmodethedeviceisconfiguredasshownintheDemuxmodeblock

diagramonpage1.ThedeviceinthismodeconsistsoffourseparateQueues: diagramonpage2.ThedeviceinthismodeconsistsoffourseparateQueues:

Queue0,Queue1,Queue2andQueue3.ThefourQueuesallhavethesame Queue0,Queue1,Queue2andQueue3.ThefourQueuesallhavethesame

commonreadport,andthereadcontrolselectingwhichQueuetoreadfrom. commonwriteport,andthereadcontrolselectingwhichQueuetoreadfrom.

TheMuxmodecanbeusedinapplicationswheremultipleincomingdatarates The Demuxmode canbe usedinapplications where a single incomingdata

fromdifferentdatapathsarebeingbufferedtoonecommondatarateanddatabus. rateisbeingbufferedtomultipleoutgoingdatarates.

WRITEPORTOPERATION

InMuxmodetherearefourindependentwriteportcontrolsforeachindividual

InDemuxmodetheinputselectpins(IS[1:0])determinewhichoneofthefour

Queue.DatacanbewrittentoanyofthefourQueuesusingitscorresponding Queuestheinputbuswillwritedatainto.Theinputselectpinsaresampledon

writeclock,writeenable,andwritechipselect.Adatawordwillbewrittenon the risingedge ofeveryWCLK, andmaychange oneveryclockedge. Thus

therising(andfallinginDDR)edgeofwriteclockprovidedWENandwritechip thereisnolatencyswitchingfromoneQueuetoanother.NotethatinDemux

selectareactive.Noteindoubledataratethesetupandholdtimesofthewrite modeonlytheWCLK0isactive,allotherinputwriteclocksarenotused.The

enablesandwritechipselectsaresampledwithrespecttotherisingedgeofits sameappliestothewriteenable(WEN0)andwritechipselect(WCS0).Data

respectivewriteclockonly.ThefallingedgeofWCLKdoesnotsamplethewrite willbewrittenontherising(andfallinginDDR)edgeofwriteclockprovidedWEN

enableandwritechipselect.

andWCSareactiveontherisingedgeoftheWCLK.Noteindoubledatarate

InFWFTmodethefirstwordwrittentoanyQueuewillautomaticallybeplaced thesetupandholdtimesoftheWENandWCSselectsaresampledwithrespect

ontotheoutputbusofthatrespectiveQueuewhenselectedonthereadportvia to the rising edge of the write clock only. The falling edge of WCLK does not

the OS[1:0] pins. There is a two cycle input pipeline and a two cycle output samplethewriteenableandwritechipselect.WhenselectingaQueueforwrite

pipeline.ItwilltaketwocyclesorthreerisingedgesoftheWCLKtomovedata operationsthenextwordcanbewrittentothatQueueimmediatelyonthenext

fromthewriteporttothequeueandtwocyclesorthoserisingedgesofRCLK clockedgeafterthenewQueueisselected.Forexample,ifIS[1:0]issetto01

tomovedatafromthequeuetothedataoutlines.Thisisregardlessofthestate (Queue1)onWCLKedge0,thenonWCLKedge1(nextreadclockedge)data

of the corresponding read enable and read chip select, provided that the can be written to Queue1 if WEN0 and WCS0 are enabled.

selectedQueuewasempty.ThisisnottrueinIDTStandardmode,wherethe

InFWFTmodethefirstwordwrittentoaselectedQueuewillautomatically

firstwordwrittentoaselectedQueuemustbeaccessedbysettingRENandRCS beplacedontotheoutputbusregardlessofthestateofthecorrespondingread

are LOW on the rising edge of RCLK.

enable, providedthatthe selectedQueue was emptyandits corresponding

outputreadyflagwasinactive.Thereisatwocycleinputpipelineandatwocycle

outputpipeline.ItwilltaketwocyclesorthreerisingedgesoftheWCLKtomove

READPORTOPERATION

InMuxmodetheoutputselectpins(OS[1:0])determinewhichoneofthefour datafromthewriteporttothequeueandtwocyclesorthoserisingedgesofRCLK

Queuestheoutputbuswillreaddatafrom.Theoutputselectpinsaresampled tomovedatafromthequeuetothedataoutlines.Thisoccursduetothenature

ontherisingedgeofeveryRCLK,andmaychangeoneveryclockedge.Thus oftheFWFTflagtiming.SubsequentwritestotheQueuethatisnotemptywill

thereisnolatencyswitchingfromoneQueuetoanother.NotethatinMuxmode notfallthroughtotheoutputbus.InIDTStandardmode,everywordincluding

onlytheRCLK0isactive,allotheroutputreadclocksarenotused.Thesame the firstwordmustbe accessedbythe readenable andreadchipselect.

applies tothereadenable(REN0)andreadchipselect(RCS0).Datawillbe

readontherising(andfallinginDDR)edgeofreadclockprovidedreadenable READPORTOPERATION

and read chip select are active (LOW). When selecting a Queue for read

In Demux mode there are four independent read port controls for each

operationsthenewwordreadfromthatQueuewillbeavailableimmediatelyon individual Queue. Data can be read from any of the four Queues using its

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

correspondingreadclock,readenable,andreadchipselect.Adatawordwill inputclocksarenotused.Thesameappliestothewriteenable(WEN0)and

be read on the rising (and falling in DDR) edge of read clock provided read writechipselect(WCS0).Datawillbewrittenontherising(andfallinginDDR)

enableandreadchipselectareactive.Therearealsofourindividualoutput edgeofwriteclockprovidedwriteenableandwritechipselectareactive(LOW)

enablesthatwilltaketheoutputbustohigh-impedance.Notethatdatawillbe ontherisingedgeofwriteclock.Writeoperationsareprohibitedifanyofthe

readfrommemoryregardlessofthestateoftheoutputenableOE[3:0]pins. fourQueues are beingpartiallyresetoranyoftheirfullflagstatus full(FF =

Asexplainedabove,inFWFTmodethefirstwordwrittentoeachQueuewill LOW).

automaticallybeplacedontotheoutputbusregardlessoftheofthestateofthe

InFWFTmode,thefirstwordwrittentoaselectedQueuewillautomatically

correspondingreadenable.Thereisatwocycleinputpipelineandatwocycle beplacedontotheoutputbusofthatrespectiveQueueregardlessofthestate

outputpipeline.ItwilltaketwocyclesorthreerisingedgesoftheWCLKtomove ofthecorrespondingreadenable,providedthattheselectedQueuewasempty

datafromthewriteporttothequeueandtwocycles orthoserisingedges of anditscorrespondingoutputreadyflagwasinactive.Thereisatwocycleinput

RCLKtomovedatafromthequeuetothedataoutlines.

pipelineandatwocycleoutputpipeline.Itwilltaketwocyclesorthreerising

edgesoftheWCLKtomovedatafromthewriteporttothequeueandtwocycles

orthoserisingedgesofRCLKtomovedatafromthequeuetothedataoutlines.

ThisoccursduetothenatureoftheFWFTflagtiming.Subsequentwritesto

theQueuethatisnotemptywillnotfallthroughtotheoutputbus.InIDTStandard

mode,everywordincludingthefirstwordmustbeaccessedbythereadenable

andreadchipselect.

BROADCASTWRITEMODE

InBroadcastWritemodethedeviceisconfiguredasshownintheBroadcast

Writemodeblockdiagramonpage2.Thedeviceinthismodeconsistsoffour

separateQueues:Queue0,Queue1,Queue2andQueue3.ThefourQueues

all have one common write port which will write data into all four Queues

simultaneouslywhenawriteoperationisinitiated,thereisnowriteselection

towritedataintoaspecificQueue.TheBroadcastWritemodecanbeusedin

applicationswhereasingleincomingdatabusneedstobesenttomultipledata

pathssimultaneously.

READPORTOPERATION

InBroadcastWritemodetherearefourindependentreadportcontrolsfor

eachindividualQueue.DatacanbereadfromanyofthefourQueuesusing

itscorrespondingreadclock,readenable,andreadchipselect.Adataword

willbereadontherising(andfallinginDDR)edgeofreadclockprovidedread

enableandreadchipselectareactive.Therearealsofourindividualoutput

enablesthatwilltaketheoutputbustohigh-impedance.Notethatdatawillbe

readfrommemoryregardlessofthestateoftheoutputenableOE[3:0]pins.

WRITEPORTOPERATION

InBroadcastWritemodetherearenoinputoroutputselectpinstoselectthe

individualQueuesseparately.ThewriteportwillwritedataintoallfourQueues

simultaneously.NotethatinBroadcastmodeonlytheWCLK0isactive,allother

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

In Demux mode, partial reset may not be performed on the two Queues

involved during Queue selection on the write port. For instance, if IS[1:0] is

switchingfrom11to10thenPRS3andPRS2maynotbeenabledfromthefirst

risingWCLKedgewithOS[1:0]=01untilthreemorerisingWCLKedgeshave

beenreceived.Inotherwords,partialresetmaynotbeperformedforaminimum

ofthreeWCLKcyclesfromthetimeanewQueueisselected. Also,ifQueue0

orQueue1arepartiallyresetbeforetheswitch,theappropriatePRSsignalmust

be HIGHatleasttRSR (resetrecoverytime)before the firstWCLKedge with

IS[1:0]=10. AnyQueues notinvolvedinthe selectioncanbe partiallyreset.

In Broadcast mode, partial reset may not be performed during write

operations.ThewriteenableandwritechipselectmustbeHIGHwithrespect

totherisingedgeofWCLK0foraminimumoftRSSbeforepartialresetcanbe

performed.IfthedeviceisoperatinginDDRmode,partialresetofanyQueue

mustbeinitiatedafterthefallingedgeofWCLK0toensuredatafromthefalling

edgearewrittenintoallfourQueuesinmemory.Thismaintainsthedataintegrity

ofallfourQueues inthe device.

SIGNALDESCRIPTIONS

INPUTS:

DATA INPUT BUS (D[39:0])

Thedatainputbuscanbe40,20,or10bitswideinDemuxandBroadcast

mode.D[39:0]are data inputs forthe 40-bitwide data bus,D[19:0]are data

inputsfor20-bitwidedatabus,andD[9:0]aredatainputsforthe10-bitwide

data bus. InMuxmode the inputbus willbe 10bits wide foreachofthe four

internalQueues.D[9:0]arededicatedtoQueue0,D[19:10]arededicatedto

Queue1,D[29:20]arededicatedtoQueue2,andD[39:30]arededicatedto

Queue 3. Data canbe writtenintoeachofthe fourQueues oneveryWCLK

cycle.Thereisatwocycleinputpipelineandatwocycleoutputpipeline.Itwill

taketwocyclesorthreerisingedgesoftheWCLKtomovedatafromthewrite

porttothequeueandtwocyclesorthoserisingedgesofRCLKtomovedata

fromthequeuetothedataoutlines.

MASTER RESET (MRS)

See Figures 11, 12, 13, Partial Reset Timing, for the associated timing

diagram.

ThereisasinglemasterresetavailableforallinternalQueuesinthisdevice.

AmasterresetisaccomplishedwhenevertheMRSinputistakentoaLOWstate.

ThisoperationsetstheinternalreadandwritepointersofallQueuestothefirst

locationinmemory.TheprogrammablealmostemptyflagwillgoLOWandthe

almostfullflagswillgoHIGH.

IfFWFT/SIsignalisLOWduringmasterresetthenIDTStandardmodeis

selected.ThismodeutilizestheemptyandfullstatusflagsfromtheEF/ORand

FF/IRdual-purposepin.Duringmasterreset,allemptyflagswillbesettoLOW

andallfullflags willbe settoHIGH.

If FWFT/SI signal is HIGH during master reset, then the First Word Fall

Throughmodeisselected. Thismodeutilizestheinputreadandoutputready

statusflagsfromtheEF/ORandFF/IRdual-purposepin.Duringmasterreset,

allinputreadyflagswillbesettoLOWandalloutputreadyflagswillbesetto

HIGH.

FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)

Thisisadualpurposepin.DuringMasterReset,thestateoftheFWFT/SI

inputdetermineswhetherthedevicewilloperateinIDTStandardmodeorFirst

Word Fall Through (FWFT) mode.

IfFWFT/SIisLOWbeforethefallingedgeofmasterreset,thenIDTStandard

modewillbeselected.ThismodeusestheEmptyFlag(EF)toindicatewhether

or not there are any words present in the Queues memory. It also uses the

FullFlagfunction(FF)toindicatewhetherornottheQueuesmemoryhasany

free space for writing. In IDT Standard mode, every word read from the

Queues,includingthefirst,mustberequestedusingtheReadEnable(REN),

Read Chip Select (RCS) and RCLK.

IfFWFT/SIisHIGHbeforethefallingedgeofmasterreset,thenFWFTmode

willbeselected.ThismodeusesOutputReady(OR)toindicatewhetherornot

there is valid data at the data outputs (Qn). It also uses Input Ready (IR) to

indicate whether or not the Queues have any free space for writing. In the

FWFTmode,thefirstwordwrittentoanemptyQueuegoesdirectlytoQnafter

threeRCLKrisingedges,providedthatthefirstRCLKmeets tSKEW param-

eters. TherewillbeaoneRCLKcycledelayiftSKEWisnotmet.RENandRCS

donotneedtobe enabled. Subsequentwords mustbe accessedusingthe

REN, RCS, and RCLK. RCS must be LOW or the outputs will be in a High-

state.

The state of the FWFT/SI input must be kept at the present state for the

minimumoftheresetrecoverytime(tRSR)aftermasterreset.Afterthistime,the

FWFT/SI acts as a serial input for loading PAE and PAF offsets into the

programmable offset registers. The serial input is used in conjunction with

SCLK,SWEN,SREN,andSDOtoaccesstheoffsetregisters.Serialprogram-

mingusingtheFWFT/SIpinfunctionsthesamewayinbothIDTStandardand

FWFTmodes.

Alldevice configurationpins suchas MD[1:0], OW[1:0], IW[1:0], IS[1:0],

OS[1:0],WDDR,RDDR,IOSEL,PFM,FSEL[1:0]andFWFT/SIneedstobe

definedbeforethemasterresetcycle.Duringamasterresettheoutputregister

isinitializedtoallzeros.Iftheoutputenable(s)areLOWduringmasterreset,

thentheoutputbuswillbeLOW.Iftheoutputenable(s)areHIGHduringmaster

reset,thentheoutputbuswillbeinHigh-impedance.RCShasnoaffectonthe

dataoutputsduringmasterreset.IftheoutputwidthOW[1:0]isconfiguredto

x10orx20,thentheunusedoutputswillbeinhigh-impedance.Amasterreset

isrequiredafterpowerupbeforeawriteoperationtoanyQueuecantakeplace.

Masterresetisanasynchronoussignalandthusthereadandwriteclockscan

be free-running or idle during master reset. See Figure 10, Master Reset

Timing,fortheassociatedtimingdiagram.

PARTIALRESET(PRS0/1/2/3)

Apartialresetisameansbywhichtheusercanresetboththereadandwrite

pointers of each individual Queue inside the device without changing the

Queue’sconfiguration.Therearefourdedicatedpartialresetsignalsthateach

correspondtoanindividualQueue.Therearerestrictions as towhenpartial

resetcanbeperformedthatapplytoeachoperatingmodes.

WRITE CLOCK (WCLK0/1/2/3)

There are a possible total of four write clocks available in this device

dependingonthemodeselected,eachcorrespondingtotheindividualQueues

inmemory.Awritecycleisinitiatedontherisingand/orfallingedgeoftheWCLK

input.Ifthewritedoubledatarate(WDDR)modepinistiedHIGHduringmaster

reset,datawillbewrittenonboththerisingandfallingedgeofWCLK0/1/2/3,

providedthatWEN0/1/2/3andWCS0/1/2/3areenabled.IfWDDRistiedLOW,

datawillbewrittenonlyontherisingedgeofWCLK0/1/2/3providedthatWEN0/

1/2/3 and WCS0/1/2/3 are enabled. The four write clocks are completely

independentofoneanother.

InMuxmode,partialresetmaynotbeperformedonthetwoQueuesinvolved

duringQueueselectiononthereadport.Forinstance,ifOS[1:0]isswitching

from00to01thenPRS0andPRS1maynotbeenabledfromthefirstrisingRCLK

edgewithOS[1:0]=01untilthreemorerisingRCLKedgeshavebeenreceived.

Inotherwords,partialresetmaynotbeperformedforaminimumofthreeRCLK

cyclesfromthetimeanewQueueisselected.Also,ifQueue0orQueue1are

partiallyresetbeforetheswitch,theappropriatePRSsignalmustreturnHIGH

atleasttRSR(resetrecoverytime)beforethefirstRCLKedgewithOS[1:0]=01.

AnyQueues notinvolvedinthe selectioncanbe partiallyreset.

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

DatasetupandholdtimesmustbemetwithrespecttotheLOW-to-HIGH(and Indoubledataratethewriteenablesignalsaresampledwithrespecttotherising

HIGH-to-LOWinDDR)transitionofthewriteclock(s).Itispermissibletostop edgeofwriteclockonly,andawordwillbewrittenonboththerisingandfalling

thewriteclock(s).Notethatwhilethewriteclocksareidle,theFF/IR0/1/2/3and edgeofwriteclockregardlessofwhetherornotthewriteenablesareactive

PAF0/1/2/3flags willnotbe updatedunless itis operatinginasynchronous onthefallingedgeofwriteclock.

timing mode (PFM=00). The write clocks can either be independent or

coincidentofoneanother.

WhenWDDRisLOW,thewriteportwillbesettosingledataratemode.In

this mode,allwriteoperations arebasedononlytherisingedgeofthewrite

InDemuxandBroadcastWritemode,onlytheWCLK0inputis available. clocks,providedthatwriteenablesandwritechipselectsareLOWduringthe

Allotherwriteclocks inputs shouldbetiedtoGND.

risingedge ofwrite clock. This pinshouldbe tiedHIGHorLOWandcannot

togglebeforeoraftermasterreset.

WRITE ENABLE (WEN0/1/2/3)

There are a possible total of four write enables available in this device READ CLOCK (RCLK0/1/2/3)

dependingonthemodeselected,oneforeachindividualQueuesinmemory.

There are a possible total of four read clocks available in this device

WhenthewriteenableinputisLOWontherisingedgeofWCLKinsingledata dependingonthemodeselected,eachcorrespondingtotheindividualQueues

rate, data is loaded on the rising edge of every WCLK cycle, provided the inmemory.Areadcycleisinitiatedontherisingand/orfallingedgeoftheRCLK

device is notfullandthe write chipselect(WCS)is enabled. The setupand input.Ifthereaddoubledatarate(RDDR)modepinistiedHIGH,datawillbe

holdtimesarereferencedwithrespecttotherisingedgeofWCLKonly.When readonboththerisingandfallingedgeofRCLK0/1/2/3,providedthatREN0/

thewriteenableinputisLOWontherisingedgeofWCLKindoubledatarate, 1/2/3 and RCS0/1/2/3 are enabled. If RDDR is tied LOW, data will be read

dataisloadedintotheselectedQueueontherisingandfallingedgeofevery onlyontherisingedgeofRCLK0/1/2/3providedthatREN0/1/2/3andRCS0/

WCLKcycle, providedthe device is notfullandthe write chipselect(WCS) 1/2/3are enabled. The fourreadclocks are completelyindependentofone

is enabled. Inthis mode, the data setupandholdtimes are referencedwith another.

respecttotherisingandfallingedgeofWCLK.NotethatWENandWCSare

sampledonlyonthe risingedge ofWCLKineitherdata rate modes.

Thereis anassociateddataaccess time(tA)forthedatatobereadoutof

theQueues.Itispermissibletostopthereadclocks.Notethatwhiletheread

DataisstoredintheQueuessequentiallyandindependentlyofanyongoing clocks are idle, the EF/OR0/1/2/3andPAE0/1/2/3flags willnotbe updated

readoperation.Whenthewriteenable(s)andwritechipselect(s)areHIGH, unless itis operatinginasynchronous timingmode(PFM=0).Thewriteand

nonewdataiswrittenintothecorrespondingQueueoneachWCLKcycle.The readclockscaneitherbeindependentorcoincident.

fourwriteenables operateindependentofoneanother.

InMuxmode,onlytheRCLK0inputisavailable.Allotherreadclockinputs

InDemuxandBroadcastmode,onlytheWEN0inputisavailable.Allother shouldbe tiedtoGND.

write enables should be tied to VCC.

READ ENABLE (REN0/1/2/3)

There are a possible total of four read enables available in this device

WRITE CHIP SELECT (WCS0/1/2/3)

Thereareapossibletotaloffourwritechipselectsavailableinthisdevice dependingonthemodeselected,oneforeachindividualQueueinmemory.

dependingonthemodeselected,oneforeachindividualQueuesinmemory. WhenthereadenableinputisLOWontherisingedgeofRCLKinsingledata

ThewritechipselectsdisablesallWritePortinputsforeachindividualQueue rate, data willbe readonthe risingedge ofeveryRCLKcycle, providedthe

ifitisheldHIGH.ToperformnormalwriteoperationsforeachindividualQueue, deviceisnotemptyandthereadchipselect(RCS)isenabled.Theassociated

thewritechipselectmustbeenabled,heldLOW.Thefourwritechipselects dataaccess time(tA)is referencedwithrespecttotherisingedgeofRCLK.

arecompletelyindependentofoneanother.

WhenthereadenableinputisLOWontherisingedgeofRCLKindoubledata

WhenthewritechipselectisLOWontherisingedgeofWCLKinsingledata rate,willbereadontherisingandfallingedgeofeveryRCLKcycle,provided

rate, data is loaded on the rising edge of every WCLK cycle, provided the thedeviceisnotemptyandRCSisenabled.Inthismode,thedataaccesstimes

deviceis notfullandthewriteenable(WEN)ofthecorrespondingQueueis arereferencedwithrespecttotherisingandfallingedgesofRCLK.Notethat

LOW.WhenthewritechipselectisLOWontherisingedgeofWCLKindouble REN is sampledonlyonthe risingedge ofRCLKineitherdata rate modes.

datarate,dataisloadedintotheselectedQueueontherisingandfallingedge

ofeveryWCLKcycle,providedthedeviceisnotfullandthewriteenable(WEN) writeoperation.Whenthereadenable(s)andreadchipselect(s)areHIGH,

ofthecorrespondingQueueisLOW. no new data is read on each RCLK cycle. The four read enables operate

WhenthewritechipselectisHIGHontherisingedgeofWCLKinsingledata independentofoneanother.

DataisstoredintheQueuessequentiallyandindependentlyofanyongoing

rate,thewriteportis disabledandnowords arewrittenontherisingedgeof

TopreventreadingfromanemptyQueue inthe IDTStandardmode, the

WCLKintotheQueue,evenifWENisLOW.IfthewritechipselectisHIGHon emptyflagofeachQueuewillgoLOWwithrespecttoRCLK,whenthetotal

therisingedgeofWCLKindoubledatarate,thewriteportisalsodisabledand numberofwordsintheQueuehasbeenreadout,thusinhibitingfurtherread

nowords arewrittenontherisingandfallingedgeofWCLKintotheQueue, operations.Uponthecompletionofavalidwritecycle,theemptyflagwillgo

evenifWENisLOW.NotethatWCSissampledontherisingedgeofWCLK HIGH with respect to RCLK two cycles later, thus allowing another read to

onlyineitherdata rate modes.

InDemuxandBroadcastmode,onlytheWCS0inputisavailable.Allother

write chipselects shouldbe tiedtoVCC.

occur,providingtSKEW ofWCLKtoRCLKis met.

InMuxmode,onlytheREN0inputisavailable.Allotherreadenablesshould

be tied to VCC.

WRITE DOUBLE DATA RATE (WDDR)

READ CHIP SELECT (RCS0/1/2/3)

Whenthewritedoubledatarate(WDDR)pinisHIGHpriortomasterreset,

Thereareapossibletotaloffourreadchipselectsavailableinthisdevice,

the write port will be set to double data rate mode. In this mode, all write eachcorrespondingtotheindividualQueueinmemory.Thereadchipselect

operationsarebasedontherisingandfallingedgeofthewriteclocks,provided inputsprovidessynchronouscontrolofthereadportforeachindividualQueue.

thatwriteenablesandwritechipselectsareLOWfortherisingclockedges. WhenthereadchipselectisheldLOW,thenextrisingedgeofthecorrespond-

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

ingRCLKwillenable the outputbus.Whenthereadchipselectgoes HIGH, operatingvoltage levels. ToselectbetweenHSTLoreHSTLVREFmustbe

thenextrisingedgeofRCLKwillsendtheoutputbusintohigh-impedanceand driven to 0.75V or 0.9V respectively.

preventthatRCLKfrominitiatingaread,regardlessofthestateofREN.During

Ifthe IOSELpinis LOWduringmasterreset, thenallapplicable LVTTLor

amasterorpartialResetthereadchipselectinputhasnoeffectontheoutput HSTL signals will be configured for LVTTL operating voltage levels. In this

bus, outputenable (OE[3:0])is the onlyinputthatprovides high-impedance configurationVREFshouldbesettothestaticcorevoltageof2.5V.

controloftheoutputbus.IfoutputenableisLOW,thedataoutputswillbeactive

ThispinshouldbetiedHIGHorLOWandcannottogglebeforeoraftermaster

regardlessofreadchipselectuntilthefirstrisingedgeofRCLKafteraresetis reset.Pleaserefertotable5foralistofapplicableLVTTL/HSTL/eHSTLsignals.

complete.AfterwardsifreadchipselectisHIGHthedataoutputswillgotohigh-

impedance. The four read chip selects are completely independent of one POWER DOWN (PD)

another.

This device has a power down feature intended for reducing power

Thereadchipselectinputsdonotaffecttheupdatingoftheflags.Forexample, consumptionforHSTL/eHSTLconfiguredinputswhenthedeviceisidlefora

whenthefirstwordiswrittentoany/allemptyQueues,theemptyflag(s)willstill long period of time. By entering the power down state certain inputs can be

go from LOW to HIGH based on a rising edge of the RCLK(s), regardless of disabled,therebysignificantlyreducingthepowerconsumptionofthepart.All

thestateofthereadchipselectinputs.Also,whenoperatingtheQueueinFWFT WENandRENsignalsmustbedisabledforaminimumoffourWCLKandRCLK

modethefirstwordwrittentoany/allemptyQueueswillstillbeclockedthrough cycles before activating the power down signal. The power down signal is

totheoutputbusonthethirdrisingedgeofRCLK(s),regardlessofthestateof asynchronousandneedstobeheldLOWthroughoutthedesiredpowerdown

readchipselectinputs,assumingthatthetSKEWparameterismet.Forthisreason time.Duringpowerdown,thefollowingconditionsfortheinputs/outputssignals

theusershouldpayextraattentiontothereadchipselectswhenadataword are:

iswrittentoany/allemptyQueuesinFWFTmode.Ifthereadchipselectinputs

areHIGHwhenanemptyQueueis writteninto,thefirstwordwillfallthrough

totheoutputregisterbutwillnotbeavailableontheoutputsbecausetheyare

inhigh-impedance.Theusermustenablethereadchipselectsonthenextrising

edgeofRCLKtoaccessthisfirstword.

•

All data in Queue(s) are retained.

Alldatainputsbecomeinactive.

Allwriteandreadpointersmaintaintheirlastvaluebeforepowerdown.

Allenables,chipselects,andclockinputpinsbecomeinactive.

Alldataoutputsbecomeinactiveandenterhigh-impedancestate.

Allflagoutputswillmaintaintheircurrentstatesbeforepowerdown.

Allprogrammableflagoffsetsmaintaintheirvalues.

Allechoclocksandenableswillbecomeinactiveandenter

high-impedancestate.

InMuxmode,onlytheRCS0inputisavailable.Allotherreadchipselectinputs

should be tied to VCC.

READ DOUBLE DATA RATE (RDDR)

Whenthereaddoubledatarate(RDDR)pintiedHIGH,thereadportwillbe

settodoubledataratemode,sampledduringmasterreset.Inthismode,allread

operationsarebasedontherisingandfallingedgeofthereadclocks,provided

thatreadenables andreadchipselects areLOW.Indoubledataratemode,

thereadenablesignalsaresampledwithrespecttotherisingedgeofreadclock

only,andawordwillbereadfromboththerisingandfallingedgeofreadclock

•

TheserialprogrammingandJTAGportwillbecomeinactiveandenter

high-impedancestate.

AllsetupandconfigurationCMOSstaticinputsarenotaffected,asthese

pins are tied to a known value and do not toggle during operation.

Allinternalcounters,registers,andflagswillremainunchangedandmaintain

regardless of whether or not read enable and read chip select are active on theircurrentstatepriortopowerdown.Clockinputscanbecontinuousandfree-

thefallingedgeofreadclock. runningduringpowerdown,butwillhavenoaffectonthepart.However,itis

WhenRDDRistiedLOWatmasterreset,thereadportwillbesettosingle recommendedthattheclockinputsbelowwhenthepowerdownisactive.To

dataratemode.Inthismode,allreadoperationsarebasedononlytherising exitpowerdownstateandresumenormaloperations,disablethepowerdown

edgeofthereadclocks,providedthatreadenablesandreadchipselectsare signalbybringingitHIGH.Theremustbeaminimumof1µswaitingperiodbefore

LOWduringtherisingedgeofreadclock.ThispinshouldbetiedHIGHorLOW readandwriteoperationscanresume.Thedevicewillcontinuefromwhereit

andcannottogglebeforeandaftermasterreset.

hadstopped,noformofresetisrequiredafterexitingpowerdownstate.The

powerdownfeaturedoesnotprovideanypowersavingswhentheinputsare

configuredforLVTTLoperation.However,itwillreducethecurrentforI/Osthat

OUTPUTENABLE(OE0/1/2/3)

Thereareapossibletotaloffourasynchronousoutputenablesavailablein are not tied directly to VCC or GND. See Figure 39, Power Down Operation

thisdevice,eachcorrespondingtotheindividualQueuesinmemory.Whenthe fortheassociatedtimingdiagram.

outputenableinputsareLOW,theoutputbusofeachindividualQueuebecome

activeanddrivesthedatacurrentlyintheoutputregister.Whentheoutputenable SERIAL CLOCK (SCLK)

inputs(OE[3:0])areHIGH,theoutputbusofeachindividualQueuegoesinto

Theserialclockisusedtoloaddataandreaddatafromintheprogrammable

high-impedance.DuringmasterorpartialResettheoutputenableistheonly offsetregisters.Datafromtheserialinputsignal(FWFT/SI)canbeloadedinto

inputthatcanplacetheoutputdatabusintohigh-impedance.Duringresetthe the offset registers on the rising edge of SCLK provided that the serial write

readchipselectinputhasnoeffectontheoutputdatabus.Thefouroutputenable enable(SWEN)signalisLOW.Datacanbereadfromtheoffsetregistersvia

inputsarecompletelyindependentofoneanother.

theserialdataoutput(SDO)signalontherisingedgeofSCLKprovidedthat

InMuxmode,onlytheOE0inputisavailable.Allotheroutputenableinputs SRENisLOW.Theserialclockcanoperateatamaximumfrequencyof10MHz.

shouldbe tiedtoGND.

The read operation is non-destructive. However, the write operation will

changetheflagoffsetsoneachSCLKrisingedgeasdatashiftsintotheregisters.

I/O SELECT (IOSEL)

TheinputsandoutputsofthisdevicecanbeconfiguredforeitherLVTTLor SERIAL WRITE ENABLE (SWEN)

HSTL/eHSTLoperation.IftheIOSELpinisHIGHduringmasterreset,thenall

Theserialwriteenableinputisanenableusedforserialprogrammingofthe

applicable LVTTL or HSTL signals will be configured for HSTL/eHSTL programmable offset registers. It is used in conjunction with the serial input

FEBRUARY01,2009

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

(FWFT/SI) and serial clock (SCLK) when programming the offset registers.

The empty/outputreadyflags are synchronous andupdatedonthe rising

WhentheserialwriteenableisLOW,dataattheserialinputisloadedintothe edgeofRCLK.InIDTStandardmode,theflagsaredoubleregister-buffered

offsetregister,onebitforeachLOW-to-HIGHtransitionofSCLK.Whenserial outputs.InFWFTmode,theflagsaretripleregister-bufferedoutputs.Thefour

writeenableis HIGH,theoffsetregisters retaintheprevious settings andno empty flags operate independent of one another and always indicate the

offsets are loaded. Serial write enable functions the same way in both IDT respectiveQueue’sstatus.

StandardandFWFTmodes.

COMPOSITEEMPTY/OUTPUTREADYFLAG(CEF/COR)

SERIAL READ ENABLE (SREN)

This status pin is used to determine the empty state of the current Queue

Theserialreadenableinputis anenableusedforreadingthevalueofthe selected.Thecompositeempty/outputreadyflagrepresentsthestateofthe

programmableoffsetregisters.Itisusedinconjunctionwiththeserialdataoutput Queueselectedonthereadport,suchthattheuserdoesnothavetomonitor

(SDO) and serial clock (SCLK) when reading the offset registers. When the eachindividualQueues’empty/outputreadyflags.Thecompositeempty/output

serialreadenableisLOW,dataattheserialdataoutputcanbereadfromthe readyflagisonlyavailableinMuxmode,sincetheoutputselectbits(OS[1:0])

offsetregister,onebitforeachLOW-to-HIGHtransitionofSCLK.Whenserial are used to select any one of the four Queues to read from.

readenableisHIGH,thereadingoftheoffsetregisterswillstop.Wheneverserial

Thetimingofthecompositeempty/outputreadyflagdiffersinIDTStandard

readenable(SREN)isactivatedvaluesintheoffsetregistersarereadstarting andFWFTmodes.InIDTStandardmode,whenswitchingfromoneQueueto

fromthefirstlocationintheoffsetregisters.TheSRENHIGHtoLOWtransition another,thecompositeemptyflagwillupdatetothestatusofthenewlyselected

copiesthevaluesintheoffsetregistersdirectlyintoaserialscanoutregister. QueueoneRCLKcycleaftertherisingedgeofRCLKthatmadethenewQueue

SRENmustbekeptLOWinordertoreadtheentirecontentsoftheoffsetregister. selection.InFWFTmode,thecompositeoutputreadyflagwillupdatetothestatus

IfatanypointSRENistoggledHIGHtoLOW,anothercopyfunctionfromthe ofthenewlyselectedQueueontwoclockcyclesaftertherisingedgeofRCLK

offset register to the serial scan out register will occur. Serial read enable thatmadethenewQueueselection.SeeFigures26,27fortheassociatedtiming

functions the same wayinbothIDTStandardandFWFTmodes.

diagram.SeeTable3and4“StatusFlagsforIDTStandardandFWFTMode

“forthetruthtableofthecompositeemptyflag.

OUTPUTS:

FULL/INPUT READY FLAG (FF/IR0/1/2/3)

DATA OUTPUT BUS (Q[39:0])

Therearefourfull/inputreadyflagsavailableinthisdevice,eachcorresponding

totheindividualQueuesinmemory.Thisisadual-purposepinthatisdetermined

basedonthestateoftheFWFT/SIpinduringmasterresetforselectingthetwo

timingmodesofthisdevice.IntheIDTStandardmode,thefullflagsareselected.

WhenanindividualQueueisfull,itsfullflagswillgoLOWaftertherisingedge

ofWCLKthatwrotethelastword,thusinhibitingfurtherwriteoperationstothe

Queue.WhenthefullflagisHIGH,theindividualQueueisnotfullandvalidwrite

operationscanbeapplied.SeeFigures14,15,16,WriteCycle,FullFlagand

First Word Latency Timing (IDT Standard Mode), for the associated timing

diagram.AlsoseeTable3“StatusFlagsforIDTStandardMode”forthetruth

tableofthefullflags.

Thedataoutputbuscanbe40,20,or10bitswideinMuxmode.Q[39:0]are

dataoutputsforthe40-bitwidedatabus,Q[19:0]aredataoutputsfor20-bitwide

databus,andQ[9:0]aredataoutputs forthe10-bitwidedatabus.InDemux

andBroadcastmodetheoutputbuswillbe10bitswideforeachofthefourinternal

Queues.Q[9:0]arededicatedtoQueue0,Q[19:10]arededicatedtoQueue

1,Q[29:20]arededicatedtoQueue2,andQ[39:30]arededicatedtoQueue

3.InFWFTmode,whenswitchingfromoneQueuetoanother,thedataofthe

newlyselectedQueuewillalwaysbepresentontheoutputbustwocyclesafter

thenextRCLKcycleafterOS[1:0]isselectedprovidingRCSisLOWregardless

ofwhetherornotRENisactive.ThuseachofthefourQueuescanbeaccessed

on every RCLK cycle.

InFWFTmode,theinputreadyflagsareselected.InputreadyflagsgoLOW

whenthereisadequatememoryspaceintheQueuesforwritingindata.The

inputreadyflagsgoHIGHaftertherisingedgeofWCLKthatwrotethelastword,

when there are no free spaces available for writing in data. See Figures 17,

18,19,WriteTiming(FWFTMode),fortheassociatedtiminginformation.Also

seeTable4“StatusFlagsforFWFTMode”forthetruthtableofthefullflags.The

inputreadystatusnotonlymeasuresthedepthoftheQueuesmemory,butalso

countsthepresenceofawordintheoutputregister.Thus,inFWFTmode,the

totalnumberofwritesnecessarytomakeIRHIGHisonegreaterthanneeded

to set FF = LOW in IDT Standard mode.

InBroadcastmode,whenanyoneofthefourfullflagsbecomesasserted,

allwriteoperationstoeveryQueuewillbedisabled.Thismaintainsdataintegrity

throughoutallfourQueuesforcomparison.Inallothermodes,thefullflagwill

onlydisablewriteoperationstoitscorrespondingQueue.

FF/IRissynchronousandupdatedontherisingedgeofWCLK.FF/IRare

doubleregister-bufferedoutputs.Thefourfullflagsoperateindependentofone

another,exceptinBroadcastmode.

EMPTY/OUTPUTREADYFLAG(EF/OR0/1/2/3)

There are four empty/output ready flags available in this device, each

correspondingtotheindividualQueuesinmemory.Thisisadual-purposepin

thatisdeterminedbasedonthestateoftheFWFT/SIpinduringmasterreset

forselectingoneofthetwotimingmodesofthisdevice.IntheIDTStandardmode,

theemptyflagsareselected.WhenanindividualQueueisempty,itsemptyflag

willgoLOW,inhibitingfurtherreadoperationsfromthatQueue.Whentheempty

flagisHIGH,theindividualQueueisnotemptyandvalidreadoperationscan

beapplied.SeeFigure24,25,ReadCycle,EmptyFlagandFirstWordLatency

Timing(IDTStandardMode),fortherelevanttiminginformation.AlsoseeTable

3“Status Flags forIDTStandardMode”forthetruthtableoftheemptyflags.

InFWFTmode,theoutputreadyflagsareselected.Outputreadyflags(OR)

goLOWatthesametimethatthefirstwordwrittentoanemptyQueueappears

ontheoutputs,whichisaminimumofthreereadclockcyclesprovidedtheRCLK

andWCLKmeetsthetSKEWparameter.ORstaysLOWaftertheRCLKLOW-

to-HIGHtransitionsthatshiftsthelastwordfromtheQueuetotheoutputs.OR

goesHIGHwhenanenabledreadoperationisperformedtoanemptyqueue.

Thepreviousdatastaysattheoutputs,indicatingthelastwordwasread.Further

datareadsareinhibiteduntilanewwordisonthebuswhenORgoesLOWagain.

See Figure 21, 22, 23, Read Timing (FWFT Mode), for the relevant timing

information.AlsoseeTable4“StatusFlagsforFWFTMode”forthetruthtable

oftheemptyflags.

TopreventdataoverflowintheIDTStandardmode,thefullflagofeachQueue

willgoLOWwithrespecttoWCLK,whenthemaximumnumberofwordshas

beenwrittenintotheQueue,thusinhibitingfurtherwriteoperations.Uponthe

completionofavalidreadcycle,thefullflagwillgoHIGHwithrespecttoWCLK

twocycleslater,thusallowinganotherwritetooccur,providedtSKEWhasbeen

met.

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

To prevent data overflow in the FWFT mode, the input ready flag of each

QueuewillgoHIGHwithrespecttoWCLK,whenthemaximumnumberofwords

hasbeenwrittenintotheQueue,thusinhibitingfurtherwriteoperations.Upon

thecompletionofavalidreadcycle,theinputreadyflagwillgoLOWwithrespect

toWCLKtwocycleslater,thusallowinganotherwritetooccur,providedtSKEW

hasbeenmet.

settingforthisvalueisstatedinTable2.SincetherearefourinternalQueues

hencefourPAFoffsetvalues,m0,m1,m2,andm3.

TherearetwotimingmodesavailableforthePAFflags,selectablebythestate

oftheProgrammableFlagMode(PFM)pinduringmasterreset.IfPFMistied

HIGH, then synchronous timing mode is selected. If PFM is tied LOW, then

asynchronoustimingmodeisselected.InsynchronousPAFconfiguration,the

PAF flag is updated on the rising edge of WCLK. In asynchronous PAF

configuration,thePAFflagisassertedLOWontheLOW-to-HIGHtransitions

COMPOSITE FULL/INPUT READY FLAG (CFF/CIR)

ThisstatuspinisusedtodeterminethefullstateofthecurrentQueueselected. of the Write Clock (WCLK). PAF is reset to HIGH on the LOW-to-HIGH

Thecompositefull/inputreadyflagrepresentsthestateoftheQueueselected transitionsoftheReadClock(RCLK).SeeFigures35and37,Synchronous

onthewriteport,suchthattheuserdoes nothavetomonitoreachindividual and Asynchronous Programmable Almost-Full Flag Timing (IDT Standard

Queues’ full/input ready flags. The composite full/input ready flag is only andFWFTmode),fortherelevanttiminginformation.

available in both Demux and Broadcast modes. When switching from one

The four programmable almost full flags operate independent of one

Queuetoanother,thecompositefull/inputreadyflagwillupdatetothestatusof another.

thenewlyselectedQueueoneWCLKcycleaftertherisingedgeofWCLKthat

madethenewQueueselection,regardlessofwhichtimingmodethedeviceis

operatingin.SeeFigure28,CompositeFullFlagfortherelevantassociated

timingdiagram.SeeTable3and4“StatusFlagsforIDTStandardandFWFT

Mode“forthetruthtableofthecompositefullflag

TABLE 6 — TSKEW MEASUREMENT

Data Port

Configuration

Status Flags

TSKEW Measurement

Datasheet

Parameter

PROGRAMMABLEALMOSTEMPTYFLAG(PAE0/1/2/3)

Therearefourprogrammablealmostemptyflags availableinthis device,

eachcorrespondingtotheindividualQueuesinmemory.Theprogrammable

almostemptyflagisanadditionalstatusflagthatnotifiestheuserwhentheQueue

isnearempty.Theusermayutilizethisfeatureasanearlyindicatorastowhen

theQueuewillbecomeempty.InIDTStandardmode,PAEwillgoLOWwhen

therearenwords orless intheQueue.InFWFTmode,thePAE willgoLOW

whentherearen-1wordsorlessintheQueue.Theoffset“n”istheemptyoffset

value.ThedefaultsettingforthisvalueisstatedinTable2.Sincetherearefour

internalQueues hence fourPAE offsetvalues, n0, n1, n2, andn3.

TherearetwotimingmodesavailableforthePAEflags,selectablebythestate

oftheProgrammableFlagMode(PFM)pinduringmasterreset.IfPFMistied

HIGH, then synchronous timing mode is selected. If PFM is tied LOW, then

asynchronoustimingmodeisselected.InsynchronousPAEconfiguration,the

PAE flag is updated on the rising edge of RCLK. In asynchronous PAE

configuration,thePAEflagisassertedLOWontheLOW-to-HIGHtransitionsof

theReadClock(RCLK).PAEisresettoHIGHontheLOW-to-HIGHtransitions

of the Write Clock (WCLK). See Figure 36, and 38, Synchronous and

AsynchronousProgrammableAlmost-EmptyFlagTiming(IDTStandardand

FWFTmode),fortherelevanttiminginformation.

DDR Input

to

EF/OR

FF/IR

PAE

Negative Edge WCLK to

Positive Edge RCLK

tSKEW2

tSKEW3

DDR Output

Negative Edge RCLK to

Positive Edge WCLK

Negative Edge WCLK to

Positive Edge RCLK

PAF

Negative Edge RCLK to

Positive Edge WCLK

DDR Input

to

EF/OR

FF/IR

PAE

Negative Edge WCLK to

Positive Edge RCLK

tSKEW2

tSKEW1

tSKEW3

SDR Output

Positive Edge RCLK to

Positive Edge WCLK

Negative Edge WCLK to

Positive Edge RCLK

PAF

Positive Edge RCLK to

Positive Edge WCLK

SDR Input

to

EF/OR

FF/IR

PAE

Positive Edge WCLK to

Positive Edge RCLK

tSKEW1

tSKEW2

tSKEW3

The four programmable almost empty flags operate independent of one

another.

DDR Output

Negative Edge RCLK to

Positive Edge WCLK

Positive Edge WCLK to

Positive Edge RCLK

PROGRAMMABLE ALMOST FULL FLAG (PAF0/1/2/3)

Therearefourprogrammablealmostfullflagsavailableinthisdevice,each

correspondingtotheindividualQueuesinmemory.Theprogrammablealmost

fullflagisanadditionalstatusflagthatnotifiestheuserwhentheQueueisnearly

full.TheusermayutilizethisfeatureasanearlyindicatorastowhentheQueue

will not be able to accept any more data and thus prevent data from being

dropped.InIDTStandardmode,ifnoreadsareperformedaftermasterreset,

PAFwillgoLOWafter(D-m)(Dmeaningthedensityoftheparticulardevice)

wordsarewrittentotheQueue.InFWFTmode,PAFwillgoLOWafter(D+1-

m)wordsarewrittentotheQueue.Theoffset“m”isthefulloffsetvalue.Thedefault

PAF

Negative Edge RCLK to

Positive Edge WCLK

SDR Input

to

EF/OR

FF/IR

PAE

Positive Edge WCLK to

Positive Edge RCLK

tSKEW1

tSKEW3

SDR Output

Positive Edge RCLK to

Positive Edge WCLK

Positive Edge WCLK to

Positive Edge RCLK

PAF

Positive Edge RCLK to

Positive Edge WCLK

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

ECHO READ CLOCK (ERCLK0/1/2/3)

OperationinDouble Data Rate Mode andFigure 28, EchoRCLKandEcho

There are four echo read clock outputs available in this device, each RENOperationfortiminginformation.Thefourechoreadclockoutputsoperate

correspondingtotheirrespective inputreadclocks inthe Queue. The echo independentofone anotherandare directcopies oftheirrespective RCLK

readclockisafree-runningclockoutput,thatwillalwaysfollowtheRCLKinput inputs.

regardless of the read enables and read chip selects. The ERCLK output

followstheRCLKinputwithanassociateddelay.Thisdelayprovidestheuser ECHOREADENABLE(EREN0/1/2/3)

withamoreeffectivereadclocksourcewhenreadingdatafromtheoutputbus.

There are four echo read enable outputs available in this device, each

Thisisespeciallyhelpfulathighspeedswhenvariableswithinthedevicemay corresponding to the individual Queues in memory. The echo read enable

causechangesinthedataaccesstimes.Thesevariationsinaccesstimemay output is provided to be used in conjunction with the echo read clock and

becausedbyambienttemperature,supplyvoltage,ordevicecharacteristics. provides the device receiving data from the Queue with a more effective

Anyvariationseffectingthedataaccesstimewillalsohaveacorresponding scheme for reading the Queues’ data. The echo read enable output is

effectontheechoreadclockoutputproducedbythedevice,thereforetheecho controlledbyinternallogicthatbecomesactiveforthereadclockcyclethata

readclockoutputleveltransitionsshouldalwaysbeatthesamepositionintime newwordisreadoutoftheQueue.Thatis,arisingedgeofreadclockwillcause

relativetothedataoutputs.Note,thatechoreadclockisguaranteedbydesign echoreadenabletogoLOW,ifbothreadenableandreadchipselectareactive

tobeslowerthantheslowestdataoutputs.RefertoFigure6,EchoReadClock andtheQueueisnotempty.Inotherwords,everycycleputsdataontheoutput

andDataOutputRelationship,Figure27,EchoReadClockandReadEnable bus anddrives EREN outputtothe LOW.

RCLK

tERCLK

ERCLK

t

A⁽⁵⁾

t

A

t

D

Q

SLOWEST⁽³⁾

6157 drw12

NOTES:

1. REN is LOW. OE is LOW.

2. tERCLK > tA, guaranteed by design.

3. Qslowest is the data output with the slowest access time, tA.

4. Time, tD is greater than zero, guaranteed by design.

5. DDR mode clocks data on rising and falling edge of RCLK.

Figure 6. Echo Read Clock and Data Output Relationship

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

tTCK

t1

t2

TCK

TDI/

TMS

tDS

tDH

tDO

TDO

tDOH

t4

TRST

6157 drw13

Notes to diagram:

t1 = tTCKLOW

t3

t2 = tTCKHIGH

t3 = tRST (reset pulse width)

t4 = tRSR (reset recovery)

Figure 7. Standard JTAG Timing

JTAG

ACELECTRICALCHARACTERISTICS

(vcc = 2.5V 5%; Tambient (Industrial) = 0°C to +85°C)

SYSTEMINTERFACEPARAMETERS

IDT72T55248

IDT72T55258

IDT72T55268

Parameter

Symbol

Test

Conditions Min. Max. Units

JTAGClockInputPeriod tTCK

-

100

40

50

-

ns

Parameter

Symbol Test Conditions Min. Max. Units

JTAGClockHIGH

JTAGClockLow

JTAGReset

tTCKHIGH

(1)

DataOutput

tDO

-

20

-

ns

tTCKLOW

tRST

(1)

DataOutputHold tDOH

0

DataInput

tDS

tDH

trise=3ns

tfall=3ns

10

-

JTAG Reset Recovery

tRSR

NOTE:

1. 50pf loading on external output signals.

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

TheStandardJTAGinterfaceconsistsofsevenbasicelements:

JTAGTIMINGSPECIFICATIONS

(IEEE1149.1COMPLIANT)

TheJTAGtestportinthisdeviceisfullycompliantwiththeIEEEStandard

TestAccessPort(IEEE1149.1)specifications.Fiveadditionalpins(TDI,TDO,

TMS, TCK and TRST) are provided to support the JTAG boundary scan

interface. Note that IDT provides appropriate Boundary Scan Description

Languageprogramfilesforthesedevices.

•

Test Access Port (TAP)

TAPcontroller

Instruction Register (IR)

Data Register Port (DR)

Bypass Register(BYR)

ID Code Register

Flag Programming

Thefollowingsections provideabriefdescriptionofeachelement.Fora

completedescriptionrefertotheIEEEStandardTestAccessPortSpecification

(IEEEStd. 1149.1-1990).

The Figure belowshows the standardBoundary-ScanArchitecture

Incell

In Pad

Outcell

Out Pad

All inputs

Eg: Dins, Clks

(BSDL file

describes the

chain order)

Core

Logic

All outputs

TDI

ID

Bypass

Flag Offset Chain

TDO

Instruction

Register

TMS

TCK

Instruction

Select

Enable

TAP

TRST

6157 drw14

Figure 8. JTAG Architecture

THETAPCONTROLLER

TEST ACCESS PORT (TAP)

TheTAPcontrollerisasynchronousfinitestatemachinethatrespondsto

TMSandTCLKsignalstogenerateclockandcontrolsignalstotheInstruction

andDataRegistersforcaptureandupdatingofdatapassedthroughtheTDI

serialinput.

The TAPinterface is a general-purpose portthatprovides access tothe

internalJTAGstatemachine.Itconsistsoffourinputports(TCLK,TMS,TDI,

TRST) and one output port (TDO).

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

1

Test-Logic

Reset

0

Input is

TMS

1

0

1

Run-Test/

Idle

Select-

DR-Scan

Select-

IR-Scan

0

1

Capture-DR

Capture-IR

0

Shift-IR

Shift-DR

1

Exit1-IR

Exit1-DR

0

Pause-IR

Pause-DR

1

Exit2-IR

Exit2-DR

0

1

Update-IR

Update-DR

1

0

1

0

6157 drw15

NOTES:

1. Five consecutive 1's at TMS will reset the TAP.

2. TAP controller resets automatically upon power-up.

Figure 9. TAP Controller State Diagram

Refer to the IEEE Standard Test Access Port Specification (IEEE Std.

1149.1)forthefullstatediagram

Capture-IRInthiscontrollerstate,theshiftregisterbankintheInstruction

RegisterparallelloadsapatternoffixedvaluesontherisingedgeofTCK.The

lasttwosignificantbits arealways requiredtobe“01”.

Shift-IR In this controller state, the instruction register gets connected

betweenTDIandTDO,andthecapturedpatterngets shiftedoneachrising

edgeofTCK.TheinstructionavailableontheTDIpinis alsoshiftedintothe

instructionregister.TDOchangesonthefallingedgeofTCK.

Exit1-IRThisisacontrollerstatewhereadecisiontoentereitherthePause-

IRstateorUpdate-IRstateismade.

Pause-IRThisstateisprovidedinordertoallowtheshiftingofinstruction

registertobetemporarilyhalted.

Exit2-DRThisisacontrollerstatewhereadecisiontoentereithertheShift-

IRstateorUpdate-IRstateismade.

Update-IRInthiscontrollerstate,theinstructionintheinstructionregister

scanchainislatchedintotheregisteroftheInstructionRegisteroneveryfalling

edgeofTCK.Thisinstructionalsobecomesthecurrentinstructiononceitislatched.

Capture-DRInthiscontrollerstate,thedataisparallelloadedintothedata

registersselectedbythecurrentinstructionontherisingedgeofTCK.

Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These

controllerstatesaresimilartotheShift-IR,Exit1-IR,Pause-IR,Exit2-IRand

Update-IRstatesintheInstructionpath.

AllstatetransitionswithintheTAPcontrolleroccurattherisingedgeofthe

TCLKpulse. TheTMSsignallevel(0or1)determinesthestateprogression

thatoccursoneachTCLKrisingedge. TheTAPcontrollertakesprecedence

overtheQueueoperationandmustberesetafterpowerupofthedevice. See

TRSTdescriptionformoredetails onTAPcontrollerreset.

Test-Logic-ResetAlltestlogicisdisabledinthiscontrollerstateenablingthe

normaloperationoftheIC.TheTAPcontrollerstatemachineisdesignedinsuch

awaythat,nomatterwhattheinitialstateofthecontrolleris,theTest-Logic-Reset

statecanbeenteredbyholdingTMSathighandpulsingTCKfivetimes.This

is the reason why the Test Reset (TRST) pin is optional.

Run-Test-IdleInthiscontrollerstate,thetestlogicintheICisactiveonlyif

certaininstructionsarepresent.Forexample,ifaninstructionactivatestheself

test,thenitwillbeexecutedwhenthecontrollerentersthisstate.Thetestlogic

inthe ICis idle otherwise.

Select-DR-ScanThis is a controllerstate where the decisiontoenterthe

DataPathortheSelect-IR-Scanstateismade.

Select-IR-Scan This is a controller state where the decision to enter the

InstructionPathismade.TheControllercanreturntotheTest-Logic-Resetstate

otherwise.

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COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

THE INSTRUCTION REGISTER

JTAG INSTRUCTION REGISTER

The Instruction register allows an instruction to be serially input into the

devicewhentheTAPcontrollerisintheShift-IRstate.Theinstructionisdecoded

toperformthefollowing:

The instruction register (IR) is eight bits long and tells the device what

instructionistobeexecuted.Informationcontainedintheinstructionincludesthe

modeofoperation(eithernormalmode,inwhichthedeviceperformsitsnormal

logic function, or test mode, in which the normal logic function is inhibited or

altered),thetestoperationtobeperformed,whichofthefourdataregistersis

tobeselectedforinclusioninthescanpathduringdata-registerscans,andthe

sourceofdatatobecapturedintotheselecteddataregisterduringCapture-DR.

•

Selecttestdataregistersthatmayoperatewhiletheinstructionis

current.Theothertestdataregistersshouldnotinterferewithchip

operationandtheselecteddataregister.

Definetheserialtestdataregisterpaththatisusedtoshiftdatabetween

TDI and TDO during data register scanning.

•

The Instruction Register is a 4 bit field (i.e. IR3, IR2, IR1, IR0) to decode

16differentpossibleinstructions.Instructionsaredecodedasfollows.

TESTDATAREGISTER

TheTestDataregistercontainsthreetestdataregisters:theBypass,the

Boundary Scan register and Device ID register.

Theseregistersareconnectedinparallelbetweenacommonserialinput

andacommonserialdataoutput.

Hex

Value

Instruction

Function

0000 EXTEST

0001 SAMPLE/PRELOAD Selectboundaryscanregister

Testexternalpins

0002 IDCODE

0003 CLAMP

0004 HIGH-IMPEDANCE Putsalloutputsinhigh-impedancestate

0007 OFFSET READ

0008 OFFSETWRITE

000F BYPASS

Private

Selectschipidentificationregister

Fixtheoutputchains toscanchainvalues

Thefollowingsections provideabriefdescriptionofeachelement.Fora

completedescription,refertotheIEEEStandardTestAccessPortSpecification

(IEEEStd. 1149.1-1990).

ReadPAE/PAFoffsetregistervalues

WritePAE/PAFoffsetregistervalues

Selectbypassregister

Severalcombinations are private (forIDT

internaluse). Donotuse codes otherthan

thoseidentifiedabove.

TEST BYPASS REGISTER

TheregisterisusedtoallowtestdatatoflowthroughthedevicefromTDI

toTDO.Itcontainsasinglestageshiftregisterforaminimumlengthintheserial

path.Whenthebypassregisterisselectedbyaninstruction,theshiftregister

stageissettoalogiczeroontherisingedgeofTCLKwhentheTAPcontroller

isintheCapture-DRstate.

JTAG INSTRUCTION REGISTER DECODING

The operation of the bypass register should not have any effect on the

operationofthedeviceinresponsetotheBYPASSinstruction.

Thefollowingsectionsprovideabriefdescriptionofeachinstruction.For

acompletedescriptionrefertotheIEEEStandardTestAccessPortSpecification

(IEEEStd. 1149.1-1990).

THE BOUNDARY-SCAN REGISTER

The boundary-scan register (BSR) is 48 bits long. It contains one

boundary-scancell(BSC)foreachnormal-functioninputpinandoneBSCfor

eachnormal-functionI/Opin(onesinglecellforbothinputdataandoutputdata).

TheBSRisused1)tostoretestdatathatistobeappliedexternallytothedevice

outputpins,and/or2)tocapturedatathatappearsinternallyattheoutputsof

the normalon-chiplogicand/orexternallyatthe device inputpins.

EXTEST

The required EXTEST instruction places the device into an external

boundary-testmodeandselectstheboundary-scanregistertobeconnected

betweenTDIandTDO.Duringthisinstruction,theboundary-scanregisteris

accessedtodrivetestdataoff-chipviatheboundaryoutputsandreceivetest

dataoff-chipviatheboundaryinputs.Assuch,theEXTESTinstructionisthe

workhorseofIEEE.Std1149.1,providingforprobe-lesstestingofsolder-joint

opens/shortsandoflogicclusterfunction.

THE DEVICE IDENTIFICATION REGISTER

The Device IdentificationRegisteris a ReadOnly32-bitregisterusedto

specify the manufacturer, part number and version of the device to be

determinedthroughtheTAPinresponsetotheIDCODEinstruction.

IDTJEDECIDnumberis0xB3.Thistranslatesto0x33whentheparityis

droppedinthe11-bitManufacturerIDfield.

SAMPLE/PRELOAD

TherequiredSAMPLE/PRELOADinstructionallowsthedevicetoremainin

a normal functional mode and selects the boundary-scan register to be

connectedbetweenTDIandTDO.Duringthisinstruction,theboundary-scan

register can be accessed via a data scan operation, to take a sample of the

functionaldataenteringandleavingthedevice.Thisinstructionisalsousedto

preloadtestdataintotheboundary-scanregisterbeforeloadinganEXTEST

instruction.

FortheIDT72T55248/72T55258/72T55268,thePartNumberfieldcon-

tainsthefollowingvalues:

Device

Part# Field

04C9 (hex)

04CA (hex)

04CB (hex)

IDT72T55248

IDT72T55258

IDT72T55268

IDCODE

TheoptionalIDCODEinstructionallowsthedevicetoremaininitsfunctional

mode andselects the optionaldevice identificationregistertobe connected

betweenTDIandTDO.Thedeviceidentificationregisterisa32-bitshiftregister

containinginformationregardingthedevicemanufacturer,devicetype,and

versioncode.Accessingthedeviceidentificationregisterdoesnotinterferewith

the operationofthe device. Also, access tothe device identificationregister

shouldbeimmediatelyavailable,viaaTAPdata-scanoperation,afterpower-

upofthedeviceoraftertheTAPhas beenresetusingtheoptionalTRSTpin

orbyotherwisemovingtotheTest-Logic-Resetstate.

31(MSB)

Version (4 bits) Part Number (16-bit) Manufacturer ID (11-bit)

0000 0033 (hex)

IDT72T55248/258/268 JTAG Device Identification Register

28 27

12 11

1 0(LSB)

1

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

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COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

CLAMP

TheoptionalCLAMPinstructionsetstheoutputsofandevicetologiclevels

OFFSET READ

Thisinstructionisanalternativetoserialreadingtheoffsetregistersforthe

determinedbythecontentsoftheboundary-scanregisterandselectstheone- PAE/PAFflags.Whenreadingtheoffsetregistersthroughthisinstruction,the

bitbypassregistertobeconnectedbetweenTDIandTDO.Beforeloadingthis dedicatedserialprogrammingsignalsmustbedisabled.

instruction,thecontentsoftheboundary-scanregistercanbepresetwiththe

SAMPLE/PRELOADinstruction.Duringthis instruction,datacanbeshifted OFFSET WRITE

throughthebypassregisterfromTDItoTDOwithoutaffectingtheconditionof

theoutputs.

Thisinstructionisanalternativetoserialprogrammingtheoffsetregistersfor

thePAE/PAFflags.Whenwritingtheoffsetregistersthroughthisinstruction,the

dedicatedserialprogrammingsignalsmustbedisabled.

HIGH-IMPEDANCE

TheoptionalHigh-Impedanceinstructionsetsalloutputs(includingtwo-state BYPASS

aswellasthree-statetypes)ofandevicetoadisabled(high-impedance)state

TherequiredBYPASSinstructionallowsthedevicetoremaininanormal

andselectstheone-bitbypassregistertobeconnectedbetweenTDIandTDO. functional mode and selects the one-bit bypass register to be connected

Duringthisinstruction,datacanbeshiftedthroughthebypassregisterfromTDI between TDI and TDO. The BYPASS instruction allows serial data to be

toTDOwithoutaffectingtheconditionofthedeviceoutputs.

transferredthroughtheICfromTDItoTDOwithoutaffectingtheoperationof

thedevice.

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

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COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

tRS

MRS

t

RSR

t

RSS

WEN

REN

t

SWEN,

SREN

tRSS

IS[1:0]⁽⁴⁾

,

OS[1:0]⁽⁴⁾

t

RSS

MD[1:0]⁽⁴⁾

t

OW[1:0]⁽⁴⁾

,

IW[1:0]⁽⁴⁾

t

HIGH = Synchronous PAE/PAF Timing

LOW = Asynchronous PAE/PAF Timing

PFM⁽⁴⁾

tRSS

HIGH = Read/Write Double Data Rate

LOW = Read/Write Single Data Rate

RDDR⁽⁴⁾

,

WDDR⁽⁴⁾

tRSS

HIGH = FWFT Mode

FWFT/SI⁽⁴⁾

LOW = IDT Standard Mode

t

RSS

HIGH = HSTL I/Os

LOW = LVTTL I/Os

IOSEL⁽⁴⁾

t

FSEL[1:0]⁽⁴⁾

tRSF

If FWFT = HIGH, OR = HIGH

If FWFT = LOW, EF = LOW

EF/OR

0/1/2/3

If FWFT = LOW, FF = HIGH

If FWFT = HIGH, IR = LOW

FF/IR

0/1/2/3

PAF0/1/2/3

PAE0/1/2/3

tRSF

OE = HIGH

OE = LOW

Q[39-0]

NOTES:

6157 drw16

1. OE can be toggled during this period.

2. PRS should be HIGH during a MRS.

3. RCLK(s), WCLK(s) and SCLK(s) can be free running or idle.

4. The state of these pins are latched when the master reset pulse is LOW.

5. JTAG clock should not toggle during master reset.

6. RCS and WCS can be HIGH or LOW until the first rising edge of RCLK after master reset is complete.

7. EREN wave form is identical to REN, ERCLK wave form is identical to RCLK.

Figure 10 . Master Reset

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

RCLK0

1

2

3

4

tRS

PRS0/1⁽¹⁾

PRS2/3⁽¹⁾

tRS

t

RSS

tRSS

tRSR

WEN0/1,

REN0/1

t

tRSR

WEN2/3,

REN2/3

tENS

00 = Queue 0

01 = Queue 1

OS[1:0]

tRSF

If FWFT = HIGH, OR = HIGH

If FWFT = LOW, EF = LOW

Current State

EF/OR0/1

tRSF

If FWFT = HIGH, OR = HIGH

If FWFT = LOW, EF = LOW

Current State

EF/OR2/3

CEF/COR

FF/IR0/1

t

RSF

If FWFT = HIGH, COR = HIGH

If FWFT = LOW, CEF = LOW

t

If FWFT = HIGH, CFF = HIGH

If FWFT = LOW, CIR = LOW

t

RSF

If FWFT = HIGH, FF = HIGH

If FWFT = LOW, IR = LOW

Current State

FF/IR2/3

PAE0/1

PAE2/3

PAF0/1

PAF2/3

t

RSF

t

tRSF

OE = HIGH

Q[39-0]^(2,4)

Output Data Queue 0

Output Data Queue 1

OE = LOW

6157 drw17

NOTES:

1. During the output selection of two Queues, partial reset of the two Queues involved are prohibited.

2. During partial reset the high-impedance control of the output is provided by OE only.

3. PRS0/1 must go LOW after the fourth rising edge of RCLK0.

4. This is the output data from Queue0 and Queue1.

Figure 11 . Partial Reset for Mux mode

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Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

WCLK0

1

2

3

4

tRS

PRS0/1⁽¹⁾

PRS2/3⁽¹⁾

tRS

t

RSS

tRSS

tRSR

WEN0,

REN0/1

t

tRSR

REN2/3

tDS

00 = Queue 0

01 = Queue 1

IS[1:0]

t

RSF

If FWFT = HIGH, OR = HIGH

If FWFT = LOW, EF = LOW

Current State

EF/OR0/1

t

RSF

If FWFT = HIGH, OR = HIGH

If FWFT = LOW, EF = LOW

Current State

EF/OR2/3

FF/IR0/1

t

If FWFT = HIGH, FF = HIGH

If FWFT = LOW, IR = LOW

t

If FWFT = HIGH, FF = HIGH

If FWFT = LOW, IR = LOW

Current State

FF/IR2/3

CFF/CIR

PAE0/1

PAE2/3

PAF0/1

PAF2/3

t

RSF

If FWFT = HIGH, FF = HIGH

If FWFT = LOW, IR = LOW

t

RSF

tRSF

Q[9-0]^(2,4)

OE = HIGH

OE = LOW

Q[19-10]^(2,5)

tRSF

Q[29-20]^(2,6)

Q[39-30]^(2,7)

OE = HIGH

OE = LOW

6157 drw18

NOTES:

1. During the output selection of two Queues, partial reset of the two Queues involved are prohibited.

2. During partial reset the high-impedance control of the output is provided by OE only.

3. PRS0/1 must go LOW after the fourth rising edge of WCLK0.

4. This is the output data from Queue0.

5. This is the output data from Queue1.

6. This is the output data from Queue2.

7. This is the output data from Queue3.

Figure 12 . Partial Reset for Demux mode

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Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

WCLK0

(1)

PRS0/1/2/3

t

RSS

REN⁽²⁾0/1/2/3

t

WEN0

tRSF

If FWFT = HIGH, OR = HIGH

If FWFT = LOW, EF = LOW

EF/OR0/1/2/3

t

RSF

If FWFT = LOW, FF = HIGH

If FWFT = HIGH, IR = LOW

FF/IR0/1/2/3

CFF/CIR

If FWFT = LOW, FF = HIGH

If FWFT = HIGH, IR = LOW

PAE0/1/2/3

PAF0/1/2/3

Q[39-0]^(3,4)

NOTES:

tRSF

OE = HIGH

OE = LOW

6157 drw19

1. If the write port is configured in double data rate, partial reset must be initiated after the falling edge of WCLK0 to ensure falling edge data is written into memory.

2. Only the read enable of the Queue involved in partial reset need to be HIGH.

3. During partial reset the high-impedance control of the outputs is provided by OE only.

4. Only affects the output of the Queue partial reset is applied to.

Figure 13. Partial Reset for Broadcast mode

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

NO WRITE

1

2

1

2

WCLK0

WEN0

tENS

tDH

tDS

tDH

tDS

tDH

Din[9:0]

Word D-1

Word D

Word D+1

Word D+2

tWFF

FF2

FF1

tWFF

FF0

tSKEW1

RCLK2

tENS

REN2

RCLK1

REN1

tENS

RCLK0

tENS

REN0

Q[29:20]

Q[19:10]

t

A

tA

t

A

t

A

t

A

t

A

tA

Previous Data in Output Register

Word 1

Word 2

Word 3

Word 4

Word 1

Word 5

Word 2

Word 6

Word 3

Word 7

Word 4

Word 1

t

A

tA

t

Previous Data in Output Register

Q[9:0]

Previous Data in Output Register

6157 drwA

NOTE:

1. WCS0, RCS0/1/2, and OE0/1/2 are LOW.

Figure 15. Write Cycle and Full Flag Timing (Broadcast Write mode, IDT Standard mode, SDR to SDR) x10 In to x10 Out

FEBRUARY01,2009

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Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

NO WRITE

1

WCLK0

WEN0

IS[1:0]

1

2

tENS

01 = Queue 1

tENH

10 = Queue 2

tENH

00 = Queue 0

10

01

00

10

01

tDH

tDS

tDH

Din[9:0]⁽²⁾

Word X-1 Queue X

Word X Queue X

Word 0 Queue 2

Word 0 Queue 1

Word 1 Queue 1

Word 0 Queue 0

tWFF

FF2

FF1

tWFF

FF0

tSKEW1

RCLK2

tENS

REN2

RCLK1

REN1

tSKEW1

tENS

tSKEW1

RCLK0

tENS

REN0

Q[29:20]

Q[19:10]

Q[9:0]

tA

Previous Data in Output Register

Word 1

Word 2

Word 1

Word 3

Word 4

Word 3

Word 2

Word 5

tA

Previous Data in Output Register

Word 2

Word 1

Word 4

tA

Previous Data in Output Register

Word 3

6157 drwB

NOTES:

1. WCS0, RCS0/1/2, and OE0/1/2 are LOW.

2. There is a two-stage pipeline so each read appears in the queue two cycles or three rising edges of WCLK later.

Figure 16. Write Cycle and Full Flag Timing (Demux mode, IDT Standard mode, SDR to SDR) x10 In to x10 Out

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

WCLK0

tENH

tENS

WEN0

Din[9:0]

WCLK1

tDH

t

DS

tDH

Word 1

Word 2

Word 3

Word 4

tENH

tENS

WEN1

tDH

tDS

tDH

D[19:10]

Word 1

Word 2

Word 3

Word 4

OR0

OR1

tWFF

tSKEW1

RCLK0

OS[1:0]

1

2

3

tENS

00 = Queue 0

01 = Queue 1

tENS

REN0

t

A

t

A

tA

Q[9:0]

Previous Data in Output Register

Word 1

Word 2

Word 3

Word 4

Word 2

t

tA

Q[19:10]

Word 1

6157 drwC

NOTE:

1. WCS0/1, and OE0/1 are LOW.

Figure 17. Write Timing (Mux mode, FWFT mode, SDR to SDR) x10 In to x10 Out

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

FEBRUARY01,2009

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

FEBRUARY01,2009

50

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

1

2

WCLK0

WEN0

tDS

tDH

tSKEW1

Din[9:0]

IR0

WD

tWFF

RCLK1

tREF

REN1

tA

t

A

tA

W1

W2

W3

W4

Q[19:10]

RCLK0

tREF

REN0

tA

W1

W2

Q[9:0]

6157 drwF

NOTES:

1. WCS0, RCS0/1, and OE0/1 are LOW.

2. Q[39:10] = 0.

Figure 21. Read Timing (Broadcast Write mode, FWFT mode, SDR to SDR) x10 In to x10 Out

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Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

1

2

WCLK0

tENS

tENH

tSKEW1

WEN0

D[9:0]

WD

tWFF

IR0

RCLK0

REN0

tENS

tA

W1

W2

W3

W4

W5

Q[9:0]

6157 drwG

NOTES:

1. WCS0, RCS0, and OE0 are LOW.

2. OS[1:0] = 00.

3. Q[39:10] = 0.

Figure 22. Read Timing (Mux mode, FWFT mode, SDR to SDR) x10 In to x10 Out

1

2

WCLK0

tENS

tENH

WEN0

tSKEW1

tDS

tDH

D[19:0]

WD

tWFF

IR0

RCLK0

tENS

REN0

t

A

t

A

tA

W1 Byte D

W1 Byte 1

W2 Byte D

W2 Byte 1

Q[9:0]

6157 drwH

NOTES:

1. WCS0, RCS0, and OE0 are LOW.

2. IS[1:0] = 00. Q[39:10] = 0.

3. WD is a 20-bit word. Q[9:0] = Byte 0, Q[19:10] = Byte 1.

Figure 23. Read Timing (Demux mode, FWFT mode, SDR to SDR) x20 In to x10 Out

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COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

RCLK1

1

2

tENS

tSKEW1

REN1

Q[19:10]

EF1

t

A

tA

Previous Data in Output Register

WX

Byte 0

WX Byte 1

tREF

RCLK0

1

2

tENS

REN0

t

A

tA

Previous Data in Output Register

WX

Byte 0

WX

Byte 1

Q[9:0]

tSKEW1

tREF

EF0

WCLK0

WEN0

IS[1:0]

t

ENS

t

ENS

t

ENS

tENH

01 = Queue 1

00 = Queue 0

01

tDS

tDH

D[19:0]

WX Byte 0 - Byte 1

6157 drwI

NOTES:

1. WCS0, RCS0/1, and OE0/1 are LOW.

2. WX is a 20-bit word. LSB = Byte 0, MSB = Byte 1.

Figure 24. Read Cycle, Empty Flag and First Word Latency (Demux mode, IDT Standard mode, SDR to SDR) x20 In to x10 Out

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

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COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

No Read

RCLK0

1

2

3

tENS

REN0

tDS

01 = Queue 1

11 = Queue 3

OS[1:0]

t

A

tA

Q[39:0]⁽³⁾

Word D-1 Queue 1

Word D Queue 1

Next Word Queue 3

t

REF

EF

t

tREF

CEF

6157 drw23

NOTES:

1. RCS0 and OE0 are LOW.

2. EF3 is HIGH.

3. Word D-1 is the second and last word in Queue 1. Word D is the last word in Queue 1.

Figure 26. Composite Empty Flag (Mux mode, IDT Standard mode, SDR to SDR) x10 In to x40 Out

RCLK0

1

2

3

tENS

REN0

tENS

01 = Queue 1

11 = Queue 3

OS[1:0]

t

A

tA

Q[39:0]⁽³⁾

Word D-1 Queue 1

Word D Queue 1

Next Word Queue 3

tREF

OR1

tREF

COR

6157 drw24

NOTES:

1. RCS0 and OE0 are LOW.

2. OR3 is LOW.

3. Word D-1 is the second and last word in Queue 1. Word D is the last word in Queue 1.

Figure 27. Composite Output Ready Flag (Mux mode, FWFT mode, SDR to SDR) x10 In to x40 Out

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IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

No Write

WCLK0

1

2

3

tENS

WEN0

tDS

01 = Queue 1

tDH

tDS

11 = Queue 3

IS[1:0]

tDS

Word D Queue 3

tDH

Word D Queue 1

tWFF

Word D+1 Queue 3

D[19:0]

FF

tWFF

CFF

6157 drw25

NOTES:

1. WCS0 is LOW.

2. FF3 is HIGH.

Figure 28. Composite Full Flag (Demux mode, IDT Standard mode, SDR to SDR) x20 In to x10 Out

No Write

WCLK0

1

2

3

tENS

WEN0

IS[1:0]

t

DS

t

DH

tDS

01 = Queue 1

11 = Queue 3

tDH

tDS

tDH

D[19:10]⁽³⁾

Word D+1 Queue 1

Word D Queue 3

Word D+1 Queue 3

tWFF

IR1

tWFF

CIR

6157 drw26

NOTES:

1. WCS0 is LOW.

2. IR3 is LOW.

3. Word D is the first word written and fell through to output (FWFT).

Figure 29. Composite Input Ready Flag (Demux mode, FWFT mode, SDR to SDR) x20 In to x10 Out

FEBRUARY01,2009

57

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

FEBRUARY01,2009

58

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

WCLK0

tENS

tENH

WEN0

tDS

tDH

n+1

tDS

tDH

n+2

tDS

tDH

n+3

W

D[9:0]

tSKEW1

a

1

2

RCLK0

b

e

h

d

g

c

i

f

tERCLK

ERCLK0

tENH

tENS

tENH

REN0

RCS0

tENS

tCLKEN

EREN0

Q[9:0]

OR0

tA

tRCSLZ

HIGH-Z

Wn+1

Wn+2

W

n+3

tREF

O/P⁽¹⁾

Reg.

Wn

Last Word

Wn+1

Wn+2

Wn+3

6157 drw28

NOTE:

1. The O/P Register is the internal output register. Its contents are available on the Qn output bus only when RCS0 and OE0 are both active, LOW, that is the bus is not in

High-Impedance state.

2. OE0 is LOW.

3. Q[39:10] = 0.

Cycle:

a&b. At this point the Queue is empty, OR0 is HIGH.

RCS0 and REN0 are both disabled, the output bus is High-Impedance.

c.

Word Wn+1 falls through to the output register, OR0 goes active, LOW.

RCS0 is HIGH, therefore the Qn outputs are High-Impedance. EREN0 goes LOW to indicate that a new word has been placed into the output register.

EREN0 goes HIGH, no new word has been placed on the output register into this cycle.

d.

e.

f.

No Operation.

RCS0 is LOW on this cycle, therefore the Qn outputs go to Low-Impedance and the contents of the output register (Wn+1) are made available.

NOTE: In FWFT mode it is important to take RCS0 active LOW at least one cycle ahead of REN0, this ensures the word (Wn+1) currently in the output register is made

available for at least one cycle, otherwise Wn+1 will overwritten by Wn+2.

g.

h.

i.

REN0 goes active LOW, this reads out the second word, Wn+2.

EREN0 goes active LOW to indicate a new word has been placed into the output register.

Word Wn+3 is read out, EREN0 remains active, LOW indicating a new word has been read out.

NOTE: Wn+3 is the last word in the Queue.

This is the next enabled read after the last word, Wn+3 has been read out. OR0 flag goes HIGH and EREN0 goes HIGH to indicate that there is no new word available.

4. OE0 is LOW, WDDR = LOW, and RDDR = LOW.

5. The truth table for EREN is shown below:

RCLK

OR

RCS

REN

EREN

↑

0

1

0

1

X

0

1

0

1

X

0

1

Figure 31. Echo RCLK and Echo Read Enable Operation (Mux/Demux/Broadcast mode, FWFT mode, SDR to SDR)

FEBRUARY01,2009

59

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

RCLK0

tERCLK

ERCLK0

REN0

tENS

RCS0

tCLKEN

EREN0

tREF

EF0

t

A

OLZ

tA

t

A

tA

t

Q[9:0]

WD-4

WD-3

WD-2

WD-1

WD Last Word

6157 drw29

NOTES:

1. The EREN0 output is “or gated” to RCS0 and REN0 and will follow these inputs provided that the Queue is not empty. If the Queue is empty, EREN0 will go HIGH to indicate that

there is no new word available.

2. The EREN0 output is synchronous to RCLK0.

3. OE0 = LOW, WDDR = HIGH, and RDDR = HIGH.

4. Q[39:10] = 0.

5. The truth table for EREN is shown below:

RCLK

EF

RCS

REN

EREN

↑

1

0

1

X

0

1

0

1

X

0

1

Figure 32. Echo Read Clock and Read Enable Operation (Mux/Demux/Broadcast mode, IDT Standard mode, SDR to SDR) x10 In to x10 Out

FEBRUARY01,2009

60

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

FEBRUARY01,2009

61

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

tCLKL

WCLK

1

2

1

tENS

tENH

WEN0

PAF0

t

PAFS

tPAFS

D - m0 words in Queue⁽¹⁾

D - (m0 +1) words in Queue⁽¹⁾

t

SKEW2⁽³⁾

RCLK0

tENH

tENS

6157 drw32

REN0

NOTES:

1. m0 = PAF0 offset .

2. D = maximum Queue depth. For density of Queue with bus-matching, refer to the bus-matching section on page 19.

3. tSKEW2 is the minimum time between a rising RCLK0 edge and a rising WCLK0 edge to guarantee that PAF0 will go HIGH (after one WCLK0 cycle plus tPAFS). If the time

between the rising edge of RCLK0 and the rising edge of WCLK0 is less than tSKEW2, then the PAF0 deassertion time may be delayed one extra WCLK0 cycle.

4. PAF0 is asserted and updated on the rising edge of WCLK0 only.

5. Select this mode by setting PFM HIGH during Master Reset.

6. RCS0 = LOW, WCS0 = LOW, WDDR = LOW, and RDDR = LOW.

Figure 35. Synchronous Programmable Almost-Full Flag Timing

(Mux/Demux/Broadcast mode, IDT Standard and FWFT mode, SDR to SDR) x10 In to x10 Out

tCLKH

tCLKL

WCLK0

tENS

tENH

WEN0

PAE0

n0 + 1 words in Queue⁽²⁾

n0 + 2 words in Queue⁽³⁾

,

n0 words in Queue

tPAES

t

SKEW2⁽⁴⁾

1

2

1

2

RCLK0

tENS

tENH

6157 drw33

REN0

NOTES:

1. The timing diagram shown is for Queue0. Queues1-3 exhibit the same behavior.

2. n0 = PAE0 offset.

3. For IDT Standard mode

4. For FWFT mode.

5. tSKEW2 is the minimum time between a rising WCLK0 edge and a rising RCLK0 edge to guarantee that PAE

0

will go HIGH (after one RCLK0 cycle plus tPAES). If the time between

the rising edge of WCLK0 and the rising edge of RCLK0 is less than tSKEW2, then the PAE

6. PAE0 is asserted and updated on the rising edge of WCLK0 only.

7. Select this mode by setting PFM HIGH during Master Reset.

0 deassertion may be delayed one extra RCLK0 cycle.

8. RCS0 = LOW, WCS0 = LOW, WDDR = LOW, and RDDR = LOW.

Figure 36. Synchronous Programmable Almost-Empty Flag Timing

(Mux/Demux/Broadcast mode, IDT Standard and FWFT mode, SDR to SDR) x10 In to x10 Out

FEBRUARY01,2009

62

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

tCLKH

tCLKL

WCLK0

tENS

tENH

WEN0

PAF0

tPAFA

D - m0 words

in Queue

D - (m0 + 1) words

in Queue

D - (m0 + 1) words in Queue

tPAFA

RCLK0

tENS

REN0

6157 drw34

NOTES:

1. m0 = PAF0 offset.

2. D = maximum Queue depth. For density of Queue with bus-matching, refer to the bus-matching section on page 19.

3. PAF0 is asserted to LOW on WCLK0 transition and reset to HIGH on RCLK0 transition.

4. Select this mode by setting PFM LOW during Master Reset.

5. RCS0 is LOW, WCS0 is LOW, WDDR = LOW, and RDDR = LOW.

Figure 37. Asynchronous Programmable Almost-Full Flag Timing

(Mux/Demux/Broadcast mode, IDT Standard and FWFT mode, SDR to SDR) x10 In to x10 Out

tCLKH

tCLKL

WCLK0

tENS

tENH

WEN0

(2)

tPAEA

(2)

n0 words in Queue

,

n0 words in Queue

,

(2)

n0 + 1 words in Queue

n 0+ 2 words in Queue

,

(3)

PAE0

(3)

n0 + 1 words in Queue

(3)

tPAEA

RCLK0

tENS

REN0

6157 drw35

NOTES:

1. n0 = PAE0 offset.

2. For IDT Standard Mode.

3. For FWFT Mode.

4. PAE0 is asserted LOW on RCLK0 transition and reset to HIGH on WCLK0 transition.

5. Select this mode by setting PFM LOW during Master Reset.

6. RCS0 is LOW, WCS0 is LOW, WDDR = LOW, and RDDR = LOW.

Figure 38. Asynchronous Programmable Almost-Empty Flag Timing

(Mux/Demux/Broadcast mode, IDT Standard and FWFT mode, SDR to SDR) x10 In to x10 Out

FEBRUARY01,2009

63

IDT72T55248/72T55258/72T55268 2.5V QuadMux DDR Flow-Control Device with

Mux/Demux/Broadcast functions 8K x 40 x 4, 16K x 40 x 4 and 32K x 40 x 4

COMMERCIALANDINDUSTRIAL

TEMPERATURERANGES

WCLK

WEN

tDH

tDS

tDH

tDS

tDH

tDS

WD10

WD11

WD12

WD13

D[39:0]

1µs

(1)

3

1

2

4

RCLK

REN

(7)

PDHZ

(2)

t

tPDLZ

tA

Hi-Z

DH⁽⁸⁾

(2)

WDS

WD1

WD2

WD3

WD4

W

Q[39:0]

tPDH

(2)

PDH

t

tPDL

PD

tERCLK

Hi-Z

ERCLK

tEREN

Hi-Z

EREN

6157 drw36

NOTES:

1. All read and write operations must have ceased a minimum of 4 WCLK and 4 RCLK cycles before power down is asserted.

2. When the PD input becomes deasserted, there will be a 1µs waiting period before read and write operations can resume.

All input and output signals will also resume after this time period.

3. Set-up and configuration static inputs are not affected during power down.

4. Serial programming and JTAG programming port are inactive during power down.

5. RCS = 0, WCS = 0 and OE = 0. These signals can toggle during and after power down.

6. All flags remain active and maintain their current states.

7. During power down, all outputs will be in high-impedance.

Figure 39. Power Down Operation

FEBRUARY01,2009

64

ORDERINGINFORMATION

XXXXX

X

XX

X

Process /

Temperature

Range

Device Type

Power

Speed

Package

BLANK

I⁽¹⁾

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

Plastic Ball Grid Array (PBGA, BB324-1)

BB

Commercial Only

Clock Cycle Time (tCLK)

5

Commercial and Industrial Speed in Nanoseconds

6-7

L

Low Power

72T55248 8,192 x 40 x 4 ⎯ 2.5V QuadMux DDR Flow-Control Device

72T55258 16,384 x 40 x 4 ⎯ 2.5V QuadMux DDR Flow-Control Device

72T55268 32,768 x 40 x 4 ⎯ 2.5V QuadMux DDR Flow-Control Device

6157 drwlast

DATASHEETDOCUMENTHISTORY

12/01/2003

03/22/2005

02/01/2009

pgs. 1, 8, 17, and 36.

pgs. 4, 6, 9, 15-18, 21-24, 32, 34, and 65.

pg. 65.

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

800-345-7015 or 408-284-8200

fax: 408-284-2775

for Tech Support:

408-360-1533

email:Flow-Controlhelp@idt.com

www.idt.com

65


型号：	72T55268L5BB
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	PBGA-324, Tray 时钟先进先出芯片内存集成电路
文件：	总65页 (文件大小：573K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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