72V3622L15PQF [IDT]
PQFP-132, Tray;
| 型号： | 72V3622L15PQF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PQFP-132, Tray |
| 文件： | 总29页 (文件大小：430K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3 VOLT CMOS SyncBiFIFOTM
256 x 36 x 2
512 x 36 x 2
IDT72V3622
IDT72V3632
IDT72V3642
1,024 x 36 x 2
• FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA
• FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB
• Select IDT Standard timing (using EFA, EFB, FFA and FFB flags
functions) or First Word Fall Through timing (using ORA, ORB, IRA
and IRB flag functions)
FEATURES:
• Memory storage capacity:
IDT72V3622
IDT72V3632
IDT72V3642
–
–
–
256 x 36 x 2
512 x 36 x 2
1,024 x 36 x 2
• Available space-saving 120-pin Thin Quad Flatpack (TQFP)
• Functionally compatible to the 5V operating IDT723622/723632/
723642
• Supports clock frequencies up to 100 MHz
• Fast access times of 6.5ns
• Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock edge
is permitted)
• Industrial temperature range (–40οC to +85οC) is available
• Green parts available, see ordering information
• Two independent clocked FIFOs buffering data in opposite direc-
tions
• Mailbox bypass register for each FIFO
• Programmable Almost-Full and Almost-Empty flags
• Microprocessor Interface Control Logic
DESCRIPTION:
TheIDT72V3622/72V3632/72V3642arefunctionallycompatibleversions
of the IDT723622/723632/723642, designed to run off a 3.3V supply for
exceptionallylow-powerconsumption. Thesedevicesaremonolithic, high-
FUNCTIONAL BLOCK DIAGRAM
MBF1
Mail 1
Register
CLKA
CSA
Port-A
Control
Logic
W/RA
RAM
ENA
ARRAY
MBA
256 x 36
512 x 36
1,024 x 36
36
FIFO1,
Mail1
Reset
Logic
RST1
Write
Pointer
Read
Pointer
36
Status Flag
Logic
EFB/ORB
AEB
FFA/IRA
AFA
FIFO 1
FS
0
1
Programmable Flag
Offset Registers
Timing
Mode
FWFT
FS
A
0
- A35
10
B0 - B35
FIFO 2
Status Flag
EFA/ORA
FFB/IRB
AFB
Logic
AEA
36
Read
Pointer
Write
Pointer
36
FIFO2,
Mail2
Reset
Logic
RST2
RAM
ARRAY
256 x 36
512 x 36
CLKB
CSB
W/RB
Port-B
Control
Logic
1,024 x 36
ENB
Mail 2
Register
MBB
4660 drw 01
MBF2
CIDTOandMtheMIDTElogRoaCrereIgAisteLredtrTadeEmaMrkoPfInEtegRrateAdDTevUiceTRecEhnologRy,IAnc NSynGcBiEFIFOisatrademarkofIntegratedDeviceTechnology,Inc.
MAY 2013
1
©
2013 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4660/8
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
These devices are a synchronous (clocked) FIFO, meaning each port
employsasynchronousinterface.Alldatatransfersthroughaportaregated
totheLOW-to-HIGHtransitionofaportclockbyenablesignals.Theclocksfor
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectionalinterfacebetweenmicroprocessorsand/orbuseswithsynchro-
nouscontrol.
DESCRIPTION(CONTINUED)
speed,low-power,CMOSBidirectionalSyncFIFO(clocked)memorieswhich
supportclockfrequenciesupto100MHzandhavereadaccesstimesasfast
as 6.5ns. Two independent 256/512/1,024 x 36 dual-port SRAM FIFOs on
boardeachchipbufferdatainoppositedirections.Communicationbetween
eachportmaybypasstheFIFOsviatwo36-bitmailboxregisters.Eachmailbox
register has a flag to signal when new mail has been stored.
PIN CONFIGURATION
B
B
B
B
35
34
33
32
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
A
A
A
A
35
34
33
32
1
2
3
4
GND
V
CC
5
B
B
B
B
B
B
V
B
B
31
30
29
28
27
26
CC
25
24
A
31
6
A30
7
GND
8
A
A
A
A
A
A
A
29
28
27
26
25
24
23
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
GND
B
B
B
B
B
B
23
22
21
20
19
18
FWFT
A
22
CC
V
A
21
20
19
18
A
A
A
GND
B
B
V
B
B
B
B
17
16
CC
15
14
13
12
GND
A
A
A
A
A
17
16
15
14
13
V
CC
GND
A12
4660 drw 03
TQFP (PN120-1, order code: PF)
TOP VIEW
2
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
aselectednumberofwordsremainintheFIFOmemory. AFAandAFBindicate
when the FIFO contains more than a selected number of words.
FFA/IRA,FFB/IRB,AFAandAFBaretwo-stagesynchronizedtotheport
clockthatwritesdataintoitsarray. EFA/ORA, EFB/ORB, AEA andAEB are
two-stage synchronized to the port clock that reads data from its array.
ProgrammableoffsetsforAEA,AEB,AFAandAFBareloaded byusingPort
A.Threedefaultoffsetsettingsarealsoprovided.TheAEAandAEBthreshold
canbesetat8,16or64locationsfromtheemptyboundaryandtheAFAand
AFBthresholdcanbesetat8,16or64locationsfromthefullboundary.Allthese
choices are made using the FS0 and FS1 inputs during Reset.
Twoormoredevicesmaybeusedinparalleltocreatewiderdatapaths.
If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption(ICC)isataminimum.Initiatinganyoperation(byactivatingcontrol
inputs)willimmediatelytakethedeviceoutofthepowerdownstate.
TheIDT72V3622/72V3632/72V3642arecharacterizedforoperationfrom
0oC to 70oC. Industrial temperature range (-40οC to +85οC) is available by
special order. They are fabricated using high speed, submicron CMOS
technology.
Thesedeviceshavetwomodesofoperation:IntheIDTStandardmode,
thefirstwordwrittentoanemptyFIFOisdepositedintothememoryarray. A
read operation is required to access that word (along with all other words
residinginmemory).IntheFirstWordFallThroughmode(FWFT),thefirstlong-
word (36-bit wide) written to an empty FIFO appears automatically on the
outputs, no read operation required (Nevertheless, accessing subsequent
wordsdoesnecessitateaformalreadrequest).ThestateoftheFWFTpinduring
FIFOoperationdeterminesthemodeinuse.
Each FIFO has a combined Empty/Output Ready Flag (EFA/ORA and
EFB/ORB)andacombinedFull/InputReadyFlag(FFA/IRAand FFB/IRB).
TheEFandFFfunctionsareselectedintheIDTStandardmode.EFindicates
whetherornottheFIFOmemoryisempty. FFshowswhetherthememoryis
fullornot.TheIRandORfunctionsareselectedintheFirstWordFallThrough
mode.IRindicateswhetherornottheFIFOhasavailablememorylocations.
ORshowswhethertheFIFOhasdataavailableforreadingornot.Itmarksthe
presenceofvaliddataontheoutputs.
EachFIFOhasaprogrammableAlmost-Emptyflag(AEAandAEB)and
aprogrammableAlmost-Fullflag(AFAandAFB). AEAandAEB indicatewhen
3
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
PIN DESCRIPTIONS
Symbol
Name
I/O
Description
A0-A35
PortAData
I/0
O
36-bitbidirectionaldataportforsideA.
ProgrammableAlmost-EmptyflagsynchronizedtoCLKA.ItisLOWwhenthenumberofwordsinFIFO2is
AEA
PortAAlmost-
EmptyFlag
(Port A) lessthanorequaltothevalueintheAlmost-EmptyAOffsetregister,X2.
ProgrammableAlmost-EmptyflagsynchronizedtoCLKB.ItisLOWwhenthenumberof words in FIFO1 is
(Port B) lessthanorequaltothevalueintheAlmost-EmptyBOffsetregister,X1.
ProgrammableAlmost-FullflagsynchronizedtoCLKA.ItisLOWwhenthenumberofempty locationsin
(Port A) FIFO1islessthanorequaltothevalueintheAlmost-FullAOffsetregister, Y1.
ProgrammableAlmost-FullflagsynchronizedtoCLKB.ItisLOWwhenthenumberofempty locationsin
(Port B) FIFO2islessthanorequaltothevalueintheAlmost-FullBOffsetregister, Y2.
AEB
AFA
AFB
PortBAlmost-
EmptyFlag
O
PortAAlmost-
Full Flag
O
PortBAlmost-
Full Flag
O
B0 - B35
CLKA
PortBData
PortAClock
I/O
I
36-bitbidirectionaldataportforsideB.
CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or
coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH
transitionofCLKA.
CLKB
PortBClock
I
CLKBisacontinuousclockthatsynchronizesalldatatransfersthroughportBand can be asynchronous or
coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are synchronized to the LOW-to-HIGH
transitionofCLKB.
CSA
CSB
Port A Chip
Select
I
I
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write on port A. The A0-A35
outputs are in the high-impedance state when CSA is HIGH.
Port B Chip
Select
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The
B0- B35 outputs are in the high-impedance state when CSB is HIGH.
EFA/ORA PortAEmpty/
OutputReady
O
This is a dual function pin. In the IDT Standard mode, the EFA function is selected. EFA indicates
whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA
indicates the presence of valid data on A0-A35 outputs, available for reading. EFA/ORA is synchronized
totheLOW-to-HIGHtransitionofCLKA.
Flag
EFB/ORB PortBEmpty/
OutputReady
O
This is a dual function pin. In the IDT Standard mode, the EFB function is selected. EFB indicates
whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB
indicates the presence of valid data on B0-B35 outputs, available for reading. EFB/ORB is synchronized to
theLOW-to-HIGHtransitionofCLKB.
Flag
ENA
Port A Enable
Port B Enable
I
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
ENB
FFA/IRA
Port A Full/
Input Ready
Flag
O
This is a dual function pin. In the IDT Standard mode, the FFA function is selected. FFA indicates whether
or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA indicates whether or
not there is space available for writing to the FIFO1 memory. FFA/IRA is synchronized to the LOW-to-
HIGHtransitionofCLKA.
FFB/IRB
Port B Full/
Input Ready
Flag
O
This is a dual function pin. In the IDT Standard mode, the FFB function is selected. FFB indicates whether
or not the FIFO2 memory is full. In the FWFT mode, the IRB function is selected. IRB indicates whether or
not there is space available for writing to the FIFO2 memory. FFB/IRB is synchronized to the LOW-to-
HIGHtransitionofCLKB.
FWFT
FirstWordFall
Through Mode
I
I
Thispinselectsthetimingmode. AHIGHonFWFTselectsIDTStandardmode, aLOWselectsFirst
Word Fall Through mode. Once the timing mode has been selected, the level on FWFT must be static
throughoutdeviceoperation.
FS1, FS0
FlagOffset
Selects
A LOW-to-HIGH transition of the FIFO Reset input latches the values of FS0 and FS1. If either FS0 or
FS1 is HIGH when the FIFO Reset input goes HIGH, one of three preset values is selected as the
offset for FIFOs Almost-Full and Almost-Empty flags. If both FIFOs are reset simultaneously and both
FS0 and FS1 are LOW when RST1 and RST2 go HIGH, the first four writes to FIFO1 load the Almost-
Empty and Almost-Full offsets for both FIFOs.
4
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
PINDESCRIPTIONS(CONTINUED)
Symbol
Name
I/O
Description
MBA
Port A Mailbox
Select
I
A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the
A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a
LOWlevelselectsFIFO2outputregisterdataforoutput.
MBB
Port B Mailbox
Select
I
A HIGH level on MBB chooses a mailbox register for a port B read or write operation. When the
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register or output and a
LOWlevelselectsFIFO1outputregisterdataforoutput.
MBF1
Mail1Register
Flag
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.
Writes to the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH
transition of CLKB when a port B read is selected and MBB is HIGH. MBF1 is set HIGH when FIFO1
isreset.
MBF2
Mail2Register
Flag
O
MBF2issetLOWbyaLOW-to-HIGHtransitionofCLKBthatwritesdata tothemail2register.Writes
to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH
transition of CLKA when a port A read is selected and MBA is HIGH. MBF2 is also set HIGH when
FIFO2 is reset.
RST1
RST2
FIFO1Reset
FIFO2Reset
I
I
ToresetFIFO1,fourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKBmust
occur while RST1 is LOW. The LOW-to-HIGH transition of RST1 latches the status of FS0 and FS1 for
AFA and AEB offset selection. FIFO1 must be reset upon power up before data is written to its RAM.
ToresetFIFO2,fourLOW-to-HIGHtransitionsofCLKAandfourLOW-to-HIGHtransitionsofCLKBmust
occur while RST2 is LOW. The LOW-to-HIGH transition of RST2 latches the status of FS0 and FS1 for
AFB and AEA offset selection. FIFO2 must be reset upon power up before data is written to its RAM.
W/RA
PortAWrite/
ReadSelect
I
I
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH
transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
W/RB
PortBWrite/
ReadSelect
A LOW selects a write operation and a HIGH selects a read operation on port B for a LOW-to-HIGH
transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RB is LOW.
5
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGSOVEROPERATING
TEMPERATURERANGE(Unlessotherwisenoted)(1)
Symbol
Rating
Commercial
–0.5to+4.6
–0.5toVCC+0.5
–0.5toVCC+0.5
±20
Unit
V
VCC
VI(2)
VO(2)
IIK
SupplyVoltageRange
InputVoltageRange
V
OutputVoltageRange
V
Input Clamp Current (VI < 0 or VI > VCC)
Output Clamp Current (VO = < 0 or VO > VCC)
Continuous Output Current (VO = 0 to VCC)
ContinuousCurrentThroughVCC or GND
StorageTemperatureRange
mA
mA
mA
mA
ο C
IOK
±50
IOUT
ICC
±50
±400
TSTG
–65to150
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect
device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
RECOMMENDEDOPERATINGCONDITIONS
Symbol
VCC(1)
VIH
Parameter
Min.
3.0
2
Typ.
3.3
—
Max.
3.6
Unit
V
SupplyVoltage
High-LevelInputVoltage
Low-LevelInputVoltage
High-LevelOutputCurrent
Low-LevelOutputCurrent
OperatingTemperature
VCC+0.5
0.8
V
VIL
—
—
—
0
—
V
IOH
—
–4
mA
mA
°C
IOL
—
8
TA
—
70
NOTE:
1. For 10ns (100 MHz operation), Vcc=3.3V +/- 0.15V, TA = 0° to +70°C; JEDEC JESD8-A compliant.
ELECTRICALCHARACTERISTICSOVERRECOMMENDED
OPERATINGTEMPERATURERANGE(Unlessotherwisenoted)
IDT72V3622
IDT72V3632
IDT72V3642
Commercial
tCLK = 10(1), 15ns
Symbol
VOH
Parameter
Test Conditions
IOH = –4 mA
Min.
Typ.(2)
Max.
Unit
V
OutputLogic"1"Voltage
VCC = 3.0V,
VCC = 3.0V,
VCC = 3.6V,
VCC = 3.6V,
VCC = 3.6V,
VCC = 3.6V,
VI = 0,
2.4
—
—
—
—
—
—
—
—
—
0.5
±10
±10
5
VOL
OutputLogic"0"Voltage
IOL = 8 mA
—
V
ILI
InputLeakageCurrent(AnyInput)
OutputLeakageCurrent
VI = VCC or 0
VO = VCC or 0
—
μA
μA
mA
mA
pF
ILO
—
ICC2(3)
ICC3(3)
CIN(4)
COUT(4)
Standby Current (with CLKA and CLKB running)
StandbyCurrent(noclocksrunning)
InputCapacitance
VI = VCC - 0.2V or 0
—
VI = VCC - 0.2V or 0
f = 1 MHz
—
1
4
—
OutputCapacitance
VO = 0,
f = 1 MHZ
8
—
pF
NOTES:
1. For 10ns speed grade only: VCC = 3.3V +/- 0.15V, TA = 0° to +70°C; JEDEC JESD8-A compliant.
2. All typical values are at VCC = 3.3V, TA = 25°C.
3. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
4. Characterized values, not currently tested.
5. Industrial temperature range is available by special order.
6
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION
The ICC(f) current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT72V3622/72V3632/72V3642 with
CLKAandCLKBsettofS. Alldatainputsanddataoutputschangestateduringeachclockcycletoconsumethehighestsupplycurrent. Dataoutputswere
disconnectedtonormalizethegraphtoazerocapacitanceload. Oncethecapacitanceloadperdata-outputchannelandthenumberofthesedevice's
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
CALCULATING POWER DISSIPATION
With ICC(f) taken from Figure 1, the maximum power dissipation (PT) of these FIFOs may be calculated by:
2
PT = VCC x ICC(f) + Σ(CL x VCC X fo)
N
where:
N
=
=
=
number of outputs = 36
CL
fo
output capacitance load
switchingfrequencyofanoutput
200
175
150
f
data = 1/2 fS
T
A
= 25οC
L = 0 pF
VCC = 3.6V
C
VCC = 3.3V
125
100
VCC = 3.0V
75
50
25
0
80
100
0
10
20
30
40
50
60
70
90
4660 drw 03a
fS
Clock Frequency MHz
Figure 1. Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS)
7
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGEANDOPERATINGTEMPERATURE
Commercial: VCC=3.3V± 0.30V; for 10ns (100 MHz) operation, VCC=3.3V ±0.15V; TA = 0ο C to +70ο C; JEDEC JESD8-A compliant
IDT72V3622L10(1)
IDT72V3632L10(1)
IDT72V3642L10(1)
IDT72V3622L15
IDT72V3632L15
IDT72V3642L15
Symbol
fS
Parameter
Min.
—
10
4.5
4.5
3
Max.
100
—
Min.
—
15
6
Max.
66.7
—
Unit
MHz
ns
Clock Frequency, CLKA or CLKB
tCLK
Clock Cycle Time, CLKA or CLKB
tCLKH
tCLKL
tDS
Pulse Duration, CLKA or CLKB HIGH
—
—
ns
Pulse Duration, CLKA and CLKB LOW
Setup Time, A0-A35 before CLKA↑and B0-B35 before CLKB↑
SetupTimeCSAbeforeCLKA↑;CSBbeforeCLKB↑
—
6
—
ns
—
4
—
ns
tENS1
tENS2
4
—
4.5
4.5
—
ns
Setup Time ENA, W/RA and MBA before CLKA↑; ENB, W/RB and MBB
beforeCLKB↑
3
—
—
ns
(2)
tRSTS
tFSS
tFWS
tDH
Setup Time, RST1 or RST2 LOW before CLKA↑ or CLKB↑
5
—
—
—
—
—
5
7.5
0
—
—
—
—
—
ns
ns
ns
ns
ns
Setup Time, FS0 and FS1 before RST1 and RST2 HIGH
SetupTime, FWFTbeforeCLKA↑
7.5
0
Hold Time, A0-A35 after CLKA
↑
and B0-B35 after CLKB
↑
0.5
0.5
1
tENH
Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/RB, ENB, and
1
MBBafterCLKB↑
(2)
tRSTH
tFSH
tSKEW1(3)
Hold Time, RST1 or RST2 LOW after CLKA
↑
or CLKB
↑
4
2
—
—
—
4
2
—
—
—
ns
ns
ns
Hold Time, FS0 and FS1 after RST1 and RST2 HIGH
Skew Time, between CLKA
↑
and CLKB
↑
for EFA/ORA, EFB/ORB, FFA/IRA,
7.5
7.5
and FFB/IRB
tSKEW2(3,4) Skew Time, between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and AFB
12
—
12
—
ns
NOTES:
1. For 10ns speed grade only: VCC = 3.3V +/- 0.15V, TA = 0° to +70°C; JEDEC JESD8-A compliant.
2. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
3. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
4. Design simulated, not tested.
5. Industrial temperature range is available by special order.
8
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING TEMPERATURE, CL = 30 pF
Commercial: VCC=3.3V± 0.30V; for 10ns (100 MHz) operation, VCC=3.3V ±0.15V; TA = 0ο C to +70ο C; JEDEC JESD8-A compliant
IDT72V3622L10(1) IDT72V3622L15
IDT72V3632L10(1) IDT72V3632L15
IDT72V3642L10(1) IDT72V3642L15
Symbol
tA
Parameter
Min.
Max.
6.5
6.5
6.5
6.5
6.5
6.5
Min.
Max.
Unit
ns
AccessTime, CLKA↑toA0-A35andCLKB↑toB0-B35
Propagation Delay Time, CLKA↑ to FFA/IRA and CLKB↑ to FFB/IRB
Propagation Delay Time, CLKA↑ to EFA/ORA and CLKB↑ to EFB/ORB
Propagation Delay Time, CLKA↑ to AEA and CLKB↑ to AEB
Propagation Delay Time, CLKA↑ to AFA and CLKB↑ to AFB
2
2
1
1
1
0
2
2
1
1
1
0
10
8
tWEF
tREF
tPAE
tPAF
tPMF
ns
8
ns
8
ns
8
ns
Propagation Delay Time, CLKA↑ to MBF1 LOW or MBF2 HIGH and CLKB↑ to
MBF2 LOW or MBF1 HIGH
8
ns
tPMR
tMDV
tRSF
Propagation Delay Time, CLKA↑ to B0-B35(2) and CLKB↑ to A0-A35(3)
2
2
1
8
2
2
1
10
10
15
ns
ns
ns
Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 Valid
6.5
10
Propagation Delay Time, RST1 LOW to AEB LOW, AFA HIGH, and MBF1 HIGH,
and RST2 LOW to AEA LOW, AFB HIGH, and MBF2 HIGH
tEN
tDIS
Enable Time, CSA and W/RA LOW to A0-A35 Active and CSB LOW and W/RB
2
1
6
6
2
1
10
8
ns
ns
HIGH to B0-B35 Active
Disable Time, CSA or W/RA HIGH to A0-A35 at high-impedance and CSB HIGH or
W/RB LOW to B0-B35 at high-impedance
NOTES:
1. For 10ns speed grade only: VCC = 3.3V +/- 0.15V, TA = 0° to +70°C; JEDEC JESD8-A compliant.
2. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
3. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
4. Industrial temperature range is available by special order.
9
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
FollowingReset,thelevelappliedtotheFWFTinputtochoosethedesired
timingmodemustremainstaticthroughoutFIFOoperation.RefertoFigure2
(Reset)foraFirstWordFallThroughselecttimingdiagram.
SIGNAL DESCRIPTION
RESET
Afterpowerup,aMasterResetoperationmustbeperformedbyproviding
a LOW pulse to RST1 and RST2 simultaneously. Afterwards, the FIFO
memories of the IDT72V3622/72V3632/72V3642 are reset separately by
taking their Reset (RST1, RST2) inputs LOW for at least four port-A Clock
(CLKA)andfourport-BClock(CLKB)LOW-to-HIGHtransitions. TheReset
inputs can switch asynchronously to the clocks. A FIFO reset initializes the
internalreadandwritepointersandforcestheInputReadyflag(IRA,IRB)LOW,
theOutputReadyflag(ORA,ORB)LOW,theAlmost-Emptyflag(AEA,AEB)
LOW,andtheAlmost-Fullflag(AFA,AFB)HIGH. ResettingaFIFOalsoforces
theMailboxFlag(MBF1, MBF2)oftheparallelmailboxregisterHIGH. After
aFIFOisreset,itsInputReadyflagissetHIGHaftertwoclockcyclestobegin
normaloperation.
ALOW-to-HIGHtransitiononaFIFOReset(RST1,RST2)inputlatches
thevalueoftheFlagSelect(FS0,FS1)inputsforchoosingtheAlmost-Fulland
Almost-Empty offset programming method. (For details see Table 1, Flag
Programming,andtheProgrammingtheAlmost-EmptyandAlmost-FullFlags
section). The relevant FIFO Reset timing diagram can be found in Figure 2.
ALMOST-EMPTYFLAGANDALMOST-FULLFLAGOFFSETPROGRAM-
MING
Fourregistersinthesedevicesareusedtoholdtheoffsetvaluesforthe
Almost-EmptyandAlmost-Fullflags.TheportBAlmost-Emptyflag(AEB)Offset
registerislabeledX1andtheportAAlmost-Emptyflag(AEA)Offsetregister
is labeled X2. The port A Almost-Full flag (AFA) Offset register is labeled Y1
andtheportBAlmost-Fullflag(AFB)OffsetregisterislabeledY2.Theindex
ofeachregisternamecorrespondstoitsFIFOnumber.Theoffsetregisterscan
be loaded with preset values during the reset of a FIFO or they can be
programmed from port A (see Table 1).
FS0 and FS1 function the same way in both IDT Standard and FWFT
modes.
— PRESET VALUES
ToloadtheFIFO'sAlmost-EmptyflagandAlmost-FullflagOffsetregisters
withoneofthethreepresetvalueslistedinTable1,atleastoneoftheflagselect
inputsmustbeHIGHduringtheLOW-to-HIGHtransitionofitsresetinput.For
example,toloadthepresetvalueof64intoX1andY1,FS0andFS1mustbe
HIGH when FlFO1 Reset (RST1) returns HIGH. Flag offset registers
associatedwithFIFO2areloadedwithoneofthepresetvaluesinthesameway
withFIFO2Reset(RST2)toggledsimultaneouslywithFIFO1Reset(RST1).
For preset value loading timing diagram, see Figure 2.
FIRST WORD FALL THROUGH (FWFT)
AfterMasterReset,theFWFTselectfunctionisactive,permittingachoice
between two possible timing modes: IDT Standard mode or First Word Fall
Through (FWFT) mode. Once the Reset (RST1, RST2) input is HIGH, a
HIGH on the FWFT input during the next LOW-to-HIGH transition of CLKA
(forFIFO1)andCLKB(forFIFO2)willselectIDTStandardmode.Thismode
uses the Empty Flag function (EFA, EFB) to indicate whether or not there
areanywordspresentintheFIFOmemory.ItusestheFullFlagfunction(FFA,
FFB) to indicate whether or not the FIFO memory has any free space for
writing.InIDTStandardmode,everywordreadfromtheFIFO,includingthe
first,mustberequestedusingaformalreadoperation.
OncetheReset(RST1, RST2)inputisHIGH, aLOWontheFWFTinput
duringthenextLOW-to-HIGHtransitionofCLKA(forFIFO1)andCLKB(for
FIFO2) will select FWFT mode. This mode uses the Output Ready function
(ORA,ORB)toindicatewhetherornotthereisvaliddataatthedataoutputs
(A0-A35orB0-B35).ItalsousestheInputReadyfunction(IRA,IRB)toindicate
whetherornottheFIFOmemoryhasanyfreespaceforwriting.IntheFWFT
mode,thefirstwordwrittentoanemptyFIFOgoesdirectlytodataoutputs,no
readrequestnecessary. Subsequentwordsmustbeaccessedbyperforming
aformalreadoperation.
— PARALLEL LOAD FROM PORT A
ToprogramtheX1,X2,Y1,andY2registersfromportA,bothFlFOsshould
be reset simultaneously with FS0 and FS1 LOW during the LOW-to-HIGH
transitionoftheResetinputs.Afterthisresetiscomplete,thefirstfourwritesto
FIFO1donotstoredataintheFIFOmemorybutloadtheoffsetregistersinthe
order Y1, X1, Y2, X2. The port A data inputs used by the offset registers are
(A7-A0), (A8-A0), or (A9-A0) for the IDT72V3622, IDT72V3632, or
IDT72V3642,respectively. Thehighestnumberedinputisusedasthemost
significantbitofthebinarynumberineachcase. Validprogrammingvaluesfor
the registers ranges from 1 to 252 for the IDT72V3622; 1 to 508 for the
IDT72V3632;and1to1,020fortheIDT72V3642. Afteralltheoffsetregisters
areprogrammedfromportA,theportBFull/InputReadyflag(FFB/IRB)isset
HIGH,andbothFIFOsbeginnormaloperation.SeeFigure3forrelevantoffset
registerparallelprogrammingtimingdiagram.
TABLE 1 — FLAG PROGRAMMING
FS1
FS0
RST1
RST2
X1 AND Y1 REGlSTERS(1)
X2 AND Y2 REGlSTERS(2)
H
H
H
H
L
H
H
L
↑
X
↑
X
↑
X
↑
X
↑
X
↑
X
↑
↑
64
X
X
64
16
X
L
X
16
H
H
L
8
X
L
X
8
L
Parallel programming via Port A
Parallel programming via Port A
NOTES:
1. X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
10
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
FIFO WRITE/READ OPERATION
andarenotrelatedtohigh-impedancecontrolofthedataoutputs.Ifaportenable
ThestateoftheportAdata(A0-A35)outputsiscontrolledbyportAChip isLOWduringaclockcycle,theport’sChipSelectandWrite/Readselectmay
Select(CSA)andportAWrite/Readselect(W/RA).TheA0-A35outputsare changestatesduringthesetupandholdtimewindowofthecycle.
inthehigh-impedancestatewheneitherCSAorW/RAisHIGH.TheA0-A35
outputs are active when both CSA and W/RA are LOW.
WhenoperatingtheFIFOinFWFTmodeandtheOutputReadyflagisLOW,
thenextwordwrittenisautomaticallysenttotheFIFO’soutputregisterbythe
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH LOW-to-HIGHtransitionoftheportclockthatsetstheOutputReadyflagHIGH.
transitionofCLKAwhenCSAisLOW, W/RAisHIGH, ENAisHIGH, MBAis WhentheOutputReadyflagisHIGH,subsequentdataisclockedtotheoutput
LOW,andFFA/IRAisHIGH. DataisreadfromFIFO2totheA0-A35outputs registersonlywhenareadisselectedusingtheport’sChipSelect,Write/Read
byaLOW-to-HIGHtransitionofCLKAwhenCSAisLOW,W/RAisLOW,ENA select,Enable,andMailboxselect.
isHIGH,MBAisLOW,andEFA/ORAisHIGH(seeTable2).FIFOreadsand
writesonportAareindependentofanyconcurrentportBoperation.Writeand theEmptyFlagtochangestateonthesecondLOW-to-HIGHtransitionofthe
Read cycle timing diagrams for Port A can be found in Figure 4 and 7. ReadClock. Thedatawordwillnotbeautomaticallysenttotheoutputregister.
WhenoperatingtheFIFOinIDTStandardmode,thefirstwordwillcause
TheportBcontrolsignalsareidenticaltothoseofportAwiththeexception Instead, data residing in the FIFO's memory array is clocked to the output
thattheportBWrite/Readselect(W/RB)istheinverseoftheportAWrite/Read registeronlywhenareadisselected usingtheport’sChipSelect,Write/Read
select(W/RA).ThestateoftheportBdata(B0-B35)outputsiscontrolledbythe select,Enable,andMailboxselect.
portBChipSelect(CSB)andportBWrite/Readselect(W/RB). TheB0-B35
outputs are in the high-impedance state when either CSB is HIGH or W/RB SYNCHRONIZED FIFO FLAGS
isLOW.TheB0-B35outputsareactivewhenCSBisLOWandW/RBisHIGH.
EachFIFOissynchronizedtoitsportclockthroughatleasttwoflip-flop
Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH stages.Thisisdonetoimproveflagsignalreliabilitybyreducingtheprobability
transition of CLKB when CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is ofmetastableeventswhenCLKAandCLKBoperateasynchronouslytoone
LOW, andFFB/IRBisHIGH. DataisreadfromFIFO1totheB0-B35outputs another. EFA/ORA, AEA, FFA/IRA, and AFA are synchronized to CLKA.
byaLOW-to-HIGHtransitionofCLKBwhenCSBisLOW,W/RBisHIGH,ENB EFB/ORB, AEB, FFB/IRB, and AFB are synchronized to CLKB. Tables
isHIGH,MBBisLOW,andEFB/ORBisHIGH(seeTable3).FIFOreadsand 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2.
writesonportBareindependentofanyconcurrentportAoperation.Writeand
Read cycle timing diagrams for Port B can be found in Figure 5 and 6.
The setup and hold time constraints to the port Clocks for the port Chip
EMPTY/OUTPUT READY FLAGS (EFA/ORA, EFB/ORB)
These are dual purpose flags. In the FWFT mode, the Output Ready
SelectsandWrite/Readselectsareonlyforenablingwriteandreadoperations (ORA, ORB) function is selected. When the Output Ready flag is HIGH,
TABLE 2 — PORT A ENABLE FUNCTION TABLE
CSA
H
L
W/RA
ENA
MBA
CLKA
Data A (A0-A35) I/O
High-Impedance
Input
Port Function
X
H
H
H
L
X
X
X
X
↑
↑
X
↑
X
↑
None
None
L
X
L
H
L
Input
FIFO1 write
Mail1write
L
H
H
Input
L
L
L
Output
None
L
L
H
L
Output
FIFO2 read
None
L
L
L
H
Output
L
L
H
H
Output
Mail2 read (set MBF2 HIGH)
TABLE 3 — PORT B ENABLE FUNCTION TABLE
CSB
H
L
W/RB
ENB
MBB
CLKB
Data B (B0-B35) I/O
Port Function
X
L
X
X
X
X
↑
↑
X
↑
X
↑
High-Impedance
Input
None
None
L
X
L
L
H
L
Input
FIFO2 write
Mail2write
L
L
H
H
Input
L
H
H
H
H
L
L
Output
None
L
H
L
Output
FIFO1 read
None
L
L
H
Output
L
H
H
Output
Mail1 read (set MBF1 HIGH)
11
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
newdataispresentintheFIFOoutputregister.WhentheOutputReadyflag
InIDTStandardmode,fromthetimeawordiswrittentoaFIFO,theEmpty
is LOW, the previous data word is present in the FIFO output register and Flagwillindicatethepresenceofdataavailableforreadinginaminimumoftwo
attemptedFIFOreadsareignored. cyclesoftheEmptyFlagsynchronizingclock.Therefore,anEmptyFlagisLOW
In the IDT Standard mode, the Empty Flag (EFA, EFB) function is ifawordinmemoryisthenextdatatobesenttotheFlFOoutputregisterand
selected.WhentheEmptyFlagisHIGH,dataisavailableintheFIFO’sRAM twocyclesoftheportClockthatreadsdatafromtheFIFOhavenotelapsed
forreadingtotheoutputregister.WhentheEmptyFlagisLOW,theprevious sincethetimethewordwaswritten.TheEmptyFlagoftheFIFOremainsLOW
datawordispresentintheFIFOoutputregisterandattemptedFIFOreadsare untilthesecondLOW-to-HIGHtransitionofthesynchronizingclockoccurs,
ignored.
TheEmpty/OutputReadyflagofaFIFOissynchronizedtotheportclock
forcing the Empty Flag HIGH; only then can data be read.
ALOW-to-HIGHtransitiononanEmpty/OutputReadyflagsynchronizing
thatreadsdatafromitsarray. ForboththeFWFTandIDTStandardmodes, clockbeginsthefirstsynchronizationcycleofawriteiftheclocktransitionoccurs
the FIFO read pointer is incremented each time a new word is clocked to its attimetSKEW1orgreaterafterthewrite.Otherwise,thesubsequentclockcycle
outputregister.ThestatemachinethatcontrolsanOutputReadyflagmonitors canbethefirstsynchronizationcycle(seeFigures8through11forEFA/ORA
a write pointer and read pointer comparator that indicates when the FIFO and EFB/ORB timing diagrams).
memorystatusisempty,empty+1,orempty+2.
InFWFTmode,fromthetimeawordiswrittentoaFIFO,itcanbeshifted FULL/INPUT READY FLAGS (FFA/IRA, FFB/IRB)
totheFIFOoutputregisterinaminimumofthreecyclesoftheOutputReady
Thisisadualpurposeflag.InFWFTmode,theInputReady(IRAandIRB)
flagsynchronizingclock.Therefore,anOutputReadyflagisLOWifawordin function is selected. In IDT Standard mode, the Full Flag (FFA and FFB)
memoryisthenextdatatobesenttotheFlFOoutputregisterandthreecycles functionisselected.Forbothtimingmodes,whentheFull/InputReadyflagis
oftheportClockthatreadsdatafromtheFIFOhavenotelapsedsincethetime HIGH,amemorylocationisfreeintheFIFOtoreceivenewdata.Nomemory
thewordwaswritten.TheOutputReadyflagoftheFIFOremainsLOWuntil locationsarefreewhentheFull/InputReadyflagisLOWandattemptedwrites
thethirdLOW-to-HIGHtransitionofthesynchronizingclockoccurs,simulta- to the FIFO are ignored.
neouslyforcingtheOutputReadyflagHIGHandshiftingthewordtotheFIFO
outputregister.
TABLE 4 — FIFO1 FLAG OPERATION (IDT STANDARD AND FWFT MODES)
Synchronized
to CLKB
Synchronized
to CLKA
Number of Words in FIFO(1,2)
IDT72V3622(3)
IDT72V3632(3)
IDT72V3642(3)
EFB/ORB
AEB
L
AFA
FFA/IRA
0
1 to X1
0
1 to X1
0
1 to X1
L
H
H
H
H
H
H
H
L
H
H
H
H
L
L
(X1+1) to [256-(Y1+1)]
(256-Y1) to 255
256
(X1+1) to [512-(Y1+1)]
(512-Y1) to 511
512
(X1+1) to [1,024-(Y1+1)]
(1,024-Y1) to 1,023
1,024
H
H
H
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no
read operation necessary), it is not included in the FIFO memory count.
3. X1 is the Almost-Empty offset for FIFO1 used by AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a reset of FIFO1 or programmed from
port A.
4. The ORB and IRA functions are active during FWFT mode; the EFB and FFA functions are active in IDT Standard mode.
TABLE 5 — FIFO2 FLAG OPERATION (IDT STANDARD AND FWFT MODES)
Synchronized
to CLKA
Synchronized
to CLKB
Number of Words in FIFO(1,2)
IDT72V3622(3)
IDT72V3632(3)
IDT72V3642(3)
EFA/ORA
AEA
L
AFB
FFB/IRB
0
1 to X2
0
1 to X2
0
1 to X2
L
H
H
H
H
H
H
H
L
H
H
H
H
L
L
(X2+1) to [256-(Y2+1)]
(256-Y2) to 255
256
(X2+1) to [512-(Y2+1)]
(512-Y2) to 511
512
(X2+1) to [1,024-(Y2+1)]
(1,024-Y2) to 1,023
1,024
H
H
H
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no
read operation necessary), it is not included in the FIFO memory count.
3. X2 is the Almost-Empty offset for FIFO2 used by AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a reset of FIFO2 or programmed from
port A.
4. The ORA and IRB functions are active during FWFT mode; the EFA and FFB functions are active in IDT Standard mode.
12
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
TheFull/InputReadyflagofaFlFOissynchronizedtotheportclockthat bythecontentsofregisterY1forAFAandregisterY2forAFB.Theseregisters
writesdatatoitsarray. ForbothFWFTandIDTStandardmodes, eachtime are loaded with preset values during a FlFO reset or programmed from port
awordiswrittentoaFIFO,itswritepointerisincremented.Thestatemachine A(seeAlmost-EmptyflagandAlmost-Fullflagoffsetprogrammingsection).
thatcontrolsaFull/InputReadyflagmonitorsawritepointerandreadpointer AnAlmost-FullflagisLOWwhenthenumberofwordsinitsFIFOisgreaterthan
comparatorthatindicateswhentheFlFOmemorystatusisfull,full-1,orfull-2. orequalto(256-Y),(512-Y),or(1,024-Y)fortheIDT72V3622,IDT72V3632,
FromthetimeawordisreadfromaFIFO,itspreviousmemorylocationisready or IDT72V3642 respectively. An Almost-Full flag is HIGH when the number
to be written to in a minimum of two cycles of the Full/Input Ready flag of words in its FIFO is less than or equal to [256-(Y+1)], [512-(Y+1)], or
synchronizingclock.Therefore,aFull/InputReadyflagisLOWiflessthantwo [1,024-(Y+1)] for the IDT72V3622, IDT72V3632, or IDT72V3642 respec-
cyclesoftheFull/InputReadyflagsynchronizingclockhaveelapsedsincethe tively. NotethatadatawordpresentintheFIFOoutputregisterhasbeenread
next memory write location has been read. The second LOW-to-HIGH frommemory.
transitionontheFull/InputReadyflagsynchronizingclockafterthereadsets
the Full/Input Ready flag HIGH.
TwoLOW-to-HIGHtransitionsoftheAlmost-Fullflagsynchronizingclock
arerequiredafteraFIFOreadforitsAlmost-Fullflagtoreflectthenewlevelof
ALOW-to-HIGHtransitiononaFull/InputReadyflagsynchronizingclock fill.Therefore,theAlmost-FullflagofaFIFOcontaining[256/512/1,024-(Y+1)]
beginsthefirstsynchronizationcycleofareadiftheclocktransitionoccursat or less words remains LOW if two cycles of its synchronizing clock have not
timetSKEW1orgreateraftertheread.Otherwise,thesubsequentclockcyclecan elapsedsincethereadthatreducedthenumberofwordsinmemoryto[256/
bethefirstsynchronizationcycle(seeFigures12through15forFFA/IRAand 512/1,024-(Y+1)]. AnAlmost-FullflagissetHIGHbythesecondLOW-to-HIGH
FFB/IRB timing diagrams).
transitionofitssynchronizingclockaftertheFIFOreadthatreducesthenumber
ofwordsinmemoryto[256/512/1,024-(Y+1)]. ALOW-to-HIGHtransitionofan
Almost-Fullflagsynchronizingclockbeginsthefirstsynchronizationcycleifit
ALMOST-EMPTY FLAGS (AEA, AEB)
TheAlmost-EmptyflagofaFIFOissynchronizedtotheportclockthatreads occursattimetSKEW2orgreaterafterthereadthatreducesthenumberofwords
datafromitsarray.ThestatemachinethatcontrolsanAlmost-Emptyflagmonitors inmemoryto[256/512/1,024-(Y+1)]. Otherwise,thesubsequentsynchroniz-
a write pointer and read pointer comparator that indicates when the FIFO ingclockcyclemaybethefirstsynchronizationcycle (seeFigures18and19).
memory status is almost-empty, almost-empty+1, or almost-empty+2. The
almost-emptystateisdefinedbythecontentsofregisterX1forAEBandregister
X2forAEA.TheseregistersareloadedwithpresetvaluesduringaFIFOreset
orprogrammedfromportA(seeAlmost-EmptyflagandAlmost-Fullflagoffset
programmingsection).AnAlmost-EmptyflagisLOWwhenitsFIFOcontains
X or less words and is HIGH when its FIFO contains (X+1) or more words. A
data word present in the FIFO output register has been read from memory.
TwoLOW-to-HIGHtransitionsoftheAlmost-Emptyflagsynchronizing
clockarerequiredafteraFIFOwriteforitsAlmost-Emptyflagtoreflectthenew
leveloffill.Therefore,theAlmost-FullflagofaFIFOcontaining(X+1)ormore
wordsremainsLOWiftwocyclesofitssynchronizingclockhavenotelapsed
sincethewritethatfilledthememorytothe(X+1)level. AnAlmost-Emptyflag
issetHIGHbythesecondLOW-to-HIGHtransitionofitssynchronizingclockafter
theFIFOwritethatfillsmemorytothe(X+1)level.ALOW-to-HIGHtransitionof
anAlmost-Emptyflagsynchronizingclockbeginsthefirstsynchronizationcycle
ifitoccursattimetSKEW2orgreaterafterthewritethatfillstheFIFOto(X+1)words.
Otherwise,thesubsequentsynchronizingclockcyclemaybethefirstsynchro-
nization cycle. (See Figures 16 and 17).
MAILBOX REGISTERS
Each FIFO has a 36-bit bypass register to pass command and control
informationbetweenportAandportBwithoutputtingitinqueue.TheMailbox
select(MBA,MBB)inputschoosebetweenamailregisterandaFIFOforaport
datatransferoperation.ALOW-to-HIGHtransitiononCLKAwritesA0-A35data
tothemail1registerwhenaportAWriteisselectedbyCSA,W/RA,andENA
andwithMBAHIGH.ALOW-to-HIGHtransitiononCLKBwritesB0-B35data
tothemail2registerwhenaportBWriteisselectedbyCSB,W/RB,andENB
andwithMBBHIGH.Writingdatatoamailregistersetsitscorrespondingflag
(MBF1orMBF2)LOW. Attemptedwritestoamailregisterareignoredwhile
themailflagisLOW.
Whendataoutputsofaportareactive,thedataonthebuscomesfromthe
FIFOoutputregisterwhentheportMailboxselectinputisLOWandfromthemail
registerwhentheportmailboxselectinputisHIGH. TheMail1RegisterFlag
(MBF1)issetHIGHbyaLOW-to-HIGHtransitiononCLKBwhenaportBRead
isselectedbyCSB,W/RB,andENBandwithMBBHIGH.TheMail2Register
Flag(MBF2)issetHIGHbyaLOW-to-HIGHtransitiononCLKAwhenaport
A read is selected by CSA, W/RA, and ENA and with MBA HIGH. The data
inamailregisterremainsintactafteritisreadandchangesonlywhennewdata
iswrittentotheregister.FormailregisterandMailRegisterFlagtimingdiagrams,
see Figure 20 and 21.
ALMOST-FULL FLAGS (AFA, AFB)
TheAlmost-FullflagofaFIFOissynchronizedtotheportclockthatwrites
datatoitsarray.ThestatemachinethatcontrolsanAlmost-Fullflagmonitorsa
writepointerandreadpointercomparatorthatindicateswhentheFIFOmemory
statusisalmost-full,almost-full-1,oralmost-full-2.Thealmost-fullstateisdefined
13
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
CLKA
CLKB
t
RSTH
t
RSTS
t
FSS
t
FSH
RST1
FWFT
tFWS
0,1
FS1,FS0
FFA/IRA
t
WFF
t
WFF
t
REF
EFB/ORB
AEB
t
t
RSF
RSF
AFA
t
RSF
MBF1
4660 drw 04
NOTES:
1. FIFO2 is reset in the same manner to load X2 and Y2 with a preset value.
2. If FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where FWFT is LOW.
Figure 2. FIFO1 Reset and Loading X1 and Y1 with a Preset Value of Eight(1) (IDT Standard and FWFT Modes)
CLKA
4
1
2
tFSS
RST1,
RST2
tFSH
0,0
FS1,FS0
tWFF
FFA/IRA
ENA
(1)
tENS2
tSKEW1
tENH
tDH
tDS
A0 - A35
First Word to FIFO1
AFA Offset
AEB Offset
(X1)
AFB Offset
AEA Offset
(Y1)
(Y2)
(X2)
CLKB
1
2
tWFF
FFB/IRB
4660 drw 05
NOTES:
1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB edge for FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
edge of CLKB is less than tSKEW1, then FFB/IRB may transition HIGH one CLKB cycle later than shown.
2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles.
Figure 3. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
14
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
tCLK
tCLKL
tCLKH
CLKA
FFA/IRA
HIGH
tENS1
tENH
CSA
t
ENS2
ENS2
t
ENH
ENH
ENH
W/RA
MBA
ENA
t
t
tENS2
t
ENS2
tENS2
t
tENH
tENH
tDH
tDS
W1(1)
W2(1)
No Operation
A0 - A35
4660 drw 06
NOTE:
1. Written to FIFO1.
Figure 4. Port A Write Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
CLKB
FFB/IRB HIGH
tENH
tENH
tENS1
CSB
tENS2
W/RB
tENH
tENH
tENS2
tENS2
MBB
tENH
tENH
tENS2
tENS2
ENB
tDH
tDS
(1)
W2(1)
No Operation
B0 - B35
W1
4660 drw 07
NOTE:
1. Written to FIFO2.
Figure 5. Port B Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
15
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
EFB/ORB HIGH
CSB
W/RB
tENS2
MBB
tENH
tENH
tENH
tENS2
tENS2
ENB
No Operation
W2(1)
t
DIS
DIS
t
t
MDV
MDV
t
A
t
A
A
t
EN
EN
B0-B35
Previous Data
W1(1)
W2(1)
(IDT Standard Mode)
t
OR
tA
t
t
B0-B35
W1(1)
W3 (1)
(FWFT Mode)
4660 drw 08
NOTE:
1. Read From FIFO1.
Figure 6. Port B Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
tCLK
tCLKH
tCLKL
CLKA
EFA/ORA HIGH
CSA
W/RA
MBA
ENA
t
ENS2
t
ENH
tENH
t
ENH
t
ENS2
t
ENS2
t
DMV
No Operation
W2(1)
t
DIS
DIS
t
A
t
A
t
EN
A0-A35
Previous Data
W1(1)
W2(1)
(Standard Mode)
t
t
MDV
t
A
OR
tA
t
EN
A0-A35
W3(1)
W1(1)
(FWFT Mode)
4660 drw 09
NOTE:
1. Read From FIFO2.
Figure 7. Port A Read Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
16
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
t
CLK
t
CLKL
tCLKH
CLKA
CSA
LOW
HIGH
WRA
tENS2
tENH
MBA
tENS2
tENH
ENA
HIGH
IRA
tDH
tDS
A0 - A35
W1
t
CLK
(1)
tSKEW1
tCLKH
tCLKL
1
2
3
CLKB
t
REF
t
REF
ORB FIFO1Empty
CSB LOW
W/RB
HIGH
LOW
MBB
tENS2
tENH
ENB
tA
B0- B35
Old Data in FIFO1 Output Register
W1
4660 drw 10
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.
If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB
cycle later than shown.
Figure 8. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)
17
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
t
CLK
t
CLKL
tCLKH
CLKA
CSA
LOW
HIGH
WRA
t
ENS2
t
ENH
ENH
MBA
tENS2
t
ENA
FFA
HIGH
tDS
tDH
A0-A35
W1
t
CLKtCLKL
(1)
SKEW1
t
CLKH
t
CLKB
1
2
t
REF
tREF
FIFO1 Empty
LOW
EFB
CSB
W/RB
HIGH
LOW
MBB
tENH
tENS2
ENB
tA
W1
B0-B35
4660 drw 11
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then the transition of EFB HIGH may occur one CLKB cycle later than shown.
Figure 9. EFB Flag Timing and First Data Read Fall Through when FIFO1 is Empty (IDT Standard Mode)
18
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
tCLK
tCLKL
tCLKH
CLKB
LOW
LOW
CSB
W/RB
tENS2
tENH
MBB
ENB
tENS2
tENH
IRB
HIGH
tDS
tDH
B0 - B35
W1
t
CLK
(1)
SKEW1
t
tCLKH
t
CLKL
1
2
3
CLKA
ORA
t
REF
t
REF
FIFO2 Empty
LOW
LOW
LOW
CSA
W/RA
MBA
tENS2
tENH
ENA
tA
Old Data in FIFO2 Output Register
W1
A0- A35
4660 drw 12
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.
If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA
cycle later than shown.
Figure 10. ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty (FWFT Mode)
19
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
t
CLK
t
CLKH
tCLKL
CLKB
LOW
LOW
CSB
W/RB
t
ENS2
ENS2
t
ENH
MBB
ENB
t
t
ENH
HIGH
FFB
tDH
tDS
W1
B0-B35
t
CLK
(1)
SKEW1
t
CLKH
t
tCLKL
1
2
CLKA
t
REF
t
REF
EFA
FIFO2 Empty
LOW
LOW
CSA
W/RA
MBA
LOW
tENS2
tENH
ENA
tA
A0-A35
W1
4660 drw 13
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then the transition of EFA HIGH may occur one CLKA cycle later than shown.
Figure 11. EFA Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode)
20
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
LOW
CSB
W/RB
HIGH
LOW
MBB
tENH
tENS2
ENB
HIGH
ORB
tA
Previous Word in FIFO1 Output Register
SKEW1
Next Word From FIFO1
B0- B35
(1)
t
tCLK
tCLKH
tCLKL
1
2
CLKA
tWEF
tWEF
FIFO1 Full
LOW
IRA
CSA
W/RA
HIGH
tENS2
tENH
MBA
tENS2
tENH
ENA
A0 - A35
NOTE:
tDS
tDH
Write
4660 drw 14
To FIFO1
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then IRA may transition HIGH one CLKA cycle later than shown.
Figure 12. IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)
21
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKB
LOW
CSB
W/RB
MBB
HIGH
LOW
tENS2
tENH
ENB
EFB
HIGH
tA
Previous Word in FIFO1 Output Register
Next Word From FIFO1
B0-B35
(1)
tSKEW1
tCLK
tCLKH
tCLKL
CLKA
1
2
t
WFF
t
WFF
FIFO1 Full
LOW
FFA
CSA
HIGH
W/RA
t
ENS2
t
ENH
ENH
MBA
t
ENS2
t
ENA
tDH
tDS
A0-A35
Write
4660 drw 15
To FIFO1
NOTE:
1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW1, then FFA may transition HIGH one CLKA cycle later than shown.
Figure 13. FFA Flag Timing and First Available Write when FIFO1 is Full (IDT Standard Mode)
22
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
LOW
CSA
W/RA LOW
LOW
MBA
ENA
tENS2
tENH
HIGH
ORA
tA
Previous Word in FIFO2 Output Register
SKEW1
Next Word From FIFO2
A0- A35
(1)
t
tCLK
tCLKH
tCLKL
1
2
CLKB
IRB
tWEF
tWEF
FIFO2 FULL
LOW
CSB
LOW
W/RB
tENS2
tENH
MBB
ENB
tENS2
tENH
tDS
tDH
Write
B0 - B35
4660 drw 16
To FIFO2
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown.
Figure 14. IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
23
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
tCLK
tCLKH
tCLKL
CLKA
LOW
LOW
LOW
CSA
W/RA
MBA
tENS2
tENH
ENA
EFA
HIGH
tA
Previous Word in FIFO2 Output Register
Next Word From FIFO2
A0-A35
(1)
tCLK
tSKEW1
tCLKH
tCLKL
CLKB
1
2
t
WFF
t
WFF
FIFO2 Full
LOW
FFB
CSB
W/RB LOW
tENH
tENS2
MBB
ENB
t
ENS2
t
ENH
tDS
tDH
Write
B0-B35
4660 drw 17
To FIFO2
NOTE:
1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW1, then FFB may transition HIGH one CLKB cycle later than shown.
Figure 15. FFB Flag Timing and First Available Write when FIFO2 is Full (IDT Standard Mode)
CLKA
tENS2
tENH
ENA
(1)
SKEW2
t
1
2
CLKB
t
PAE
t
PAE
AEB
X1 Words in FIFO1
(X1+1) Words in FIFO1
ENS2
t
tENH
ENB
4660 drw 18
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
Figure 16. Timing for AEB when FIFO1 is Almost-Empty (IDT Standard and FWFT Modes)
24
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
CLKB
tENS2
tENH
ENB
(1)
tSKEW2
1
CLKA
2
t
PAE
t
PAE
AEA
X2 Words in FIFO2
(X2+1) Words in FIFO2
ENS2
t
tENH
ENA
4660 drw 19
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
Figure 17. Timing for AEA when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes)
(1)
SKEW2
t
1
2
t
CLKA
ENA
tENS2
tENH
PAF
t
PAF
(D-Y1) Words in FIFO1
[D-(Y1+1)] Words in FIFO1
AFA
CLKB
tENS2
tENH
ENB
4660 drw 20
NOTES:
1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown.
2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT72V3622, 512 for the IDT72V3632, 1,024 for the IDT72V3642.
Figure 18. Timing for AFA when FIFO1 is Almost-Full (IDT Standard and FWFT Modes)
25
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
(1)
SKEW2
t
1
2
CLKB
tENS2
tENH
ENB
AFB
t
PAF
tPAF
(D-Y2) Words in FIFO2
[D-(Y2+1)] Words in FIFO2
CLKA
tENH
tENS2
ENA
4660 drw 21
NOTES:
1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKB cycle later than shown.
2. FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 256 for the IDT72V3622, 512 for the IDT72V3632, 1,024 for the IDT72V3642.
Figure 19. Timing for AFB when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)
CLKA
tENH
tENS1
CSA
W/RA
MBA
t
ENH
t
ENS1
t
ENH
t
ENS2
tENH
tENS2
ENA
A0 - A35
CLKB
tDH
t
DS
W1
t
PMF
tPMF
MBF1
CSB
W/RB
MBB
ENB
tENH
tENS2
t
MDV
tEN
t
PMR
tDIS
FIFO1 Output Register
W1 (Remains valid in Mail1 Register after read)
B0 - B35
4660 drw 22
Figure 20. Timing for Mail1 Register and MBF1 Flag (IDT Standard and FWFT Modes)
26
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
CLKB
tENS1
tENH
CSB
W/RB
MBB
ENB
t
ENS1
ENS2
t
ENH
t
t
ENH
tENS2
t
t
ENH
DH
tDS
W1
B0-B35
CLKA
t
PMF
tPMF
MBF2
CSA
W/RA
MBA
ENA
tENH
tENS2
t
PMR
tEN
tDIS
t
MDV
W1 (Remains valid in Mail 2 Register after read)
A0-A35
4660 drw23
FIFO2 Output Register
Figure 21. Timing for Mail2 Register and MBF2 Flag (IDT Standard and FWFT Modes)
27
IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURERANGE
PARAMETER MEASUREMENT INFORMATION
3.3V
Ω
330
From Output
Under Test
30 pF (1)
Ω
510
PROPAGATION DELAY
LOAD CIRCUIT
3V
3V
Timing
Input
1.5V
High-Level
1.5V
Input
1.5V
GND
GND
3V
t
S
th
t
W
3V
Data,
Enable
Input
1.5V
1.5V
Low-Level
1.5V
1.5V
GND
Input
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3V
Output
Enable
1.5V
1.5V
t
PZL
GND
tPLZ
3V
≈
3V
Input
1.5V
1.5V
1.5V
Low-Level
Output
GND
V
OL
tPD
t
PZH
tPD
V
OH
V
OH
In-Phase
Output
1.5V
1.5V
High-Level
Output
1.5V
t
PHZ
V
OL
≈ OV
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
4660 drw 24
NOTE:
1. Includes probe and jig capacitance.
Figure 22. Load Circuit and Voltage Waveforms
28
ORDERING INFORMATION
X
XXXXXX
X
XX
X
X
X
Device Type Power
Speed
Package
Process/
Temperature
Range
BLANK
8
Tube or Tray
Tape and Reel
BLANK
G
Commercial (0°C to +70°C)
Green
PF
Thin Quad Flat Pack (TQFP, PN120-1)
10
15
Clock Cycle Time (tCLK
)
Commercial Only
Low Power
Speed in Nanoseconds
L
72V3622
72V3632
72V3642
256 x 36 x 2 3.3V SyncBiFIFO
™
™
512 x 36 x 2 3.3V SyncBiFIFO
1,024 x 36 x 2 3.3V SyncBiFIFO
™
4660 drw 25
NOTE:
1. Industrial temperature range is available by special order.
DATASHEETDOCUMENTHISTORY
12/19/2000
03/21/2001
08/01/2001
12/18/2001
02/10/2009
05/09/2013
05/15/2013
pg. 11.
pgs. 6 and 7.
pgs. 6, 8, 9 and 29.
pg. 27.
pgs. 1 and 29.
pgs. 1-3, 6, 8, 9 and 29.
pg. 29.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-360-1753
email:FIFOhelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
29
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