72V831L15TFI [IDT]
TQFP-64, Tray;
| 型号： | 72V831L15TFI |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | TQFP-64, Tray |
| 文件： | 总16页 (文件大小：165K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT72V801
IDT72V811
IDT72V821
IDT72V831
IDT72V841
IDT72V851
3.3 VOLT DUAL CMOS SyncFIFO™
DUAL 256 X 9, DUAL 512 X 9,
DUAL 1,024 X 9, DUAL 2,048 X 9,
DUAL 4,096 X 9 , DUAL 8,192 X 9
FEATURES:
EachofthetwoFIFOs(designatedFIFOAandFIFOB)containedinthe
IDT72V801/72V811/72V821/72V831/72V841/72V851hasa9-bitinputdata
port (DA0 - DA8, DB0 - DB8) and a 9-bit output data port (QA0 - QA8,
QB0 - QB8).Eachinputportis controlledbya free-runningclock(WCLKA,
WCLKB), and two Write Enable pins (WENA1, WENA2, WENB1, WENB2).
DataiswrittenintoeachofthetwoarraysoneveryrisingclockedgeoftheWrite
Clock (WCLKA, WCLKB) when the appropriate Write Enable pins are
asserted.
TheoutputportofeachFIFObankiscontrolledbyitsassociated clockpin
(RCLKA, RCLKB) and two Read Enable pins (RENA1, RENA2, RENB1,
RENB2).TheReadClockcanbetiedtotheWriteClockforsingleclockoperation
orthetwoclockscanrunasynchronousofoneanotherfordualclockoperation.
AnOutputEnablepin(OEA,OEB)is providedonthereadportofeachFIFO
forthree-stateoutputcontrol.
• The IDT72V801 is equivalent to two IDT72V201 256 x 9 FIFOs
• The IDT72V811 is equivalent to two IDT72V211 512 x 9 FIFOs
• The IDT72V821 is equivalent to two IDT72V221 1,024 x 9 FIFOs
• The IDT72V831 is equivalent to two IDT72V231 2,048 x 9 FIFOs
• The IDT72V841 is equivalent to two IDT72V241 4,096 x 9 FIFOs
• The IDT72V851 is equivalent to two IDT72V251 8,192 x 9 FIFOs
• Offers optimal combination of large capacity, high speed,
design flexibility and small footprint
• Ideal for prioritization, bidirectional, and width expansion
applications
• 10 ns read/write cycle time
• 5V input tolerant
• Separate control lines and data lines for each FIFO
• Separate Empty, Full, programmable Almost-Empty and
Almost-Full flags for each FIFO
• Enable puts output data lines in high-impedance state
• Space-saving 64-pin plastic Thin Quad Flat Pack (TQFP/
STQFP)
EachofthetwoFIFOshastwofixedflags,Empty(EFA,EFB)andFull(FFA,
FFB). Twoprogrammableflags,Almost-Empty(PAEA,PAEB)andAlmost-Full
(PAFA,PAFB),areprovidedforeachFIFObanktoimprovememoryutilization.
Ifnotprogrammed,theprogrammableflagsdefaulttoEmpty+7forPAEAand
PAEB, and Full-7 for PAFA and PAFB.
• Industrial temperature range (–40°C to +85°C) is available
• Green parts available, see ordering information
TheIDT72V801/72V811/72V821/72V831/72V841/72V851architecture
lendsitselftomanyflexibleconfigurationssuchas:
• 2-levelprioritydatabuffering
• Bidirectionaloperation
• Widthexpansion
• Depthexpansion
ThisFIFOisfabricatedusingIDT'shigh-performancesubmicronCMOS
technology.
DESCRIPTION:
TheIDT72V801/72V811/72V821/72V831/72V841/72V851/72V851are
dualsynchronous(clocked)FIFOs. Thedeviceisfunctionallyequivalentto
twoIDT72V201/72V211/72V221/72V231/72V241/72V251FIFOsinasingle
packagewithallassociatedcontrol,data,andflaglinesassignedtoseparate
pins.
FUNCTIONAL BLOCK DIAGRAM
EFA
PAEA
PAFA
FFA
WCLKB
WCLKA
WENA1
WENA2
WENB1
DA0 - DA8
DB0 - DB8
LDA
LDB
WENB2
INPUT REGISTER
OFFSET REGISTER
INPUT REGISTER
OFFSET REGISTER
EFB
FLAG
LOGIC
FLAG
LOGIC
WRITE CONTROL
LOGIC
WRITE CONTROL
LOGIC
PAEB
PAFB
FFB
RAM ARRAY
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9, 8,192 x 9
RAM ARRAY
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9, 8,192 x 9
WRITE POINTER
READ POINTER
WRITE POINTER
READ POINTER
READ CONTROL
LOGIC
READ CONTROL
LOGIC
OUTPUT REGISTER
OUTPUT REGISTER
RESET LOGIC
RESET LOGIC
4093 drw 01
RCLKB
RENB1
RENB2
RSA
OEA
RSB
RCLKA
OEB
QB0 - QB8
QA0 - QA8
RENA1
RENA2
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
OCTOBER 2008
1
©2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4093/4
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
PIN CONFIGURATION
QB0
1
2
3
4
5
6
7
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
QA
QA
QA
QA
QA
QA
QA
QA
1
2
3
4
5
6
7
8
FFB
EFB
OEB
RENB
RCLKB
RENB
GND
Vcc
PAEB
2
1
9
V
CC
10
11
12
13
14
15
16
WENA
WCLKA
WENA
RSA
DA
DA
DA
2
/LDA
PAFB
DB
0
1
DB
DB
DB
DB
1
2
3
4
8
7
6
4093 drw 02
TQFP (PN64-1, order code: PF)
STQFP (PP64-1, order code: TF)
TOP VIEW
OCTOBER22,2008
2
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
PINDESCRIPTIONS
TheIDT72V801/72V811/72V821/72V831/72V841/72V851'stwoFIFOs,
referredtoasFIFOAandFIFOB,areidenticalineveryrespect.Thefollowing
descriptiondefinestheinputandoutputsignalsforFIFOA.Thecorresponding
signal names for FIFO B are provided in parentheses.
Symbol
DA0-DA8
DB0-DB8
RSA, RSB
Name I/O
ADataInputs
BDataInputs
Reset
Description
I
I
I
9-bit data inputs to RAM array A.
9-bit data inputs to RAM array B.
When RSA (RSB) is set LOW, the associated internal read and write pointers of array A (B) are set to the first
location; FFA (FFB) and PAFA (PAFB) go HIGH, and PAEA (PAEB) and EFA (EFB) go LOW. After power-
up, a reset of both FIFOs A and B is required before an initial WRITE.
WCLKA
WCLKB
Write Clock
I
I
Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the write enable(s)
areasserted.
WENA1
WENB1
WriteEnable1
If FIFO A (B) is configured to have programmable flags, WENA1 (WENB1) is the only write enable pin that can be
used. When WENA1 (WENB1) is LOW, data A (B) is written into the FIFO on every LOW-to-HIGH transition
WCLKA (WCLKB). If the FIFO is configured to have two write enables, WENA1 (WENB1) must be LOW and
WENA2 (WENB2) must be HIGH to write data into the FIFO. Data will not be written into the FIFO if FFA (FFB) is
LOW.
WENA2/LDA
WENB2/LDB
WriteEnable2/
Load
I
FIFO A (B) is configured at reset to have either two write enables or programmable flags. If LDA (LDB) is HIGH at
reset, this pin operates as a second Write Enable. If WENA2/LDA (WENB2/LDB) is LOW at reset this pin operates
as a controltoloadandreadthe programmable flagoffsets forits respective array. Ifthe FIFOis configuredtohave
two write enables, WENA1 (WENB1) must be LOW and WENA2 (WENB2) must be HIGH to write data into FIFO
A (B). Data will not be written into FIFO A (B) if FFA (FFB) is LOW. If the FIFO is configured to have programmable
flags, LDA (LDB)is heldLOWtowrite orreadthe programmable flagoffsets.
QA0-QA8
QB0-QB8
ADataOutputs
BDataOutputs
Read Clock
O
O
I
9-bitdata outputs fromRAMarrayA.
9-bitdata outputs fromRAMarrayB.
RCLKA
RCLKB
Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when RENA1(RENB1) and
RENA2 (RENB2) are asserted.
RENA1
RENB1
ReadEnable1
ReadEnable2
OutputEnable
Empty Flag
I
I
When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from FIFO A (B) on every LOW-to-HIGH
transition of RCLKA (RCLKB). Data will not be read from Array A (B) if EFA (EFB) is LOW.
RENA2
RENB2
When RENA1 (RENB1) and RENA2 (RENB2) are LOW, data is read from the FIFO A (B) on every LOW-to-
HIGH transition of RCLKA (RCLKB). Data will not be read from array A (B) if the EFA (EFB) is LOW.
OEA
I
When OEA (OEB) is LOW, outputs DA0-DA8 (DB0-DB8) are active. If OEA (OEB) is HIGH, the OEB outputs DA0-
DA8(DB0-DB8)willbe ina high-impedance state.
EFA
EFB
O
O
O
O
When EFA (EFB) is LOW, FIFO A (B) is empty and further data reads from the output are inhibited. When EFA
(EFB) is HIGH, FIFO A (B) is not empty. EFA (EFB) is synchronized to RCLKA (RCLKB).
PAEA
PAEB
Programmable
Almost-EmptyFlag
When PAEA (PAEB) is LOW, FIFO A (B) is Almost-Empty based on the offset programmed into the appropriate
offset register. The default offset at reset is Empty+7. PAEA (PAEB) is synchronized to RCLKA (RCLKB).
PAFA
PAFB
Programmable
Almost-FullFlag
WhenPAFA (PAFB)is LOW, FIFOA(B)is Almost-Fullbasedonthe offsetprogrammedintothe appropriate offset
register. The default offset at reset is Full-7. PAFA (PAFB) is synchronized to WCLKA (WCLKB).
FFA
FFB
FullFlag
When FFA (FFB) is LOW, FIFO A (B) is full and further data writes into the input are inhibited. When FFA (FFB) is
HIGH, FIFO A (B) is not full. FFA (FFB) is synchronized to WCLKA (WCLKB).
VCC
Power
Ground
+3.3V power supply pin.
0V groundpin.
GND
3
OCTOBER22,2008
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
ABSOLUTEMAXIMUMRATINGS
RECOMMENDEDOPERATING
Symbol
Rating
Commercial
Unit
CONDITIONS
VTERM
TerminalVoltagewith
Respect to GND
StorageTemperature
DCOutputCurrent
–0.5 to +5
V
Symbol
Parameter
Min
Typ.
Max
Unit
VCC
Supply Voltage(Com’l & Ind’l) 3.0
3.3
3.6
V
TSTG
IOUT
–55to+125
–50to+50
°C
mA
GND
VIH
Supply Voltage(Com’l & Ind’l)
0
0
—
V
V
V
InputHighVoltage
(Com’l & Ind’l)
NOTE:
2.0
—
5.0
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
VIL
TA
TA
InputLowVoltage
(Com’l & Ind’l)
—
0
—
—
0.8
70
OperatingTemperature
Commercial
°
C
OperatingTemperature
Industrial
-40
⎯
85
°
C
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial :VCC = 3.3V ± 0.3V, TA = -40°C to +85°C)
IDT72V801
IDT72V811
IDT72V821
IDT72V831
IDT72V841
IDT72V851
Commercial and Industrial (1)
tCLK = 10, 15, 20 ns
Symbol
Parameter
InputLeakageCurrent(AnyInput)
OutputLeakageCurrent
Min.
–1
Typ.
Max.
Unit
µ A
µ A
V
(2)
ILI
—
–1
10
(3)
ILO
–10
2.4
—
—
VOH
VOL
Output Logic “1” Voltage, IOH = –2 mA
Output Logic “0” Voltage, IOL = 8 mA
—
—
0.4
—
V
(4,5,6)
ICC1
Active Power Supply Current (both FIFOs)
StandbyCurrent
—
—
—
—
40
10
mA
mA
(3,7)
ICC2
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
2. Measurements with 0.4 ≤ VIN ≤ VCC.
3. OEA, OEB ≥ VIH, 0.4 ≤ VOUT ≤ VCC.
4. Tested with outputs disabled (IOUT = 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical ICC1 = 2[0.17 + 0.48*fS + 0.02*CL*fS] (in mA).
These equations are valid under the following conditions:
VCC = 3.3V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
CAPACITANCE(TA = +25
°
C, f = 1.0MHz)
Conditions
VIN = 0V
Symbol
Parameter
Max.
Unit
(2)
CIN
InputCapacitance
10
pF
(1,2)
COUT
Output Capacitance
VOUT = 0V
10
pF
NOTE:
1. With output deselected (OEA, OEB ≥ VIH).
2. Characterized values, not currently tested.
OCTOBER22,2008
4
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
ACELECTRICALCHARACTERISTICS(1)
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V± 0.3V, TA = -40°C to +85°C)
Commercial
Com’l & Ind’l
Commercial
IDT72V801L10
IDT72V811L10
IDT72V821L10
IDT72V831L10
IDT72V841L10
IDT72V851L10
IDT72V801L15
IDT72V811L15
IDT72V821L15
IDT72V831L15
IDT72V841L15
IDT72V851L15
IDT72V801L20
IDT72V811L20
IDT72V821L20
IDT72V831L20
IDT72V841L20
IDT72V851L20
Symbol
fS
Parameter
Min.
—
2
Max.
100
6.5
—
—
—
—
—
—
—
—
—
—
10
Min.
—
2
Max.
66.7
10
Min.
—
2
Max.
50
Unit
MHz
ns
Clock Cycle Frequency
DataAccessTime
Clock Cycle Time
Clock High Time
tA
12
tCLK
tCLKH
tCLKL
tDS
10
4.5
4.5
3
15(1)
—
—
—
—
—
—
—
—
—
—
15
20
8
—
—
—
—
—
—
—
—
—
—
20
ns
6
ns
Clock Low Time
6
8
ns
DataSet-upTime
DataHoldTime
4
5
ns
tDH
0.5
3
1
1
ns
tENS
tENH
tRS
EnableSet-upTime
EnableHoldTime
ResetPulseWidth(2)
ResetSet-upTime
ResetRecoveryTime
4
5
ns
0.5
10
8
1
1
ns
15
10
10
—
0
20
12
12
—
0
ns
tRSS
tRSR
tRSF
tOLZ
tOE
ns
8
ns
ResettoFlagTimeandOutputTime
—
0
ns
(3)
OutputEnabletoOutputinLow-Z
—
6
—
8
—
10
ns
OutputEnabletoOutputValid
3
3
3
ns
(3)
tOHZ
tWFF
tREF
tPAF
tPAE
tSKEW1
OutputEnabletoOutputinHigh-Z
3
6
3
8
3
10
ns
Write Clock to Full Flag
—
—
—
—
5
6.5
6.5
6.5
6.5
—
—
—
—
—
6
10
—
—
—
—
8
12
ns
Read Clock to Empty Flag
10
12
ns
WriteClocktoProgrammableAlmost-FullFlag
ReadClocktoProgrammableAlmost-EmptyFlag
10
12
ns
ns
10
12
Skew Time Between Read Clock and Write Clock
for Empty Flag and Full Flag
—
—
ns
tSKEW2
Skew Time Between Read Clock and Write Clock for
ProgrammableAlmost-EmptyFlagandProgrammable
Almost-FullFlag
14
—
18
—
20
—
ns
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
3.3V
330Ω
D.U.T.
ACTESTCONDITIONS
30pF*
510Ω
In Pulse Levels
GND to 3.0V
3ns
InputRise/FallTimes
InputTimingReferenceLevels
OutputReferenceLevels
OutputLoad
4093 drw 03
1.5V
1.5V
or equivalent circuit
See Figure 1
Figure 1. Output Load
*Includes jig and scope capacitances.
5
OCTOBER22,2008
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
When either of the two Read Enable, RENA1, RENA2 (RENB1, RENB2)
associatedwithFIFOA(B)isHIGH,theoutputregisterholdsthepreviousdata
and no new data is allowed to be loaded into the register.
When all the data has been read from FIFO A (B), the Empty Flag, EFA
(EFB) will go LOW, inhibiting further read operations. Once a valid write
operationhas beenaccomplished, EFA (EFB)willgoHIGHaftertREF anda
valid read can begin. The Read Enables, RENA1, RENA2(RENB1, RENB2)
are ignored when FIFO A (B) is empty.
SIGNALDESCRIPTIONS
FIFOAandFIFOBareidenticalineveryrespect.Thefollowingdescription
explainstheinteractionofinputandoutputsignalsforFIFOA.Thecorrespond-
ing signal names for FIFO B are provided in parentheses.
INPUTS:
Data In (DA0 – DA8, DB0 – DB8) — DA0 - DA8 are the nine data inputs
formemoryarrayA. DB0 -DB8 are the nine data inputs formemoryarrayB.
Output Enable (OEA, OEB) — When Output Enable, OEA (OEB) is
enabled(LOW),theparalleloutputbuffersofFIFOA(B)receivedatafromtheir
respective output register. When Output Enable, OEA (OEB) is disabled
(HIGH), the QA(QB)outputdata bus is ina high-impedance state.
CONTROLS:
Reset(RSA,RSB)—ResetofFIFOA(B)isaccomplishedwheneverRSA
(RSB)inputistakentoaLOWstate.Duringreset,theinternalreadandwrite
pointersassociatedwiththeFIFOaresettothefirstlocation.Aresetisrequired
after power-up before a write operation can take place. The Full Flag, FFA
(FFB)andProgrammableAlmost-FullFlag,PAFA(PAFB)willberesettoHIGH
aftertRSF. TheEmptyFlag,EFA(EFB)andProgrammableAlmost-EmptyFlag,
PAEA(PAEB)willberesettoLOWaftertRSF. Duringreset,theoutputregister
isinitializedtoallzerosandtheoffsetregistersareinitializedtotheirdefault
values.
Write Enable 2/Load (WENA2/LDA, WENB2/LDB) — This is a dual-
purposepin. FIFOA(B)isconfiguredatResettohaveprogrammableflags
ortohavetwowriteenables,whichallowsdepthexpansion. IfWENA2/LDA
(WENB2/LDB) issetHIGHatReset,RSA=LOW(RSB=LOW),thispinoperates
as a secondWrite Enable pin.
IfFIFOA(B)isconfiguredtohavetwowriteenables,whenWriteEnable
1,WENA1(WENB1)isLOWandWENA2/LDA(WENB2/LDB)isHIGH,datacan
beloadedintotheinputregisterandRAMarrayontheLOW-to-HIGHtransition
ofeveryWriteClock,WCLKA(WCLKB). Dataisstoredinthearraysequentially
and independently of any on-going read operation.
Inthisconfiguration,whenWENA1(WENB1)isHIGHand/orWENA2/LDA
(WENB2/LDB)is LOW,the inputregisterofArrayAholds the previous data
and no new data is allowed to be loaded into the register.
Topreventdataoverflow,theFullFlag,FFA(FFB)willgoLOW,inhibiting
furtherwriteoperations. Uponthecompletionofavalidreadcycle,FFA(FFB)
willgoHIGHaftertWFF,allowingavalidwritetobegin. WENA1,(WENB1)and
WENA2/LDA (WENB2/LDB)are ignoredwhenthe FIFOis full.
WriteClock(WCLKA,WCLKB)—AwritecycletoArrayA(B)isinitiated
ontheLOW-to-HIGHtransitionofWCLKA(WCLKB). Dataset-upandhold
times must be met with respect to the LOW-to-HIGH transition of WCLKA
(WCLKB). The Full Flag, FFA (FFB) and Programmable Almost-Full Flag,
PAFA(PAFB)aresynchronizedwithrespecttotheLOW-to-HIGHtransitionof
theWriteClock,WCLKA(WCLKB).
The Write and Read clock can be asynchronous or coincident.
Write Enable 1 (WENA1, WENB1) — If FIFO A (B) is configured for
programmable flags,WENA1(WENB1)is theonlyenablecontrolpin.Inthis
configuration,whenWENA1(WENB1)isLOW,datacanbeloadedintotheinput
register of RAM Array A (B) on the LOW-to-HIGH transition of every Write
Clock, WCLKA (WCLKB). Data is stored in Array A (B) sequentially and
independently of any on-going read operation.
FIFOA(B)isconfiguredtohaveprogrammableflagswhentheWENA2/
LDA(WENB2/LDB)issetLOWatReset,RSA = LOW(RSB = LOW). EachFIFO
In this configuration, when WENA1 (WENB1) is HIGH, the input register
holds the previous data and no new data is allowed to be loaded into the
register.
IftheFIFOisconfiguredtohavetwowriteenables,whichallowsfordepth
expansion. See Write Enable 2 paragraph below for operation in this
configuration.
Topreventdataoverflow,FFA(FFB)willgoLOW,inhibitingfurtherwrite
operations. Uponthecompletionofavalidreadcycle,theFFA(FFB)willgo
HIGHaftertWFF,allowingavalidwritetobegin. WENA1(WENB1)isignored
when FIFO A (B) is full.
LDA
LDB
0
WENA1
WENB1
0
WCLKA
WCLKB
OPERATION ON FIFO A
OPERATION ON FIFO B
Empty Offset (LSB)
Empty Offset (MSB)
FullOffset(LSB)
Full Offset (MSB)
0
1
1
0
1
NoOperation
WriteIntoFIFO
NoOperation
Read Clock (RCLKA, RCLKB) — Data can be read from Array A (B)
onthe LOW-to-HIGHtransitionofRCLKA(RCLKB). The EmptyFlag, EFA
(EFB)andProgrammableAlmost-EmptyFlag,PAEA(PAEB)aresynchronized
withrespecttotheLOW-to-HIGHtransitionofRCLKA(RCLKB).
1
NOTE:
4093 tbl 08
The Write and Read Clock can be asynchronous or coincident.
1. For the purposes of this table, WENA2 and WENB2 = VIH.
2. The same selection sequence applies to reading from the registers. RENA1 and RENA2
(RENB1 and RENB2) are enabled and read is performed on the LOW-to-HIGH transition
of RCLKA (RCLKB).
Read Enables (RENA1, RENA2, RENB1, RENB2) — When both Read
Enables,RENA1,RENA2(RENB1,RENB2)areLOW,dataisreadfromArray
A(B)totheoutputregisterontheLOW-to-HIGHtransitionoftheReadClock,
RCLKA (RCLKB).
Figure 2. Writing to Offset Registers for FIFOs A and B
OCTOBER22,2008
6
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
containsfour8-bitoffsetregisterswhichcanbeloadedwithdataontheinputs,
orreadontheoutputs. SeeFigure3fordetailsofthesizeoftheregistersand ortwooffsetregisters canbe writtenandthenbybringingLDA (LDB)HIGH,
thedefaultvalues. FIFOA(B)isreturnedtonormalread/writeoperation.WhenLDA(LDB)isset
However,writingalloffsetregistersdoesnothavetooccuratonetime. One
IfFIFOA(B)isconfiguredtohaveprogrammableflags,whentheWENA1 LOW, and WENA1 (WENB1) is LOW, the next offset register in sequence is
(WENB1)andWENA2/LDA(WENB2/LDB)aresetLOW,dataontheDA(DB) written.
inputsarewrittenintotheEmpty(LeastSignificantBit)Offsetregisteronthefirst
ThecontentsoftheoffsetregisterscanbereadontheQA(QB)outputswhen
LOW-to-HIGHtransitionoftheWCLKA(WCLKB). Dataarewrittenintothe WENA2/LDA (WENB2/LDB) is set LOW and both Read Enables RENA1,
Empty (Most Significant Bit) Offset register on the second LOW-to-HIGH RENA2(RENB1,RENB2)aresetLOW. DatacanbereadontheLOW-to-HIGH
transitionofWCLKA(WCLKB),intotheFull(LeastSignificantBit)Offsetregister transitionofthe ReadClockRCLKA(RCLKB).
onthethirdtransition,andintotheFull(MostSignificantBit)Offsetregisteron
A read and write should not be performed simultaneously to the offset
thefourthtransition. ThefifthtransitionofWCLKA(WCLKB)againwritestothe registers.
Empty(LeastSignificantBit)Offsetregister.
72V801 - 256 x 9 x 2
72V811 - 512 x 9 x 2
72V821 - 1,024 x 9 x 2
8
8
8
8
7
7
0
0
0
0
8
8
8
8
0
0
0
7
7
8
8
8
8
7
7
0
0
0
0
Empty Offset (LSB)
Default Value 007H
Empty Offset (LSB) Reg.
Empty Offset (LSB) Reg.
Default Value 007H
Default Value 007H
1
1
(MSB)
0
(MSB)
00
Full Offset (LSB)
Full Offset (LSB) Reg.
Default Value 007H
Full Offset (LSB) Reg.
Default Value 007H
Default Value 007H
1
0
0
1
(MSB)
0
(MSB)
00
72V831 - 2,048 x 9 x 2
72V841 - 4,096 x 9 x 2
72V851 - 8,192 x 9 x 2
8
8
8
8
7
0
0
0
0
8
8
8
8
0
0
0
0
8
8
8
8
0
0
0
0
7
7
7
7
Empty Offset (LSB)
Default Value 007H
Empty Offset (LSB)
Default Value 007H
Empty Offset (LSB) Reg.
Default Value 007H
3
4
2
(MSB)
0000
(MSB)
00000
(MSB)
000
7
Full Offset (LSB)
Full Offset (LSB)
Full Offset (LSB) Reg.
Default Value 007H
2
Default Value 007H
3
Default Value 007H
4
(MSB)
0000
(MSB)
(MSB)
000
00000
4093 drw 05
Figure 3. Offset Register Formats and Default Values for the A and B FIFOs
7
OCTOBER22,2008
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
the IDT72V831's FIFO A (B), (4,096-m) writes to the IDT72V841's FIFO A
(B), or (8,1912-m) writes to the IDT72V851's FIFO A (B).
FFA(FFB)issynchronizedwithrespecttotheLOW-to-HIGHtransitionof
theWriteClockWCLKA(WCLKB). Theoffset“m”isdefinedintheFullOffset
Registers.
IfthereisnoFulloffsetspecified,PAFA(PAFB)willgoLOWatFull-7words.
PAFA(PAFB)issynchronizedwithrespecttotheLOW-to-HIGHtransition
oftheWriteClockWCLKA(WCLKB).
OUTPUTS:
Full Flag (FFA, FFB) — FFA (FFB) will go LOW, inhibiting further write
operations, when Array A (B) is full. If no reads are performed after reset,
FFA (FFB)willgoLOWafter256writes tothe IDT72V801's FIFOA(B), 512
writestotheIDT72V811'sFIFOA(B),1,024writestotheIDT72V821'sFIFO
A (B), 2,048 writes to the IDT72V831's FIFO A (B), 4,096 writes to the
IDT72V841's FIFO A (B), or 8,192 writes to the IDT72V851's FIFO A (B).
FFA(FFB)issynchronizedwithrespecttotheLOW-to-HIGHtransitionof
theWriteClockWCLKA(WCLKB).
ProgrammableAlmost–EmptyFlag(PAEA,PAEB)—PAEA(PAEB)will
goLOWwhenthereadpointeris"n+1"locationslessthanthewritepointer.
Theoffset"n"isdefinedintheEmptyOffsetRegisters. Ifnoreadsareperformed
after reset, PAEA (PAEB) will go HIGH after "n+1" writes to FIFO A (B).
IfthereisnoEmptyoffsetspecified,PAEA(PAEB)willgoLOWatEmpty+7
words.
EmptyFlag(EFA,EFB)—EFA(EFB)willgoLOW,inhibitingfurtherread
operations,whenthereadpointerisequaltothewritepointer,indicatingthat
Array A (B) is empty.
EFA(EFB)issynchronizedwithrespecttotheLOW-to-HIGHtransitionof
the Read Clock RCLKA (RCLKB).
PAEA(PAEB)issynchronizedwithrespecttotheLOW-to-HIGHtransition
of the Read Clock RCLKA (RCLKB).
ProgrammableAlmost–FullFlag(PAFA,PAFB)—PAFA(PAFB)willgo
LOWwhentheamountofdatainArrayA(B)reachestheAlmost-Fullcondition.
Ifnoreadsareperformedafterreset,PAFA(PAFB)willgoLOWafter(256-m)
writestotheIDT72V801'sFIFOA(B),(512-m)writestotheIDT72V811'sFIFO
A (B), (1,024-m) writes to the IDT72V821's FIFO A (B), (2,048-m) writes to
Data Outputs (QA0 –QA8, QB0 –QB8 )—QA0 -QA8 are the nine data
outputsformemoryarrayA,QB0-QB8aretheninedataoutputsformemory
array B.
TABLE 1: STATUS FLAGS FOR A AND B FIFOS
NUMBER OF WORDS IN ARRAY A
FFA
FFB
PAFA
PAFB
PAEA
PAEB
EFA
EFB
NUMBER OF WORDS IN ARRAY B
IDT72V801
IDT72V811
0
1 to n(1)
IDT72V821
0
1 to n(1)
0
1 to n(1)
H
H
H
H
L
H
H
H
L
L
L
L
H
H
H
H
(n+1)to(256-(m+1))
(256-m)(2) to255
256
(n+1)to(512-(m+1))
(512-m)(2) to511
512
(n+1)to(1,024-(m+1))
(1,024-m)(2) to1,023
1,024
H
H
H
L
NUMBER OF WORDS IN ARRAY A
FFA
FFB
PAFA
PAFB
PAEA
PAEB
EFA
EFB
NUMBER OF WORDS IN ARRAY B
IDT72V831
0
1 to n(1)
IDT72V841
0
1 to n(1)
IDT72V851
0
1 to n(1)
H
H
H
H
L
H
H
H
L
L
L
L
H
H
H
H
(n+1)to(2,048-(m+1))
(2,048-m)(2) to2,047
2,048
(n+1)to(4,096-(m+1))
(4,096-m)(2) to4,095
4,096
(n+1)to(8,192-(m+1))
(8,192-m)(2) to8,191
8,192
H
H
H
L
NOTES:
1. n = Empty Offset (n = 7 default value)
2. m = Full Offset (m = 7 default value)
OCTOBER22,2008
8
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tRS
RSA (RSB)
t
RSS
tRSR
tRSR
tRSR
RENA1, RENA2
(RENB1, RENB2)
t
RSS
WENA1
(WENB1)
tRSS
WENA2/LDA(1)
(WENB2/LDB)
t
t
RSF
RSF
EFA, PAEA
(EFB, PAEB)
FFA, PAFA
(FFA, PAFA)
t
RSF
OEA (OEB) = 1(2)
OEA (OEB) = 0
QA
0
- QA
8
(QB
0
- QB8)
4093 drw 06
NOTES:
1. Holding WENA2/LDA (WENB2/LDB) HIGH during reset will make the pin act as a second Write Enable pin. Holding WENA2/LDA (WENB2/LDB) LOW during reset will make
the pin act as a load enable for the programmable flag offset registers.
2. After reset, QA0 - QA8 (QB0 - QB8) will be LOW if OEA (OEB) = 0 and tri-state if OEA (OEB) = 1.
3. The clocks RCLKA, WCLKA (RCLKB, WCLKB) can be free-running during reset.
Figure 4. Reset Timing
tCLK
tCLKH
tCLKL
WCLKA (WCLKB)
tDH
tDS
(DA
0
- DA
8
DB
0
- DB
8)
DATA IN VALID
tENH
tENS
WENA1
NO OPERATION
NO OPERATION
(WENB1)
tENH
tENS
WENA2 (WENB2)
(If Applicable)
t
WFF
tWFF
FFA
(FFB)
(1)
SKEW1
t
RCLKA (RCLKB)
RENA1, RENA2
(RENB1, RENB2)
4093 drw 07
NOTE:
1. tSKEW1 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for FFA (FFB) to change during the current clock cycle. If the time
between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then FFA (FFB) may not change state until the next WCLKA (WCLKB)
edge.
Figure 5. Write Cycle Timing
9
OCTOBER22,2008
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tCLK
tCLKH
tCLKL
RCLKA (RCLKB)
tENH
tENS
RENA1, RENA2
(RENB1, RENB2)
NO OPERATION
t
REF
t
REF
EFA (EFB)
tA
QA
0
0
- QA
8
VALID DATA
(QB
- QB8)
tOLZ
tOHZ
tOE
OEA (OEB)
(1)
SKEW1
t
WCLKA, WCLKB
WENA1 (WENB1)
WENA2 (WENB2)
4093 drw 08
NOTE:
1. tSKEW1 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for EFA (EFB) to change during the current clock cycle. If the time
between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW1, then EFA (EFB) may not change state until the next RCLKA (RCLKB)
edge.
Figure 6. Read Cycle Timing
WCLKA
(WCLKB)
tDS
DA
0
- DA
8
D1
D2
D3
(DB
0
- DB8)
tENS
D0 (First Valid
WENA1
(WENB1)
tENS
WENA2 (WENB2)
(If Applicable)
(1)
tFRL
tSKEW1
RCLKA
(RCLKB)
t
REF
EFA (EFB)
tENS
RENA1, RENA2
(RENB1, RENB2)
tA
tA
QA
0
- QA
8
D0
D1
(QB
0
- QB8)
tOLZ
tOE
OEA (OEB)
4093 drw 09
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).
Figure 7. First Data Word Latency Timing
OCTOBER22,2008
10
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
NO WRITE
NO WRITE
NO WRITE
WCLKA
(WCLKB)
tSKEW1
tSKEW1
tDS
tDH
DA
0
- DA
8
(DB0
- DB8)
t
WFF
tWFF
t
WFF
FFA (FFB)
(1)
ENS
t
t
ENS
ENS
t
ENH
WENA1
(WENB1)
(1)
ENS
t
t
ENH
t
WENA2
(WENB2)
(If Applicable)
RCLKA
(RCLKB)
tENH
tENH
tENS
tENS
RENA1
(RENB2)
tA
LOW
OEA
(OEB)
tA
QA
0
- QA
8
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
(QB
0
- QB8)
4093 drw 10
NOTE:
1. Only one of the two Write Enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.
Figure 8. Full Flag Timing
WCLKA (WCLKB)
tDS
tDS
DA
0
- DA
8
DATA WRITE 1
DATA WRITE 2
(DB
0
- DB8)
tENS
tENH
tENS
tENH
WENA1, (WENB1)
tENS
tENS
tENH
tENH
WENA2 (WENB2)
(If Applicable)
(1)
FRL
(1)
FRL
t
t
tSKEW1
tSKEW1
RCLKA (RLCKB)
tREF
tREF
tREF
EFA (EFB)
RENA1, RENA2
(RENB1, RENB2)
LOW
OEA (OEB)
tA
QA
0
- QA
8
DATA READ
DATA IN OUTPUT REGISTER
(QB
0
- QB8)
4093 drw 11
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL maximum = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).
Figure 9. Empty Flag Timing
11
OCTOBER22,2008
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tCLKH
tCLKL
(4)
WCLKA
(WCLKB)
tENH
tENS
WENA1
(WENB1
tENS
tENH
WENA2
(WENB2)
(If Applicable)
t
PAF
Full - (m+1) words in FIFO (1)
(2)
PAFA
(PAFB)
Full - m words in FIFO
(3)
SKEW2
t
t
PAF
RCLKA
(RCLKB)
tENS
tENH
RENA1, RENA2
(RENB1, RENB2)
4093 drw 12
NOTES:
1. m = PAF offset.
2. (256-m) words for the IDT72V801, (512-m) words the IDT72V811, (1,024-m) words for the IDT72V821, (2,048-m) words for the IDT72V831, (4,096-m) words for the IDT72V841,
or (8,192-m) words for the IDT72V851.
3. tSKEW2 is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for PAFA (PAFB) to change during that clock cycle. If the time between
the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than tSKEW2, then PAFA (PAFB) may not change state until the next WCLKA (WCLKB)
rising edge.
4. If a write is performed on this rising edge of the Write Clock, there will be Full - (m-1) words in FIFO A (B) when PAFA (PAFB) goes LOW.
Figure 10. Programmable Full Flag Timing
tCLKH
tCLKL
WCLKA
(WCLKB)
tENH
tENS
WENA1
(WENB1)
tENS
tENH
WENA2
(WENB2)
(If Applicable)
n words in FIFO(1)
PAEA,
PAEB
n+1 words in FIFO
(2)
tSKEW2
t
PAE
t
PAE
(3)
RCLKA
(RCLKB)
tENS
tENH
RENA1, RENA2
(RENB1, RENB2)
4093 drw 13
NOTES:
1. n = PAE offset.
2. tSKEW2 is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for PAEA (PAEB) to change during that clock cycle. If the time between
the rising edge of WCLKA (WCLKB) and the rising edge of RCLKA (RCLKB) is less than tSKEW2, then PAEA (PAEB) may not change state until the next RCLKA (RCLKB)
rising edge.
3. If a read is performed on this rising edge of the Read Clock, there will be Empty + (n-1) words in FIFO A (B) when PAEA (PAEB) goes LOW.
Figure 11. Programmable Empty Flag Timing
OCTOBER22,2008
12
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
tCLK
tCLKH
tCLKL
WCLKA (WCLKB)
tENH
tENS
LDA (LDB)
tENS
WENA1 (WENB1)
tDS
tDH
DA
0
- DA
7
(DB
0
- DB7)
PAE OFFSET
(LSB)
PAE OFFSET
(MSB)
PAF OFFSET
(LSB)
PAF OFFSET
(MSB)
4093 drw 14
Figure 12. Write Offset Register Timing
tCLK
tCLKH
tCLKL
RCLKA (RCLKB)
tENS
tENH
LDA (LDB)
tENS
RENA1, RENA2
(RENB1, RENB2)
tA
QA
0
- QA
7
DATA IN OUTPUT REGISTER
(QB
0
- QB7)
EMPTY OFFSET
(LSB)
EMPTY OFFSET
(MSB)
FULL OFFSET
(LSB)
FULL OFFSET
(MSB)
4093 drw 15
Figure 13. Read Offset Register Timing
13
OCTOBER22,2008
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
begrounded(seeFigure14). Inthisconfiguration,theWriteEnable2/Load
WENA2/LDA(WENB2/LDB)pinissetLOWatResetsothatthepinoperates
as acontroltoloadandreadtheprogrammableflagoffsets.
OPERATINGCONFIGURATIONS
SINGLEDEVICECONFIGURATION— WhenFIFOA(B)is inaSingle
DeviceConfiguration,theReadEnable2RENA2(RENB2)controlinputcan
RSA (RSB)
WCLKA (WCLKB)
RCLKA (RCLKB)
IDT
72V801
WENA1 (WENB1)
RENA1 (RENB1)
OEA (OEB)
72V811
72V821
72V831
72V841
72V851
WENA2/LDA (WENB2/LDB)
DA - DA (DB - DB
FFA (FFB)
PAFA (PAFB)
QA
EFA (EFB)
PAEA (PAEB)
0 - QA8 (QB0 - QB8)
0
8
0
8)
FIFO
A (B)
RENA2 (RENB2)
4093 drw 16
Figure 14. Block Diagram of One of the IDT72V801/72V811/72V821/72V831/72V841/72V851's
two FIFOs configured as a single device
WIDTH EXPANSION CONFIGURATION — Word width may be in- be attained by adding additional IDT72V801/72V811/72V821/72V831/
creased simply by connecting the corresponding input control signals of 72V841/72V851s.
FIFOs A and B. A composite flag should be created for each of the end-
When these devices are in a Width Expansion Configuration, the Read
pointstatusflagsEFAandEFB,alsoFFAandFFB). ThepartialstatusflagsPAEA, Enable 2 (RENA2 and RENB2) control inputs can be grounded (see Figure
PAFB, PAEA and PAFB can be detected from any one device. Figure 15 15). Inthisconfiguration,theWriteEnable2/Load(WENA2/LDA,WENB2/LDB)
demonstrates an 18-bit word width using the two FIFOs contained in one pinsaresetLOWatResetsothatthepinoperatesasacontroltoloadandread
IDT72V801/72V811/72V821/72V831/72V841/72V851. Anywordwidthcan theprogrammableflagoffsets.
9
RESET
DB0 - DB8
RCLKA
RSB
RSA
EFA
EFB
EMPTY FLAG
READ CLOCK
DATA IN
18
DA0 - DA8
9
RAM
ARRAY
A
RAM
ARRAY RCLKB
B
WRITE CLOCK
WCLKB
RENA1
WENB1
OEA1
WCLKA
RENB1
READ ENABLE
256x9
512x9
1,024x9
2,048x9
4,096x9
8,192x9
256x9
512x9
WENA1
WRITE ENABLE
OEB
OUTPUT ENABLE
1,024x9
WENA2/LDA
WRITE ENABLE/LOAD
2,048x9 2WENB2/LDB
4,096x9
8,192x9
FFA
FFB
DATA OUT
18
QB0 - QB8
9
FULL FLAG
RENA2
QA0 - QA8 RENB2
4093 drw 17
9
Figure 15. Block diagram of the two FIFOs contained in one IDT72V801/72V811/72V821/72V831/72V841/72V851
configured for an 18-bit width-expansion
OCTOBER22,2008
14
IDT72V801/72V8211/72V821/72V831/72V841/72V851 3.3V DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
theintermixeddataaccordingtotype,sendingonekindtoFIFOAandtheother
kind to FIFO B. Then, at the outputs, each data type is transferred to its
appropriate destination. Additional IDT72V801/72V811/72V821/72V831/
72V841/72V851s permit more than two priority levels. Priority buffering is
particularly useful in network applications.
TWO PRIORITY DATA BUFFER
CONFIGURATION
The two FIFOs contained in the IDT72V801/72V811/72V821/72V831/
72V841/72V851 can be used to prioritize two different types of data shared
on a system bus. When writing from the bus to the FIFO, control logic sorts
Image
Processing
Card
RAM ARRAY A
RCLKA
Clock
Data
WCLKA
OEA
WENA1
RENA
Address
Control
9
DA0-D
A8QA0-QA8
9
I/O Data
RENA2
V
CC
WENA2
Processor
Clock
IDT
72V801
72V811
72V821
72V831
72V841
72V851
Address
Control
Data
Voice
RAM ARRAY B
9
9
Processing
Card
RCLKB
WCLKB
Clock
Data
WENB1
OEB2
RAM
RENB1
Address
Control
B8 QB0-QB8
D
B0-D
I/O Data
9
WENB2 RENB2
9
4093 drw 18
VCC
Figure 16. Block Diagram of Two Priority Configuration
follows,aprocessorcanwritedatatoaperipheralcontrollerviaFIFOA,and,
in turn, the peripheral controller can write the processor via FIFO B.
BIDIRECTIONALCONFIGURATION
The two FIFOs of the IDT72V801/72V811/72V821/72V831/72V841/
72V851canbeusedtobufferdataflowintwodirections.Intheexamplethat
RAM ARRAY A
VCC
RENA2
WENA2
RCLKA
WCLKA
OEA
WENA1
RENA1
Peripheral
Controller
DA0-DA8
QA0-QA8
9
9
Processor
Clock
DMA Clock
IDT
72V801
72V811
72V821
72V831
72V841
72V851
Address
Control
Address
Control
I/O Data
Data
Data
RAM ARRAY B
9
9
RCLKB
WENB1
RENB1
RAM
9
OEB
QB0-QB8
DB0-DB8
RENB2
WCLKB
9
9
WENB2
4093 drw 19
VCC
Figure 17. Block Diagram of Bidirectional Configuration
15
OCTOBER22,2008
DEPTHEXPANSION—TheseFIFOscanbeadaptedtoapplicationsthat TheIDT72V801/72V811/72V821/72V831/72V841/72V851operates inthe
require greater than 256/512/1,024/2,048/4,096/8,192 words. The exist- DepthExpansionconfigurationwhenthefollowingconditionsaremet:
enceofdoubleenablepinsonthereadandwriteportsallowdepthexpansion.
TheWriteEnable2/Load(WENA2,WENB2)pinsareusedasasecondwrite thesepinsoperateassecondWriteEnables.
1. WENA2/LDAandWENB2/LDBpinsareheldHIGHduring Resetsothat
enablesinadepthexpansionconfiguration,thustheProgrammableflagsare
settothe defaultvalues. Depthexpansionis possible byusingone enable
2. External logic is used to control the flow of data.
Please see the Application Note "DEPTH EXPANSION OF IDT'S SYN-
inputforsystemcontrolwhiletheotherenableinputiscontrolledbyexpansion CHRONOUS FIFOs USING THE RING COUNTER APPROACH" for
logictodirecttheflowofdata. Atypicalapplicationwouldhavetheexpansion details of this configuration.
logicalternatedataaccessfromonedevicetothenextinasequentialmanner.
ORDERING INFORMATION
XXXXX
X
XX
XX
X
X
Device Type
Power
Speed
Package
Process/
Temperature
Range
Commercial (0°C to +70°C)
Industrial (-40°C to +85°C)
BLANK
I(1)
G(2)
Green
Thin Quad Flatpack (TQFP, PN64-1)
Slim Thin Plastic Quad Flatpack (STQFP, PP64-1)
PF
TF
10
15
20
Commercial Only
Commercial And Industrial
Commercial Only
Clock Cycle Time
(tCLK), speed in
Nanoseconds
L
Low Power
72V801
72V811
72V821
72V831
72V841
72V851
256 x 9 ⎯ 3.3 Volt DUAL SyncFIFO
512 x 9 ⎯ 3.3 Volt DUAL SyncFIFO
1,024 x 9 ⎯ 3.3 Volt DUAL SyncFIFO
2,048 x 9 ⎯ 3.3 Volt DUAL SyncFIFO
4,096 x 9 ⎯ 3.3 Volt DUAL SyncFIFO
8,192 x 9 ⎯ 3.3 Volt DUAL SyncFIFO
4093 drw 20
NOTES:
1. Industrial temperature range product for the 15ns speed grade is available as a standard device.
2. Green parts available. For specific speeds and packages contact your local sales office.
DATASHEETDOCUMENTHISTORY
04/24/2001
02/02/2006
10/22/2008
pgs. 4, 5 and 16
pgs. 1 and 16.
pg. 16.
CORPORATE HEADQUARTERS
6024 Silver Creek Valley Road
San Jose, CA 95138
for SALES:
for Tech Support:
408-360-1753
email:FIFOhelp@idt.com
800-345-7015 or 408-284-8200
fax: 408-284-2775
www.idt.com
16
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