74ALVC162334PAG8 [IDT]
3.3V CMOS 16-BIT UNIVERSAL BUS DRIVER;
| 型号： | 74ALVC162334PAG8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3V CMOS 16-BIT UNIVERSAL BUS DRIVER 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总6页 (文件大小：92K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS 16-BIT
UNIVERSAL BUS
DRIVER WITH
IDT74ALVC162334
3-STATE OUTPUTS
DESCRIPTION:
FEATURES:
This16-bituniversalbusdriverisbuiltusingadvanceddualmetalCMOS
technology. Data flow from A to Y is controlled by the output-enable (OE)
input. Thedeviceoperatesinthetransparentmodewhenthelatch-enable
(LE) input is low. When LE is high, the A data is latched if the clock (CLK)
input is held at a high or low logic level. If LE is high, the A data is stored
inthelatch/flip-floponthelow-to-hightransitionofCLK. When OEishigh,
the outputs are in the high-impedance state.
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
The ALVC162334 has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driver has been designed to drive ±12mA at the designated threshold
levels.
• CMOS power levels (0.4μ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP package
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA
• Low Switching Noise
APPLICATIONS:
• SDRAM Modules
• PC Motherboards
• Workstations
FUNCTIONALBLOCKDIAGRAM
1
OE
48
CLK
25
LE
47
A1
1
D
2
Y1
C
1
CLK
TO 15 OTHER CHANNELS
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
JUNE 2016
1
© 2016 Integrated Device Technology, Inc.
DSC-4687/7
IDT74ALVC162334
3.3VCMOS16-BITUNIVERSALBUSDRIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
Description
Max
Unit
V
(2)
VTERM
VTERM
TSTG
IOUT
Terminal Voltage with Respect to GND
–0.5 to +4.6
OE
Y1
1
(3)
CLK
A1
48
47
46
45
44
43
42
41
40
39
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
Storage Temperature
DC Output Current
–65 to +150
–50 to +50
±50
°C
mA
mA
2
Y2
3
A2
IIK
Continuous Clamp Current,
VI < 0 or VI > VCC
4
GND
GND
IOK
Continuous Clamp Current, VO < 0
–50
mA
mA
Y3
Y4
5
A3
A4
ICC
ISS
Continuous Current through each
VCC or GND
±100
6
NOTES:
7
VCC
VCC
A5
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
8
Y5
Y6
9
A6
2. VCC terminals.
3. All terminals except VCC.
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
GND
A7
Y7
Y8
38
37
36
35
34
33
32
31
30
29
28
27
26
CAPACITANCE (TA = +25°C, F = 1.0MHz)
A8
Symbol
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
Y9
A9
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
5
7
7
7
9
9
pF
pF
pF
Y10
A10
GND
A11
A12
VCC
COUT
GND
COUT
NOTE:
Y11
Y12
VCC
Y13
Y14
1. As applicable to the device type.
A13
A14
GND
A15
A16
LE
FUNCTIONTABLE(1)
Inputs
Outputs
GND
OE
H
L
LE
X
CLK
X
Ax
X
Yx
Z
Y15
Y16
NC
L
X
L
L
L
L
X
H
L
H
L
25
L
H
H
↑
L
↑
H
H
TSSOP
TOP VIEW
(2)
L
H
L or H
X
Y0
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑ = LOW-to-HIGH transition
PINDESCRIPTION
Pin Names
Description
OE
CLK
LE
3-State Output Enable Inputs (Active LOW)
Register Input Clock
2. Output level before the indicated steady-state input conditions were established.
Latch Enable (Active LOW)
Data Inputs
A x
Y x
3-State Outputs
2
IDT74ALVC162334
INDUSTRIALTEMPERATURERANGE
3.3VCMOS16-BITUNIVERSALBUSDRIVERWITH3-STATEOUTPUTS
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
Input HIGH Current
VCC = 3.6V
VCC = 3.6V
VCC = 3.6V
VI = VCC
—
—
—
—
—
—
—
5
5
μA
μA
μA
Input LOW Current
VI = GND
VO = VCC
VO = GND
IOZH
IOZL
VIK
VH
High Impedance Output Current
(3-State Output pins)
—
10
—
10
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
VCC = 3.3V
–0.7
–1.2
V
Input Hysteresis
—
—
100
0.1
—
40
mV
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
μA
ΔICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
750
μA
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
VCC = 2.3V to 3.6V
Min.
Max.
—
Unit
V
VOH
Output HIGH Voltage
IOH = – 0.1mA
IOH = – 4mA
IOH = – 6mA
IOH = – 4mA
IOH = – 8mA
IOH = – 6mA
IOH = – 12mA
IOL = 0.1mA
IOL = 4mA
VCC – 0.2
VCC = 2.3V
VCC = 2.7V
VCC = 3V
1.9
1.7
2.2
2
—
—
—
—
2.4
2
—
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
—
—
—
—
—
—
0.2
0.4
0.55
0.4
0.6
0.55
0.8
V
IOL = 6mA
VCC = 2.7V
VCC = 3V
IOL = 4mA
IOL = 8mA
IOL = 6mA
IOL = 12mA
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
3
IDT74ALVC162334
3.3VCMOS16-BITUNIVERSALBUSDRIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Symbol
CPD
Parameter
Test Conditions
Typical
Typical
36
Unit
PowerDissipationCapacitanceOutputsenabled
PowerDissipationCapacitanceOutputsdisabled
CL = 0pF, f = 10Mhz
31
7
pF
CPD
11
SWITCHINGCHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tW
Parameter
Min.
150
1
Max.
—
Min.
150
—
Max.
—
Min.
150
1.1
Max.
—
Unit
MHz
ns
PropagationDelay
4.4
4.5
3.6
Ax to Yx
PropagationDelay
1
1
1
1
5.8
5.2
6.4
4.7
—
—
—
—
6
1.3
1
5
4.9
5.4
5
ns
ns
ns
ns
LE to Yx
PropagationDelay
5.4
6.4
5.1
CLK toYx
OutputEnableTime
1.1
1.7
OE to Yx
OutputDisableTime
OE to Yx
Pulse Duration, LE LOW
Pulse Duration, CLK HIGH or LOW
Set-upTime,databeforeCLK↑
Set-up Time, data before LE↑, CLK HIGH
Set-up Time, data before LE↑, CLKLOW
HoldTime,dataafterCLK↑
Hold Time, data after LE↑, CLK HIGH or LOW
OutputSkew(2)
3.3
3.3
1.4
1.2
1.4
0.9
1.1
—
—
—
—
—
—
—
—
—
3.3
3.3
1.7
1.6
1.5
0.9
1.1
—
—
—
—
—
—
—
—
—
3.3
3.3
1.5
1.3
1.2
0.9
1.1
—
—
—
—
—
—
—
—
500
ns
ns
ns
ns
ns
ns
ns
ps
tW
tSU
tSU
tSU
tH
tH
tSK(O)
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74ALVC162334
INDUSTRIALTEMPERATURERANGE
3.3VCMOS16-BITUNIVERSALBUSDRIVERWITH3-STATEOUTPUTS
TESTCIRCUITSANDWAVEFORMS
TESTCONDITIONS
V
V
0V
IH
T
SAME PHASE
INPUT TRANSITION
t
PHL
t
PLH
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V
Unit
V
V
V
V
OH
OUTPUT
T
VLOAD
VIH
6
6
2 x Vcc
Vcc
OL
t
PHL
tPLH
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
V
V
IH
T
OPPOSITE PHASE
INPUT TRANSITION
VT
Vcc / 2
150
V
VLZ
VHZ
CL
mV
mV
pF
0V
ALVC Link
150
30
Propagation Delay
V
LOAD
VCC
Open
GND
DISABLE
ENABLE
V
V
IH
T
500Ω
CONTROL
INPUT
VIN
VOUT
Pulse(1, 2)
Generator
0V
D.U.T.
tPZL
tPLZ
V
LOAD/2
V
LOAD/2
OUTPUT
NORMALLY
LOW
500Ω
SWITCH
CLOSED
VT
RT
V
V
OL + VLZ
OL
CL
t
PHZ
tPZH
OUTPUT
NORMALLY
HIGH
ALVC Link
V
OH
SWITCH
OPEN
V
0V
T
VOH -
VHZ
Test Circuit for All Outputs
0V
DEFINITIONS:
ALVC Link
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
V
IH
T
DATA
INPUT
V
0V
t
SU
t
H
SWITCHPOSITION
V
IH
V
TIMING
INPUT
Test
Switch
VLOAD
GND
T
0V
Open Drain
Disable Low
Enable Low
t
REM
V
IH
V
ASYNCHRONOUS
CONTROL
T
0V
V
IH
V
Disable High
Enable High
SYNCHRONOUS
CONTROL
T
t
SU
0V
t
H
All Other Tests
Open
ALVC Link
Set-up, Hold, and Release Times
V
V
IH
T
INPUT
0V
tPLH1
tPHL1
LOW-HIGH-LOW
V
V
V
OH
V
T
PULSE
T
OUTPUT 1
OL
tW
tSK (x)
tSK (x)
V
V
V
OH
HIGH-LOW-HIGH
PULSE
V
T
T
ALVC Link
OUTPUT 2
OL
tPLH2
tPHL2
Pulse Width
tSK(x) = tPLH2
-
tPLH1 or
t
PHL2
-
t
PHL1
ALVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74ALVC162334
3.3VCMOS16-BITUNIVERSALBUSDRIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
X
XX
ALVC
Bus-Hold Family
XXX
XX
X
XX
Device Type Package
Temp. Range
Blank
8
Tube
Tape and Reel
PAG
334
162
Thin Shrink Small Outline Package - Green
16-Bit Universal Bus Driver with 3-State Outputs
Double-Density with Resistors, 12mA
Blank No Bus-Hold
74 – 40°C to +85°C
DATASHEETDOCUMENTHISTORY
06/15/2016
Pg.
6
Updated the ordering information by adding Tape and Reel.
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6
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