74ALVCH162721PA [IDT]
TSSOP-56, Tube;
| 型号： | 74ALVCH162721PA |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | TSSOP-56, Tube 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总6页 (文件大小：66K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
IDT74ALVCH162721
3.3V CMOS 20-BIT
FLIP-FLOP WITH 3-STATE
OUTPUTS AND BUS-HOLD
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
This20-bitflip-flopisbuiltusingadvanceddualmetalCMOStechnology.The
20 flip-flops of the ALVCH162721 are edge-triggered D-type flip-flops with
qualifiedclockstorage.Onthepositivetransitionoftheclock(CLK)input,the
deviceprovidestruedataattheQoutputsiftheclock-enable(CLKEN)inputis
low. If CLKEN is high, no data is stored.
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4µ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP package
Abufferedoutput-enable(OE)inputplacesthe20outputsineitheranormal
logicstate(highorlow)orahigh-impedancestate.Inthehigh-impedancestate,
theoutputsneitherloadnordrivethebuslinessignificantly.Thehigh-impedance
stateandincreaseddriveprovidethecapabilitytodrivebuslineswithoutneed
forinterfaceorpullupcomponents.OEdoesnotaffecttheinternaloperationof
the flip-flops. Old data can be retained or new data can be entered while the
outputsareinthehigh-impedancestate.
TheALVCH162721hasseriesresistorsinthedeviceoutputstructurewhich
will significantly reduce line noise when used with light loads. This driver has
beendesignedtodrive±12mAatthedesignatedthresholdlevels.
The ALVCH162721 has “bus-hold” which retains the inputs’ last state
whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputsand
eliminatestheneedforpull-up/downresistor.
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA
• Low switching noise
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONALBLOCKDIAGRAM
1
OE
56
CLK
29
CLKEN
CE
C1
1D
2
Q1
55
D1
To 19 Other Channels
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
JANUARY 2004
1
© 2004 Integrated Device Technology, Inc.
DSC-4566/2
IDT74ALVCH162721
3.3VCMOS20-BITFLIP-FLOPWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
Description
Max
Unit
V
(2)
VTERM
Terminal Voltage with Respect to GND
–0.5 to +4.6
1
2
3
4
OE
Q1
56
55
54
53
52
51
CLK
D1
(3)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
TSTG
IOUT
IIK
Storage Temperature
DC Output Current
–65 to +150
–50 to +50
±50
°C
mA
mA
Q2
D2
GND
Continuous Clamp Current,
VI < 0 or VI > VCC
GND
D3
5
6
Q3
Q4
IOK
Continuous Clamp Current, VO < 0
–50
mA
mA
D4
ICC
ISS
Continuous Current through each
VCC or GND
±100
VCC
7
VCC
D5
50
49
8
Q5
Q6
Q7
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
9
48
D6
10
D7
47
46
45
11
12
13
14
15
16
17
18
GND
Q8
GND
D8
2. VCC terminals.
3. All terminals except VCC.
Q9
Q10
Q11
Q12
44
D9
43
42
D10
D11
D12
D13
GND
D14
D15
D16
VCC
D17
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
41
40
39
38
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
5
7
7
7
9
9
pF
pF
pF
Q13
GND
Q14
COUT
CI/O
19
20
21
22
23
24
25
26
27
NOTE:
1. As applicable to the device type.
Q15
37
36
35
Q16
VCC
Q17
PINDESCRIPTION
Pin Names
Description
34
33
32
OE
3–StateOutputEnableInput(ActiveLOW)
DataInputs(1)
Q18
D18
Dx
GND
GND
Qx
3-StateOutputs
Q19
Q20
NC
31
30
29
D19
CLK
ClockInput
D20
CLKEN
N C
Clock Enable Input (Active LOW)
NoInternalConnection
28
CLKEN
NOTE:
TSSOP
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
TOP VIEW
(1)
FUNCTION TABLE (EACH FLIP-FLOP)
Inputs
Output
Qx
OE
L
CLKEN
CLK
Dx
X
(2)
H
L
L
L
X
X
↑
↑
Q0
L
H
L
H
L
L
(2)
L
L or H
X
Q0
H
X
X
Z
NOTES:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High Impedance
↑ = LOW-to-HIGH transition
2. Output level before the indicated steady-state input conditions were established.
2
IDT74ALVCH162721
INDUSTRIALTEMPERATURERANGE
3.3VCMOS20-BITFLIP-FLOPWITH3-STATEOUTPUTS
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
Operating Condition: TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
Input HIGH Current
VCC = 3.6V
VCC = 3.6V
VCC = 3.6V
VI = VCC
—
—
—
—
—
—
—
±5
±5
µA
µA
µA
Input LOW Current
VI = GND
VO = VCC
VO = GND
IOZH
IOZL
VIK
VH
High Impedance Output Current
(3-State Output pins)
—
±10
±10
–1.2
—
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
VCC = 3.3V
–0.7
V
Input Hysteresis
—
—
100
0.1
—
40
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
∆ICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
750
µA
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLDCHARACTERISTICS
Symbol
IBHH
Parameter(1)
Test Conditions
VI = 2V
Min.
–75
75
Typ.(2)
—
Max.
—
Unit
Bus-HoldInputSustainCurrent
VCC = 3V
µA
IBHL
VI = 0.8V
—
—
IBHH
Bus-HoldInputSustainCurrent
Bus-Hold Input Overdrive Current
VCC = 2.3V
VCC = 3.6V
VI = 1.7V
–45
45
—
—
µA
µA
IBHL
VI = 0.7V
—
—
IBHHO
VI = 0 to 3.6V
—
—
±500
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3
IDT74ALVCH162721
3.3VCMOS20-BITFLIP-FLOPWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
Max.
—
Unit
VOH
Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 4mA
IOH = – 6mA
IOH = – 4mA
IOH = – 8mA
IOH = – 6mA
IOH = – 12mA
IOL = 0.1mA
IOL = 4mA
VCC – 0.2
V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
1.9
1.7
2.2
2
—
—
—
—
2.4
2
—
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
—
—
—
—
—
—
0.2
0.4
0.55
0.4
0.6
0.55
0.8
V
IOL = 6mA
VCC = 2.7V
VCC = 3V
IOL = 4mA
IOL = 8mA
IOL = 6mA
IOL = 12mA
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Symbol
CPD
Parameter
Test Conditions
Typical
55
Typical
59
Unit
PowerDissipationCapacitanceOutputsenabled
PowerDissipationCapacitanceOutputsdisabled
CL = 0pF, f = 10Mhz
pF
CPD
46
49
SWITCHINGCHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
fMAX
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tSU
Parameter
Min.
150
1
Max.
—
Min.
150
—
Max.
Min.
150
1
Max.
—
Unit
—
MHz
ns
PropagationDelay
6.7
6.2
5.3
CLK to Qx
OutputEnableTime
1
1
7.2
6.3
—
—
7
1
1
5.8
5
ns
ns
OE to Qx
OutputDisableTime
OE to Qx
5.4
Set-upTime,databeforeCLK↑
Set-upTime, CLKEN beforeCLK↑
HoldTime,dataafterCLK↑
Hold Time, CLKEN after CLK↑
Pulse Width, CLK HIGH or LOW
OutputSkew(2)
4
3.4
0
—
—
—
—
—
—
3.6
3.1
0
—
—
—
—
—
—
3.1
2.7
0
—
—
ns
ns
ns
ns
ns
ps
tSU
tH
—
tH
0
0
0
—
tW
3.3
—
3.3
—
3.3
—
—
tSK(O)
500
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74ALVCH162721
INDUSTRIALTEMPERATURERANGE
3.3VCMOS20-BITFLIP-FLOPWITH3-STATEOUTPUTS
TESTCIRCUITSANDWAVEFORMS
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
TESTCONDITIONS
tPHL
tPHL
tPLH
tPLH
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V
Unit
V
VOH
VT
VOL
OUTPUT
VLOAD
VIH
6
6
2 x Vcc
Vcc
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
VIH
VT
0V
VT
Vcc / 2
150
V
OPPOSITE PHASE
INPUT TRANSITION
VLZ
VHZ
CL
mV
mV
pF
150
ALVC Link
30
Propagation Delay
VLOAD
Open
GND
DISABLE
VCC
ENABLE
VIH
VT
CONTROL
INPUT
500Ω
0V
tPZL
tPLZ
VIN
VOUT
(1, 2)
Pulse
VLOAD/2
D.U.T.
VLOAD/2
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
Generator
VT
VLZ
VOL
500Ω
tPHZ
tPZH
RT
CL
OUTPUT
NORMALLY
HIGH
VOH
VHZ
SWITCH
OPEN
VT
0V
ALVC Link
0V
Test Circuit for All Outputs
ALVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
VIH
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
DATA
INPUT
VT
0V
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
tSU
tH
VIH
VT
0V
VIH
VT
0V
VIH
VT
0V
TIMING
INPUT
SWITCHPOSITION
Test
Switch
VLOAD
GND
tREM
ASYNCHRONOUS
CONTROL
Open Drain
Disable Low
Enable Low
SYNCHRONOUS
CONTROL
Disable High
Enable High
tSU
tH
ALVC Link
All Other Tests
Open
VIH
Set-up, Hold, and Release Times
VT
INPUT
0V
tPLH1
tPHL1
VOH
VT
VOL
LOW-HIGH-LOW
VT
PULSE
OUTPUT 1
OUTPUT 2
tSK (x)
tSK (x)
tW
VOH
VT
VOL
HIGH-LOW-HIGH
PULSE
VT
ALVC Link
tPLH2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHL2
Pulse Width
ALVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74ALVCH162721
3.3VCMOS20-BITFLIP-FLOPWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT
Temp. Range
XXX
XX
ALVC
X
XXX
XX
Device Type Package
Bus-Hold Family
Thin Shrink Small Outline Package
20-Bit Flip-Flop with 3-State Outputs
PA
721
162 Double-Density with Resistors, ±12mA
H
Bus-Hold
74
–40°C to +85°C
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(408) 654-6459
www.idt.com
6
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