74ALVCH16501PAG8 [IDT]
TSSOP-56, Reel;型号: | 74ALVCH16501PAG8 |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | TSSOP-56, Reel |
文件: | 总7页 (文件大小:79K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
3.3V CMOS 18-BIT UNIVERSAL IDT74ALVCH16501
BUS TRANSCEIVER WITH
3-STATE OUTPUTS
AND BUS-HOLD
FEATURES:
DESCRIPTION:
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
This 18-bit universal bus transceiver is built using advanced dual metal
CMOStechnology.Dataflowineachdirectioniscontrolledbyoutput-enable
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
• CMOS power levels (0.4μ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in SSOP and TSSOP packages
(OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CLKAB and
CLKBA)inputs. ForA-to-Bdata flow, the device operates inthe transparent
modewhenLEABis high. WhenLEABis low,theAdatais latchedifCLKAB
isheldatahighorlowlogiclevel.IfLEABislow,theAdataisstoredinthelatch/
flip-floponthelow-to-hightransitionofCLKAB.WhenOEABishigh,theoutputs
areactive.WhenOEABislow,theoutputsareinthehigh-impedancestate.
DataflowforBtoAissimiliartothatofAtoBbutusesOEBA,LEBA,andCLKBA.
Theoutputenablesarecomplementary(OEABisactivehighandOEBAisactive
low).
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Suitable for heavy loads
The ALVCH16501 has been designed with a ±24mA output driver. This
driveriscapableofdrivingamoderatetoheavyloadwhilemaintainingspeed
performance.
The ALVCH16501 has “bus-hold” which retains the inputs’ last state
whenevertheinputbusgoestoahighimpedance.Thispreventsfloatinginputs
andeliminatestheneedforpull-up/downresistors.
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONALBLOCKDIAGRAM
1
OEAB
55
CLKAB
2
LEAB
28
LEBA
30
CLKBA
27
OEBA
3
A1
1D
54
B1
C1
CLK
1D
C1
CLK
TO 17 OTHER CHANNELS
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
MAY 2006
1
© 2006 Integrated Device Technology, Inc.
DSC-4738/4
IDT74ALVCH16501
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
Description
Max
Unit
V
(2)
VTERM
Terminal Voltage with Respect to GND
–0.5 to +4.6
(3)
VTERM
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
V
1
2
3
4
OEAB
LEAB
A1
56
55
54
53
52
GND
TSTG
IOUT
IIK
Storage Temperature
DC Output Current
–65 to +150
–50 to +50
±50
° C
mA
mA
CLKAB
B1
Continuous Clamp Current,
VI < 0 or VI > VCC
GND
A2
GND
B2
IOK
Continuous Clamp Current, VO < 0
–50
mA
mA
5
ICC
ISS
Continuous Current through each
VCC or GND
±100
A3
6
51
50
49
48
B3
VCC
7
VCC
B4
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
8
A4
A5
9
B5
A6
10
11
12
13
14
15
16
17
18
19
20
21
22
B6
47
46
45
44
43
42
41
40
39
38
37
36
2. VCC terminals.
3. All terminals except VCC.
GND
A7
GND
B7
B8
A8
A9
B9
A10
A11
A12
B10
B11
B12
GND
B13
B14
B15
VCC
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
5
7
7
7
9
9
pF
pF
pF
GND
A13
COUT
CI/O
A14
NOTE:
A15
1. As applicable to the device type.
VCC
A16
35
34
33
32
23
24
25
26
27
28
B16
A17
GND
A18
B17
GND
31
30
29
B18
OEBA
LEBA
CLKBA
GND
PINDESCRIPTION
Pin Names
Description
SSOP/ TSSOP
TOP VIEW
OEAB
OEBA
LEAB
LEBA
CLKAB
CLKBA
Ax
A-to-B Output Enable Input
B-to-A Output Enable Input (Active LOW)
A-to-B Latch Enable Input
B-to-A Latch Enable Input
A-to-B Clock Input
B-to-A Clock Input
A-to-B Data Inputs or B-to-A 3-State Outputs(1)
B-to-A Data Inputs or A-to-B 3-State Outputs(1)
Bx
NOTE:
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
2
IDT74ALVCH16501
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
FUNCTIONTABLE(1,2)
Inputs
Output
OEAB
L
LEAB
X
CLKAB
Ax
X
L
Bx
Z
X
X
H
H
L
H
H
X
H
L
H
L
H
L
↑
H
L
↑
H
X
H
(3)
H
L
L or H
B
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is similar, but uses OEBA, LEBA, and
CLKBA.
2. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
↑ = LOW-to-HIGH Transition
3. Output level before the indicated steady-state input conditions were established.
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
OperatingCondition:TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
Input HIGH Current
VCC = 3.6V
VCC = 3.6V
VCC = 3.6V
VI = VCC
—
—
—
—
—
—
—
5
5
µA
µA
µ A
Input LOW Current
VI = GND
VO = VCC
VO = GND
IOZH
IOZL
VIK
VH
High Impedance Output Current
(3-State Output pins)
—
10
—
10
Clamp Diode Voltage
VCC = 2.3V, IIN = –18mA
VCC = 3.3V
–0.7
–1.2
V
Input Hysteresis
—
—
100
0.1
—
40
mV
µ A
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
ΔICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
750
µ A
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
3
IDT74ALVCH16501
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
BUS-HOLDCHARACTERISTICS
Symbol
IBHH
Parameter(1)
Test Conditions
VI = 2V
Min.
–75
75
Typ.(2)
—
Max.
—
Unit
Bus-HoldInputSustainCurrent
VCC = 3V
µ A
IBHL
VI = 0.8V
—
—
IBHH
Bus-HoldInputSustainCurrent
Bus-HoldInputOverdrive Current
VCC = 2.3V
VCC = 3.6V
VI = 1.7V
–45
45
—
—
µ A
µ A
IBHL
VI = 0.7V
—
—
IBHHO
VI = 0 to 3.6V
—
—
±500
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
VCC – 0.2
2
Max.
—
Unit
VOH
OutputHIGHVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
V
—
VCC = 2.3V
1.7
—
VCC = 2.7V
2.2
—
VCC = 3V
2.4
—
VCC = 3V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
2
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
0.2
0.4
0.7
0.4
0.55
V
—
IOL = 12mA
IOL = 12mA
IOL = 24mA
—
VCC = 2.7V
VCC = 3V
—
—
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Symbol
CPD
Parameter
Test Conditions
Typical
Typical
Unit
PowerDissipationCapacitanceOutputsenabled
PowerDissipationCapacitanceOutputsdisabled
CL = 0pF, f = 10Mhz
44
6
54
6
pF
CPD
4
IDT74ALVCH16501
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
SWITCHINGCHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
fMAX
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPZH
tPZL
tPZH
tPZL
tPHZ
tPLZ
tPHZ
tPLZ
tSU
Parameter
Min.
150
1
Max.
—
Min.
150
—
Max.
—
Min.
150
1
Max.
—
Unit
MHz
ns
PropagationDelay
Ax to Bx or Bx to Ax
PropagationDelay
LE to Ax or Bx
4.8
4.5
3.9
1.1
1.2
1.3
1
5.7
6.1
6.3
5.8
5.3
6.2
—
—
—
—
—
—
5.3
5.6
6
1.3
1.4
1.1
1
4.6
4.9
5
ns
ns
ns
ns
ns
ns
PropagationDelay
CLK to Ax or Bx
OutputEnableTime
OEBA to Ax
OutputEnableTime
OEAB to Bx
5.3
4.6
5.7
4.6
4.2
5
OutputDisableTime
OEBA to Ax
1.3
1.5
1.3
1.4
OutputDisableTime
OEAB to Bx
Set-upTime,databeforeCLK↑
Set-upTime,databeforeLE↓
2.2
1.9
1.3
0.6
1.4
3.3
3.3
—
—
—
—
—
—
—
—
—
2.1
1.6
1.1
0.6
1.7
3.3
3.3
—
—
—
—
—
—
—
—
—
1.7
1.5
1
—
—
—
—
—
—
—
500
ns
ns
tSU
CLK LOW
CLK HIGH
tH
tH
HoldTime,dataafterCLK↑
0.7
1.4
3.3
3.3
—
ns
ns
ns
ns
ps
Hold Time, data after LE↓, CLK HIGH or LOW
Pulse Width, LE HIGH
tW
tW
Pulse Width, CLK HIGH or LOW
(2)
tSK(o)
NOTES:
OutputSkew
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2
Skew between any two outputs of the same package and switching in the same direction.
5
IDT74ALVCH16501
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
TESTCONDITIONS
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
tPHL
tPHL
tPLH
tPLH
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V Unit
VOH
VT
VOL
OUTPUT
VLOAD
VIH
6
6
2 x Vcc
Vcc
V
V
2.7
1.5
300
300
50
2.7
1.5
300
300
50
VIH
VT
0V
VT
Vcc / 2
150
V
OPPOSITE PHASE
INPUT TRANSITION
VLZ
VHZ
CL
mV
mV
pF
150
ALVC Link
30
Propagation Delay
VLOAD
Open
GND
DISABLE
VCC
ENABLE
VIH
VT
0V
CONTROL
INPUT
500Ω
tPZL
tPLZ
VIN
VOUT
(1, 2)
Pulse
VLOAD/2
D.U.T.
VLOAD/2
OUTPUT
NORMALLY
LOW
SWITCH
VT
Generator
VLZ
VOL
CLOSED
500Ω
tPHZ
tPZH
RT
CL
OUTPUT
NORMALLY
HIGH
VOH
VHZ
SWITCH
OPEN
VT
0V
ALVC Link
0V
Test Circuit for All Outputs
ALVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
VIH
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
DATA
INPUT
VT
0V
tSU
tH
VIH
VT
0V
TIMING
INPUT
SWITCHPOSITION
Test
Switch
VLOAD
GND
Open
tREM
VIH
ASYNCHRONOUS
CONTROL
Open Drain
Disable Low
Enable Low
VT
0V
VIH
VT
0V
SYNCHRONOUS
CONTROL
Disable High
Enable High
tSU
tH
ALVC Link
All Other Tests
VIH
Set-up, Hold, and Release Times
VT
INPUT
0V
tPLH1
tPHL1
VOH
VT
LOW-HIGH-LOW
VT
PULSE
OUTPUT 1
OUTPUT 2
VOL
tSK (x)
tSK (x)
tW
VOH
VT
VOL
HIGH-LOW-HIGH
PULSE
VT
ALVC Link
tPLH2
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
tPHL2
Pulse Width
ALVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
6
IDT74ALVCH16501
3.3VCMOS18-BITUNIVERSALBUSTRANSCEIVERWITH3-STATEOUTPUTS
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
IDT
ALVC
Bus-Hold Family
XX
Device Type Package
X
XXX
XX
XXX
Temp. Range
Shrink Small Outline Package
PV
SSOP - Green
Thin Shrink Small Outline Package
TSSOP - Green
PVG
PA
PAG
18-Bit Universal Bus Transceiver with 3-State Outputs
Double-Density, 24mA
501
16
H
Bus-Hold
– 40°C to +85°C
74
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7
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