74ALVCH374SO [IDT]

SOIC-20, Tube;


型号：	74ALVCH374SO
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	SOIC-20, Tube 光电二极管逻辑集成电路触发器
文件：	总6页 (文件大小：89K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74ALVCH374

3.3VCMOSOCTALPOSITIVEEDGE-TRIGGEREDD-TYPE

INDUSTRIALTEMPERATURERANGE

3.3V CMOS OCTAL POSITIVE

IDT74ALVCH374

EDGE-TRIGGERED D-TYPE

FLIP-FLOP WITH 3-STATE

OUTPUTS AND BUS-HOLD

DESCRIPTION:

FEATURES:

–

0.5 MICRON CMOS Technology

Thisoctalpostiveedge-triggeredD-typeflip-flopisbuiltusingadvanced

dual metal CMOS technology. The ALVCH374 device is particularly

suitableforimplementingbufferregisters,I/Oports,bidirectionalbusdrivers,

andworkingregisters.Onthepositivetransitionoftheclock(CLK)input,the

Qoutputs are settothe logiclevels atthe data (D)inputs.

Typical t (o) (Output Skew) < 250ps

ESD > 2000V per MIL-STD-883, Method 3015;

> 200V using machine model (C = 200pF, R = 0)

VCC = 3.3V ±0.3V, Normal Range

–

= 2.7V to 3.6V, Extended Range

VCC = 2.5V ±0.2V

Abufferedoutput-enable(OE)inputcanbeusedtoplacetheeightoutputs

ineithera normallogicstate (highorlowlogiclevels)ora high-impedance

state.Inthehigh-impedancestate,theoutputsneitherloadnordrivethebus

lines significantly.The high-impedance state andincreaseddrive provide

thecapabilitytodrivebuslineswithoutinterfaceorpullupcomponents. OE

does notaffectinternaloperations ofthelatch.Olddatacanberetainedor

newdatacanbeenteredwhiletheoutputsareinthehigh-impedancestate.

CMOS power levels (0.4µW typ. static)

Rail-to-Rail output swing for increased noise margin

Available in SOIC, SSOP, QSOP, and TSSOP packages

Drive Features for ALVCH374:

–

High Output Drivers: ±24mA

Suitable for heavy loads

The ALVCH374 has been designed with a ±24mA output driver. This

driver is capable of driving a moderate to heavy load while maintaining

speedperformance.

APPLICATIONS:

• 3.3V High Speed Systems

• 3.3Vandlowervoltagecomputingsystems

The ALVCH374 has a “bus-hold” which retains the inputs’ last state

wheneverthe inputbus goes toa highimpedance.This prevents floating

inputs andeliminates the needforpull-up/downresistors.

FUNCTIONALBLOCKDIAGRAM

CLK

¹D

¹Q

¹D

TO SEVEN OTHER CHANNELS

INDUSTRIAL TEMPERATURE RANGE

MARCH1999

1999 Integrated Device Technology, Inc.

DSC-4473/-

IDT74ALVCH374

INDUSTRIALTEMPERATURERANGE

3.3VCMOSOCTALPOSITIVEEDGE-TRIGGEREDD-TYPE

ABSOLUTE MAXIMUM RATINGS⁽¹⁾

PIN CONFIGURATION

Symbol

Description

Max.

Unit

(2)

VTERM

Terminal Voltage with Respect to GND

– 0.5 to +4.6

(3)

VTERM

Terminal Voltage with Respect to GND –0.5 to VCC +0.5

VCC

⁸Q

⁸D

¹Q

¹D

²D

²Q

³Q

³D

⁴D

⁴Q

IOUT

IIK

DC Output Current

– 50 to +50

±50

Continuous Clamp Current,

VI < 0 or VI > VCC

IOK

Continuous Clamp Current, VO < 0

–50

⁷D

SO20-2

SO20-7

SO20-8

SO20-9

ICC

ISS

TSTG

Continuous Current through each VCC

or GND

±100

⁷Q

⁶Q

⁶D

Storage Temperature

– 65 to +150

°C

ALVC Link

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a

stress rating only and functional operation of the device at these or

any other conditions above those indicated in the operational sections

of this specification is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect reliability.

2. V^CCterminals.

⁵D

⁵Q

CLK

GND

3. All terminals except V

SSOP/ TVSOP/ TSSOP/ QSOP

TOP VIEW

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol

Parameter⁽¹⁾

Conditions

Typ.

Max.

Unit

CIN

Input Capacitance

VIN = 0V

COUT

CI/O

Output Capacitance

I/O Port Capacitance

VOUT = 0V

VIN = 0V

ALVC Link

NOTE:

1. As applicable to the device type.

PIN DESCRIPTION

Pin Names

Description

CLK

3-State Output Enable Input (Active LOW)

Clock Input

(1)

Data Inputs

3-State Outputs

NOTE:

1. These pins have “Bus-hold”. All other pins are standard inputs,

outputs, or I/Os.

(1)

FUNCTION TABLE (each flip=flop)

Inputs

Output

CLK

↑

Q₀

Hor L

NOTE:

1. H = HIGH Voltage Level

L = LOW Voltage Level

X = Don’t Care

Z = High-Impedance

↑ = LOW-to-HIGH Transition

Q = Level of Q before the indicated steady-state input conditions were

established.

1998 Integrated Device Technology, Inc.

DSC-123456

IDT74ALVCH374

3.3VCMOSOCTALPOSITIVEEDGE-TRIGGEREDD-TYPE

INDUSTRIALTEMPERATURERANGE

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Following Conditions Apply Unless Otherwise Specified:

Operating Condition: TA = –40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

Typ.⁽¹⁾

Max.

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

VCC = 2.3V to 2.7 V

VCC = 2.7V to 3.6V

VCC = 3.6V

1.7

—

0.7

VIL

Input LOW Voltage Level

—

0.8

IIH

Input HIGH Current

VI = VCC

—

± 5

± 10

– 1.2

—

µA

IIL

Input LOW Current

VCC = 3.6V

VI = GND

VO = VCC

VO = GND

—

IOZH

IOZL

VIK

High Impedance Output Current

(3-State Output pins)

Clamp Diode Voltage

Input Hysteresis

VCC = 3.6V

—

µA

—

VCC = 2.3V, IIN = –18mA

VCC = 3.3V

– 0.7

100

0.1

µA

ICCL

ICCH

ICCZ

∆ICC

Quiescent Power Supply Current

VCC = 3.6V

VIN = GND or VCC

Quiescent Power Supply

Current Variation

One input at V_CC– 0.6V,

other inputs at VCC or GND

—

750

µA

ALVC Link

NOTE:

1. Typical values are at V^CC= 3.3V, +25°C ambient.

BUS-HOLD CHARACTERISTICS

Symbol

Parameter⁽¹⁾

Test Conditions

Min.

Typ.⁽²⁾

Max.

Unit

IBHH

Bus-Hold Input Sustain Current

VCC = 3.0V

VCC = 2.3V

VCC = 3.6V

VI = 2.0V

VI = 0.8V

VI = 1.7V

VI = 0.7V

VI = 0 to 3.6V

– 75

—

µA

IBHL

– 45

—

IBHH

IBHL

Bus-Hold Input Sustain Current

Bus-Hold Input Overdrive Current

µA

—

IBHHO

IBHLO

—

± 500

µA

ALVC Link

NOTES:

1. Pins with Bus-hold are identified in the pin description.

2. Typical values are at V = 3.3V, +25°C ambient.

IDT74ALVCH374

INDUSTRIALTEMPERATURERANGE

3.3VCMOSOCTALPOSITIVEEDGE-TRIGGEREDD-TYPE

OUTPUT DRIVE CHARACTERISTICS

Symbol

Parameter

Test Conditions⁽¹⁾

IOH = – 0.1mA

Min.

Max.

Unit

VOH

Output HIGH Voltage

VCC = 2.3V to 3.6V

_CC= 2.3V

VCC – 0.2

—

I_OH= – 6mA

IOH = – 12mA

—

VCC = 2.3V

1.7

2.2

2.4

VCC = 2.7V

—

VCC = 3.0V

—

VCC = 3.0V

IOH = – 24mA

IOL = 0.1mA

IOL = 6mA

—

VOL

Output LOW Voltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.7

0.4

0.55

IOL = 12mA

I_OL= 24mA

VCC = 2.7V

V_CC= 3.0V

ALVC Link

NOTE:

1. V^IHand V^ILmust be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the

appropriate V^CCrange. T^A= – 40°C to + 85°C.

OPERATING CHARACTERISTICS, T = 25 C

VCC = 2.5V ± 0.2V

Typical

VCC = 3.3V ± 0.3V

Typical

Unit

Symbol

Parameter

Power Dissipation Capacitance

Outputs enabled

Test Conditions

CPD

CL = 0pF, f = 10Mhz

CPD

Power Dissipation Capacitance

Outputs disabled

SWITCHINGCHARACTERISTICS⁽¹⁾

VCC = 2.5V ± 0.2V

VCC = 2.7V

VCC = 3.3V ± 0.3V

Symbol

tPLH

Parameter

Propagation Delay

Min

Max.

Min

Max.

Min

Max.

Unit

—

2.2

t_PHL

CLK to xQ

tPZH

Output Enable Time

OE to xQ

Output Disable Time

OE to xQ

—

8.5

9.5

—

7.5

6.5

1.5

6.5

5.5

tPZL

tPHZ

tPLZ

3.3

—

3.3

—

3.3

—

tSU

Pulse Duration, CLK HIGH or LOW

Setup Time, data before CLK↑

Hold Time, data after CLK↑

1.5

(2)

tSK(o)

Output Skew

—

500

NOTES:

1. See test circuits and waveforms. T^A= – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

IDT74ALVCH374

3.3VCMOSOCTALPOSITIVEEDGE-TRIGGEREDD-TYPE

INDUSTRIALTEMPERATURERANGE

TESTCIRCUITSANDWAVEFORMS

PROPAGATIONDELAY

TESTCONDITIONS

Symbol

(1)

(2)

VIH

VCC = 3.3V ±0.3V VCC = 2.7V VCC = 2.5V ±0.2V

Unit

SAME PHASE

INPUT TRANSITION

VLOAD

2 xVcc

Vcc

t^PHL

t^PLH

VIH

2.7

1.5

300

2.7

1.5

300

VOH

VOL

OUTPUT

VCC / 2

150

t^PHL

t^PLH

VIH

VHZ

150

OPPOSITE PHASE

INPUT TRANSITION

ALVC Link

TEST CIRCUITS FOR ALL OUTPUTS

ENABLEANDDISABLETIMES

LOAD

Open

GND

DISABLE

ENABLE

V^IH

V^T

CONTROL

INPUT

500Ω

V^IN

V^OUT

Pulse^{(1, 2)}

Generator

t^PLZ

t^PZL

D.U.T.

V^LOAD/2

V^LZ

OUTPUT

NORMALLY

LOW

SWITCH

CLOSED

500Ω

R^T

C^L

V^OL

t^PHZ

tPZH

V^OH

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

ALVC Link

V^T

DEFINITIONS:

C^L= Load capacitance: includes jig and probe capacitance.

R^T= Termination resistance: should be equal to Z^OUTof the Pulse

ALVC Link

Generator.

NOTE:

1. Diagram shown for input Control Enable-LOW and input Control

Disable-HIGH.

SET-UP, HOLD, AND RELEASE TIMES

NOTES:

1. Pulse Generator for All Pulses: Rate ≤ 10MHz; t ≤ 2.5ns; t ≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 10MHz; t^F≤ 2ns; t^R≤ 2ns.

V^IH

SWITCHPOSITION

DATA

INPUT

t^H

Test

Switch

V^IH

TIMING

INPUT

Open Drain

Disable Low

Enable Low

Disable High

Enable High

All Other tests

VLOAD

t^REM

V^IH

ASYNCHRONOUS

CONTROL

GND

Open

V^IH

V^T

SYNCHRONOUS

CONTROL

t^SU

ALVC Link

OUTPUT SKEW - ^TSK(x)

V^IH

V^T

PULSEWIDTH

INPUT

t^PLH1

t^PHL1

V^OH

LOW-HIGH-LOW

PULSE

V^T

OUTPUT 1

OUTPUT 2

V^OL

t^SK(x)

SK (x)

t^W

V^OH

HIGH-LOW-HIGH

PULSE

V^T

V^OL

ALVC Link

t^PLH2

t^PHL2

SK(x)

PLH2 - PLH1 or PHL2 - PHL1

t t t

= t

ALVC Link

NOTES:

1. For t^SK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For t^SK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74ALVCH374

INDUSTRIALTEMPERATURERANGE

3.3VCMOSOCTALPOSITIVEEDGE-TRIGGEREDD-TYPE

ORDERINGINFORMATION

Device Type Package

Temp. Range

ALVC

XXX

IDT

Bus-Hold

Small Outline IC (SO20-2)

Shrink Small Outline Package (SO20-7)

Quarter-size Small Outline Package (SO20-8)

Thin Shrink Small Outline Package (SO20-9)

374

Octal Positive Edge-Triggered D-Type Flip-Flop with 3-State

Outputs, ±24mA

Bus-Hold

–40°C to +85°C

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