74ALVCHR162245PAG [IDT]
3.3V CMOS 16-BIT BUS TRANSCIEVER;
| 型号： | 74ALVCHR162245PAG |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | 3.3V CMOS 16-BIT BUS TRANSCIEVER |
| 文件： | 总6页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3.3V CMOS 16-BIT
BUS TRANSCIEVER
WITH 3-STATE OUTPUTS
AND BUS-HOLD
IDT74ALVCHR162245
DESCRIPTION:
FEATURES:
This 16-bit bus transceiver is built using advanced dual metal CMOS
technology. The ALVCHR162245 device is designed for asynchronous
communicationbetweendatabuses. Thecontrol-functionimplementation
minimizesexternaltimingrequirements.
• 0.5 MICRON CMOS Technology
• Typical tSK(o) (Output Skew) < 250ps
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• VCC = 2.5V ± 0.2V
This device can be used as two 8-bit transceivers or one 16-bit
transceiver. It allows data transmission from the A bus to the B bus or from
the B bus to the A bus, depending on the logic level at the direction control
(DIR)input.Theoutput-enable(OE)inputcanbeusedtodisablethedevice
so that the buses are effectively isolated.
The ALVCHR162245 has series resistors in the device output structure
which will significantly reduce line noise when used with light loads. This
driverhasbeendesignedtodrive±12mAatthedesignatedthresholdlevels.
The ALVCHR162245 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
• CMOS power levels (0.4μ W typ. static)
• Rail-to-Rail output swing for increased noise margin
• Available in TSSOP package
DRIVE FEATURES:
• Balanced Output Drivers: ±12mA
• Low Switching Noise
APPLICATIONS:
• 3.3V high speed systems
• 3.3V and lower voltage computing systems
FUNCTIONAL BLOCK DIAGRAM
1
24
1DIR
2DIR
48
2
25
13
1
OE
2
OE
47
46
44
43
41
40
38
36
35
33
32
30
1
A
1
2
A
1
1
B
1
2
B
1
1
A
2
2A
2
3
3
14
16
17
2
B
2
1
B
2
1
1
A3
2
A
5
1
B3
2
B3
A
4
5
6
2
A
4
6
1
B4
2
B4
1A
2A
5
19
20
22
8
9
1
B
5
2
B5
29
27
1
A
2A
6
1
1
B
B
6
2
2
B
B
6
1A
7
2A
7
11
7
7
37
26
1A8
2A8
12
23
1B8
2B8
IDTandtheIDTlogoareregisteredtrademarksofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
SEPTEMBER 2016
1
© 2016 Integrated Device Technology, Inc.
DSC-4606/6
IDT74ALVCHR162245
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
Symbol
Description
Max
Unit
V
(2)
VTERM
Terminal Voltage with Respect to GND –0.5 to +4.6
Terminal Voltage with Respect to GND –0.5 to VCC+0.5
(3)
1
2
3
4
5
6
7
8
9
1
DIR
1
OE
VTERM
V
48
47
46
45
44
TSTG
IOUT
IIK
Storage Temperature
DC Output Current
–65 to +150
–50 to +50
±50
°C
mA
mA
1
1
B
1
2
1
A1
B
1A2
Continuous Clamp Current,
VI < 0 or VI > VCC
GND
GND
IOK
Continuous Clamp Current, VO < 0
–50
mA
mA
1
B3
1
A
3
4
ICC
ISS
Continuous Current through each
VCC or GND
±100
1
B4
1
A
43
42
41
NOTES:
V
CC
V
CC
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
1
B5
1A
5
1
B6
1
A6
40
39
GND
GND
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2. VCC terminals.
3. All terminals except VCC.
1
1
2
2
B7
B8
B1
B2
1
A
7
8
38
37
36
35
34
33
1
A
CAPACITANCE (TA = +25°C, F = 1.0MHz)
2
2
A1
Symbol
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
A2
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
5
7
7
7
9
9
pF
pF
pF
COUT
CI/O
GND
GND
2
2
B
3
4
2
2
A
3
4
NOTE:
B
1. As applicable to the device type.
32
31
A
VCC
V
CC
PIN DESCRIPTION
Pin Names
30
29
28
27
26
25
2
2
B
5
2
A5
Description
B6
2
A6
xOE
DIR
Output Enable Inputs (Active LOW)
Direction Control Inputs
GND
GND
2
2
B
7
8
2
2
2
A
7
8
xAx(1)
xBx(1)
Side A Inputs or 3-State Outputs
Side B Inputs or 3-State Outputs
B
A
NOTE:
2DIR
OE
1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.
TSSOP
TOP VIEW
(1)
FUNCTION TABLE (EACH 8-BIT SECTION)
Inputs
xOE
L
xDIR
Outputs
Bus B data to A bus
Bus A data to B bus
High Z State
L
H
X
L
H
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
Z = High-Impedance
2
IDT74ALVCHR162245
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
Input HIGH Current
VCC = 3.6V
VCC = 3.6V
VCC = 3.6V
VI = VCC
VI = GND
VO = VCC
VO = GND
—
—
—
—
—
—
—
5
5
μA
μA
μA
Input LOW Current
IOZH
IOZL
VIK
VH
High Impedance Output Current
(3-State Output pins)
Clamp Diode Voltage
—
10
—
10
VCC = 2.3V, IIN = –18mA
VCC = 3.3V
–0.7
–1.2
V
Input Hysteresis
—
—
100
0.1
—
mV
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VCC = 3.6V
VIN = GND or VCC
40
μA
ΔICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
—
—
750
μA
NOTE:
1. Typical values are at VCC = 3.3V, +25°C ambient.
BUS-HOLD CHARACTERISTICS
Symbol
IBHH
Parameter(1)
Test Conditions
VI = 2V
Min.
– 75
75
Typ.(2)
—
Max.
—
Unit
Bus-Hold Input Sustain Current
VCC = 3V
μA
IBHL
VI = 0.8V
—
—
IBHH
Bus-Hold Input Sustain Current
Bus-Hold Input Overdrive Current
VCC = 2.3V
VCC = 3.6V
VI = 1.7V
– 45
45
—
—
μA
μA
IBHL
VI = 0.7V
—
—
IBHHO
VI = 0 to 3.6V
—
—
±500
IBHLO
NOTES:
1. Pins with Bus-Hold are identified in the pin description.
2. Typical values are at VCC = 3.3V, +25°C ambient.
3
IDT74ALVCHR162245
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
Max.
—
Unit
VOH
Output HIGH Voltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 4mA
IOH = – 6mA
IOH = – 4mA
IOH = – 8mA
IOH = – 6mA
IOH = – 12mA
IOL = 0.1mA
IOL = 4mA
VCC – 0.2
V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
1.9
1.7
2.2
2
—
—
—
—
2.4
2
—
—
VOL
Output LOW Voltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
—
—
—
—
—
—
0.2
0.4
0.55
0.4
0.6
0.55
0.8
V
IOL = 6mA
VCC = 2.7V
VCC = 3V
IOL = 4mA
IOL = 8mA
IOL = 6mA
IOL = 12mA
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range. TA = –
40°C to + 85°C.
OPERATING CHARACTERISTICS, TA = 25°C
VCC = 2.5V ± 0.2V
VCC = 3.3V ± 0.3V
Symbol
CPD
Parameter
Test Conditions
Typical
Typical
Unit
PowerDissipationCapacitanceOutputsenabled
PowerDissipationCapacitanceOutputsdisabled
CL = 0pF, f = 10Mhz
24
4
32
5
pF
CPD
SWITCHINGCHARACTERISTICS(1)
VCC = 2.5V ± 0.2V
Min. Max.
4.9
VCC = 2.7V
VCC = 3.3V ± 0.3V
Symbol
tPLH
Parameter
Min.
Max.
Min.
Max.
Unit
Propagation Delay
xAx to xBx or xBx to xAx
Output Enable Time
xOE to xAx or xBx
Output Disable Time
xOE to xAx or xBx
OutputSkew(2)
1
—
4.7
1
4.2
ns
ns
ns
ps
tPHL
tPZH
1
1
6.8
6.3
—
—
—
—
6.7
5.7
—
1
1
5.6
5.5
500
tPZL
tPHZ
tPLZ
tSK(o)
—
—
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74ALVCHR162245
INDUSTRIAL TEMPERATURE RANGE
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
TEST CIRCUITS AND WAVEFORMS
TEST CONDITIONS
V
V
0V
IH
T
SAME PHASE
INPUT TRANSITION
Symbol VCC(1)=3.3V±0.3V VCC(1)=2.7V VCC(2)=2.5V±0.2V
Unit
t
PHL
t
PLH
V
V
V
OH
T
OL
OUTPUT
VLOAD
VIH
6
6
2 x Vcc
Vcc
V
2.7
1.5
300
300
50
2.7
1.5
300
300
50
V
t
PHL
tPLH
VT
Vcc / 2
150
V
V
IH
T
OPPOSITE PHASE
INPUT TRANSITION
V
VLZ
VHZ
CL
mV
mV
pF
0V
150
ALVC Link
Propagation Delay
30
V
LOAD
Open
GND
DISABLE
V
CC
ENABLE
V
V
IH
T
CONTROL
INPUT
500Ω
0V
tPZL
tPLZ
VIN
VOUT
Pulse(1, 2)
Generator
V
LOAD/2
D.U.T.
V
LOAD/2
OUTPUT
NORMALLY
LOW
SWITCH
CLOSED
VT
VLZ
VOL
500Ω
t
PHZ
tPZH
RT
CL
OUTPUT
NORMALLY
HIGH
V
V
OH
HZ
SWITCH
OPEN
V
0V
T
ALVC Link
0V
Test Circuit for All Outputs
ALVC Link
Enable and Disable Times
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
V
IH
T
1. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2ns; tR ≤ 2ns.
DATA
INPUT
V
0V
t
SU
t
H
V
IH
V
TIMING
INPUT
SWITCHPOSITION
T
0V
Test
Switch
VLOAD
GND
t
REM
V
IH
V
ASYNCHRONOUS
CONTROL
Open Drain
Disable Low
Enable Low
T
0V
V
IH
V
SYNCHRONOUS
CONTROL
T
Disable High
Enable High
t
SU
0V
t
H
ALVC Link
All Other Tests
Open
Set-up, Hold, and Release Times
V
V
IH
T
INPUT
0V
tPLH1
tPHL1
V
V
V
OH
LOW-HIGH-LOW
T
V
T
PULSE
OUTPUT 1
OL
tSK (x)
tSK (x)
t
W
V
V
V
OH
T
HIGH-LOW-HIGH
PULSE
V
T
OUTPUT 2
OL
ALVC Link
t
PLH2
t
PHL2
Pulse Width
t
SK(x) = tPLH2
-
tPLH1 or
t
PHL2
-
t
PHL1
ALVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74ALVCHR162245
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
INDUSTRIAL TEMPERATURE RANGE
ORDERING INFORMATION
XX
ALVC
XXX
XX
X
X
XX
Device Type Package
Bus-Hold Family
Temp. Range
Tube
Tape and Reel
Blank
8
PAG
245
R162
H
Thin Shrink Small Outline Package - Green
16-Bit Bus Transceiver with 3-State Outputs
Double-Density with Resistors, 12mA
Bus-Hold
74
-40°C to +85°C
DatasheetDocumentHistory
09/19/2016
Pg.
6
Updated the ordering information by adding Tape and Reel.
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6
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