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74ALVCHR16245LRG4 [TI]

16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS; 具有三态输出的16位总线收发器
74ALVCHR16245LRG4
型号： 74ALVCHR16245LRG4
厂家： TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述：

16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
具有三态输出的16位总线收发器

总线收发器 输出元件
文件： 总13页 (文件大小：293K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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SN74ALVCHR16245  
16-BIT BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES064G–DECEMBER 1995–REVISED OCTOBER 2004  
FEATURES  
DGG OR DL PACKAGE  
(TOP VIEW)  
•
Member of the Texas Instruments Widebus™  
Family  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1DIR  
1B1  
1B2  
GND  
1B3  
1B4  
1OE  
1A1  
1A2  
GND  
1A3  
1A4  
•
•
•
•
Operates From 1.65 V to 3.6 V  
Max tpd of 4.2 ns at 3.3 V  
2
3
±12-mA Output Drive at 3.3 V  
4
All Outputs Have Equivalent 26-Ω Series  
Resistors, So No External Resistors Are  
Required  
5
6
7
V
CC  
V
CC  
8
•
•
•
Bus Hold on Data Inputs Eliminates the Need  
for External Pullup/Pulldown Resistors  
1B5  
1B6  
GND  
1B7  
1B8  
2B1  
2B2  
GND  
2B3  
2B4  
1A5  
1A6  
GND  
1A7  
1A8  
2A1  
2A2  
GND  
2A3  
2A4  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds JESD 22  
- 2000-V Human-Body Model (A114-A)  
- 200-V Machine Model (A115-A)  
DESCRIPTION/ORDERING INFORMATION  
This 16-bit (dual-octal) noninverting bus transceiver is  
designed for 1.65-V to 3.6-V VCC operation.  
V
CC  
V
CC  
2B5  
2B6  
GND  
2B7  
2B8  
2DIR  
2A5  
2A6  
GND  
2A7  
2A8  
2OE  
The  
SN74ALVCHR16245  
is  
designed  
for  
asynchronous communication between data buses.  
The control-function implementation minimizes  
external timing requirements.  
This device can be used as two 8-bit transceivers or  
one 16-bit transceiver. It allows data transmission  
from the A bus to the B bus or from the B bus to the  
A
bus, depending on the logic level at the  
direction-control (DIR) input. The output-enable (OE)  
input can be used to disable the device so that the  
buses are effectively isolated.  
All outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω series resistors to reduce overshoot  
and undershoot.  
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors  
with the bus-hold circuitry is not recommended.  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
SN74ALVCHR16245LR  
SN74ALVCHR16245GR  
SN74ALVCHR16245KR  
74ALVCHR16245ZQLR  
TOP-SIDE MARKING  
ALVCHR16245  
SSOP - DL  
Tape and reel  
Tape and reel  
TSSOP - DGG  
VFBGA - GQL  
ALVCHR16245  
-40°C to 85°C  
Tape and reel  
VR245  
VFBGA - ZQL (Pb-free)  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1995–2004, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
SN74ALVCHR16245  
16-BIT BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES064G–DECEMBER 1995–REVISED OCTOBER 2004  
GQL OR ZQL PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
A
B
C
D
E
F
G
H
J
K
TERMINAL ASSIGNMENTS(1)  
1
2
3
4
5
6
A
B
C
D
E
F
1DIR  
1B2  
1B4  
1B6  
1B8  
2B1  
2B3  
2B5  
2B7  
2DIR  
NC  
NC  
NC  
NC  
1OE  
1A2  
1A4  
1A6  
1A8  
2A1  
2A3  
2A5  
2A7  
2OE  
1B1  
1B3  
1B5  
1B7  
2B2  
2B4  
2B6  
2B8  
NC  
GND  
VCC  
GND  
GND  
VCC  
GND  
1A1  
1A3  
1A5  
1A7  
2A2  
2A4  
2A6  
2A8  
NC  
G
H
J
GND  
VCC  
GND  
NC  
GND  
VCC  
GND  
NC  
K
(1) NC - No internal connection  
FUNCTION TABLE  
(each 8-bit section)  
INPUTS  
OPERATION  
OE  
DIR  
L
L
L
B data to A bus  
A data to B bus  
Isolation  
H
H
X
2
SN74ALVCHR16245  
16-BIT BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES064G–DECEMBER 1995–REVISED OCTOBER 2004  
LOGIC DIAGRAM (POSITIVE LOGIC)  
24  
1
2DIR  
1DIR  
48  
25  
13  
1OE  
1B1  
2OE  
2B1  
36  
47  
1A1  
2A1  
2
To Seven Other Channels  
To Seven Other Channels  
Pin numbers shown are for the DGG and DL packages.  
ABSOLUTE MAXIMUM RATINGS(1)  
over operating free-air temperature range (unless otherwise noted)  
MIN  
-0.5  
-0.5  
MAX  
4.6  
UNIT  
VCC  
VI  
Supply voltage range  
Input voltage range  
V
Except I/O ports(2)  
I/O ports(2)(3)  
4.6  
V
-0.5  
-0.5  
VCC + 0.5  
VCC + 0.5  
-50  
VO  
IIK  
Output voltage range(2)(3)  
Input clamp current  
V
VI < 0  
mA  
mA  
mA  
mA  
IOK  
IO  
Output clamp current  
VO < 0  
-50  
Continuous output current  
Continuous current through each VCC or GND  
±50  
±100  
70  
DGG package  
DL package  
θJA  
Package thermal impedance(4)  
Storage temperature range  
63  
°C/W  
°C  
GQL/ZQL package  
42  
Tstg  
-65  
150  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.  
(3) This value is limited to 4.6 V maximum.  
(4) The package thermal impedance is calculated in accordance with JESD 51-7.  
3
SN74ALVCHR16245  
16-BIT BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES064G–DECEMBER 1995–REVISED OCTOBER 2004  
RECOMMENDED OPERATING CONDITIONS(1)  
MIN  
MAX  
UNIT  
VCC  
Supply voltage  
1.65  
3.6  
V
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
0.65 × VCC  
VIH  
High-level input voltage  
1.7  
2
V
V
0.35 × VCC  
VIL  
Low-level input voltage  
0.7  
0.8  
VCC  
VCC  
-2  
VI  
Input voltage  
0
0
V
V
VO  
Output voltage  
VCC = 1.65 V  
VCC = 2.3 V  
VCC = 2.7 V  
VCC = 3 V  
-6  
IOH  
High-level output current  
Low-level output current  
mA  
mA  
-8  
-12  
2
VCC = 1.65 V  
VCC = 2.3 V  
VCC = 2.7 V  
VCC = 3 V  
6
IOL  
8
12  
10  
85  
∆t/∆v  
Input transition rise or fall rate  
Operating free-air temperature  
ns/V  
TA  
-40  
°C  
(1) All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
4
SN74ALVCHR16245  
16-BIT BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES064G–DECEMBER 1995–REVISED OCTOBER 2004  
ELECTRICAL CHARACTERISTICS  
over recommended operating free-air temperature range (unless otherwise noted)  
PARAMETER  
TEST CONDITIONS  
VCC  
1.65 V to 3.6 V  
1.65 V  
2.3 V  
MIN TYP(1)  
VCC - 0.2  
MAX  
UNIT  
IOH = -100 µA  
IOH = -2 mA  
IOH = -4 mA  
1.2  
1.9  
1.7  
2.4  
2
VOH  
2.3 V  
V
IOH = -6 mA  
3 V  
IOH = -8 mA  
IOH = -12 mA  
IOL = 100 µA  
IOL = 2 mA  
IOL = 4 mA  
2.7 V  
3 V  
2
1.65 V to 3.6 V  
1.65 V  
2.3 V  
0.2  
0.45  
0.4  
VOL  
2.3 V  
0.55  
0.55  
0.6  
V
IOL = 6 mA  
3 V  
IOL = 8 mA  
2.7 V  
IOL = 12 mA  
VI = VCC or GND  
VI = 0.58 V  
3 V  
0.8  
II  
3.6 V  
±5  
µA  
µA  
25  
-25  
45  
1.65 V  
2.3 V  
3 V  
VI = 1.07 V  
VI = 0.7 V  
II(hold)  
VI = 1.7 V  
-45  
75  
VI = 0.8 V  
VI = 2 V  
-75  
VI = 0 to 3.6 V(2)  
VO = VCC or GND  
VI = VCC or GND,  
3.6 V  
3.6 V  
±500  
±10  
40  
(3)  
IOZ  
µA  
µA  
µA  
pF  
pF  
ICC  
∆ICC  
Ci  
IO = 0  
3.6 V  
One input at VCC - 0.6 V, Other inputs at VCC or GND  
Control inputs VI = VCC or GND  
A or B ports VO = VCC or GND  
3 V to 3.6 V  
3.3 V  
750  
4
9
Cio  
3.3 V  
(1) All typical values are at VCC = 3.3 V, TA = 25°C.  
(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to  
another.  
(3) For I/O ports, the parameter IOZ includes the input leakage current.  
SWITCHING CHARACTERISTICS  
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)  
VCC = 2.5 V  
± 0.2 V  
VCC = 3.3 V  
± 0.3 V  
VCC = 1.8 V  
VCC = 2.7 V  
MIN MAX  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
TYP  
MIN  
1
MAX  
MIN  
1
MAX  
(1)  
tpd  
ten  
tdis  
A or B  
OE  
B or A  
B or A  
B or A  
4.9  
6.8  
6.3  
4.7  
6.7  
5.7  
4.2  
5.6  
5.5  
ns  
ns  
ns  
(1)  
(1)  
1
1
OE  
1
1
(1) This information was not available at the time of publication.  
5
SN74ALVCHR16245  
16-BIT BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES064G–DECEMBER 1995–REVISED OCTOBER 2004  
OPERATING CHARACTERISTICS  
TA = 25°C  
VCC = 1.8 V  
VCC = 2.5 V  
VCC = 3.3 V  
PARAMETER  
TEST CONDITIONS  
UNIT  
TYP  
TYP  
24  
4
TYP  
32  
5
(1)  
Outputs enabled  
Outputs disabled  
Power dissipation  
capacitance  
Cpd  
CL = 50 pF, f = 10 MHz  
pF  
(1)  
(1) This information was not available at the time of publication.  
6
SN74ALVCHR16245  
16-BIT BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
www.ti.com  
SCES064G–DECEMBER 1995–REVISED OCTOBER 2004  
PARAMETER MEASUREMENT INFORMATION  
V
LOAD  
S1  
Open  
R
L
From Output  
Under Test  
TEST  
S1  
GND  
t
Open  
V
LOAD  
GND  
pd  
/t  
/t  
C
t
t
L
PLZ PZL  
R
L
(see Note A)  
PHZ PZH  
LOAD CIRCUIT  
INPUT  
V
CC  
V
M
V
LOAD  
C
L
R
L
V
∆
V
I
t /t  
r f  
1.8 V  
V
V
2.7 V  
2.7 V  
V
/2  
/2  
2 × V  
2 × V  
6 V  
6 V  
1 kΩ  
500 Ω  
500 Ω  
500 Ω  
0.15 V  
0.15 V  
0.3 V  
≤2 ns  
≤2 ns  
≤2.5 ns  
≤2.5 ns  
30 pF  
30 pF  
50 pF  
50 pF  
CC  
CC  
CC  
2.5 V ± 0.2 V  
2.7 V  
V
CC  
CC  
CC  
1.5 V  
1.5 V  
3.3 V ± 0.3 V  
0.3 V  
t
w
V
I
V
I
V
M
V
M
Input  
Timing  
Input  
V
M
0 V  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
t
su  
t
h
V
I
Output  
Control  
(low-level  
enabling)  
Data  
Input  
V
I
V
V
M
M
V
M
V
M
0 V  
0 V  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
t
t
PLZ  
PZL  
Output  
Waveform 1  
S1 at V  
LOAD  
(see Note B)  
V
V
/2  
LOAD  
V
I
V
M
Input  
V
M
V
M
V + V  
∆
OL  
0 V  
OL  
t
t
PZH  
PHZ  
t
t
PHL  
PLH  
Output  
Waveform 2  
S1 at GND  
V
OH  
V
V
OH  
V
OH  
− V  
∆
V
M
Output  
V
M
V
M
0 V  
OL  
(see Note B)  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
NOTES: A. C includes probe and jig capacitance.  
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.  
O
D. The outputs are measured one at a time, with one transition per measurement.  
E.  
F.  
G.  
t
t
t
and t  
and t  
and t  
are the same as t  
.
dis  
.
PLZ  
PZL  
PLH  
PHZ  
are the same as t  
PZH  
en  
are the same as t .  
PHL pd  
H. All parameters and waveforms are not applicable to all devices.  
Figure 1. Load Circuit and Voltage Waveforms  
7
PACKAGE OPTION ADDENDUM  
www.ti.com  
4-Oct-2005  
PACKAGING INFORMATION  
Orderable Device  
74ALVCHR16245GRE4  
74ALVCHR16245LRG4  
74ALVCHR16245ZQLR  
SN74ALVCHR16245GR  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
TSSOP  
DGG  
48  
48  
56  
48  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SSOP  
VFBGA  
TSSOP  
DL  
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
ZQL  
DGG  
1000 Green (RoHS &  
no Sb/Br)  
SNAGCU  
Level-1-260C-UNLIM  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74ALVCHR16245KR  
SN74ALVCHR16245LR  
ACTIVE  
ACTIVE  
VFBGA  
SSOP  
GQL  
DL  
56  
48  
1000  
TBD  
SNPB  
Level-1-240C-UNLIM  
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan  
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS  
&
no Sb/Br)  
-
please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 1  
MECHANICAL DATA  
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001  
DL (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
48 PINS SHOWN  
0.025 (0,635)  
48  
0.0135 (0,343)  
0.008 (0,203)  
0.005 (0,13)  
M
25  
0.010 (0,25)  
0.005 (0,13)  
0.299 (7,59)  
0.291 (7,39)  
0.420 (10,67)  
0.395 (10,03)  
Gage Plane  
0.010 (0,25)  
0°–ā8°  
1
24  
0.040 (1,02)  
0.020 (0,51)  
A
Seating Plane  
0.004 (0,10)  
0.008 (0,20) MIN  
PINS **  
0.110 (2,79) MAX  
28  
48  
0.630  
56  
DIM  
0.380  
(9,65)  
0.730  
A MAX  
A MIN  
(16,00) (18,54)  
0.370  
(9,40)  
0.620  
0.720  
(15,75) (18,29)  
4040048/E 12/01  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).  
D. Falls within JEDEC MO-118  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
MECHANICAL DATA  
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998  
DGG (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
48 PINS SHOWN  
0,27  
0,17  
M
0,08  
0,50  
48  
25  
6,20  
6,00  
8,30  
7,90  
0,15 NOM  
Gage Plane  
0,25  
1
24  
0°–8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
48  
56  
64  
DIM  
A MAX  
12,60  
12,40  
14,10  
13,90  
17,10  
16,90  
A MIN  
4040078/F 12/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
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