74LVC377APY9 [IDT]
SSOP-20, Reel;型号: | 74LVC377APY9 |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | SSOP-20, Reel |
文件: | 总6页 (文件大小:68K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
3.3V CMOS 8-BIT REGISTER
IDT74LVC377A
WITH CLOCK ENABLE
AND 5 VOLT TOLERANT I/O
DESCRIPTION:
FEATURES:
This 8-bit register with clock enable is built using advanced dual metal
CMOStechnology. This high-speed,lowpowerdevice is an8-bitregister
withabufferedcommonclock,bufferedoutputdrive,andsynchronousclock
enable, that is ideal for driving high capacitance loads such as memory
address anddata buses.
• 0.5 MICRON CMOS Technology
• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
• VCC = 3.3V ± 0.3V, Normal Range
• VCC = 2.7V to 3.6V, Extended Range
• CMOS power levels (0.4μ W typ. static)
• Rail-to-rail output swing for increased noise margin
• All inputs, outputs, and I/O are 5V tolerant
• Supports hot insertion
Allpins canbedrivenfromeither3.3Vor5Vdevices. This featureallows
the use ofthese devices as translators ina mixed3.3V/5Vsupplysystem.
• Available in SOIC, SSOP, QSOP, and TSSOP packages
DRIVE FEATURES:
• High Output Drivers: ±24mA
• Reduced system switching noise
APPLICATIONS:
• 5V and 3.3V mixed voltage systems
• Data communication and telecommunication systems
FUNCTIONALBLOCKDIAGRAM
CE
Ox
Q
D
Dx
CP
C
TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.
INDUSTRIAL TEMPERATURE RANGE
OCTOBER 1999
1
© 1999 Integrated Device Technology, Inc.
DSC-4589/2
IDT74LVC377A
3.3VCMOSOCTAL8-BITREGISTERWITHCLOCKENABLE
INDUSTRIALTEMPERATURERANGE
ABSOLUTEMAXIMUMRATINGS(1)
PINCONFIGURATION
Symbol
VTERM
TSTG
Description
Terminal Voltage with Respect to GND
Storage Temperature
Max
Unit
V
–0.5 to +6.5
–65 to +150
–50 to +50
–50
° C
mA
mA
IOUT
DC Output Current
1
2
3
CE
O0
D0
D1
O1
20
19
18
17
VCC
IIK
IOK
Continuous Clamp Current,
VI < 0 or VO < 0
O7
D7
D6
O6
ICC
ISS
Continuous Current through each
VCC or GND
±100
mA
NOTE:
4
5
6
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
16
15
14
13
12
O2
D2
O5
D5
7
8
D3
O3
D4
O4
CP
9
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Parameter(1)
Conditions
VIN = 0V
VOUT = 0V
VIN = 0V
Typ.
Max. Unit
10
Symbol
GND
11
CIN
Input Capacitance
Output Capacitance
I/O Port Capacitance
4.5
6
8
8
pF
pF
pF
COUT
CI/O
5.5
SOIC/ SSOP/ QSOP/ TSSOP
TOP VIEW
6.5
NOTE:
1. As applicable to the device type.
PINDESCRIPTION
Pin Names
Description
CE
CP
Ox
Dx
Clock Enable Input (Active LOW)
Clock Input
Data Outputs
Data Inputs
FUNCTION TABLE(1)
Inputs
Internal
Q Value
NC
Outputs
CE CP
Dx
X
L
Ox
Function
Hold Value
H
L
L
↑
↑
↑
NC
L
L
LoadInputData
H
H
H
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don’t Care
↑ = LOW-to-HIGH Transition
2
IDT74LVC377A
3.3VCMOSOCTAL8-BITREGISTERWITHCLOCKENABLE
INDUSTRIALTEMPERATURERANGE
DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE
FollowingConditionsApplyUnlessOtherwiseSpecified:
OperatingCondition:TA = –40°C to +85°C
Symbol
Parameter
Test Conditions
Min.
1.7
2
Typ.(1)
—
Max.
—
Unit
VIH
Input HIGH Voltage Level
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
V
—
—
VIL
Input LOW Voltage Level
Input Leakage Current
VCC = 2.3V to 2.7V
VCC = 2.7V to 3.6V
—
—
—
—
0.7
0.8
V
IIH
IIL
VCC = 3.6V
VI = 0 to 5.5V
—
—
5
µA
µ A
IOZH
IOZL
High Impedance Output Current
(3-State Output pins)
VCC = 3.6V
VO = 0 to 5.5V
—
—
10
IOFF
VIK
VH
Input/Output Power Off Leakage
Clamp Diode Voltage
VCC = 0V, VIN or VO ≤ 5.5V
—
—
—
50
µ A
V
VCC = 2.3V, IIN = –18mA
–0.7
–1.2
Input Hysteresis
VCC = 3.3V
VCC = 3.6V
—
—
100
—
—
10
mV
µA
ICCL
ICCH
ICCZ
Quiescent Power Supply Current
VIN = GND or VCC
(2)
3.6 ≤ VIN ≤ 5.5V
—
—
—
—
10
ΔICC
Quiescent Power Supply Current
Variation
One input at VCC - 0.6V, other inputs at VCC or GND
500
µ A
NOTES:
1. Typical values are at VCC = 3.3V, +25°C ambient.
2. This applies in the disabled state only.
OUTPUTDRIVECHARACTERISTICS
Symbol
Parameter
TestConditions(1)
Min.
VCC – 0.2
2
Max.
—
Unit
VOH
OutputHIGHVoltage
VCC = 2.3V to 3.6V
IOH = – 0.1mA
IOH = – 6mA
IOH = – 12mA
V
VCC = 2.3V
VCC = 2.3V
VCC = 2.7V
VCC = 3V
—
1.7
—
2.2
—
2.4
—
VCC = 3V
IOH = – 24mA
IOL = 0.1mA
IOL = 6mA
2.2
—
VOL
OutputLOWVoltage
VCC = 2.3V to 3.6V
VCC = 2.3V
—
0.2
0.4
0.7
0.4
0.55
V
—
IOL = 12mA
IOL = 12mA
IOL = 24mA
—
VCC = 2.7V
VCC = 3V
—
—
NOTE:
1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.
TA = – 40°C to + 85°C.
3
IDT74LVC377A
3.3VCMOSOCTAL8-BITREGISTERWITHCLOCKENABLE
INDUSTRIALTEMPERATURERANGE
OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C
Symbol
Parameter
Test Conditions
Typical
Unit
CPD
PowerDissipationCapacitanceperTransceiverOutputsenabled
PowerDissipationCapacitanceperTransceiverOutputsdisabled
CL = 0pF, f = 10Mhz
pF
CPD
SWITCHINGCHARACTERISTICS(1)
VCC = 2.7V
Max.
VCC = 3.3V ± 0.3V
Symbol
tPLH
tPHL
tSU
Parameter
Min.
Min.
Max.
Unit
PropagationDelay
1.5
9.5
1
8.5
ns
CP to Ox
Data Setup Time, Dx to CP
Data Hold Time, Dx to CP
Clock Enable Data Setup Time, CE to CP
Clock Enable Data Hold Time, CE to CP
CLK Pulse Width, HIGH or LOW
2.5
1.5
3
—
—
—
—
—
—
2.5
1.5
3
—
—
—
—
—
500
ns
ns
ns
ns
ns
ps
tH
tSU
tH
1.5
3.3
—
1.5
3.3
—
tW
(2)
tSK(o)
OutputSkew
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.
2. Skew between any two outputs of the same package and switching in the same direction.
4
IDT74LVC377A
3.3VCMOSOCTAL8-BITREGISTERWITHCLOCKENABLE
INDUSTRIALTEMPERATURERANGE
TESTCIRCUITSANDWAVEFORMS
TESTCONDITIONS
VIH
VT
0V
SAME PHASE
INPUT TRANSITION
(1)
(1)
(2)
tPHL
tPHL
Symbol VCC =3.3V±0.3V VCC =2.7V VCC =2.5V±0.2V Unit
tPLH
tPLH
VOH
VT
VOL
OUTPUT
VLOAD
VIH
6
6
2 x Vcc
Vcc
V
V
2.7
1.5
300
300
50
2.7
1.5
300
300
50
VT
Vcc / 2
150
V
VIH
VT
0V
OPPOSITE PHASE
INPUT TRANSITION
VLZ
VHZ
CL
mV
mV
pF
150
LVC Link
30
Propagation Delay
VLOAD
Open
GND
VCC
DISABLE
ENABLE
VIH
VT
0V
CONTROL
INPUT
500Ω
tPZL
tPLZ
VIN
VOUT
(1, 2)
Pulse
D.U.T.
VLOAD/2
VLOAD/2
Generator
OUTPUT
NORMALLY
LOW
SWITCH
VLOAD
VT
VOL+VLZ
VOL
500Ω
RT
tPHZ
tPZH
CL
VOH
VOH-VHZ
OUTPUT
NORMALLY
HIGH
SWITCH
GND
VT
0V
LVC Link
0V
Test Circuit for All Outputs
LVC Link
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
NOTES:
1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
VIH
DATA
INPUT
SWITCHPOSITION
VT
0V
Test
Switch
VLOAD
GND
Open
tSU
tH
VIH
TIMING
INPUT
Open Drain
Disable Low
Enable Low
VT
0V
tREM
VIH
ASYNCHRONOUS
CONTROL
VT
Disable High
Enable High
0V
VIH
SYNCHRONOUS
CONTROL
All Other Tests
VT
tSU
0V
tH
VIH
LVC Link
VT
0V
Set-up, Hold, and Release Times
INPUT
tPLH1
tPHL1
VOH
VT
VOL
LOW-HIGH-LOW
OUTPUT 1
VT
PULSE
tSK (x)
tSK (x)
VOH
tW
VT
VOL
HIGH-LOW-HIGH
PULSE
OUTPUT 2
VT
LVC Link
tPLH2
tPHL2
Pulse Width
tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1
LVC Link
Output Skew - tSK(X)
NOTES:
1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.
2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.
5
IDT74LVC377A
3.3VCMOSOCTAL8-BITREGISTERWITHCLOCKENABLE
INDUSTRIALTEMPERATURERANGE
ORDERINGINFORMATION
LVC
XX
Device Type Package
X
IDT
XXXX
XX
Bus-Hold
Temp. Range
SO
PY
Q
Small Outline IC (gull wing)
Shrink Small Outline Package
Quarter Size Small Outline Package
PG
Thin Shrink Small Outline Package
377A 8-bit Register with Clock Enable, 24mA
Blank No Bus-hold
-40°C to +85°C
74
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6
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