74LVCH16646APA8 [IDT]

Bus Driver/Transceiver;


型号：	74LVCH16646APA8
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Bus Driver/Transceiver
文件：	总8页 (文件大小：118K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

IDT74LVCH16646A

3.3VCMOS16-BITBUSTRANSCEIVER/REGISTER

INDUSTRIALTEMPERATURERANGE

IDT74LVCH16646A

3.3V CMOS 16-BIT BUS

TRANSCEIVER/REGISTER

WITH 3-STATE OUTPUTS,

5 VOLT TOLERANT I/O AND BUS-HOLD

FEATURES:

DESCRIPTION:

• Typical tSK(o) (Output Skew) < 250ps

The LVCH16646A 16-bit bus transceiver and register is built using

advanced dual metal CMOS technology. This high-speed, low power

device is organizedas twoindependent8-bitD-type transceivers with3-

state D-type registers.The controls circuitry is organized for multiplexed

transmission of data between A bus and B bus either directly or from the

internalstorageregisters.Each8-bittransceiver/registerfeaturesdirection

control(DIR),over-ridingOutputEnablecontrol(OE)andSelectlines(SAB

andSBA)toselecteitherreal-timedataorstoreddata.Separateclockinputs

areprovidedforAandBportregisters.DataontheAorBdatabus,orboth,

canbe storedinthe internalregisters bythe low-to-hightransitions atthe

appropriateclockpins.Flow-throughorganizationofsignalpins simplifies

layout.Allinputs are designedwithhysteresis forimprovednoise margin.

Allpinscanbedrivenfromeither3.3Vor5Vdevices. Thisfeatureallows

the use of this device as a translator in a mixed 3.3V/5V supply system.

TheLVCH16646Ahas beendesignedwitha ±24mAoutputdriver.This

driver is capable of driving a moderate to heavy load while maintaining

speedperformance.

• ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

machine model (C = 200pF, R = 0)

• VCC = 3.3V ± 0.3V, Normal Range

• VCC = 2.7V to 3.6V, Extended Range

• CMOS power levels (0.4μ W typ. static)

• All inputs, outputs, and I/O are 5V tolerant

• Supports hot insertion

• Available in TSSOP and TVSOP packages

DRIVE FEATURES:

• High Output Drivers: ±24mA

• Reduced system switching noise

APPLICATIONS:

• 5V and 3.3V mixed voltage systems

• Data communication and telecommunication systems

The LVCH16646A has “bus-hold” which retains the inputs’ last state

whenevertheinputgoestoahighimpedance. Thispreventsfloatinginputs

andeliminates the needforpull-up/downresistors.

FUNCTIONALBLOCKDIAGRAM

2OE

1OE

1DIR

2DIR

2CLKBA

1CLKBA

2SBA

1SBA

2CLKAB

1CLKAB

2SAB

2A1

1SAB

One of Eight Channels

1A1 ⁵

1B1

2B1

TO SEVEN OTHER CHANNELS

TheIDTlogoisaregisteredtrademarkofIntegratedDeviceTechnology,Inc.

INDUSTRIAL TEMPERATURE RANGE

JUNE 2006

DSC-3787/4

IDT74LVCH16646A

3.3VCMOS16-BITBUSTRANSCEIVER/REGISTER

INDUSTRIALTEMPERATURERANGE

ABSOLUTEMAXIMUMRATINGS⁽¹⁾

PINCONFIGURATION

Symbol

VTERM

TSTG

Description

Terminal Voltage with Respect to GND

Storage Temperature

Max

Unit

–0.5 to +6.5

–65 to +150

–50 to +50

–50

° C

1OE

1DIR

IOUT

DC Output Current

1CLKBA

1CLKAB

IIK

IOK

Continuous Clamp Current,

VI < 0 or VO < 0

1SBA

GND

1B1

1SAB

GND

1A1

ICC

ISS

Continuous Current through each

VCC or GND

±100

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation

of the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

1B2

VCC

1A2

VCC

1B3

1B4

1A3

1A4

1B5

1A5

GND

1A6

CAPACITANCE (TA = +25°C, F = 1.0MHz)

GND

1B6

Symbol

Parameter⁽¹⁾

Conditions

VIN = 0V

VOUT = 0V

VIN = 0V

Typ.

Max. Unit

CIN

Input Capacitance

Output Capacitance

I/O Port Capacitance

4.5

COUT

CI/O

6.5

1A7

1B7

1B8

2B1

6.5

1A8

2A1

NOTE:

1. As applicable to the device type.

2B2

2A2

2B3

GND

2A3

GND

2B4

2B5

2A4

2A5

PINDESCRIPTION

Pin Names

Description

2B6

VCC

2B7

2A6

VCC

2A7

xAx

Data Register A Inputs⁽¹⁾

Data Register B Outputs

DataRegisterBInputs⁽¹⁾

DataRegisterAOutputs

Clock Pulse Inputs

xBx

2B8

2A8

xCLKAB, xCLKBA

xSAB, xSBA

xOE

GND

OutputDataSourceSelectInputs

OutputEnableInputs

2SBA

2SAB

xDIR

DirectionControlInputs

2CLKBA

2CLKAB

NOTE:

1. These pins have "Bus-Hold". All other pins are standard inputs, outputs, or I/Os.

2OE

2DIR

TSSOP/ TVSOP

TOP VIEW

IDT74LVCH16646A

3.3VCMOS16-BITBUSTRANSCEIVER/REGISTER

INDUSTRIALTEMPERATURERANGE

FUNCTIONTABLE⁽¹⁾

(2)

Inputs

Data I/O

xOE

xDIR

xCLKAB

xCLKBA

xSAB

xSBA

xAx

Input

xBx

Operation or Function

Store A, Bunspecified⁽²⁾

Store B, Aunspecified⁽²⁾

Store A and B data

↑

Unspecified

Input

Unspecified

Input

↑

Input

H or L

Input

Isolation,holdstorage

Output

Input

Real time B data to A bus

Stored B data to A bus

Real time A data to B bus

Stored A data to B bus

H or L

Input

Output

H or L

Input

NOTES:

1. H = HIGH Voltage Level

X = Don’t Care

L = LOW Voltage Level

↑ = LOW-to-HIGH transition

2. The data output functions may be enabled or disabled by various signals at the xOE or xDIR inputs. Data input functions are always enabled, i.e. data at the bus pins will

be stored on every LOW-to-HIGH transition of the clock inputs.

DCELECTRICALCHARACTERISTICSOVEROPERATINGRANGE

FollowingConditionsApplyUnlessOtherwiseSpecified:

OperatingCondition:TA = –40°C to +85°C

Symbol

Parameter

Test Conditions

Min.

1.7

Typ.⁽¹⁾

—

Max.

—

Unit

VIH

Input HIGH Voltage Level

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

VIL

Input LOW Voltage Level

Input Leakage Current

VCC = 2.3V to 2.7V

VCC = 2.7V to 3.6V

—

0.7

0.8

IIH

IIL

VCC = 3.6V

VI = 0 to 5.5V

—

µA

µ A

IOZH

IOZL

IOFF

VIK

High Impedance Output Current

(3-State Output pins)

VCC = 3.6V

VO = 0 to 5.5V

—

Input/Output Power Off Leakage

Clamp Diode Voltage

VCC = 0V, VIN or VO ≤ 5.5V

—

µ A

VCC = 2.3V, IIN = –18mA

–0.7

–1.2

Input Hysteresis

VCC = 3.3V

VCC = 3.6V

—

100

—

µA

ICCL

ICCH

ICCZ

Quiescent Power Supply Current

VIN = GND or VCC

(2)

3.6 ≤ VIN ≤ 5.5V

—

ΔICC

Quiescent Power Supply Current

Variation

One input at VCC - 0.6V, other inputs at VCC or GND

500

µ A

NOTES:

1. Typical values are at VCC = 3.3V, +25°C ambient.

2. This applies in the disabled state only.

IDT74LVCH16646A

3.3VCMOS16-BITBUSTRANSCEIVER/REGISTER

INDUSTRIALTEMPERATURERANGE

BUS

xCLKBA xSAB

xOE xCLKAB

xSBA

xDIR

xCLKBA xSAB

xDIR xOE xCLKAB

xSBA

Real-Time Transfer

Bus A to B

Real-Time Transfer

Bus B to A

BUS

xCLKBA xSAB

xOE xCLKAB

xSBA

xCLKBA xSAB

xDIR

xOE xCLKAB

xSBA

xDIR

↑

H or L

↑

H or L

↑

Storage from

A, B, or A and B

Transfer Stored

Data to A and/or B

IDT74LVCH16646A

3.3VCMOS16-BITBUSTRANSCEIVER/REGISTER

INDUSTRIALTEMPERATURERANGE

BUS-HOLDCHARACTERISTICS

Symbol

IBHH

Parameter⁽¹⁾

Test Conditions

VI = 2V

Min.

–75

Typ.⁽²⁾

—

Max.

—

Unit

Bus-HoldInputSustainCurrent

VCC = 3V

µ A

IBHL

VI = 0.8V

—

IBHH

Bus-HoldInputSustainCurrent

Bus-HoldInputOverdrive Current

VCC = 2.3V

VCC = 3.6V

VI = 1.7V

—

µ A

IBHL

VI = 0.7V

—

IBHHO

VI = 0 to 3.6V

—

±500

IBHLO

NOTES:

1. Pins with Bus-Hold are identified in the pin description.

2. Typical values are at VCC = 3.3V, +25°C ambient.

OUTPUTDRIVECHARACTERISTICS

Symbol

Parameter

TestConditions⁽¹⁾

Min.

VCC – 0.2

Max.

—

Unit

VOH

OutputHIGHVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

IOH = – 0.1mA

IOH = – 6mA

IOH = – 12mA

—

VCC = 2.3V

1.7

—

VCC = 2.7V

2.2

—

VCC = 3V

2.4

—

VCC = 3V

IOH = – 24mA

IOL = 0.1mA

IOL = 6mA

—

VOL

OutputLOWVoltage

VCC = 2.3V to 3.6V

VCC = 2.3V

—

0.2

0.4

0.7

0.4

0.55

—

IOL = 12mA

IOL = 24mA

—

VCC = 2.7V

VCC = 3V

—

NOTE:

1. VIH and VIL must be within the min. or max. range shown in the DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table for the appropriate VCC range.

TA = – 40°C to + 85°C.

OPERATING CHARACTERISTICS, VCC = 3.3V ± 0.3V, TA = 25°C

Symbol

Parameter

Test Conditions

Typical

Unit

CPD

PowerDissipationCapacitanceperTransceiverOutputsenabled

PowerDissipationCapacitanceperTransceiverOutputsdisabled

CL = 0pF, f = 10Mhz

CPD

IDT74LVCH16646A

3.3VCMOS16-BITBUSTRANSCEIVER/REGISTER

INDUSTRIALTEMPERATURERANGE

SWITCHINGCHARACTERISTICS⁽¹⁾

VCC = 2.7V

Max.

VCC = 3.3V ± 0.3V

Symbol

fMAX

tPLH

tPHL

tPLH

tPHL

tPLH

tPHL

tPZH

tPZL

tPZH

tPZL

tPHZ

tPLZ

tPHZ

tPLZ

tSU

Parameter

Min.

150

—

Min.

150

1.3

Max.

—

Unit

MHz

—

PropagationDelay

6.8

5.7

xAx to xBx or xBx to xAx

PropagationDelay

—

3.2

7.9

9.2

8.5

7.7

7.8

—

1.8

1.7

1.3

1.4

2.1

6.7

7.7

6.9

7.2

6.9

xCLKBA or xCLKAB to xAx or xBx

PropagationDelay

xSBA or xSAB to xAx or xBx

OutputEnableTime

xOE to xAx or Bx

OutputEnableTime

xDIR to xAx or Bx

OutputDisableTime

xOE to xAx or Bx

OutputDisableTime

xDIR to xAx or Bx

Set-upTime

2.9

0.3

—

xAx or xBx before CLKAB↑ or CLKBA↑

HoldTime

xAx or xBx after CLKAB↑ or CLKBA↑

Pulse Duration, CLK HIGH or LOW

3.3

—

3.3

—

(2)

tSK(o)

OutputSkew

—

500

NOTES:

1. See TEST CIRCUITS AND WAVEFORMS. TA = – 40°C to + 85°C.

2. Skew between any two outputs of the same package and switching in the same direction.

IDT74LVCH16646A

3.3VCMOS16-BITBUSTRANSCEIVER/REGISTER

INDUSTRIALTEMPERATURERANGE

TESTCIRCUITSANDWAVEFORMS

TESTCONDITIONS

VIH

SAME PHASE

INPUT TRANSITION

tPHL

tPLH

(1)

(2)

Symbol VCC =3.3V±0.3V VCC =2.7V VCC =2.5V±0.2V Unit

VOH

VOL

OUTPUT

VLOAD

VIH

2 x Vcc

Vcc

2.7

1.5

300

2.7

1.5

300

VIH

OPPOSITE PHASE

INPUT TRANSITION

Vcc / 2

150

VLZ

VHZ

LVC Link

150

Propagation Delay

DISABLE

ENABLE

VLOAD

Open

GND

VIH

VCC

CONTROL

INPUT

tPZL

tPLZ

500Ω

VIN

VLOAD/2

VOUT

VLOAD/2

OUTPUT

NORMALLY

LOW

(1, 2)

Pulse

SWITCH

CLOSED

D.U.T.

VLZ

VOL

Generator

tPHZ

tPZH

500Ω

VOH

VHZ

OUTPUT

NORMALLY

HIGH

SWITCH

OPEN

LVC Link

Test Circuit for All Outputs

Enable and Disable Times

NOTE:

DEFINITIONS:

CL = Load capacitance: includes jig and probe capacitance.

1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.

RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.

NOTES:

1. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.

2. Pulse Generator for All Pulses: Rate ≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.

VIH

DATA

INPUT

tSU

SWITCHPOSITION

VIH

TIMING

INPUT

Test

Switch

V^LOAD

GND

Open

tREM

VIH

Open Drain

Disable Low

Enable Low

ASYNCHRONOUS

CONTROL

VIH

SYNCHRONOUS

CONTROL

Disable High

Enable High

tSU

LVC Link

All Other Tests

Set-up, Hold, and Release Times

VIH

LOW-HIGH-LOW

INPUT

tPLH1

tPHL1

PULSE

VOH

OUTPUT 1

OUTPUT 2

VOL

tSK (x)

HIGH-LOW-HIGH

PULSE

tSK (x)

VOH

VOL

LVC Link

Pulse Width

tPLH2

tPHL2

tSK(x) = tPLH2 - tPLH1 or tPHL2 - tPHL1

LVC Link

Output Skew - tSK(X)

NOTES:

1. For tSK(o) OUTPUT1 and OUTPUT2 are any two outputs.

2. For tSK(b) OUTPUT1 and OUTPUT2 are in the same bank.

IDT74LVCH16646A

3.3VCMOS16-BITBUSTRANSCEIVER/REGISTER

INDUSTRIALTEMPERATURERANGE

ORDERINGINFORMATION

IDT

XXXX

LVC

Device Type Package

Bus-Hold

Family

Temp. Range

Thin Shrink Small Outline Package

TSSOP - Green

Thin Very Small Outline Package

PAG

TVSOP - Green

PFG

16-Bit Bus Transceiver/Register with

3-State Outputs and 5 Volt Tolerant I/O

646A

Double-Density, 24mA

Bus-hold

-40°C to +85°C

CORPORATE HEADQUARTERS

6024 Silver Creek Valley Road

San Jose, CA 95138

for SALES:

800-345-7015 or 408-284-8200

fax: 408-284-2775

for Tech Support:

logichelp@idt.com

www.idt.com

74LVCH16646APA8 [IDT]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E