75P52100S100BS [IDT]

Telecom IC;


型号：	75P52100S100BS
厂家：	INTEGRATED DEVICE TECHNOLOGY
描述：	Telecom IC
文件：	总3页 (文件大小：435K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Datasheet

Brief

75P52100

NETWORK SEARCH ENGINE

64K x 72 Entries

To request the full IDT75P52100 datasheet, please contact your local

IDT Sales Representative or call 1-800-345-7015

DeviceDescription

BlockDiagram

IDT provides proven, industry-leading network search engines

(NSEs)andacomprehensivesuiteofsoftwarethatenableandaccelerate

theintelligentprocessingofnetworkservicesincommunicationsequip-

ment.AsapartofthecompleteIDTclassificationsubsystemthatincludes

content inspection engines, the IDT family of NSEs delivers high-

performance,feature-rich,easy-to-use,integratedsearchaccelerators.

TheIDT 75P52100NSEisahighperformancepipelinedlow-power,

synchronous full-ternary 64K x 72 entry device. Each entry location in

theNSEhasbothaDataentryandanassociatedMaskentry. TheNSE

devicesintegratecontentaddressablememory(CAM)technologywith

high-performancelogic. ThedevicecanperformLookupandLearnNSE

operationsplusRead,Write,BurstWrite,andDualWritemaintenance

operations.

The IDT 75P52100 NSE device has a bi-directional bus that is a

multiplexedaddressanddatabusthatcansupport100millionsustained

searchespersecond. Thisdeviceprovidesarraysegmentswhichcan

beconfiguredtoenablemultiplewidthlookupsfrom36to576bitswide.

TheIDT75P52100requiresa1.8-voltVDDsupply,auserselectable1.8

or2.5-voltVDDQ supply,anda2.5-voltVBIAS supply. This NSEdevice

provides the user with flexibility and control in determining the device

power. Only the array segments that will be used for a specific NSE

operation are powered up while the unused segments are not.

The IDT 75P52100 utilizes IDT’s latest high-performance 1.8V

CMOSprocessingtechnologyandis packagedinaJEDECStandard,

thermallyenhanced, lowprofile BallGridArray. The options include a

304 BGA, satisfying smaller footprint requirements and a 372 BGA

package that is compatible with IDT's 32K x 72 Entry (75P42100) and

128K x 72 Entry (75P62100) NSE devices.

LAST NSE

Configuration Registers

and

SRAM CONTROL

ASIC FEEDBACK

LAST SRAM

Ram Control Circuits

CLOCK

CCLK

PHASE

Counter

BURST

RESET

Index

Bus

ARRAY

REQSTB

R/W

NSE

RESPONSE

BUS

Instruction

Command

Bus

NSE

REQUEST

BUS

Request

Data

Address

Bypass

DATA

Bus

Comparand Registers

Global Mask Registers

Result Register

MMOUT

MATCHOUT

5333 drw 01

SystemConfigurations

TheIDTNSEs aredesignedtofulfilltheneeds ofvarious types of

networking systems. In solutions requiring data searching such as

routers,asystemconfigurationasshowninFigure1.0mayberealized.

Maximum flexibility is provided by allowing one board design to be

populatedtodayusingeithertheIDT75P42100or75P52100NSEsand

laterupgradedtouseIDT’s75K62100NSE.ApplicationsnoteAN-279

discusseshowtoaccommodateoneboarddesignforanyoftheseNSEs.

Inthiscompatibleconfiguration,theNSEinterfacesdirectlytoan

ASIC/FPGAforlookups androutes anIndextoanassociatedSRAM

device,whichsuppliesthenexthopaddressviaanSRAMDataBusto

the ASIC. The NSE provides the required control signals to directly

hookuptoZBT™orSynchronousPipelineBurstSRAM. Lookupresults

canalsobefeddirectlybacktotheASIC/FPGAwithouttheuseofexternal

SRAM.Controloftheassociatedhandshakesignalsisprovidedbyall

NSEstoadapttoeitherconfiguration.

Figure 1.0 ASIC / Compatible NSE / SRAM configuration

Optional

IDT

75P42100

ASIC

ZBT

75P52100

SyncSRAM

FPGA

75K62100

Network Search Engine

5333 drw02

JUNE 2003

DSC-5333/03



Network Search Engine 64K x 72 Entries

Datasheet Brief 75P52100

Features

■ SRAM No Wait Read

■

AnSRAMNoWaitReadisaReadinstructiontoanexternalSRAMthat

canbepipelinedwithinaseriesofoperationsanddoesnotrequiretheuser

towaitfortheReadtocompletebeforeloadingthenextinstruction.

Full Ternary 64K x 72 bit content addressable memory

■

Upgradeable to 128K x 72 NSE

■

PowerManagement

■DualWrite

■

GlobalMaskRegisters

In addition to individual writes, the NSE has the ability to perform

simultaneous writes to a Data entry and a respective external SRAM

location.

■

Segmentsindividuallyconfigurable

■

36/72/144/288/576multiplewidthlookups

■

100Msustainedlookups persecondat72and144widthlookups

■ Lookup

■

Alookupcanberequestedin72-bit,144-bit,288-bitor576-bitwidths.

A36-bitlookupcanbeaccomplishedbyusingtwoGlobalMaskRegisters.

■ Learn

The NSE implements a fully autonomous Learn Instruction, which

providesamechanismfortheusertowritealookupentryintoanunused

Burstwriteforhighspeedtableupdates

■

Multi-match

■

Learn new entries

■

Dualbusinterface

■

Cascadable to8devices withnoglue logicorlatencypenalty

locationintheNSEandtheassociateddatainexternalSRAM.

Thisallows

■

GluelessinterfacetostandardZBT™or

the user to update an entry into the NSE which had not previously been

stored. The Learn writes the new entry, making it available for future

lookups.

SynchronousPipelinedBurstSRAMs

■

BoundaryScanJTAGInterface(IEEE1149.1compliant)

■

1.8V core power supply

SRAM Interface

■

2.5V VBIASpower supply

The NSE provides all required address and control signals for a

gluelessSRAMinterface. TheNSEprovidesapipelinedbypasspathfor

reads or writes to the external SRAM. The ASIC/FPGA handles the

pipeliningofthedatatoandfromtheSRAM.

■

User selectable 2.5V or 1.8V I/O supply

FunctionalHighlights

Data and Mask Array

Mask

Registers

The NSEhas Data cellentries andassoci-

There are fourbasictypes ofregisters supported:

■ ConfigurationRegistersareusedatinitializationtodefinethe

segmentationoftheentries,timingofoutputsandtheSRAMinterface.

■ GlobalMaskRegisters are providedtosupportLookup

instructionsbymaskingindividualbitsduringasearch.

■ ComparandRegistersassistintheLearnInstruction.

■ ResultRegisters are usedtostore the resultingindexofa search

from a Lookup or Learn operation.

Data

atedMaskcellentriesasshowninFig.1.1. This

combinationofData andMaskcellentries en-

ables theNSEtostore0,1orX,makingitafull

ternary Network Search Engine. During a

lookup operation, both arrays are used along

withaGlobalMaskRegistertofindamatchtoa

requesteddataword.

A5333drw03

Figure 1.1

Bus Interface

Synchronous Burst Write

Theburstwritefeaturehasnolimitonthenumberofcontinuouswrite

accessesandsupportsinitializationoftheNSE.

TheNSEutilizesadualbusinterfaceconsistingoftheNSERequest

Bus and the NSE Response Bus.

The NSERequestBus is comprisedofthe CommandBus andthe

RequestDataBus. TheCommandBushandlestheinstructiontotheNSE

whiletheRequestDataBus is themaindatapathtotheNSE.

The72bitbi-directionalRequestDataBusfunctionsasamultiplexed

address and data bus, which performs the writing and reading of NSE

entries,as wellas presentinglookupdatatothedevice.

TheNSEResponseBus is comprisedofanindependentunidirec-

tionalIndexBuswhichdrivestheresultofthelookup(orindex)toeither

an SRAM device or an ASIC. In addition to driving the Index, the NSE

ResponseBusalsodrivestheassociatedSRAMcontrolsignals(CE/OE,

andWE)foreitherZBT™ orSynchronousPipelineBurst SRAMdevices.

Width Segmentation Capability

TheNSEsarecapableofperforminglookupsforcomparisonsondata

structuresof72bits,144bits,288bits and576bits. Thesedeviceshas

canbeconfiguredtomeetvarioussystemrequirements.

■ SingleWidthArray

■ MultipleWidthArrayswithinaSingleDevice

Multi Match

TheMulti-Matchfeaturesignalstotheuserthatmorethanonematch

hasresulted. Theresultofthelookup,whichdefinesthehighestpriority

match,issentalongwiththeMulti-Matchsignal.

Command Bus

TheCommandBusloadsthespecificinstructionsintotheNSE.These

include:

Power Savings and Classification Features

SeethefullIDT75P52100Datasheetformoreinformation.

■ ReadorWrite

AReadorWriteinstructionoperatesonaspecifieddataentry,mask

entry, or register.

Network Search Engine 64K x 72 Entries

Datasheet Brief 75P52100

SignalDescriptions

Pin Function

I/O

Description

NSE Request Bus:

Request Strobe

Instruction

Input

This input signifies a valid input request and signals the startof an NSE operation cycle.

These two fields of the Command bus define the instruction to be performed by the NSE and the lookup

type. The lookup type is selected only for operational type commands (Lookups, Learns) and is a "don't

care" for maintenance type commands (all Reads and Writes).

Lookup Type

This field is within the Command bus. During Lookup or Write operations, this field defines which of the

Global Mask Register groups are being accessed. This field is a "don't care" for Read, SRAM No Wait

Read, and Learn Operations.

Command

Bus

Global Mask

Input

Comparand and

Result Register

Select

This is a multiplexed field within the Command Bus that specifies both the Result Register to store the

Index into, and the Comparand Register to use. This field is sampled every inputclock cycle. The first

cycle decodes the selected Comparand Register and the second decodes the selected Result Register.

Input/Output The Request Data Bus is a multiplexed address/data bus used to perform reads (and writes) from (to) the

Three State NSE, and to present search data for lookups.

Request Data Bus

NSE Response Bus:

Address

This bus is used to drive the address of an external SRAM, or feedback Lookup result information

directly to the NSE's ASIC/FPGA. The Index Bus contain the encoded location at which the compare was

found, the address of the NSE which found the result and the Lookup type.

Output

Three State

Index Bus

Device ID

Lookup Type

Output

This signal is driven along with the Index Bus. It is connected to the CE input pin of a ZBT SRAM or to the

Chip Enable/ Output Enable

Write Enable

Three State OE pin of a PBSRAM.

Output

This signal is driven along with the Index bus. It is used to assert the WE pin of an external SRAM. It is

Three State active for both SRAM write operations and the Learn command.

This signal is sent back when the data is read from the NSE on the Request Data Bus, or when the data

being read from the associated external SRAM.

Read Acknowledge

Match Acknowledge

Output

This is signal is sentwith the Index. It will be driven low if there was no match, high if a match was found.

Valid

Lookup Bit

This signal is sent with the Index. It will be driven high upon the completion of a lookup, even if the

lookup did not result in a hit.

This signal is sent with the Index. It shall go active when a) multiple hits occur in one segment; or, b) one

or more hits occur in two (or more) segments; or, c) one or more hits occur in multiple devices that are

depth cascaded.

Multi Match

Output

(Open Drain)

Depth Expansion:

These three DC pins are used to define the Device Address for each of the eight possible depth

expanded NSE devices in an NSE system.

Device Address

Input

Match

Input

The Match Input signal is driven by all upstream Match Output signals. This indicates to all down stream

NSEs that a hit in a higher priority NSE has occurred.

Match

Output

The Match Output signal signifies that a match has occurred in the NSE. The signal is fed into a Match

Input line of all lower priority NSE(s).

Output

Clock and Initialization:

Clock Input

Input

All inputs and outputs are referenced to the positive edge of this clock.

Clock Phase Enable

Reset

This signal is used to generate an internal clock at ½ the frequency of the input clock.

This pin will force all outputs to a high impedence condition, as well as clearing the NSE enable bit.

This signal will advance an internal address counter to allow for burst writes when writing to the Data/Mask

memory in the NSE. This provides a mechanism to conveniently initialize the NSE memory.

Advance Burst Address

Last NSE

Input

This pin defines which NSE device will drive the ASIC Feedback signals to the ASIC/FPGA.

This pin defines which NSE device will drive the SRAM control signals CE/OE and WE. It also defaults

this device to driving the Index Bus when there is no ongoing operation preventing the bus from floating.

Last SRAM

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6.42

75P52100S100BS [IDT]

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