810252AGILF [IDT]
VCXO and Synchronous Ethernet Jit ter At tenuator;
| 型号： | 810252AGILF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | VCXO and Synchronous Ethernet Jit ter At tenuator 时钟 光电二极管 外围集成电路 石英晶振 压控振荡器 晶体 |
| 文件： | 总16页 (文件大小：257K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VCXO and Synchronous Ethernet
Jitter Attenuator
810252I
Data Sheet
General Description
Features
The 810252I is a high performance, low jitter/low phase noise
VCXO. The 810252I uses a low frequency and low cost pullable
crystal to achieve jitter attenuation for synchronous Ethernet
applications. The 810252I can take an input of 25MHz and produce
two LVCMOS outputs of 25MHz.
• Two single-ended outputs (LVCMOS or LVTTL levels),
output Impedance: 15
• Phase jitter attenuation by the VCXO-PLL using a 25MHz pullable
external crystal (XTAL)
• Input frequencies: 25MHz or 125MHz
• Output frequency: 25MHz
The device is packaged in a small 16 lead TSSOP package and is
ideal for use on space constrained boards typically encountered in
most synchronous ethernet applications.
• PLL loop bandwidth adjustable by external components
• Full 3.3V or 2.5V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in lead-free (RoHS 6) package
Applications
• Synchronous Ethernet v0.39a
• End equipment compliant with Std IEEE 802.039a
Pin Assignment
Block Diagram
CLK_IN
VDD
PLL_SEL
GND
Q0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
(External Loop Filter Inputs)
LF1
LF1
LF0
PLL_SEL
OE
Q1
VDDO
OE
LF0
GND
25MHz
XTAL_IN
VDDA
VDD
10 XTAL_OUT
GND
(25MHz or 125MHz
Input Frequency Auto Detect)
9
Q0
810252I
Pre-
Divider
Pulldown
CLK_IN
PFD
CP
1
0
VCXO
25MHz
Q1
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm
package body
(÷1 or ÷5)
VCXO-PLL
G Package
Top View
©2016 Integrated Device Technology, Inc
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Revision B March 3, 2016
810252I Data Sheet
Table 1. Pin Descriptions
Number
Name
Type
Description
When logic HIGH, the VCXO-PLL is enabled. When LOW, the VCXO-PLL is in
bypass mode. LVCMOS/LVTTL interface levels.
1
PLL_SEL
Input
Pullup
Pullup
2, 9, 12
GND
Q0, Q1
VDDO
OE
Power
Output
Power
Input
Power supply ground.
3, 4
5
Single-ended clock outputs. LVCMOS/ LVTTL interface levels.
Output power supply pin.
6
Output enable pin for Qx outputs. LVCMOS/LVTTL interface levels.
Analog supply pin.
7
VDDA
VDD
Power
Power
8, 15
Core supply pins.
10,
11
XTAL_OUT,
XTAL_IN
Input
VCXO crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
Analog
Input/
Output
13, 14
16
LF0, LF1
CLK_IN
Loop filter connection node pins.
Input
Pulldown
Single-ended clock input. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
CIN
Input Capacitance
4
8
VDD, VDDO = 3.465V
VDD, VDDO = 2.625V
pF
CPD
Power Dissipation Capacitance
5
pF
RPULLUP
Input Pullup Resistor
51
51
15
20
k
k
RPULLDOWN Input Pulldown Resistor
V
DDO = 3.3V 5%
ROUT Output Impedance
VDDO = 2.5V 5%
©2016 Integrated Device Technology, Inc
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810252I Data Sheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
4.6V
Inputs, VI
XTAL_IN
Other Inputs
0V to VDD
-0.5V to VDD + 0.5V
Outputs, VO
-0.5V to VDD + 0.5V
81.2C/W (0 mps)
-65C to 150C
Package Thermal Impedance, JA
Storage Temperature, TSTG
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics, VDD = VDDO = 3.3V 5%, TA = -40°C to 85°C
Symbol
VDD
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
Units
V
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
3.465
VDD
3.465
40
VDDA
VDDO
IDD
VDD – 0.07
3.135
3.3
V
3.3
V
mA
mA
mA
IDDA
7
IDDO
No Load
5
Table 3B. Power Supply DC Characteristics, VDD = VDDO = 2.5V 5%, TA = -40°C to 85°C
Symbol
VDD
Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
Units
V
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
2.625
VDD
2.625
35
VDDA
VDDO
IDD
VDD – 0.07
2.375
2.5
V
2.5
V
mA
mA
mA
IDDA
7
IDDO
No Load
5
©2016 Integrated Device Technology, Inc
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810252I Data Sheet
Table 3C. LVCMOS/LVTTL DC Characteristics, VDD = VDDO = 3.3V 5% or 2.5V 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
VDD = 3.465V
Minimum
Typical
Maximum
Units
V
2
VDD + 0.3
Input
VIH
High Voltage
VDD = 2.625V
1.7
-0.3
-0.3
VDD + 0.3
V
VDD = 3.465V
0.8
0.7
150
5
V
Input
VIL
Low Voltage
VDD = 2.625V
V
CLK_IN
VDD = VIN = 3.465V or 2.625V
VDD = VIN = 3.465V or 2.625V
VDD = 3.465V or 2.625V, VIN = 0V
µA
µA
µA
µA
V
Input
IIH
High Current
OE, PLL_SEL
CLK_IN
-5
-150
2.6
Input
IIL
Low Current
OE, PLL_SEL
V
DD = 3.465V or 2.625V, VIN = 0V
DDO = 3.3V 5%
V
VOH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VDDO = 2.5V 5%
VDDO = 3.3V 5%
VDDO = 2.5V 5%
1.8
V
0.6
0.5
V
VOL
V
NOTE 1: Outputs terminated with 50 to VDDO/2. See Parameter Measurement Information section. Load Test Circuit diagrams.
AC Electrical Characteristics
Table 4A. AC Characteristics, VDD = VDDO = 3.3V 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
25
Maximum
Units
MHz
MHz
MHz
MHz
ps
fREF
Input Reference Frequency
125
25
fVCO
VCXO-PLL Frequency
Output Frequency
fOUT
25
tJIT(CC)
tsk(o)
Cycle-to-Cycle Jitter; NOTE 1
Output Skew; NOTE 2, 3
25
15
ps
RMS Phase Jitter (Random);
NOTE 4
f
OUT = 25MHz, Integration Range:
12kHz – 5MHz
tjit()
0.25
ps
tJIT(PER)
tR / tF
odc
Period Jitter, RMS
2.7
1100
52
ps
ps
%
%
Output Rise/Fall Time
Output Duty Cycle; NOTE 5
Output Duty Cycle; NOTE 6
20% to 80%
550
48
odc
45
55
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE: Characterized using a 537Hz VCXO-PLL Loop Bandwidth. Refer to VCXO_PLL Applications Section.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Refer to the Phase Noise Plot.
NOTE 5: Specified with the VCXO-PLL free running high.
NOTE 6: Specified with the VCXO-PLL locked.
©2016 Integrated Device Technology, Inc
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Revision B March 3, 2016
810252I Data Sheet
Table 4B. AC Characteristics, VDD = VDDO = 2.5V 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
25
Maximum
Units
MHz
MHz
MHz
MHz
ps
fREF
Input Reference Frequency
125
25
fVCO
VCXO-PLL Frequency
Output Frequency
fOUT
25
tJIT(CC)
tsk(o)
Cycle-to-Cycle Jitter; NOTE 1
Output Skew; NOTE 2, 3
20
25
ps
RMS Phase Jitter (Random);
NOTE 4
f
OUT = 25MHz, Integration Range:
12kHz – 5MHz
tjit
0.26
ps
tJIT(PER)
tR / tF
odc
Period Jitter, RMS
5.7
1850
52
ps
ps
%
%
Output Rise/Fall Time
Output Duty Cycle; NOTE 5
Output Duty Cycle; NOTE 6
20% to 80%
700
48
odc
44
56
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE: Characterized using a 537Hz VCXO-PLL Loop Bandwidth. Refer to VCXO_PLL Applications Section.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Refer to the Phase Noise Plot.
NOTE 5: Specified with the VCXO-PLL free running high.
NOTE 6: Specified with the VCXO-PLL locked.
©2016 Integrated Device Technology, Inc
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Revision B March 3, 2016
810252I Data Sheet
Typical Phase Noise (3.3V)
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc
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Revision B March 3, 2016
810252I Data Sheet
Typical Phase Noise (2.5V)
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc
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Revision B March 3, 2016
810252I Data Sheet
Parameter Measurement Information
1.65V 5%
1.65V 5%
1.25V 5%
1.25V 5%
SCOPE
V
SCOPE
DD,
V
DD,
V
DDO
V
DDO
V
DDA
V
Qx
DDA
Qx
GND
GND
-1.65V 5%
-1.25V 5%
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
2.5V Core/2.5V LVCMOS Output Load AC Test Circuit
VDDO
2
VDDO
2
VDDO
2
Q0, Q1
➤
➤
tcycle n
tcycle n+1
➤
➤
tjit(cc) = tcycle n – tcycle n+1
|
|
1000 Cycles
Cycle-to-Cycle Jitter
RMS Phase Jitter
VOH
VDDO
VREF
Qx
Qy
2
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
VDDO
2
tsk(o)
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
Period Jitter
Output Skew
©2016 Integrated Device Technology, Inc
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Revision B March 3, 2016
810252I Data Sheet
Parameter Measurement Information, continued
VDDO
2
Q0, Q1
80%
80%
tPW
tPERIOD
20%
20%
Q0, Q1
tR
tF
tPW
x 100%
odc =
tPERIOD
Output Duty Cycle/Pulse Width/Period
Output Rise/Fall Time
Application Information
Recommendations for Unused Input Pins
Inputs:
Outputs:
LVCMOS Control Pins
LVCMOS Outputs
All control pins have internal pullups; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
All unused LVCMOS outputs can be left floating. There should be no
trace attached.
©2016 Integrated Device Technology, Inc
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Revision B March 3, 2016
810252I Data Sheet
Schematic Example
Figure 1 shows an example of 810252I application schematic. In this
example, the device is operated at VDD = 3.3V. The decoupling
capacitors should be as close as possible to the power pin. The
input is driven by an LVCMOS driver. An optional 3-pole filter can
also be used for additional spur reduction. It is recommended that
the loop filter components be laid out for the 3-pole option. This will
also allow the 2-pole filter to be used.
3-pole loop filter example - (optional)
R3
LF0
LF1
Rs
TBD
VDD
TBD
VDDO
Cp
C3
C1
Cs
TBD
TBD
0.1u
TBD
C2
0.1u
VDD
VDD
R2
10
9
10
11
12
13
14
15
16
8
GND
VDD
VDDA
OE
VDDO
Q1
Q0
GND
PLL_SEL
XTAL_OU T
XTAL_IN
VDDA
7
6
5
4
3
2
1
XTAL_OUT
XTAL_IN
GND
LF0
LF1
OE
Q1
C5
SPARE
X2
C30
0.01u
C45
10u
Q0
VDD
CLK_IN
Rs
1K
PLL_SEL
C6
Cp
SPARE
Cs
0.001 uF
Zo = 50
10uF
C4
0.1u
U1
R4
33
LVCMOS_Receiv er
Logic Control Input Examples
2-pole loop filter
Set Logic
Input to
'1'
Set Logic
Input to
'0'
VDD
VDD
VDD=VDDO=3.3V
Q1
R1
33
Zo = 50
RU1
1K
RU2
Not Install
Zo = 50
LVCMOS_Driver
R5
33
To Logic
Input
To Logic
Input
pins
pins
LVCMOS_Receiv er
RD1
Not Install
RD2
1K
Figure 1. 810252I Schematic Example
©2016 Integrated Device Technology, Inc
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Revision B March 3, 2016
810252I Data Sheet
VCXO-PLL EXTERNAL COMPONENTS
Choosing the correct external components and having a proper
printed circuit board (PCB) layout is a key task for quality operation
of the VCXO-PLL. In choosing a crystal, special precaution must be
taken with the package and load capacitance (CL). In addition,
frequency, accuracy and temperature range must also be
The frequency of oscillation in the third overtone mode is not
necessarily at exactly three times the fundamental frequency. The
mechanical properties of the quartz element dictate the position of
the overtones relative to the fundamental. The oscillator circuit may
excite both the fundamental and overtone modes simultaneously.
This will cause a nonlinearity in the tuning curve. This potential
problem is why VCXO crystals are required to be tested for absence
of any activity inside a 200 ppm window at three times the
fundamental frequency. Refer to FL_3OVT and FL_3OVT_spurs in the
crystal Characteristics table.
considered. Since the pulling range of a crystal also varies with the
package, it is recommended that a metal-canned package like HC49
be used. Generally, a metal-canned package has a larger pulling
range than a surface mounted device (SMD). For crystal selection
information, refer to the VCXO Crystal Selection Application Note.
The crystal’s load capacitance CL characteristic determines its
resonating frequency and is closely related to the VCXO tuning
range. The total external capacitance seen by the crystal when
installed on a board is the sum of the stray board capacitance, IC
package lead capacitance, internal varactor capacitance and any
installed tuning capacitors (CTUNE).
The crystal and external loop filter
LF0
LF1
components should be kept as
close as possible to the device.
Loop filter and crystal traces
should be kept short and
RS
CS
CP
separated from each other. Other
signal traces should be kept
separate and not run underneath
the device, loop filter or crystal
components.
If the crystal CL is greater than the total external capacitance, the
VCXO will oscillate at a higher frequency than the crystal
XTAL_IN
CTUNE
specification. If the crystal CL is lower than the total external
capacitance, the VCXO will oscillate at a lower frequency than the
crystal specification. In either case, the absolute tuning range is
reduced. The correct value of CL is dependant on the characteristics
of the VCXO. The recommended CL in the Crystal Parameter Table
balances the tuning range by centering the tuning curve.
25MHz
XTAL_OUT
CTUNE
VCXO Characteristics Table
VCXO-PLL Loop Bandwidth Selection Table
Symbol
kVCXO
Parameter
Typical
15000
9.8
Units
Hz/V
pF
Bandwidth
Crystal
Frequency
(MHz)
RS (k)
CS (µF)
CP (µF)
VCXO Gain
CV_LOW
CV_HIGH
Low Varactor Capacitance
High Varactor Capacitance
215Hz (Low)
537Hz (Mid)
886Hz (High)
25
25
25
0.4
1.0
10
10
10
0.01
0.001
0.001
22.7
pF
1.65
Crystal Characteristics
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
Mode of Oscillation
Frequency
Fundamental
25
fN
fT
fS
MHz
ppm
ppm
0C
Frequency Tolerance
Frequency Stability
20
20
Operating Temperature Range
Load Capacitance
Shunt Capacitance
Pullability Ratio
-40
+85
CL
10
4
pF
CO
pF
CO / C1
FL_3OVT
220
240
3rd Overtone FL
200
200
ppm
ppm
FL_3OVT_spurs 3rd Overtone FL Spurs
ESR Equivalent Series Resistance
20
1
Drive Level
mW
ppm
ppm
First Year
Ten Years
3
Aging @ 25 0C
10
©2016 Integrated Device Technology, Inc
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Revision B March 3, 2016
810252I Data Sheet
Power Considerations
This section provides information on power dissipation and junction temperature for the 810252I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the 810252I is the sum of the core power plus the analog power plus the power dissipated in the load(s). The
following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
•
•
Power (core)MAX = VDD_MAX * (IDD + IDDA + IDDO) = 3.465V *(40mA + 7mA + 5mA) = 180.18mW
Output Impedance ROUT Power Dissipation due to Loading 50 to VDD/2
Output Current IOUT = VDD_MAX / [2 * (50 + ROUT)] = 3.465V / [2 * (50 + 15)] = 26.7mA
•
•
Power Dissipation on the ROUT per LVCMOS output
Power (ROUT) = ROUT * (IOUT)2 = 15 * (26.7mA)2 = 10.7mW per output
Total Power (ROUT) = 10.7mW * 2 = 21.4mW
Dynamic Power Dissipation at 25MHz
Power (25MHz) = CPD * Frequency * (VDD)2 = 8pF * 25MHz * (3.465V)2 = 2.4mW per output
Total Power (25MHz) = 2.4mW * 2 = 4.8mW
Total Power Dissipation
•
Total Power
= Power (core)MAX + Power (ROUT) + Power (25MHz)
= 180.18mW + 21.4mW + 4.8mW
= 206.38mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond
wire and bond pad temperature remains below 125°C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA
Tj = Junction Temperature
JA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and
a multi-layer board, the appropriate value is 81.2°C/W per Table 5 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.296W *81.2°C/W = 101.7°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of
board (multi-layer).
Table 5. Thermal Resistance JA for 16 Lead TSSOP, Forced Convection
JA by Velocity
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
81.2°C/W
73.9°C/W
70.2°C/W
©2016 Integrated Device Technology, Inc
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810252I Data Sheet
Reliability Information
Table 6. JA vs. Air Flow Table for a 16 Lead TSSOP
JA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
81.2°C/W
73.9°C/W
70.2°C/W
Transistor Count
The transistor count for 810252I: 1025
Package Outline and Package Dimensions
Package Outline - G Suffix for 16 Lead TSSOP
Table 7. Package Dimensions for 16 Lead TSSOP
All Dimensions in Millimeters
Symbol
Minimum
Maximum
N
A
16
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.5
0.80
0.19
0.09
4.90
c
D
E
6.40 Basic
E1
e
4.30
4.50
0.65 Basic
L
0.45
0°
0.75
8°
aaa
0.10
Reference Document: JEDEC Publication 95, MO-153
©2016 Integrated Device Technology, Inc
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Revision B March 3, 2016
810252I Data Sheet
Ordering Information
Table 8. Ordering Information
Part/Order Number
810252AGILF
Marking
Package
Shipping Packaging
Tube
Temperature
-40C to 85C
-40C to 85C
10252AIL
10252AIL
16 Lead “Lead-Free” TSSOP
16 Lead “Lead-Free” TSSOP
810252AGILFT
Tape & Reel
©2016 Integrated Device Technology, Inc
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Revision B March 3, 2016
810252I Data Sheet
Revision History Sheet
Rev
Table
Page
Description of Change
Date
T4A
4
3.3V AC Characteristics Table - Added additional odc row with specs of 45min and 55max.
Added Notes 5 & 6.
B
7/17/2012
T4B
5
1
2.5V AC Characteristics Table - Added additional odc row with specs of 44min and 56max.
Added Notes 5 & 6.
Features List: deleted ‘Absolute pull range is 80 ppm’
B
B
8/1/12
HiPerClock references have been deleted throughout the datasheet
T4A
T4B
T8
4
5
Added ‘high’ to Note 5.
Added ‘high’ to Note 5.
10/5/12
14
Deleted quantity from Tape and Reel.
Removed ICS from part numbers where needed.
Revision history - Corrected spelling errors in section one of this table.
Updated header and footer.
B
15
3/3/16
©2016 Integrated Device Technology, Inc
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Revision B March 3, 2016
810252I Data Sheet
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相关型号：
810252BKI-02
PLL Based Clock Driver, 810252 Series, 2 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.925 MM HEIGHT, MO-220VHHD-2, VFQFN-32
IDT
810252BKI-02LF
PLL Based Clock Driver, 810252 Series, 2 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32
IDT
810252BKI-02T
PLL Based Clock Driver, 810252 Series, 2 True Output(s), 0 Inverted Output(s), 5 X 5 MM, 0.925 MM HEIGHT, MO-220VHHD-2, VFQFN-32
IDT
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