813252CKI-02 [IDT]
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER; VCXO抖动衰减器和FEMTOCLOCK ™乘法器
| 型号： | 813252CKI-02 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER |
| 文件： | 总22页 (文件大小：648K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
VCXO JITTER ATTENUATOR &
FEMTOCLOCK™ MULTIPLIER
ICS813252I-02
GENERAL DESCRIPTION
FEATURES
The ICS813252I-02 is
a
member of the
• Two LVPECL outputs
ICS
HiperClockS™ family of high performance clock
solutions from IDT. The ICS813252I-02 is a PLL
based synchronous multiplier that is optimized for
PDH or SONET to Ethernet clock jitter attenuation
Each output supports independent frequency selection at
25MHz, 125MHz, 156.25MHz and 312.5MHz
HiPerClockS™
• Two differential inputs support the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
and frequency translation. The device contains two internal
frequency multiplication stages that are cascaded in series.
The first stage is a VCXO PLL that is optimized to provide
reference clock jitter attenuation. The second stage is a
FemtoClock™ frequency multiplier that provides the low jitter,
high frequency Ethernet output clock that easily meets Gigabit
and 10 Gigabit Ethernet jitter requirements. Pre-divider and
output divider multiplication ratios are selected using device
selection control pins. The multiplication ratios are optimized
to support most common clock rates used in PDH, SONET
and Ethernet applications. The VCXO requires the use of an
external, inexpensive pullable crystal. The VCXO uses external
passive loop filter components which allows configuration of
the PLL loop bandwidth and damping characteristics. The
device is packaged in a space-saving 32-VFQFN package and
supports industrial temperature range.
• Accepts input frequencies from 8kHz to 155.52MHz including
8kHz, 1.544MHz, 2.048MHz, 19.44MHz, 25MHz, 77.76MHz,
125MHz and 155.52MHz
• Attenuates the phase jitter of the input clock by using a low-
cost pullable fundamental mode VCXO crystal
• VCXO PLL bandwidth can be optimized for jitter attenuation
and reference tracking using external loop filter connection
• FemtoClock frequency multiplier provides low jitter, high
frequency output
• Absolute pull range: 50ppm
• FemtoClock VCO frequency: 625MHz
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(10kHz – 20MHz): 1.3ps (maximum)
• 3.3V supply voltage
• -40°C to 85°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
LF1
LF0
1
2
3
4
5
6
7
8
VEE
24
23
22
21
20
19
18
17
nQB
QB
ISET
VEE
VCCO
nQA
QA
ICS813252I-02
CLK_SEL
VCC
RESERVED
VEE
VEE
ODASEL_0
9 10 11 12 13 14 15 16
32-Lead VFQFN
5mm x 5mm x 0.925 package body
K Package
Top View
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
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CS813252CKI-02 REV. A OCTOBER 22, 2008
ICS813252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
BLOCK DIAGRAM
Loop
Filter
25MHz
Output Divider
QA
Pullup
PDSEL_[2:0]
00 = 25 (default)
01 = 5
nQA
10 = 4
11 = 2
VCXO Input
Pre-Divider
CLK0
Phase
Detector
0
1
nCLK0
2
000 = 1
ODASEL_[1:0]
FemtoClock PLL
625MHz
001 = 193
010 = 256
011 = 2430
100 = 3125
101 = 9720
110 = 15625
VCXO
Charge
Pump
CLK1
nCLK1
Output Divider
QB
VCXO Feedback Divider
÷3125
Pulldown
00 = 25 (default)
01 = 5
CLK_SEL
nQB
10 = 4
11 = 2
111 = 19440
VCXO Jitter Attenuation PLL
(default)
2
ODBSEL_[1:0]
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
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CS813252CKI-02 REV. A OCTOBER 22, 2008
ICS813252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Analog
Input/Output
Description
Loop filter connection node pins.
LF0 is the output. LF1 is the input.
1, 2
LF1, LF0
Analog
Input/Output
3
ISET
VEE
Charge pump current setting pin.
4, 8, 18, 24
5
Power
Negative supply pins.
Input clock select. When HIGH selects CLK1/nCLK1.
When LOW, selects CLK0/nCLK0. LVCMOS/LVTTL interface levels.
CLK_SEL
Input
Pulldown
Pullup
6, 12, 27
7
VCC
Power
Core power supply pins.
RESERVED
Reserved
Reserved pin. Do not connect.
9,
10,
11
PDSEL_2,
PDSEL_1,
PDSEL_0
Pre-divider select pins. LVCMOS/LVTTL interface levels.
See Table 3A.
Input
13
VCCA
Power
Input
Analog supply pin.
14,
15
16,
17
ODBSEL_1,
ODBSEL_0
ODASEL_1,
ODASEL_0
Frequency select pins for Bank B output. See Table 3B.
LVCMOS/LVTTL interface levels.
Frequency select pins for Bank A output. See Table 3B.
LVCMOS/LVTTL interface levels.
Pulldown
Pulldown
Input
19, 20
21
QA, nQA
VCCO
Output
Power
Output
Differential Bank A clock outputs. LVPECL interface levels.
Output power supply pin.
22, 23
QB, nQB
Differential Bank B clock outputs. LVPECL interface levels.
Pullup/
Pulldown
25
26
28
29
nCLK1
CLK1
Input
Input
Input
Input
Input
Power
Inverting differential clock input. VCC/2 bias voltage when left floating.
Pulldown Non-inverting differential clock input.
Pullup/
nCLK0
Inverting differential clock input. VCC/2 bias voltage when left floating.
Pulldown
CLK0
Pulldown Non-inverting differential clock input.
30,
31
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
32
VCCX
Power supply pin for VCXO charge pump.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
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VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
TABLE 3A. PRE-DIVIDER FUNCTION TABLE
TABLE 3B. OUTPUT DIVIDER FUNCTION TABLE
Inputs
Inputs
Output Divider Value
Pre-Divider Value
ODxSEL_1
ODxSEL_0
PDSEL_2
PDSEL_1 PDSEL_0
0
0
1
1
0
1
0
1
25 (default)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
193
5
4
2
256
2430
3125
9720
15625
19440 (default)
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VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
TABLE 3C. FREQUENCY FUNCTION TABLE
Input
Frequency
(MHz)
VCXO
FemtoClock
Femtoclock
Pre-Divider
Value
Output Divider Output Frequency
Frequency Feedback Divider VCO Frequency
Value
(MHz)
(MHz)
Value
(MHz)
0.008
0.008
0.008
0.008
1.544
1.544
1.544
1.544
2.048
2.048
2.048
2.048
19.44
19.44
19.44
19.44
25
1
25
25
625
25
5
25
125
1
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
25
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
625
1
4
156.25
312.5
25
1
2
193
25
5
193
125
193
4
156.25
312.5
25
193
2
256
25
5
256
125
256
4
156.25
312.5
25
256
2
2430
2430
2430
2430
3125
3125
3125
3125
9720
9720
9720
9720
15625
15625
15625
15625
19440
19440
19440
19440
25
5
125
4
156.25
312.5
25
2
25
5
25
125
25
4
156.25
312.5
25
25
2
77.76
77.76
77.76
77.76
125
25
5
125
4
156.25
312.5
25
2
25
5
125
125
125
4
156.25
312.5
25
125
2
155.52
155.52
155.52
155.52
25
5
125
4
156.25
312.5
2
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VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θ
37°C/W (0 mps)
-65°C to 150°C
JA
Storage Temperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical Maximum Units
VCC
VCCA
VCCO
VCCX
IEE
Core Supply Voltage
3.3
3.3
3.3
3.3
3.465
VCC
V
V
Analog Supply Voltage
Output Supply Voltage
Charge Pump Supply Voltage
Power Supply Current
Analog Supply Current
VCC – 0.15
3.135
3.465
3.465
235
V
3.135
V
mA
mA
ICCA
15
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
Input Low Voltage
CLK_SEL,
2
VCC + 0.3
0.8
V
V
-0.3
ODASEL_[0:1],
ODBSEL_[0:1]
V
CC = VIN = 3.465V
150
5
µA
µA
µA
Input
High Current
IIH
PDSEL[0:2]
VCC = VIN = 3.465V
CLK_SEL,
ODASEL_[0:1],
ODBSEL_[0:1]
V
CC = 3.465V, VIN = 0V
-5
Input
Low Current
IIL
PDSEL[0:2]
VCC = 3.465V, VIN = 0V
-150
µA
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
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ICS813252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
VIN = VCC = 3.465V
VIN = 0V, VCC = 3.465V
Minimum Typical Maximum Units
CLK0/nCLK0,
CLK1/nCLK1
150
µA
CLK0, CLK1
-5
-150
µA
µA
V
IIL
Input Low Current
nCLK0, nCLK1
VIN = 0V, VCC = 3.465V
VPP
Peak-to-Peak Input Voltage; NOTE 1
0.15
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
VCC - 0.85
V
NOTE 1: VIL should not be less than -0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 4D. LVPECL DC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCCO - 1.4
VCCO - 2.0
0.6
Typical
Maximum Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
VSWING
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
TABLE 5. AC CHARACTERISTICS, VCC = VCCO = VCCX = 3.3V 5ꢀ, VEE = 0V, TA = -40°C TO 85°C
Symbol
fIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Frequency
Output Frequency
0.008
25
155.52
312.5
MHz
MHz
fOUT
125MHz fOUT, 25MHz crystal
Integration Range:
10kHz – 20MHz
125MHz fOUT, 25MHz crystal,
RMS Phase Jitter (Random);
NOTE 1
tjit(Ø)
1.3
10
ps
ps
Accumulated Jitter, RMS;
NOTE 2
tjit(acc)
20K Cycles
tjit(pk-pk) Peak-to-Peak Jitter
100K Random Cycles
35
75
ps
ps
ꢀ
tsk(o)
odc
Output Skew; NOTE 2, 3
Output Duty Cycle
Output Rise/Fall Time
PLL Lock Time
45
55
tR / tF
tLOCK
20ꢀ to 80ꢀ
200
700
175
ps
ms
Characterized with outputs at the same frequency using the loop filter components for the mid loop bandwidth.
Refer to VCXO-PLL Loop Bandwidth Selection Table.
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load condtions.
Measured at the output differential cross points.
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
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CS813252CKI-02 REV. A OCTOBER 22, 2008
ICS813252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
TYPICAL PHASE NOISE @ 125MHZ
125MHz
RMS Phase Jitter (Random)
10kHz to 20MHz = 0.98ps (typical)
OFFSET FREQUENCY (HZ)
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
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VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PARAMETER MEASUREMENT INFORMATION
2V
2V
VCC
SCOPE
VCC,
VCCO,
VCCX
Qx
nCLKꢀ,
nCLK1
VCCA
VPP
VCMR
Cross Points
CLKꢀ,
CLK1
LVPECL
nQx
VEE
VEE
-1.3V ꢀ.1ꢁ6V
DIFFERENTIAL INPUT LEVEL
3.3V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
nFOUTx
FOUTx
Phase Noise Mask
nFOUTy
FOUTy
tsk(o)
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
OUTPUT SKEW
PHASE JITTER
nQA, nQB
QA, QB
nQA, nQB
QA, QB
8ꢀ%
tF
8ꢀ%
tR
VSWING
2ꢀ%
tPW
tPERIOD
2ꢀ%
tPW
tPERIOD
odc =
x 1ꢀꢀ%
OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD
OUTPUT RISE/FALL TIME
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VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
3.3V
VDD
VDDX
VDDA
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perfor-
mance, power supply isolation is required. The ICS813252I-02
provides separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCX, VCCA, and
VCCO should be individually connected to the power supply
plane through vias, and 0.01µF bypass capacitors should be used
for each pin. Figure 1 illustrates this for a generic VCC pin and
also shows that VCCA requires that an additional 10Ω resistor
along with a 10µF bypass capacitor be connected to the VCCA pin.
.01µF
.01µF
10Ω
10Ω
10µF
.01µF
10µF
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V /2 is
generated by the bias resistors R1, R2 and C1. This bias CcCircuit
should be located as close as possible to the input pin. The ratio
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
CC
and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
V_REF
CLKx
nCLKx
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
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CS813252CKI-02 REV. A OCTOBER 22, 2008
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VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals.VSWING and VOH must meet the VPP and
VCMR input requirements.Figures 3A to 3F show interface examples
for the HiPerClockS CLK/nCLK input driven by the most common
driver types. The input interfaces suggested here are examples
only. Please consult with the vendor of the driver component to
confirm the driver termination requirements.For example in Figure
3A, the input termination applies for IDT HiPerClockS open emitter
LVHSTL drivers. If you are using an LVHSTL driver from another
vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
LVPECL
Input
nCLK
HiPerClockS
LVHSTL
Input
R1
50
R2
50
ICS
HiPerClockS
LVHSTL Driver
R1
50
R2
50
R3
50
FIGURE 3A. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY AN IDT OPEN EMITTER
FIGURE 3B. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
HIPERCLOCKS LVHSTL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiver
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V LVDS DRIVER
2.5V
2.5V
3.3V
3.3V
2.5V
R3
R4
120
120
Zo = 50Ω
Zo = 50Ω
*R3
*R4
33
33
Zo = 60Ω
Zo = 60Ω
CLK
CLK
nCLK
nCLK
HiPerClockS
HiPerClockS
Input
SSTL
HCSL
R1
50
R2
50
R1
120
R2
120
*Optional – R3 and R4 can be 0Ω
FIGURE 3F. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 2.5V SSTL DRIVER
FIGURE 3E. HIPERCLOCKS CLK/nCLK INPUT
DRIVEN BY A 3.3V HCSL DRIVER
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
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CS813252CKI-02 REV. A OCTOBER 22, 2008
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VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
VFQFN EPADTHERMAL RELEASE PATH
In order to maximize both the removal of heat from the package
and the electrical performance, a land pattern must be
incorporated on the Printed Circuit Board (PCB) within the footprint
of the package corresponding to the exposed metal pad or
exposed heat slug on the package, as shown in Figure 4. The
solderable area on the PCB, as defined by the solder mask, should
be at least the same size/shape as the exposed pad/slug area on
the package to maximize the thermal/electrical performance.
Sufficient clearance should be designed on the PCB between the
outer edges of the land pattern and the inner edges of pad pattern
for the leads to avoid any shorts.
are application specific and dependent upon the package power
dissipation as well as electrical conductivity requirements. Thus,
thermal and electrical analysis and/or testing are recommended
to determine the minimum number needed. Maximum thermal
and electrical performance is achieved when an array of vias is
incorporated in the land pattern. It is recommended to use as
many vias connected to ground as possible. It is also
recommended that the via diameter should be 12 to 13mils (0.30
to 0.33mm) with 1oz copper via barrel plating. This is desirable to
avoid any solder wicking inside the via during the soldering process
which may result in voids in solder between the exposed pad/
slug and the thermal land. Precautions should be taken to
eliminate any solder voids between the exposed heat slug and
the land pattern. Note: These recommendations are to be used
as a guideline only. For further information, refer to the Application
Note on the Surface Mount Assembly of Amkor’s Thermally/
Electrically Enhance Leadfame Base Package, Amkor Technology.
While the land pattern on the PCB provides a means of heat
transfer and electrical grounding from the package to the board
through a solder joint, thermal vias are necessary to effectively
conduct from the surface of the PCB to the ground plane(s). The
land pattern must be connected to ground through these vias.
The vias act as “heat pipes”. The number of vias (i.e.“heat pipes”)
SOLDER
SOLDER
PIN
PIN
EXPOSED HEAT SLUG
PIN PAD
GROUND PLANE
LAND PATTERN
(GROUND PAD)
PIN PAD
THERMAL VIA
FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVPECL OUTPUTS
INPUTS:
CLK/nCLK INPUTS
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required, but
for additional protection, a 1kΩ resistor can be tied from CLK to
ground.
LVCMOS CONTROL PINS
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
12
CS813252CKI-02 REV. A OCTOBER 22, 2008
ICS813252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are rec-
ommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal dis-
tortion. Figures 5A and 5B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts
may exist and it would be recommended that the board design-
ers simulate to guarantee compatibility across all printed circuit
and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 5A. LVPECL OUTPUT TERMINATION
FIGURE 5B. LVPECL OUTPUT TERMINATION
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
13
CS813252CKI-02 REV. A OCTOBER 22, 2008
ICS813252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
SCHEMATIC EXAMPLE
Figure 6 shows an example of the ICS813252I-02 application
schematic. In this example, the device is operated at V =
can also be used for additional spur reduction. It is
recommended that the loop filter components be laid out for
the 3-pole option. This will also allow the 2-pole filter to be
used.
V
= V = 3.3V. The decoupling capacitors shouldCCbe
CCX
CCO
located as close as possible to the power pin. The input is
driven by a 3.3V LVPECL driver. An optional 3-pole filter
FIGURE 6. ICS813252I-02 SCHEMATIC EXAMPLE
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
14
CS813252CKI-02 REV. A OCTOBER 22, 2008
ICS813252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
VCXO-PLL EXTERNAL COMPONENTS
Choosing the correct external components and having a proper
printed circuit board (PCB) layout is a key task for quality
operation of the VCXO-PLL. In choosing a crystal, special
precaution must be taken with the package and load
capacitance (C ). In addition, frequency, accuracy and
temperature rangLe must also be considered. Since the pulling
range of a crystal also varies with the package, it is
recommended that a metal-canned package like HC49 be used.
Generally, a metal-canned package has a larger pulling range
than a surface mounted device (SMD). For crystal selection
information, refer to the VCXO Crystal Selection Application
Note.
the crystal specification. In either case, the absolute tuning
range is reduced. The correct value of C is dependent on the
L
characteristics of the VCXO.The recommended C in the Crystal
Parameter Table balances the tuning range by Lcentering the
tuning curve.
The VCXO-PLL Loop Bandwidth Selection Table shows R , C
S
S
and C values for recommended high, mid and low loop
P
bandwidth configurations. The device has been characterized
using these parameters. For other configurations, refer to the
Loop Filter Component Selection for VCXO Based PLLs
Application Note.
LF0
LF1
ISET
The crystal and external loop
filter components should be
kept as close as possible to the
The crystal’s load capacitance C characteristic determines its
L
resonating frequency and is closely related to the VCXO tuning
range. The total external capacitance seen by the crystal when
installed on a board is the sum of the stray board capacitance,
IC package lead capacitance, internal varactor capacitance and
RS RSET
device. Loop filter and crystal
traces should be kept short and
separated from each other.
Other signal traces should be
kept separate and not run
underneath the device, loop
filter or crystal components.
CP CS
any installed tuning capacitors (C ).
TUNE
XTAL_IN
If the crystal’s C is greater than the total external capacitance,
the VCXO will oLscillate at a higher frequency than the crystal
CTUNE
25MHz
CTUNE
XTAL_OUT
specification. If the crystal’s C is lower than the total external
L
capacitance, the VCXO will oscillate at a lower frequency than
VCXO CHARACTERISTICS TABLE
Symbol Parameter
Typical
15,700
9.9
Unit
Hz/V
pF
kVCXO
VCXO Gain
CV_LOW
CV_HIGH
Low Varactor Capacitance
High Varactor Capacitance
22.2
pF
VCXO-PLL APPROXIMATE LOOP BANDWIDTH SELECTION TABLE
Bandwidth
10Hz (Low)
90Hz (Mid)
300Hz (High)
Crystal Frequency (MHz)
RS (kΩ)
121
CS (µF)
1.0
CP (µF)
0.01
RSET (kΩ)
9.09
25MHz
25MHz
25MHz
221
0.1
0.001
0.0001
2.21
680
0.1
2.21
CRYSTAL CHARACTERISTICS
Symbol Parameter
Mode of Operation
Minimum Typical
Maximum
Units
Fundamental
fN
fT
fS
Frequency
25
MHz
ppm
ppm
°C
Frequency Tolerance
Frequency Stability
Operating Temperature Range
Load Capacitance
Shunt Capacitance
Pullability Ratio
20
20
-40
85
CL
10
4
pF
CO
pF
CO/C1
ESR
220
240
Equivalent Series Resistance
Drive Level
20
1
mW
ppm
Aging @ 25°C
3 per year
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
15
CS813252CKI-02 REV. A OCTOBER 22, 2008
ICS813252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS813252I-02.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS813252I-02 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core) = V
* I
= 3.465V * 235mA = 814.275mW
EE_MAX
MAX
CC_MAX
Power (outputs) = 30mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power
(3.465V, with all outputs switching) = 814.275mW + 60mW = 874.275mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θ
= Junction-to-Ambient Thermal Resistance
JA
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming no air
flow and a multi-layer board, the appropriate value is 37°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.874W * 37°C/W = 117.3°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θ FOR 32 LEAD VFQFN, FORCED CONVECTION
JA
θ vs. 0 Air Flow (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
37.0°C/W
32.4°C/W
29.0°C/W
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
16
CS813252CKI-02 REV. A OCTOBER 22, 2008
ICS813252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 7.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V – 2V.
CCO
•
•
For logic high, V = V
= V
– 0.9V
CCO_MAX
OUT
OH_MAX
)
= 0.9V
OH_MAX
(V
– V
CCO_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
– V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
– 2V))/R ] * (V
– V
) = [(2V – (V
– V
/R ] * (V
– V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
_MAX
CCO
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V – 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
– V
) = [(2V – (V
– V
/R ] * (V
– V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
_MAX
CCO
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V – 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
17
CS813252CKI-02 REV. A OCTOBER 22, 2008
ICS813252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
RELIABILITY INFORMATION
TABLE 7. θ VS. AIR FLOW TABLE FOR 32 LEAD VFQFN
JA
θ vs. 0 Air Flow (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
37.0°C/W
32.4°C/W
29.0°C/W
TRANSISTOR COUNT
The transistor count for ICS813252I-02 is: 6579
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
18
CS813252CKI-02 REV. A OCTOBER 22, 2008
ICS813252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
PACKAGE OUTLINE AND DIMENSIONS - K SUFFIX FOR 32 LEAD VFQFN
NOTE: The above mechanical package drawing is a generic drawing that applies to any pin count VFQFN package. This drawing is not
intended to convey the actual pin count or pin layout of this device.The pin count and pinout are shown on the front page. The package
dimensions are in Table 8 below.
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS (VHHD -2/ -4)
SYMBOL
Minimum
Maximum
N
A
32
0.80
0
1.0
A1
A3
b
0.05
0.25 Reference
0.18
0.30
e
0.50 BASIC
ND
8
8
NE
D, E
D2, E2
L
5.0 BASIC
3.0
3.3
0.30
0.50
Reference Document: JEDEC Publication 95, MO-220
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
19
CS813252CKI-02 REV. A OCTOBER 22, 2008
ICS813252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
TABLE 9. ORDERING INFORMATION
Part/Order Number
813252CKI-02
Marking
ICS3252CI02
ICS3252CI02
ICS352CI02L
ICS352CI02L
Package
Shipping Packaging
tray
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
32 Lead VFQFN
813252CKI-02T
813252CKI-02LF
813252CKI-02LFT
32 Lead VFQFN
2500 tape & reel
tray
32 Lead "Lead-Free" VFQFN
32 Lead "Lead-Free" VFQFN
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT
reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments.
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
20
CS813252CKI-02 REV. A OCTOBER 22, 2008
ICS813252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
REVISION HISTORY SHEET
Description of Change
Ordering Information Table - added ICS prefix in the Part/Order Number.
Rev
Table
Page
Date
A
T9
20
5/6/08
IDT™ / ICS™ VCXO JITTER ATTENUATOR/MULTIPLIER
21
CS813252CKI-02 REV. A OCTOBER 22, 2008
ICS813252I-02
VCXO JITTER ATTENUATOR & FEMTOCLOCK™ MULTIPLIER
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
For Tech Support
netcom@idt.com
+480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
Fax: 408-284-2775
www.IDT.com/go/contactIDT
United States
800-345-7015 (inside USA)
+408-284-8200 (outside USA)
© 2007 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
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