813253AGT [IDT]
Clock Generator, 340MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, TSSOP-24;
| 型号： | 813253AGT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 340MHz, PDSO24, 4.40 X 7.80 MM, 0.92 MM HEIGHT, TSSOP-24 光电二极管 |
| 文件： | 总22页 (文件大小：710K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
FEMTOCLOCK™ JITTER ATTENUATOR &
FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
ICS813253
GENERAL DESCRIPTION
FEATURES
• Three differential LVPECL outputs
The ICS813253 is a member of the HiperClockS™
ICS
family of high performance clock solutions from
IDT. The ICS813253 is a PLL based synchronous
clock generator that is optimized for Gigabit
Ethernet and PCI-Express clock jitter attenuation
• One differential input supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
HiPerClockS™
• Accepts input frequencies from 19.6MHz to 136MHz, includ-
ing: 25MHz, 62.5MHz, 100MHz and 125MHz input clocks
and frequency translation. The device contains two internal
frequency multiplication stages that are cascaded in series.The
first stage is a VCXO PLL that is optimized to provide
reference clock jitter attenuation. The second stage is a
FemtoClock frequency multiplier that provides the low
jitter, high frequency Gigabit Ethernet or PCI-Express
output clock.
• Attenuates the phase jitter of the input clock by using a low-
cost pullable funamental mode VCXO crystal
• Outputs common Gigabit Ethernet or PCI-Express clock rates
• VCXO PLL bandwidth can be optimized for jitter attenuation
and reference tracking using external loop filter connection
• Absolute pull range: 110ppm
• FemtoClock frequency multiplier provides low jitter,
Predivider and output divider multiplication ratios are selected
using device selection control pins. The multiplication ratios are
optimized to support most common clock rates used in Gigabit
Ethernet and PCI-Express applications. The VCXO requires
the use of an external, inexpensive pullable crystal. The VCXO
uses external passive loop filter components which allows
configuration of the PLL loop bandwidth and damping
characteristics.
high frequency output
• FemtoClock range: 490MHz - 680MHz
• RMS phase jitter @ 156.25MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.37ps (typical)
• Full 3.3Vsupply, or 3.3V Core/2.5V output supply
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
OE
LF
VCCA
VCC
VCCO
nQ0
Q0
PSEL0
VEE
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
PIN ASSIGNMENT
VCCO
nQ2
Q2
nQ1
Q1
ICS813253
24-Lead TSSOP
4.40mm x 7.8mm x 0.92mm
package body
FSEL0
VEE
G Package
Top View
PSEL1
9
16
15
14
13
FSEL1
nBypass
CLK
XTAL_OUT
XTAL_IN
VEE
10
11
12
nCLK
BLOCK DIAGRAM
External
Loop Filter Input
Q0
Pullup
nBypass
nQ0
Q1
0
Output
Divider
2, 4, 5, 25
Pulldown
CLK
FemtoClock
Frequency
Multiplier x25
Pre-Divider
1, 2.5,
Phase
Detector
VCXO
1
Pullup/Pulldown
nCLK
4, 5
nQ1
Q2
Pullup
PSEL0
Pullup
Pullup
VCXO Jitter Attenuation PLL
PSEL1
FSEL0
nQ2
Pullup
Pullup
FSEL1
OE
IDT™ / ICS™ JITTER ATTENUATOR/FREQUENCY TRANSLATOR
1
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Analog
Input/Output
Description
1
LF
Loop filter connection node pin.
2
3
VCCA
VCC
Power
Analog supply pin.
Power
Power
Output
Core power supply pin.
4, 23
5, 6
VCCO
Output power supply pins.
nQ0, Q0
Differential clock outputs. LVPECL interface levels.
7,
9
PSEL0,
PSEL1
Input
Power
Input
Pullup
Pre-divider select pins. See Table 3A.
8, 12, 17
VEE
Negative supply pins.
10,
11
XTAL_OUT,
XTAL_IN
VCXO crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
Pullup/
Pulldown
13
nCLK
Input
Inverting differential clock input. VCC/2 bias voltage when left floating.
14
15
CLK
Input
Input
Pulldown Non-inverting differential clock input.
nBypass
Pullup
Pullup
PLL Bypass control pin. See Table 3D.
Select pins. See Table 3B.
16,
18
FSEL1,
FSEL0
Input
19, 20
21, 22
Q1, nQ1
Q2, nQ2
Output
Output
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
Output enable. When logic LOW, the clock outputs are HiZ.
When logic HIGH, the clock outputs are enabled.
LVCMOS/LVTTL interface levels. See Table 3C.
24
OE
Input
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
kΩ
kΩ
RPULLDOWN Input Pulldown Resistor
RPULLUP Input Pullup Resistor
51
51
TABLE 3A. PRE-DIVIDER FUNCTION TABLE
Inputs
TABLE 3B. FSEL FUNCTION TABLE
Inputs
Output Divider
Function
FSEL1
FSEL0
PSEL1
PSEL0
Pre-divider Function
0
0
1
1
0
1
0
1
÷2
÷4
0
0
÷1
0
1
1
1
0
1
÷2.5
÷4
÷5
÷25
÷5
IDT™ / ICS™ JITTER ATTENUATOR/FREQUENCY TRANSLATOR
2
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
TABLE 3C. OE FUNCTION TABLE
Input
OE
0
Clock Outputs
Q0:Q2
nQ0:nQ2
HIGH
LOW
1
Enabled
Enabled
TABLE 3D. BYPASS FUNCTION TABLE
nBypass Input
Operation
0
VCXO jitter attenuation PLL and FemtoClock multiplier bypassed. Input passed directly to N divider.
Normal operation mode.
1 (default)
TABLE 3E. FREQUENCY FUNCTION TABLE
Input
VCXO
Frequency
(MHz)
FemtoClock
Frequency
(MHz)
Output
Frequency
(MHz)
Frequency
(MHz)
Input
Divider
Output
Divider
PSEL1:0
FSEL1:0
25
00
1
25
25
25
25
25
25
25
25
25
25
25
25
20
20
20
20
25
25
25
25
625
625
625
625
625
625
625
625
625
625
625
625
500
500
500
500
625
625
625
625
00
2
312.5
156.25
125
25
00
00
00
01
01
01
01
10
10
10
10
11
11
11
11
11
11
11
11
1
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
00
01
10
11
4
25
1
5
25
1
25
2
25
62.5
62.5
62.5
62.5
100
100
100
100
100
100
100
100
125
125
125
125
2.5
2.5
2.5
2.5
4
312.5
156.25
125
4
5
25
2
25
312.5
156.25
125
4
4
4
5
4
25
2
25
5
250
5
4
125
5
5
100
5
25
2
20
5
312.5
156.25
125
5
4
5
5
5
25
25
IDT™ / ICS™ JITTER ATTENUATOR/FREQUENCY TRANSLATOR
3
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θ
70°C/W (0 mps)
-65°C to 150°C
JA
Storage Temperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA=0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical
Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.135
VCC – 0.12
3.135
3.3
3.3
3.3
3.465
VCC
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
3.465
132
12
V
mA
mA
mA
ICCA
ICCO
19
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, VCCO = 2.5V 5ꢀ, TA=0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.135
VCC – 0.12
2.375
3.3
3.3
2.5
3.465
VCC
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
2.625
132
12
V
mA
mA
mA
ICCA
ICCO
19
TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VCC + 0.3
V
V
Input Low Voltage
Input High Current
Input Low Current
-0.3
0.8
5
VCC = VIN = 3.465V
µA
µA
IIL
VCC = 3.465V, VIN = 0V
-150
IDT™ / ICS™ JITTER ATTENUATOR/FREQUENCY TRANSLATOR
4
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
TABLE 4D. DIFFERENTIAL DC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
VIN = VCC = 3.465V
VIN = 0V, VCC = 3.465V
Minimum Typical Maximum Units
IIH
Input High Current nCLK, CLK
150
µA
µA
µA
V
nCLK
CLK
-150
-5
IIL
Input Low Current
V
IN = 0V, VCC = 3.465V
VPP
Peak-to-Peak Input Voltage
0.15
1.3
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
VCC - 0.85
V
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VCC + 0.3V.
TABLE 4E. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, VCCO = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA=0°C TO 70°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCCO - 1.4
VCCO - 2.0
0.6
Typical
Maximum Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
VSWING
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
TABLE 5A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
PSEL = ÷1
PSEL = ÷2.5
PSEL = ÷4
PSEL = ÷5
FSEL = ÷2
FSEL = ÷4
FSEL = ÷5
FSEL = ÷25
Minimum Typical Maximum Units
19.6
49
27.2
68
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
fIN
Input Frequency
78.4
98
108.8
136
340
170
136
27.2
245
122.5
98
fOUT
Output Frequency
19.6
156.25MHz, 25MHz crystal
Integration Range:
RMS Phase Jitter (Random);
NOTE 1
tjit(Ø)
0.37
ps
1.875MHz - 20MHz
tR / tF
tjit(cc)
tjit(per)
tsk(o)
odc
Output Rise/Fall Time
Cycle-to-Cycle Jitter; NOTE 2, 3
Period Jitter; NOTE 4
Output Skew; NOTE 3, 5
Output Duty Cycle
20ꢀ to 80ꢀ
400
8
800
40
3
ps
ps
ps
ps
ꢀ
1
60
52
48
tLOCK
PLL Lock Time
ms
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Jitter performance using crystal inputs.
NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load condtions.
Measured at the output differential cross points.
IDT™ / ICS™ JITTER ATTENUATOR/FREQUENCY TRANSLATOR
5
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
TABLE 5B. AC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, VCCO = 2.5V 5ꢀ, TA=0°C TO 70°C
Symbol Parameter
Test Conditions
PSEL = ÷1
PSEL = ÷2.5
PSEL = ÷4
PSEL = ÷5
FSEL = ÷2
FSEL = ÷4
FSEL = ÷5
FSEL = ÷25
Minimum Typical Maximum Units
19.6
49
27.2
68
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
fIN
Input Frequency
78.4
98
108.8
136
340
170
136
27.2
245
122.5
98
fOUT
Output Frequency
19.6
156.25MHz, 25MHz crystal
Integration Range:
RMS Phase Jitter (Random);
NOTE 1
tjit(Ø)
0.35
ps
1.875MHz - 20MHz
tR / tF
tjit(cc)
tjit(per)
tsk(o)
odc
Output Rise/Fall Time
Cycle-to-Cycle Jitter; NOTE 2, 3
Period Jitter; NOTE 4
Output Skew; NOTE 3, 5
Output Duty Cycle
20ꢀ to 80ꢀ
350
7.5
0.5
700
40
ps
ps
ps
ps
ꢀ
2.5
60
48
52
tLOCK
PLL Lock Time
ms
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Outputs terminated with 50Ω to VCCO - 2V.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Jitter performance using crystal inputs.
NOTE 5: Defined as skew between outputs at the same supply voltage and with equal load condtions.
Measured at the output differential cross points.
IDT™ / ICS™ JITTER ATTENUATOR/FREQUENCY TRANSLATOR
6
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
TYPICAL PHASE NOISE AT 156.25MHZ (3.3V/3.3V)
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.37ps (typical)
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 156.25MHZ (3.3V/2.5V)
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.35ps (typical)
OFFSET FREQUENCY (HZ)
IDT™ / ICS™ JITTER ATTENUATOR/FREQUENCY TRANSLATOR
7
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
PARAMETER MEASUREMENT INFORMATION
2V
2.8V 0.04V
2V
2V
2.8V 0.04V
SCOPE
VCC,
VCCO
Qx
VCC
SCOPE
Qx
VCCO
VCCA
VCCA
LVPECL
nQx
LVPECL
VEE
nQx
VEE
-1.3V 0.165V
-0.5V 0.125V
3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
VCC
Phase Noise Plot
nCLK
VPP
VCMR
Cross Points
CLK
VEE
Phase Noise Mask
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
DIFFERENTIAL INPUT LEVEL
VOH
VREF
nQ0:nQ2
Q0:Q2
➤
➤
VOL
tcycle n
tcycle n+1
➤
➤
1σ contains 68.26ꢀ of all measurements
2σ contains 95.4ꢀ of all measurements
3σ contains 99.73ꢀ of all measurements
4σ contains 99.99366ꢀ of all measurements
6σ contains (100-1.973x10-7)ꢀ of all measurements
tjit(cc) = tcycle n – tcycle n+1
1000 Cycles
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
CYCLE-TO-CYCLE JITTER
PERIOD JITTER
IDT™ / ICS™ JITTER ATTENUATOR/FREQUENCY TRANSLATOR
8
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
nQ0:nQ2
Q0:Q2
nFOUTx
FOUTx
tPW
tPERIOD
nFOUTy
FOUTy
tPW
odc =
x 100ꢀ
tsk(o)
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT SKEW
80ꢀ
tF
80ꢀ
tR
VSWING
20ꢀ
Clock
Outputs
20ꢀ
OUTPUT RISE/FALL TIME
IDT™ / ICS™ JITTER ATTENUATOR/FREQUENCY TRANSLATOR
9
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS813253 provides
separate power supplies to isolate any high switching noise
3.3V
VCC
.01µF
.01µF
from the outputs to the internal PLL. VCC, VCCA, and VCCO
should be individually connected to the power supply plane
10Ω
through vias, and bypass capacitors should be used for each
pin. To achieve optimum jitter performance, power supply iso-
lation is required. Figure 1 illustrates how a 10Ω resistor along
with a 10mF and a .01mF bypass capacitor should be con-
nected to each VCCA pin.
VCCA
10 µF
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
The ratio of R1 and R2 might need to be adjusted to position
the V_REF in the center of the input voltage swing. For
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF ~ V /2 is
CC
example, if the input clock swing is only 2.5V and V = 3.3V,
V_REF should be 1.25V and R2/R1 = 0.609.
generated by the bias resistors R1, R2 and C1. This bias
circuit should be located as close as possible to the input pin.
CC
VCC
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
IDT™ / ICS™ JITTER ATTENUATOR/FREQUENCY TRANSLATOR
10
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUT:
OUTPUTS:
LVPECL OUTPUT
For applications not requiring the use of the crystal oscillator
input, both XTAL_IN and XTAL_OUT can be left floating. Though
not required, but for additional protection, a 1kΩ resistor can be
tied from XTAL_IN to ground.
All unused LVPECL outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output
pair should either be left floating or terminated.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating.Though not required, but
for additional protection, a 1kΩ resistor can be tied from CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are rec-
ommended only as guidelines.
transmission lines. Matched impedance techniques should be
used to maximize operating frequency and minimize signal dis-
tortion. Figures 3A and 3B show two different layouts which are
recommended only as guidelines. Other suitable clock layouts
may exist and it would be recommended that the board design-
ers simulate to guarantee compatibility across all printed circuit
and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs. Therefore, terminating
resistors (DC current path to ground) or current sources must be
used for functionality. These outputs are designed to drive 50Ω
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Z
o = 50Ω
o = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
Z
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
IDT™ / ICS™ JITTER ATTENUATOR/FREQUENCY TRANSLATOR
11
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 4A and Figure 4B show examples of termination for 2.5V
LVPECL driver. These terminations are equivalent to terminating
50Ω to V - 2V. For V = 2.5V, the V - 2V is very close to ground
level. The R3 in Figure 4B can be eliminated and the termination
is shown in Figure 4C.
CC
CC
CC
2.5V
VCC=2.5V
2.5V
2.5V
VCC=2.5V
Zo = 50 Ohm
R1
R3
250
250
+
Zo = 50 Ohm
Zo = 50 Ohm
+
-
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
2,5V LVPECL
Driv er
R2
62.5
R4
62.5
R3
18
FIGURE 4A. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 4B. 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V
VCC=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driv er
R1
50
R2
50
FIGURE 4C. 2.5V LVPECL TERMINATION EXAMPLE
IDT™ / ICS™ JITTER ATTENUATOR/FREQUENCY TRANSLATOR
12
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
DESCRIPTION OF THE PLL STAGES
The ICS813253 is a two stage device, a VCXO PLL followed by
a low phase noise FemtoClock frequency multiplier. The VCXO
uses an external pullable crystal which can be pulled 110ppm
by the VCXO PLL circuitry to phase lock it to the input reference
frequency.
To prevent jitter on the clock output due to modulation of the
VCXO PLL by the phase detector frequency, the following general
rule should be observed:
ƒ (Phase Detector)
NBW (VCXO PLL) ≤
20
VCXO PLL LOOP RESPONSE CONSIDERATIONS
ƒ(Phase Detector) = Input Frequency ÷ Pre-Divider)
The PLL loop damping factor is determined by:
Loop response characteristics of the VCXO PLL is affected by
the VCXO feedback divider value (bandwidth and damping
factor), and by the external loop filter components (bandwidth,
nd
damping factor, and 2 frequency response). A practical range
of VCXO PLL bandwidth is from about 1Hz to about 1kHz. The
setting of VCXO PLL bandwidth and damping factor is covered
later in this document. A PC based PLL bandwidth calculator is
also under development. For assistance with loop bandwidth
suggestions or value calculation, please contact Idt applications.
RS
2
ICP x CS x KO
DF = x
Feedback Divider
WHERE:
CS = Value of capacitor CS in loop filter in Farads
Table 3E shows frequency translation configuration examples.
EXTERNAL VCXO PLL COMPONENTS
Capacitors with low microphonic sensitivity should be used. PPS
film type capacitors are one type that perform well in this
environment. Below 5Hz, shielding should be considered to
prevent excessive phase wander (low frequency phase jitter or
clock phase deviation).
In general, the loop damping factor should be 0.7 or greater to
ensure output stability. A higher damping factor will create less
peaking in the passband. A higher damping factor may also
increase lock time and output clock jitter when there is excess
digital noise in the system application, due to the reduced ability
of the PLL to respond to and therefore compensate for phase
noise ingress.
SETTING THE VCXO PLL LOOP RESPONSE
The VCXO PLL loop response is determined both by fixed device
characteristics and by other characterizes set by the user. This
includes the values of RS, CS, CP and RSET as shown in the External
VCXO PLL Components figure on this page.
The external crystal devices and loop filter components should
be kept close to the device. Loop filter and crystal PCB
connection traces should be kept short and well separated from
each other and from other signal traces. Other signal traces
shouldnot run underneath the device, the loop filter or crystal
components.
The VCXO PLL loop bandwidth is approximated by:
RS x ICP x KO
NBW (VCXO PLL) =
2π x Feedback Divider
WHERE:
RS = Value of resistor RS in loop filter in Ohms
ICP = Charge pump current in amps (see table on page 12)
KO = VCXO Gain in Hz/V
LF
1
RS
CP
CS
The above equation calculates the “normalized” loop bandwidth
(denoted as “NBW”) which is approximately equal to the - 3dB
bandwidth. NBW does not take into account the effects of damping
factor or the second pole imposed by CP. It does, however, provide
a useful approximation of filter performance.
11
12
IDT™ / ICS™ JITTER ATTENUATOR/FREQUENCY TRANSLATOR
13
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
NOTES ON SETTING THE VALUE OF CP
As another general rule, the following relationship should be
maintained between components CS and CP in the loop filter:
VCXO PLL input voltage can hit the supply or ground rail
resulting in non-linear loop response.
CS
CP =
CP should be increased in value until it just starts affecting the
passband peak.
20
CP establishes a second pole in the VCXO PLL loop filter. For
higher damping factors (> 1), calculate the value of CP based
on a CS value that would be used for a damping factor of 1.
This will minimize baseband peaking and loop instability that
can lead to output jitter.
NOTES ON EXTERNAL CRYSTAL LOAD CAPACITORS
In the loop filter schematic diagram, capacitors are shown
between pin 10 to ground and between pin 11 to ground. These
are optional crystal load capacitors which can be used to center
tune the external pullable crystal (the crystal frequency can
only be lowered by adding capacitance, it cannot be raised).
Note that the addition of external load capacitors will decrease
the crystal pull range and the Kvco value.
CP also dampens VCXO PLL input voltage modulation by the
charge pump correction pulses. A CP value that is too low will
result in increased output phase noise at the phase detector
frequency due to this. In extreme cases where input jitter is
high, charge pump current is high, and CP is too small, the
EXAMPLE LOOP FILTER COMPONENT VALUES FOR VARIOUS VCXO DIVIDER SELECTIONS
Input Frequency
25MHz
Bandwidth
1000
Dampening
RS (K)
CS (µF)
1.0
CS (µF)
0.01
2.4
3.0
5
5
25MHz
400
10.0
0.1
IDT™ / ICS™ JITTER ATTENUATOR/FREQUENCY TRANSLATOR
14
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
VCXO CRYSTAL SELECTION
Choosing a crystal with the correct characteristics is one of the
most critical steps in using a Voltage Controlled Crystal Oscillator
(VCXO). The crystal parameters affect the tuning range and
accuracy of a VCXO. Below are the key variables and an example
of using the crystal parameters to calculate the tuning range of
the VCXO.
Oscillator
CV
CV
VCXO (Internal)
XTAL
CS1
CS2
CL1
CL2
Optional
FIGURE 5: VCXO OSCILLATOR CIRCUIT EXAMPLE
CV Varactor capacitance, varies due to the change in
control voltage
CL1, CL2 Load tuning capacitance used for fine tuning or
centering nominal frequency
CS1, CS2 Stray Capacitance caused by pads, vias, and other
board parasitics
CRYSTAL PARAMETER EXAMPLES
Symbol Parameter
Minimum Typical Maximum Units
fN
fT
fS
Nominal Frequency
19.6
27.2
15
15
70
8
MHz
ppm
ppm
°C
Frequency Tolerance
Frequency Stability
Operating Temperature Range
Load Capacitance
Shunt Capacitance
Pullability Ratio
0
CL
pF
CO
7
pF
C0/C1
ESR
250
20
1
Equivalent Series Resistance
Drive Level
mW
ppm
Aging @ 25°C
3 per year
Mode of Operation
Fundemental
VARACTOR PARAMETERS
Symbol Parameter
Test Condition Typical Unit
CV LOW
CV HIGH
Low Varactor Capacitance
High Varactor Capacitance
VC = 0V
52
pF
pF
VC = 3.3V
5.2
IDT™ / ICS™ JITTER ATTENUATOR/FREQUENCY TRANSLATOR
15
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
FORMULAS
(CL1 + CS1 + CV_LOW) · (CL2 + CS2 + CV_LOW
)
(CL1 + CS1 + CV_HIGH · (CL2 + CS2 + CV_HIGH
)
CLOW
=
CHIGH
=
(CL1 + CS1 + CV_LOW) + (CL2 + CS2 + CV_LOW
)
(CL1 + CS1 + CV_HIGH) + (CL2 + CS2 + CV_HIGH
)
CHigh is the effective capacitance due to the high varactor
capacitance, load capacitance and stray capacitance.
CLow is the effective capacitance due to the low varactor
capacitance, load capacitance and stray capacitance.
CLow determines the high frequency component on the
TPR (Total Pull Range).
CHigh determines the low frequency component on the
TPR (Total Pull Range).
1
1
TPR =
–
· 106
(
)
2 · C0/C1 · (1+CLOW /C0)
2 · C0/C1 · (1+CHIGH/C0)
AbsolutePullRange (APR) = TotalPullRange – (FrequencyTolerance + FrequencyStability + Aging)
EXAMPLE CALCULATIONS -TBD
IDT™ / ICS™ JITTER ATTENUATOR/FREQUENCY TRANSLATOR
16
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS813253.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS813253 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for V = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
CC
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core) = V
* I
= 3.465V * 132mA = 457.38mW
EE_MAX
MAX
CC_MAX
Power (outputs) = 30mW/Loaded Output pair
MAX
If all outputs are loaded, the total power is 3 * 30mW = 90mW
Total Power
(3.465V, with all outputs switching) = 457.28mW + 90mW = 547.38mW
_MAX
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
TM
device. The maximum recommended junction temperature for HiPerClockS devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.547W * 65°C/W = 105.6°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θ FOR 24 LEAD TSSOP, FORCED CONVECTION
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
IDT™ / ICS™ JITTER ATTENUATOR/FREQUENCY TRANSLATOR
17
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
•
•
For logic high, V = V
= V
– 0.9V
CC_MAX
OUT
OH_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V ) =
OH_MAX
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
_MAX
OH_MAX
CCO_MAX
L
CCO
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
_MAX
OL_MAX
CCO_MAX
OL_MAX
L
CCO
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
IDT™ / ICS™ JITTER ATTENUATOR/FREQUENCY TRANSLATOR
18
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
RELIABILITY INFORMATION
TABLE 7. θ VS. AIR FLOW TABLE FOR 24 LEAD TSSOP
JA
θ by Velocity (Meters per Second)
JA
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS813253 is: 2915
IDT™ / ICS™ JITTER ATTENUATOR/FREQUENCY TRANSLATOR
19
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
24
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
IDT™ / ICS™ JITTER ATTENUATOR/FREQUENCY TRANSLATOR
20
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS813253AG
Marking
Package
Shipping Packaging Temperature
ICS813253AG
ICS813253AG
ICS813253AGLF
ICS813253AGLF
24 Lead TSSOP
tube
0°C to 70°C
ICS813253AGT
ICS813253AGLF
ICS813253AGLFT
24 Lead TSSOP
2500 tape & reel
tube
0°C to 70°C
0°C to 70°C
0°C to 70°C
24 Lead "Lead-Free" TSSOP
24 Lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
IDT™ / ICS™ JITTER ATTENUATOR/FREQUENCY TRANSLATOR
21
ICS813253AG REV. A JANUARY 5, 2007
ICS813253
FEMTOCLOCK™ JITTER ATTENUATOR & FREQUENCY TRANSLATOR W/LVPECL OUTPUTS
PRELIMINARY
Innovate with IDT and accelerate your future networks. Contact:
www.IDT.com
For Sales
800-345-7015
408-284-8200
Fax: 408-284-2775
For Tech Support
netcom@idt.com
480-763-2056
Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
Europe
IDT Europe, Limited
321 Kingston Road
Leatherhead, Surrey
KT22 7TU
United States
800 345 7015
#20-03 Wisma Atria
England
+408 284 8200 (outside U.S.)
Singapore 238877
+44 (0) 1372 363 339
Fax: +44 (0) 1372 378851
+65 6 887 5505
© 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be
trademarks or registered trademarks used to identify products or services of their respective owners.
Printed in USA
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明