82P33810_16 [IDT]
Synchronization Management Unit for IEEE 1588 and Synchronous Ethernet;型号: | 82P33810_16 |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | Synchronization Management Unit for IEEE 1588 and Synchronous Ethernet |
文件: | 总13页 (文件大小:285K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Synchronization Management Unit for
IEEE 1588 and Synchronous Ethernet
82P33810
Short Form Datasheet
This is a short form datasheet and is intended to provide an overview only. Additional details are available from IDT. Contact information may be found on
the last page.
HIGHLIGHTS
•
Synchronization Management Unit (SMU) provides tools to manage
physical layer and packet based synchronous clocks for IEEE 1588 /
PTP Telecom Profile applications
•
FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS output sync pulses
that are aligned with the selected external input sync pulse input and
frequency locked to the associated reference clock input
DPLL1 and DPLL2 can be configured with bandwidths between 0.09
mHz and 567 Hz
DPLL1 and DPLL2 lock to input references with frequencies between
1 PPS and 650 MHz
DPLL3 locks to input references with frequencies between 8 kHz and
650 MHz
DPLL1 and DPLL2 comply with ITU-T G.8262 for Synchronous
Ethernet Equipment Clock (EEC), and G.813 for Synchronous Equip-
ment Clock (SEC); and Telcordia GR-253-CORE for Stratum 3 and
SONET Minimum Clock (SMC)
DPLL1 and DPLL2 generate clocks with PDH, TDM, GSM, CPRI/
OBSAI, 10/100/1000 Ethernet and GNSS frequencies; these clocks
are directly available on OUT1 and OUT8
DPLL1 and DPLL2 can be configured as DCOs to synthesize IEEE
1588 clocks
DPLL3 generates N x 8 kHz clocks up to 100 MHz that are output on
OUT10 and OUT11
•
•
Supports independent IEEE 1588 and Synchronous Ethernet
(SyncE) timing paths
Combo mode provides SyncE physical layer frequency support for
IEEE 1588 Telecom Boundary Clocks (T-BC) and Telecom Time
Slave Clocks (T-TSC) per G.8273.2
•
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Digital PLL 1 (DPLL1) and DPLL 2 can be configured as Digitally
Controlled Oscillators (DCOs) for PTP clock synthesis
DCO frequency resolution is [(77760 / 1638400) * 2^-48] or
~1.686305041e-10 ppm
•
•
DPLL1 and DPLL2 generate G.8262 compliant SyncE clocks
Two independent Time of Day (ToD) counters/time accumulators, one
associated with each of DPLL1 and DPLL2, can be used to track dif-
ferences between the two time domains and to time-stamp external
events
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DPLL3 performs rate conversions to frequency synchronization inter-
faces or for other general purpose timing applications
APLL1 and APLL2 generate clocks with jitter < 1 ps RMS (12 kHz to
20 MHz) for: 1000BASE-T and 1000BASE-X
Fractional-N input dividers support a wide range of reference fre-
quencies
•
•
APLL1 and APLL2 can be connected to DPLL1 or DPLL2
APLL1 and APLL2 generate 10/100/1000 Ethernet, 10G Ethernet, or
SONET/SDH frequencies
•
•
Locks to 1 Pulse Per Second (PPS) references
It can be configured from an external EEPROM after reset
•
Any of eight common TCXO/OCXO frequencies can be used for the
System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz,
24.576 MHz, 25 MHz or 30.72 MHz
The I2C slave, SPI or the UART interface can be used by a host pro-
cessor to access the control and status registers
The I2C master interface can automatically load a device configura-
tion from an external EEPROM after reset
DPLL1 or DPLL3 can be connected to an internal composite clock
generator that outputs its 64 kHz synchronization signal on OUT8
Differential outputs OUT3 to OUT6 output clocks with frequencies
between 1 PPS and 650 MHz
Single ended outputs OUT1, OUT2, OUT7 and OUT8 output clocks
with frequencies between 1 PPS and 125 MHz
Single ended outputs OUT10 and OUT11 output clocks N*8kHz multi-
ples up to 100 MHz
DPLL1 and DPLL2 support independent programmable delays for
each of IN3 to IN14; the delay for each input is programmable in
steps of 0.61 ns with a range of ~±78 ns
The input to output phase delay of DPLL1 and DPLL2 is programma-
ble in steps of 0.0745 ps with a total range of ±20 μs
The clock phase of each of the output dividers for OUT1 (from
APLL1) to OUT8 is individually programmable in steps of ~200 ps
with a total range of +/-180°
FEATURES
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•
•
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•
•
Composite clock inputs (IN1 and IN2) accept 64 kHz synchronization
interface signals per ITU-T G.703
Differential reference inputs (IN3 to IN8) accept clock frequencies
between 1 PPS and 650 MHz
Single ended inputs (IN9 to IN14) accept reference clock frequencies
between 1 PPS and 162.5 MHz
Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any
clock reference input
Reference monitors qualify/disqualify references depending on activ-
ity, frequency and LOS pins
Automatic reference selection state machines select the active refer-
ence for each DPLL based on the reference monitors, priority tables,
revertive and non-revertive settings and other programmable settings
Fractional-N input dividers enable the DPLLs to lock to a wide range
of reference clock frequencies including: 10/100/1000 Ethernet, 10G
Ethernet, OTN, SONET/SDH, PDH, TDM, GSM, CPRI and GNSS
frequencies
Any reference input (IN3 to IN14) can be designated as external sync
pulse inputs (1 PPS, 2 kHz, 4 kHz or 8 kHz) associated with a select-
able reference clock input
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1149.1 JTAG Boundary Scan
144-pin CABGA green package
©2016 Integrated Device Technology, Inc.
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Revision 6, March 29, 2016
82P33810 Short Form Datasheet
•
ITU-T G.8273.2 Telecom Boundary Clock (T-BC) and Telecom
Time Slave Clock (T-TSC)
APPLICATIONS
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Access routers, edge routers, core routers
Carrier Ethernet switches
•
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ITU-T G.8264 Synchronous Equipment Timing Source (SETS)
ITU-T G.8263 Packet-based Equipment Clock (PEC)
ITU-T G.8262 Synchronous Ethernet Equipment Clock (EEC)
ITU-T G.813 Synchronous Equipment Clock (SEC)
Telcordia GR-253-CORE Stratum 3 Clock (S3) and SONET Mini-
mum Clock (SMC)
Multiservice access platforms
PON OLT
LTE eNodeB
IEEE 1588 / PTP Telecom Profile clock synthesizer
DESCRIPTION
The 82P33810 Synchronization Management Unit (SMU) provides tools to manage timing references, clock sources and timing paths for IEEE
1588 / Precision Time Protocol (PTP) and Synchronous Ethernet (SyncE) based clocks. The device supports up to three independent timing paths
that control: PTP clock synthesis; SyncE clock generation; and general purpose frequency translation. The device supports physical layer timing with
Digital PLLs (DPLLs) and it supports packet based timing with Digitally Controlled Oscillators (DCOs). Input-to- input, input-to-output and output-to-
output phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly synchronize Ethernet interfaces; as well as
SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs).
The 82P33810 accepts six differential reference inputs and six single ended reference inputs that can operate at common GNSS, Ethernet,
SONET/SDH and PDH frequencies that range in frequency from 1 Pulse Per Second (PPS) to 650 MHz. The device also provides two Alternate Mark
Inversion (AMI) inputs for Composite Clock (CC) signals bearing 64 kHz, 8 kHz and 0.4 kHz synchronization information. The references are continu-
ally monitored for loss of signal and for frequency offset per user programmed thresholds. All of the references are available to all three DPLLs. The
active reference for each DPLL is determined by forced selection or by automatic selection based on user programmed priorities and locking allow-
ances and based on the reference monitors and LOS inputs.
The 82P33810 can accept a clock reference and an associated phase locked sync signal as a pair. DPLL1 or DPLL2 can lock to the clock refer-
ence and align the frame sync and multi-frame sync outputs with the paired sync input. The device allows any of the differential or single ended refer-
ence inputs to be configured as sync inputs that can be associated with any of the other differential or single ended reference inputs. The input sync
signals can have a frequency of 1 PPS, 2 kHz, 4 kHz or 8 kHz. This feature enables DPLL1 or DPLL2 to phase align its frame sync and multi-frame
sync outputs with a sync input without the need use a low bandwidth setting to lock directly to the sync input.
DPLL1 and DPLL2 support four primary operating modes: Free-Run, Locked, Holdover and DCO. In Free-Run mode the DPLLs synthesize clocks
based on the system clock alone. In Locked mode the DPLLs filter reference clock jitter with the selected bandwidth. In Locked mode, the long-term
output frequency accuracy is the same as the long term frequency accuracy of the selected input reference. In Holdover mode, the DPLL uses fre-
quency data acquired while in Locked mode to generate accurate frequencies when input references are not available. In DCO mode the DPLL con-
trol loop is opened and the DCO can be controlled by a PTP clock recovery servo running on an external processor to synthesize PTP clocks.
The 82P33810 requires a system clock for its reference monitors and other digital circuitry. The frequency accuracy of the system clock deter-
mines the frequency accuracy of the DPLLs in Free-Run mode. The frequency stability of the system clock determines the frequency stability of the
DPLLs in Free-Run mode and in Holdover mode; and it affects the wander generation of the DPLLs in Locked and DCO modes.
When used with a suitable system clock, DPLL1 and DPLL2 meet the frequency accuracy, pull-in, hold-in, pull-out, noise generation, noise toler-
ance, transient response, and holdover performance requirements of the following applications: ITU-T G.8262/G.813 EEC/SEC options 1 and 2, ITU-
T G.8263, ITU-T G.8273.2, Telcordia GR-1244 Stratum 3 (S3), Telcordia GR-253-CORE Stratum 3 (S3) and SONET Minimum Clock (SMC).
DPLL1 and DPLL2 can be configured with a range of selectable filtering bandwidths from 0.09 mHz to 567 Hz. The 17 mHz bandwidth can be
used to lock the DPLL directly to a 1 PPS reference. The 69 mHz and the 92 mHz bandwidths can be used for G.8273.2. The 92 mHz bandwidth can
be used for G.8262/G.813 Option 2 or Telcordia GR-253-CORE S3 or SMC applications. The bandwidths in the range 1.1 Hz to 8.9 Hz can be used
for G.8262/G.813 Option 1 applications. Bandwidths above 10 Hz can be used in jitter attenuation and rate conversion applications.
DPLL1 and DPLL2 are each connected to Time of Day (ToD) counters or time accumulators; these ToD counters/time accumulators can be used
to track differences between the two time domains and to time-stamp external events by using reference inputs as triggers.
DPLL3 supports three primary operation modes: Free-Run, Locked and Holdover. DPLL3 is a wideband (BW > 25Hz) frequency translator that can
be used, for example, to convert a recovered line clock to a 1.544 MHz or 2.048 MHz synchronization interface clock.
In Telecom Boundary Clock (T-BC) and Telecom Time Slave Clock (T-TSC) applications per ITU-T G.8275.2, DPLL1 and DPLL2 are both used;
one DPLL is configured as a DCO to synthesize PTP clocks and the other DPLL is configured as an EEC/SEC to generate physical layer clocks.
Combo mode provides physical layer frequency support from the EEC/SEC to the PTP clock.
©2016 Integrated Device Technology, Inc.
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82P33810 Short Form Datasheet
In Synchronous Equipment Timing Source (SETS) applications per ITU-T G.8264, DPLL1 or DPLL2 can be configured as an EEC/SEC to output
clocks for the T0 reference point and DPLL3 can be used to output clocks for the T4 reference point.
Clocks generated by DPLL1 or DPLL2 can be passed through APLL1 or APLL2 which are LC based jitter attenuating Analog PLLs (APLLs). The
output clocks generated by APLL1 and APLL2 are suitable for serial GbE and lower rate interfaces.
The device provides an AMI output for a CC signal bearing 64 kHz, 8 kHz and 0.4 kHz synchronization information. The CC output can be con-
nected to either DPLL1 or DPLL3.
All 82P33810 control and status registers are accessed through an I2C slave, SPI or the UART microprocessor interface. For configuring the
DPLLs, APLL1 and APLL2, the I2C master interface can automatically load a configuration from an external EEPROM after reset.
FUNCTIONAL BLOCK DIAGRAM
System Clock
LOS0 / XO_FREQ0
LOS1 / XO_FREQ1
LOS2 / XO_FREQ2
SYS PLL
OutDiv
OutDiv
OUT1
OUT2
LOS3
APLL1
APLL2
ToD/ Time
Accumulator
OutDiv
OutDiv
OUT3p/n
OUT4p/n
IN1(CC)
IN2(CC)
Composite
Clocks
DPLL1 /
DCO1
IN3(P/N)
IN4(P/N)
IN5(P/N)
OutDiv
OutDiv
OutDiv
OUT5p/n
OUT6p/n
OUT7
Reference
monitors
IN6(P/N)
IN7(P/N)
DPLL2 /
DCO2
Reference
selection
IN8(P/N)
OutDiv
OUT8
Frac-N input
dividers
IN9
ToD/ Time
Accumulator
IN10
Composite
Clock
OUT9
IN11
IN12
IN13
IN14
OutDiv
OutDiv
OUT10
OUT11
DPLL3
ex_sync module
I2CMaster
FRSYNC_8K_1PPS
MFRSYNC_2K_1PPS
Control and
Status
I2CSlave,
SPI, UART
Registers
JTAG
Figure 1. Functional Block Diagram
©2016 Integrated Device Technology, Inc.
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82P33810 Short Form Datasheet
1
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
11
12
SONET/SDH/LO
S3
IC
IC
IC
IC
VDDAO
OUT5_POS
VDDAO
OUT6_POS
CAP2
IC
IC
A
B
A
B
MPU_MODE1/I
2CM_SCL
VSSAO
VDDAO
VDDAO
VSSAO
VSSAO
OUT5_NEG
VSSAO
OUT6_NEG
VSSA
CAP1
IC
IC
SDO/I2C_SD
A/UART_TX
MPU_MODE0/I Mfrsync_2K_
2CM_SDA
VDDA
VSSA
VSSA
VSS
OUT7
VSSD
VDDA
VSSA
VDDA
VSSA
CS/I2C_AD0
CAP3
OUT8
C
C
1PPS
SDI/I2C_AD2 SCLK/I2C_SC
/UART_RX
VDDA
VSSCOM
VDDD
OUT11
OUT10
D
D
L
CLKE/I2C_AD
1
Frsync_8K_1PP
S
OSCI
TMS
TCK
VSSA
VDDA
VDDA
VDDA
IC
VSSA
IC
VDDDO
VSSDO
VSS
VDDDO
VSSD
VSS
VSSDO
VDDD
IC
VSSA
VSSA
VSS
DPLL3_LOCK
IN14
IN13
E
F
E
F
VSS
VSS
VDDA
IN12
IN11
IN8_NEG
IN7_NEG
IN8_POS
IN7_POS
DPLL2_LOCK
G
G
xo_freq0/
LOS0
VSSA
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
DPLL1_LOCK
INT_REQ
IN2
IN10
IN9
VSSD
VDDD_1_8
IN6_POS
IN5_POS
H
J
H
J
xo_freq1/
LOS1
xo_freq2/
LOS2
IN6_NEG
IN5_NEG
VDDA
VSSA
VDDA
VSSA
TRSTB
VSSAO
OUT2
RSTB
VSSDO
MS_SL
IN1
K
K
TDI
VDDAO
TDO
IC
VDDDO
OUT1
VSSD
VDDD_1_8
IN4_NEG
IN4_POS
L
L
OUT4_POS OUT4_NEG
VSSAO
VDDAO
OUT3_POS OUT3_NEG
VSSDO
VDDDO
OUT9_POS OUT9_NEG
IN3_NEG
IN3_POS
M
M
1
2
3
4
5
6
7
8
9
10
11
12
Figure 2. Pin Assignment (Top View)
©2016 Integrated Device Technology, Inc.
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82P33810 Short Form Datasheet
2
PIN DESCRIPTION
Table 1: Pin Description
Pin No.
Name
I/O
Type
Description
Global Control Signal
OSCI: Crystal Oscillator System Clock
A clock provided by a crystal oscillator is input on this pin. It is the system clock for the
device. The oscillator frequency is selected via pins XO_FREQ0 ~ XO_FREQ2
E1
K8
OSCI
I
CMOS
CMOS
MS/SL: Master / Slave Selection
This pin, together with the MS_SL_CTRL bit, controls whether the device is configured as the
Master or as the Slave. The signal level on this pin is reflected by the MASTER_SLAVE bit.
I
MS/SL
pull-up
SONET/SDH: SONET / SDH Frequency Selection
During reset, this pin determines the default value of the IN_SONET_SDH bit (b2, 09H):
High: The default value of the IN_SONET_SDH bit is ‘1’ (SONET);
Low: The default value of the IN_SONET_SDH bit is ‘0’ (SDH).
After reset, this pin takes on the operation of LOS3
SONET/SDH/
LOS3
I
A11
K6
CMOS
CMOS
pull-down
LOS3- This pin is used to disqualify input clocks.
I
RSTB: Reset
Refer to section 2.2 reset operation for detail.
RSTB
pull-up
XO_FREQ0 ~ XO_FREQ2: These pins set the oscillator frequency.
XO_FREQ[2:0] Oscillator Frequency (MHz)
000
001
010
011
100
101
110
111
10.000
12.800
13.000
19.440
20.000
24.576
25.000
30.720
XO_FREQ0/
LOS0
XO_FREQ1/
LOS1
XO_FREQ2/
LOS2
H1
J1
J2
I
CMOS
pull-down
LOS0 ~ LOS2 - These pins are used to disqualify input clocks. After reset, this pin takes on
the operation of LOS0-LOS2
Input Clock and Frame Synchronization Input Signal
IN1: Input Clock 1
A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is input on this pin.
AMI input has internal 1k ohm to 1.5V termination. This pin can also be used as a frame
pulse input, and in this case a 8 kHz signal can be input on this pin.
K10
K9
IN1
IN2
I
I
AMI
AMI
IN2: Input Clock 2
A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is input on this pin.
AMI input has internal 1k ohm to 1.5V termination. This pin can also be used as a frame
pulse input, and in this case a 8 kHz signal can be input on this pin.
IN3_POS / IN3_NEG: Positive / Negative Input Clock 3
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
M12
M11
IN3_POS
IN3_NEG
I
I
I
I
I
I
PECL/LVDS
PECL/LVDS
PECL/LVDS
PECL/LVDS
PECL/LVDS
PECL/LVDS
IN4_POS / IN4_NEG: Positive / Negative Input Clock 4
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
L12
L11
IN4_POS
IN4_NEG
IN5_POS / IN5_NEG: Positive / Negative Input Clock 5
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
K12
K11
IN5_POS
IN5_NEG
IN6_POS / IN6_NEG: Positive / Negative Input Clock 6
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
J12
J11
IN6_POS
IN6_NEG
IN7_POS / IN7_NEG: Positive / Negative Input Clock 7
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
G12
G11
IN7_POS
IN7_NEG
IN8_POS / IN8_NEG: Positive / Negative Input Clock 8
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
F12
F11
IN8_POS
IN8_NEG
©2016 Integrated Device Technology, Inc.
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Revision 6, March 29, 2016
82P33810 Short Form Datasheet
Table 1: Pin Description (Continued)
Pin No.
Name
I/O
Type
Description
IN9: Input Clock 9
I
J10
IN9
CMOS
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
pull-down
IN10: Input Clock 10
I
H10
G10
F10
E11
E10
IN10
IN11
IN12
IN13
IN14
CMOS
CMOS
CMOS
CMOS
CMOS
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
pull-down
IN11: Input Clock 11
I
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
pull-down
IN12: Input Clock 12
I
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
pull-down
IN13: Input Clock 13
I
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
pull-down
IN14: Input Clock 14
I
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
pull-down
Output Frame Synchronization Signal
FRSYNC
_8K_1PPS
FRSYNC_8K_1PPS: 8 kHz Frame Sync Output
CMOS
E12
C12
O
O
An 8 kHz signal or a 1PPS sync signal is output on this pin.
MFRSYNC
_2K_1PPS
MFRSYNC_2K_1PPS: 2 kHz Multiframe Sync Output
CMOS
A 2 kHz signal or a 1PPS sync signal is output on this pin.
Output Clock
L8
K5
OUT1
OUT2
OUT1 ~ OUT2: Output Clock 1 ~ 2
O
O
O
O
O
O
CMOS
M5
M6
OUT3_POS
OUT3_NEG
OUT3_POS / OUT3_NEG: Positive / Negative Output Clock 3
PECL/LVDS
This output is set to LVDS by default.The LVDS output has internal 100 ohm termination.
M1
M2
OUT4_POS
OUT4_NEG
OUT4_POS / OUT4_NEG: Positive / Negative Output Clock 4
PECL/LVDS
This output is set to LVDS by default.The LVDS output has internal 100 ohm termination.
A6
B6
OUT5_POS
OUT5_NEG
OUT5_POS / OUT5_NEG: Positive / Negative Output Clock 5
PECL/LVDS
This output is set to LVDS by default.The LVDS output has internal 100 ohm termination.
A8
B8
OUT6_POS
OUT6_NEG
OUT6_POS / OUT6_NEG: Positive / Negative Output Clock 6
PECL/LVDS
This output is set to LVDS by default.The LVDS output has internal 100 ohm termination.
C4
C10
OUT7
OUT8
OUT7 ~ OUT8: Output Clock 7 ~ 8
CMOS
OUT9_POS / OUT9_NEG: Positive / Negative Output Composite Clock
A 64 kHz + 8 kHz or 64 kHz + 8 kHz + 0.4 kHz composite clock is differentially output on this
pair of pins.
M9
M10
OUT9_POS
OUT9_NEG
O
O
AMI
D12
D11
OUT10
OUT11
OUT10 ~ OUT11: Output Clock 10 ~ 11
CMOS
Miscellaneous
CAP1, CAP2 and CAP3: Analog Power Filter Capacitor connection 1 to 3. These capacitors
are be part of the power filtering.
CAP1, CAP2,
CAP3
C9, A9, D8
Lock Signal
DPLL3_LOCK
This pin goes high when DPLL3 is locked
DPLL2_LOCK
This pin goes high when DPLL2 is locked
DPLL1_LOCK
This pin goes high when DPLL1 is locked
DPLL3_LOCK
DPLL2_LOCK
DPLL1_LOCK
E9
G9
H9
O
O
O
CMOS
CMOS
CMOS
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82P33810 Short Form Datasheet
Table 1: Pin Description (Continued)
Pin No.
Name
I/O
Type
Description
Microprocessor Interface
O
INT_REQ: Interrupt Request
This pin is used as an interrupt request.
J9
INT_REQ
CMOS
Tri-state
MPU_MODE[1:0]: Microprocessor Interface Mode Selection
During reset, these pins determine the default value of the MPU_SEL_CNFG[1:0] bits as fol-
lows:
00: I2C mode
01: SPI mode
10: UART mode
11: I2C master (EEPROM) mode
I2CM_SCL: Serial Clock Line
In I2C master mode, the serial clock is output on this pin.
I2CM_SDA: Serial Data Input for I2C Master Mode
In I2C master mode, this pin is used as the for the serial data.
MPU_MODE1/
I2CM_SCL
B11
C11
I/O
CMOS/
pull-down Open Drain
MPU_MODE0/
I2CM_SDA
SDI: Serial Data Input
In Serial mode, this pin is used as the serial data input. Address and data on this pin are seri-
ally clocked into the device on the rising edge of SCLK.
SDI/I2C_AD2/
UART_RX
I
I2C_AD2: Device Address Bit 2
In I2C mode, I2C_AD[2:0] pins are the address bus of the microprocessor interface.
D9
CMOS
pull-down
UART_RX
In UART mode, this pin is used as the receive data (UART Receive)
CLKE: SCLK Active Edge Selection
In Serial mode, this pin is an input, it selects the active edge of SCLK to update the SDO:
High - The falling edge;
Low - The rising edge.
I
E5
C8
CLKE/I2C_AD1
CS/I2C_AD0
CMOS
pull-down
I2C_AD1: Device Address Bit 1
In I2C mode, I2C_AD[2:0] pins are the address bus of the microprocessor interface.
CS: Chip Selection
In Serial modes, this pin is an input.A transition from high to low must occur on this pin for
each read or write operation and this pin should remain low until the operation is over.
I
CMOS
pull-up
I2C_AD0: Device Address Bit 0
In I2C mode, I2C_AD[2:0] pins are the address bus of the microprocessor interface.
SCLK: Shift Clock
In Serial mode, a shift clock is input on this pin.
Data on SDI is sampled by the device on the rising edge of SCLK. Data on SDO is updated
on the active edge of SCLK. The active edge is determined by the CLKE.
D10
SCLK/I2C_SCL
I
CMOS
I2C_SCL: Serial Clock Line
In I2C mode, the serial clock is input on this pin.
SDO: Serial Data Output
In Serial mode, this pin is used as the serial data output. Data on this pin is serially clocked
out of the device on the active edge of SCLK.
SDO/I2C_SDA/
UART_TX
CMOS/
Open Drain
I2C_SDA: Serial Data Input/Output
In I2C mode, this pin is used as the input/output for the serial data.
C5
I/O
UART_TX:
In UART mode, this pin is used as the transmit data (UART Transmit)
©2016 Integrated Device Technology, Inc.
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82P33810 Short Form Datasheet
Table 1: Pin Description (Continued)
Pin No.
Name
I/O
Type
Description
JTAG (per IEEE 1149.1)
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK.
I
F1
K3
TMS
CMOS
CMOS
pull-up
TRSTB: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port.
This pin should be connected to ground when JTAG is not used.
I
TRSTB
pull-up
TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely
retain their state.
I
G1
TCK
CMOS
pull-down
TDI: JTAG Test Data Input
The test data are input on this pin. They are clocked into the device on the rising edge of
TCK.
I
L3
L5
TDI
CMOS
CMOS
pull-up
TDO: JTAG Test Data Output
The test data are output on this pin. They are clocked out of the device on the falling edge of
TCK.
O
TDO
tri-state
TDO pin outputs a high impedance signal except during the process of data scanning.
Power & Ground
C1, C6, C7, D2, F2, F9,
G2, H2, K1, K2
VDDA: Analog Core Power - +3.3V DC nominal
VDDA
Power
-
-
A5, A7, B2, B3, L4, M4
E4, E6, L7, M8
D5,F7
VDDAO
VDDDO
VDDD
Power
Power
Power
Power
VDDAO: Analog Output Power - +3.3V DC nominal
VDDDO: Digital Output Power - +3.3V DC nominal
VDDD: Digital Core Power - +3.3V DC nominal
VDDD_1_8: Digital Core Power - +1.8V DC nominal
VSSA: Ground
L10, H12
VDDD_1_8
B9, C2, D1, D6, D7, E2,
E8, F3, F8, H3, L1, L2
VSSA
Ground
B1, B4, B5, B7, K4, M3
E7, F4, K7, M7
D4, F6, H11, L9
D3
VSSAO
VSSDO
VSSD
Ground
Ground
Ground
Ground
VSSAO: Ground
VSSDO: Ground
VSSD: Ground
VSSCOM: Ground
VSS: Ground
VSSCOM
-
-
C3, F5, G4, G5, G6, G8,
H4, H5, H6, H7, H8, J3,
J4, J5, J6, J7, J8
VSS
Ground
Other
A1, A2, A3, A4, A10,
A12, B10, B12, E3, G3,
G7, L6
IC: Internal Connection
Internal Use. This pin must be left open for normal operation.
IC
-
-
©2016 Integrated Device Technology, Inc.
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82P33810 Short Form Datasheet
2.1.2
OUTPUTS
2.1
RECOMMENDATIONS FOR UNUSED INPUT
AND OUTPUT PINS
Status Pins
2.1.1
INPUTS
For applications not requiring the use of a status pin, we recommend
bringing out to a test point for debugging purposes.
Control Pins
Single-Ended Clock Outputs
All control pins have internal pull-ups or pull-downs; additional resis-
tance is not required but can be added for additional protection. A 1kΩ
resistor can be used.
All unused single-ended clock outputs can be left floating, or can be
brought out to a test point for debugging purposes.
Differential Clock Outputs
Single-Ended Clock Inputs
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output pair
should either be left floating or terminated.
For protection, unused single-ended clock inputs should be tied to
ground.
Differential Clock Inputs
For applications not requiring the use of a differential input, both
*_POS and *_NEG can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from _POS to ground.
©2016 Integrated Device Technology, Inc.
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Revision 6, March 29, 2016
82P33810 Short Form Datasheet
PACKAGE DIMENSIONS
Figure 3. 144-Pin BAG Package Dimensions
©2016 Integrated Device Technology, Inc.
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Revision 6, March 29, 2016
82P33810 Short Form Datasheet
Figure 4. 144-Pin BAG Package Recommended Land Pattern
©2016 Integrated Device Technology, Inc.
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Revision 6, March 29, 2016
82P33810 Short Form Datasheet
ORDERING INFORMATION
Table 2: Ordering Information
Part/Order Number
Package
Shipping Packaging
Tray
Temperature
-40o to +85oC
-40o to +85oC
82P33810ABAG
82P33810ABAG8
144-pin CABGA green package
144-pin CABGA green package
Tape & Reel
"G" after the two-letter package code denotes Pb-Free configuration, RoHS compliant.
©2016 Integrated Device Technology, Inc.
12
Revision 6, March 29, 2016
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Fax: 408-284-2775
www.IDT.com
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document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
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