82P33814_17 [IDT]
Synchronization Management Unit for IEEE 1588 and 10G/40G/100G Synchronous Ethernet;型号: | 82P33814_17 |
厂家: | INTEGRATED DEVICE TECHNOLOGY |
描述: | Synchronization Management Unit for IEEE 1588 and 10G/40G/100G Synchronous Ethernet |
文件: | 总12页 (文件大小:340K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Synchronization Management Unit for
82P33814
Datasheet
IEEE 1588 and 10G/40G/100G Synchronous Ethernet
This is a short form datasheet and is intended to provide an overview only. Additional details are available from IDT. Contact information may be found
on the last page.
•
•
•
DPLL1 and DPLL2 lock to input references with frequencies
between 1 PPS and 650 MHz
DPLL3 locks to input references with frequencies between 8 kHz
and 650 MHz
DPLL1 and DPLL2 comply with ITU-T G.8262 for Synchronous
Ethernet Equipment Clock (EEC), and G.813 for Synchronous
Equipment Clock (SEC); and Telcordia GR-253-CORE for Stratum
3 and SONET Minimum Clock (SMC)
DPLL1 and DPLL2 generate clocks with PDH, TDM, GSM, CPRI/
OBSAI, 10/100/1000 Ethernet and GNSS frequencies; these clocks
are directly available on OUT1 and OUT8
DPLL1 and DPLL2 can be configured as DCOs to synthesize IEEE
1588 clocks
DPLL3 generates N x 8 kHz clocks up to 100 MHz that are output
on OUT9 and OUT10
APLL1 and APLL2 can be connected to DPLL1 or DPLL2
APLL1 and APLL2 generate 10/100/1000 Ethernet, 10G Ethernet,
or SONET/SDH frequencies
Any of eight common TCXO/OCXO frequencies can be used for
the System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20
MHz, 24.576 MHz, 25 MHz or 30.72 MHz
The I2C slave, SPI or the UART interface can be used by a host
processor to access the control and status registers
The I2C master interface can automatically load a device configura-
tion from an external EEPROM after reset
Differential outputs OUT3 to OUT6 output clocks with frequencies
between 1 PPS and 650 MHz
Single ended outputs OUT1, OUT2, OUT7 and OUT8 output clocks
with frequencies between 1 PPS and 125 MHz
Single ended outputs OUT9 and OUT10 output clocks N*8kHz mul-
tiples up to 100 MHz
DPLL1 and DPLL2 support independent programmable delays for
each of IN1 to IN6; the delay for each input is programmable in
steps of 0.61 ns with a range of ~±78 ns
The input to output phase delay of DPLL1 and DPLL2 is program-
mable in steps of 0.0745 ps with a total range of ±20 μs
The clock phase of each of the output dividers for OUT1 (from
APLL1) to OUT8 is individually programmable in steps of ~200 ps
with a total range of +/-180°
HIGHLIGHTS
•
Synchronization Management Unit (SMU) provides tools to man-
age physical layer and packet based synchronous clocks for IEEE
1588 / PTP Telecom Profile applications
•
•
Supports independent IEEE 1588 and Synchronous Ethernet
(SyncE) timing paths
Combo mode provides SyncE physical layer frequency support for
IEEE 1588 Telecom Boundary Clocks (T-BC) and Telecom Time
Slave Clocks (T-TSC) per G.8273.2
•
•
•
Digital PLL 1 (DPLL1) and DPLL 2 can be configured as Digitally
Controlled Oscillators (DCOs) for PTP clock synthesis
DCO frequency resolution is [(77760 / 1638400) * 2^-48] or
~1.686305041e-10 ppm
•
•
•
•
DPLL1 and DPLL2 generate G.8262 compliant SyncE clocks
Two independent Time of Day (ToD) counters/time accumulators,
one associated with each of DPLL1 and DPLL2, can be used to
track differences between the two time domains and to time-stamp
external events
•
•
•
•
•
•
DPLL3 performs rate conversions to frequency synchronization
interfaces or for other general purpose timing applications
APLL1 and APLL2 generate clocks with jitter < 1 ps RMS (12 kHz
to 20 MHz) for: 1000BASE-T and 1000BASE-X
Fractional-N input dividers support a wide range of reference fre-
quencies
•
•
•
•
•
•
•
•
Locks to 1 Pulse Per Second (PPS) references
It can be configured from an external EEPROM after reset
FEATURES
•
•
•
•
•
Differential reference inputs (IN1 to IN4) accept clock frequencies
between 1 PPS and 650 MHz
Single ended inputs (IN5 to IN6) accept reference clock frequen-
cies between 1 PPS and 162.5 MHz
Loss of Signal (LOS) pins (LOS0 to LOS3) can be assigned to any
clock reference input
Reference monitors qualify/disqualify references depending on
activity, frequency and LOS pins
Automatic reference selection state machines select the active ref-
erence for each DPLL based on the reference monitors, priority
tables, revertive and non-revertive settings and other programma-
ble settings
•
•
•
•
1149.1 JTAG Boundary Scan
72-pin QFN green package
•
Fractional-N input dividers enable the DPLLs to lock to a wide
range of reference clock frequencies including: 10/100/1000 Ether-
net, 10G Ethernet, OTN, SONET/SDH, PDH, TDM, GSM, CPRI
and GNSS frequencies
APPLICATIONS
•
•
•
•
•
•
•
Access routers, edge routers, core routers
Carrier Ethernet switches
Multiservice access platforms
PON OLT
LTE eNodeB
IEEE 1588 / PTP Telecom Profile clock synthesizer
ITU-T G.8273.2 Telecom Boundary Clock (T-BC) and Telecom
Time Slave Clock (T-TSC)
ITU-T G.8264 Synchronous Equipment Timing Source (SETS)
ITU-T G.8263 Packet-based Equipment Clock (PEC)
•
•
•
Any reference input (IN1 to IN6) can be designated as external
sync pulse inputs (1 PPS, 2 kHz, 4 kHz or 8 kHz) associated with a
selectable reference clock input
FRSYNC_8K_1PPS and MFRSYNC_2K_1PPS output sync pulses
that are aligned with the selected external input sync pulse input
and frequency locked to the associated reference clock input
DPLL1 and DPLL2 can be configured with bandwidths between
0.09 mHz and 567 Hz
•
•
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82P33814 Datasheet
•
•
ITU-T G.8262 Synchronous Ethernet Equipment Clock (EEC)
ITU-T G.813 Synchronous Equipment Clock (SEC)
•
Telcordia GR-253-CORE Stratum 3 Clock (S3) and SONET Mini-
mum Clock (SMC)
DESCRIPTION
The 82P33814 Synchronization Management Unit (SMU) provides tools to manage timing references, clock sources and timing paths for IEEE
1588 / Precision Time Protocol (PTP) and Synchronous Ethernet (SyncE) based clocks. The device supports up to three independent timing paths
that control: PTP clock synthesis; SyncE clock generation; and general purpose frequency translation. The device supports physical layer timing with
Digital PLLs (DPLLs) and it supports packet based timing with Digitally Controlled Oscillators (DCOs). Input-to- input, input-to-output and output-to-
output phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly synchronize lower-rate Ethernet interfaces; as
well as CPRI/OBSAI, SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs).
The 82P33814 accepts four differential reference inputs and two single ended reference inputs that can operate at common GNSS, Ethernet,
SONET/SDH and PDH frequencies that range in frequency from 1 Pulse Per Second (PPS) to 650 MHz. The references are continually monitored for
loss of signal and for frequency offset per user programmed thresholds. All of the references are available to all three DPLLs. The active reference for
each DPLL is determined by forced selection or by automatic selection based on user programmed priorities and locking allowances and based on
the reference monitors and LOS inputs.
The 82P33814 can accept a clock reference and an associated phase locked sync signal as a pair. DPLL1 or DPLL2 can lock to the clock refer-
ence and align the frame sync and multi-frame sync outputs with the paired sync input. The device allows any of the differential or single ended refer-
ence inputs to be configured as sync inputs that can be associated with any of the other differential or single ended reference inputs. The input sync
signals can have a frequency of 1 PPS, 2 kHz, 4 kHz or 8 kHz. This feature enables DPLL1 or DPLL2 to phase align its frame sync and multi-frame
sync outputs with a sync input without the need use a low bandwidth setting to lock directly to the sync input.
DPLL1 and DPLL2 support four primary operating modes: Free-Run, Locked, Holdover and DCO. In Free-Run mode the DPLLs synthesize clocks
based on the system clock alone. In Locked mode the DPLLs filter reference clock jitter with the selected bandwidth. In Locked mode, the long-term
output frequency accuracy is the same as the long term frequency accuracy of the selected input reference. In Holdover mode, the DPLL uses fre-
quency data acquired while in Locked mode to generate accurate frequencies when input references are not available. In DCO mode the DPLL con-
trol loop is opened and the DCO can be controlled by a PTP clock recovery servo running on an external processor to synthesize PTP clocks.
The 82P33814 requires a system clock for its reference monitors and other digital circuitry. The frequency accuracy of the system clock deter-
mines the frequency accuracy of the DPLLs in Free-Run mode. The frequency stability of the system clock determines the frequency stability of the
DPLLs in Free-Run mode and in Holdover mode; and it affects the wander generation of the DPLLs in Locked and DCO modes.
When used with a suitable system clock, DPLL1 and DPLL2 meet the frequency accuracy, pull-in, hold-in, pull-out, noise generation, noise toler-
ance, transient response, and holdover performance requirements of the following applications: ITU-T G.8262/G.813 EEC/SEC options 1 and 2, ITU-
T G.8263, ITU-T G.8273.2, Telcordia GR-1244 Stratum 3 (S3), Telcordia GR-253-CORE Stratum 3 (S3) and SONET Minimum Clock (SMC).
DPLL1 and DPLL2 can be configured with a range of selectable filtering bandwidths from 0.09 mHz to 567 Hz. The 17 mHz bandwidth can be
used to lock the DPLL directly to a 1 PPS reference. The 69 mHz and the 92 mHz bandwidths can be used for G.8273.2. The 92 mHz bandwidth can
be used for G.8262/G.813 Option 2 or Telcordia GR-253-CORE S3 or SMC applications. The bandwidths in the range 1.1 Hz to 8.9 Hz can be used
for G.8262/G.813 Option 1 applications. Bandwidths above 10 Hz can be used in jitter attenuation and rate conversion applications.
DPLL1 and DPLL2 are each connected to Time of Day (ToD) counters or time accumulators; these ToD counters/time accumulators can be used
to track differences between the two time domains and to time-stamp external events by using reference inputs as triggers.
DPLL3 supports three primary operation modes: Free-Run, Locked and Holdover. DPLL3 is a wideband (BW > 25Hz) frequency translator that can
be used, for example, to convert a recovered line clock to a 1.544 MHz or 2.048 MHz synchronization interface clock.
In Telecom Boundary Clock (T-BC) and Telecom Time Slave Clock (T-TSC) applications per ITU-T G.8275.2, DPLL1 and DPLL2 are both used;
one DPLL is configured as a DCO to synthesize PTP clocks and the other DPLL is configured as an EEC/SEC to generate physical layer clocks.
Combo mode provides physical layer frequency support from the EEC/SEC to the PTP clock.
In Synchronous Equipment Timing Source (SETS) applications per ITU-T G.8264, DPLL1 or DPLL2 can be configured as an EEC/SEC to output
clocks for the T0 reference point and DPLL3 can be used to output clocks for the T4 reference point.
Clocks generated by DPLL1 or DPLL2 can be passed through APLL1 or APLL2 which are LC based jitter attenuating Analog PLLs (APLLs). The
output clocks generated by APLL1 and APLL2 are suitable for serial GbE and lower rate interfaces.
All 82P33814 control and status registers are accessed through an I2C slave, SPI or the UART microprocessor interface. For configuring the
DPLLs, APLL1 and APLL2, the I2C master interface can automatically load a configuration from an external EEPROM after reset.
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82P33814 Datasheet
FUNCTIONAL BLOCK DIAGRAM
SystemClock
LOS0 / XO_FREQ0
LOS1 / XO_FREQ1
LOS2 / XO_FREQ2
SYS PLL
OutDiv
OutDiv
OUT1
OUT2
LOS3
APLL1
APLL2
ToD/ Time
Accumulator
OutDiv
OutDiv
OUT3p/n
OUT4p/n
DPLL1 /
DCO1
IN1(P/N)
IN2(P/N)
IN3(P/N)
IN4(P/N)
OutDiv
OutDiv
OUT5p/n
OUT6p/n
Reference
monitors
DPLL2 /
DCO2
Reference
selection
OutDiv
OutDiv
OUT7
OUT8
IN5
IN6
Frac-N input
dividers
ToD/ Time
Accumulator
OutDiv
OutDiv
OUT9
DPLL3
OUT10
ex_sync module
I2CMaster
FRSYNC_8K_1PPS
MFRSYNC_2K_1PPS
Control and
Status
I2CSlave,
SPI, UART
Registers
JTAG
Figure 1. Functional Block Diagram
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82P33814 Datasheet
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PIN ASSIGNMENT
1
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
DPLL3_LOCK
VC2
2
VDDD_1_8
VDDA
3
RSTB
VDDA
4
SDO/I2C_SDA/UART_TX
SCLK/I2C_SCL
CS/I2C_AD0
VDDA
5
VDDA
6
OSCi
7
CLKE/I2C_AD1
SDI/I2C_AD2/UART_RX
MPU_MODE1/I2CM_SCL
MPU_MODE0/I2CM_SDA
MFRSYNC_2K_1PPS
FRSYNC_8K_1PPS
VDDD_1_8
XO_FREQ0/LOS0
XO_FREQ1/LOS1
8
9
XO_FREQ2/LOS2
VDDA
VDDA
VDDA
VC1
82P33814
10
11
12
13
14
15
16
17
18
TMS
IN6
TRSTB
TCK
VDDD
IN4_NEG
TDI
38 IN4_POS
37
TDO
IN5
Figure 2. Pin Assignment (Top View)
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82P33814 Datasheet
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PIN DESCRIPTION
Table 1: Pin Description
Pin No.
Name
I/O
Type
Description
Global Control Signal
OSCI: Crystal Oscillator System Clock
A clock provided by a crystal oscillator is input on this pin. It is the system clock for the
device. The oscillator frequency is selected via pins XO_FREQ0 ~ XO_FREQ2
6
OSCI
I
CMOS
CMOS
MS/SL: Master / Slave Selection
This pin, together with the MS_SL_CTRL bit, controls whether the device is configured as the
Master or as the Slave. The signal level on this pin is reflected by the MASTER_SLAVE bit.
I
58
MS/SL
pull-up
I
59
52
LOS3
RSTB
CMOS
CMOS
LOS3- This pin is used to disqualify input clocks. See input clocks section for more details.
pull-down
I
RSTB: Reset
Refer to section 2.2 reset operation for detail.
pull-up
XO_FREQ0 ~ XO_FREQ2: These pins set the oscillator frequency.
XO_FREQ[2:0] Oscillator Frequency (MHz)
000
001
010
011
100
101
110
111
10.000
12.800
13.000
19.440
20.000
24.576
25.000
30.720
XO_FREQ0/
LOS0
XO_FREQ1/
LOS1
XO_FREQ2/
LOS2
7
8
9
I
pull-down
CMOS
LOS0 ~ LOS2 - These pins are used to disqualify input clocks. See input clocks section for
more details. After reset, this pin takes on the operation of LOS0-LOS2
Input Clock and Frame Synchronization Input Signal
IN1_POS / IN1_NEG: Positive / Negative Input Clock 1
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
31
32
IN1_POS
IN1_NEG
I
I
I
I
PECL/LVDS
PECL/LVDS
PECL/LVDS
PECL/LVDS
CMOS
IN2_POS / IN2_NEG: Positive / Negative Input Clock 1
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
33
34
IN2_POS
IN2_NEG
IN3_POS / IN3_NEG: Positive / Negative Input Clock 3
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
35
36
IN3_POS
IN3_NEG
IN4_POS / IN4_NEG: Positive / Negative Input Clock 4
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
38
39
IN4_POS
IN4_NEG
IN5: Input Clock 5
I
37
41
IN5
IN6
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
pull-down
IN6: Input Clock 6
I
CMOS
A reference clock is input on this pin.This pin can also be used as a sync input, and in this
case a 2 kHz, 4 kHz, 8 kHz, or 1PPS signal can be input on this pin.
pull-down
Output Frame Synchronization Signal
FRSYNC
_8K_1PPS
FRSYNC_8K_1PPS: 8 kHz Frame Sync Output
CMOS
43
44
O
O
An 8 kHz signal or a 1PPS sync signal is output on this pin.
MFRSYNC
_2K_1PPS
MFRSYNC_2K_1PPS: 2 kHz Multiframe Sync Output
CMOS
A 2 kHz signal or a 1PPS sync signal is output on this pin.
Output Clock
30
28
OUT1
OUT2
OUT1 ~ OUT2: Output Clock 1 ~ 2
O
CMOS
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82P33814 Datasheet
Table 1: Pin Description (Continued)
Pin No.
Name
I/O
Type
Description
25
26
OUT3_POS
OUT3_NEG
OUT3_POS / OUT3_NEG: Positive / Negative Output Clock 3
This output is set to LVDS by default.The LVDS output has internal 100 ohm termination.
O
PECL/LVDS
21
22
OUT4_POS
OUT4_NEG
OUT4_POS / OUT4_NEG: Positive / Negative Output Clock 4
This output is set to LVDS by default.The LVDS output has internal 100 ohm termination.
O
O
O
O
O
PECL/LVDS
PECL/LVDS
PECL/LVDS
CMOS
71
70
OUT5_POS
OUT5_NEG
OUT5_POS / OUT5_NEG: Positive / Negative Output Clock 5
This output is set to LVDS by default.The LVDS output has internal 100 ohm termination.
68
67
OUT6_POS
OUT6_NEG
OUT6_POS / OUT6_NEG: Positive / Negative Output Clock 6
This output is set to LVDS by default.The LVDS output has internal 100 ohm termination.
65
63
OUT7
OUT8
OUT7 ~ OUT8: Output Clock 7 ~ 8
OUT9 ~ OUT10: Output Clock 9 ~ 10
Miscellaneous
61
60
OUT9
OUT10
CMOS
VC1: APLL1 VC Output
An external RC filter (a resistor in series with a capacitor to ground, and another capacitor in
parallel) should be connected to this pin.
13
1
VC1
VC2
O
O
Analog
Analog
VC2: APLL2 VC Output
An external RC filter (a resistor in series with a capacitor to ground, and another capacitor in
parallel) should be connected to this pin.
Lock Signal
DPLL3_LOCK
This pin goes high when DPLL3 is locked
DPLL2_LOCK
This pin goes high when DPLL2 is locked
DPLL1_LOCK
This pin goes high when DPLL1 is locked
54
56
55
DPLL3_LOCK
DPLL2_LOCK
DPLL1_LOCK
O
O
O
CMOS
CMOS
CMOS
Microprocessor Interface
O
INT_REQ: Interrupt Request
This pin is used as an interrupt request.
57
INT_REQ
CMOS
Tri-state
MPU_MODE[1:0]: Microprocessor Interface Mode Selection
During reset, these pins determine the default value of the MPU_SEL_CNFG[1:0] bits as fol-
lows:
00: I2C mode
01: SPI mode
10: UART mode
11: I2C master (EEPROM) mode
I2CM_SCL: Serial Clock Line
In I2C master mode, the serial clock is output on this pin.
I2CM_SDA: Serial Data Input for I2C Master Mode
In I2C master mode, this pin is used as the for the serial data.
MPU_MODE1/
I2CM_SCL
46
45
I/O
CMOS/
pull-down Open Drain
MPU_MODE0/
I2CM_SDA
SDI: Serial Data Input
In Serial mode, this pin is used as the serial data input. Address and data on this pin are seri-
ally clocked into the device on the rising edge of SCLK.
SDI/I2C_AD2/
UART_RX
I
I2C_AD2: Device Address Bit 2
In I2C mode, I2C_AD[2:0] pins are the address bus of the microprocessor interface.
47
CMOS
pull-down
UART_RX
In UART mode, this pin is used as the receive data (UART Receive)
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82P33814 Datasheet
Table 1: Pin Description (Continued)
Pin No.
Name
I/O
Type
Description
CLKE: SCLK Active Edge Selection
In Serial mode, this pin is an input, it selects the active edge of SCLK to update the SDO:
High - The falling edge;
Low - The rising edge.
I
48
CLKE/I2C_AD1
CMOS
pull-down
I2C_AD1: Device Address Bit 1
In I2C mode, I2C_AD[2:0] pins are the address bus of the microprocessor interface.
CS: Chip Selection
In Serial modes, this pin is an input.A transition from high to low must occur on this pin for
I
each read or write operation and this pin should remain low until the operation is over.
49
50
CS/I2C_AD0
CMOS
CMOS
pull-up
I2C_AD0: Device Address Bit 0
In I2C mode, I2C_AD[2:0] pins are the address bus of the microprocessor interface.
SCLK: Shift Clock
In Serial mode, a shift clock is input on this pin.
Data on SDI is sampled by the device on the rising edge of SCLK. Data on SDO is updated
on the active edge of SCLK. The active edge is determined by the CLKE.
SCLK/I2C_SCL
I
I2C_SCL: Serial Clock Line
In I2C mode, the serial clock is input on this pin.
SDO: Serial Data Output
In Serial mode, this pin is used as the serial data output. Data on this pin is serially clocked
out of the device on the active edge of SCLK.
SDO/I2C_SDA/
UART_TX
CMOS
Open Drain
I2C_SDA: Serial Data Input/Output
In I2C mode, this pin is used as the input/output for the serial data.
51
I/O
UART_TX:
In UART mode, this pin is used as the transmit data (UART Transmit)
JTAG (per IEEE 1149.1)
TMS: JTAG Test Mode Select
The signal on this pin controls the JTAG test performance and is sampled on the rising edge
of TCK.
I
14
15
TMS
CMOS
CMOS
pull-up
TRSTB: JTAG Test Reset (Active Low)
A low signal on this pin resets the JTAG test port.
This pin should be connected to ground when JTAG is not used.
I
TRSTB
pull-up
TCK: JTAG Test Clock
The clock for the JTAG test is input on this pin. TDI and TMS are sampled on the rising edge
of TCK and TDO is updated on the falling edge of TCK.
If TCK is idle at a low level, all stored-state devices contained in the test logic will indefinitely
retain their state.
I
16
TCK
CMOS
pull-down
TDI: JTAG Test Data Input
The test data are input on this pin. They are clocked into the device on the rising edge of
TCK.
I
17
18
TDI
CMOS
CMOS
pull-up
TDO: JTAG Test Data Output
The test data are output on this pin. They are clocked out of the device on the falling edge of
TCK.
O
TDO
tri-state
TDO pin outputs a high impedance signal except during the process of data scanning.
Power & Ground
2, 3, 4, 5, 10 11, 12
20, 24, 69, 72
VDDA
VDDAO
VDDDO
Power
Power
Power
-
VDDA: Analog Core Power - +3.3V DC nominal
VDDAO: Analog Output Power - +3.3V DC nominal
VDDDO: Digital Output Power - +3.3V DC nominal
27, 29, 64, 66
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82P33814 Datasheet
Table 1: Pin Description (Continued)
Pin No.
Name
I/O
Type
Description
VDDD: Digital Core Power - +3.3V DC nominal
40, 62
42, 53
VDDD
VDDD_1_8
VSSAO
VSS
Power
Power
VDDD_1_8: Digital Core Power - +1.8V DC nominal
VSSAO: Ground
19,23
Ground
Ground
73 (e_PAD)
-
VSS: Ground
For applications not requiring the use of a differential input, both
*_POS and *_NEG can be left floating. Though not required, but for
additional protection, a 1kΩ resistor can be tied from _POS to ground.
2.1
RECOMMENDATIONS FOR UNUSED INPUT
AND OUTPUT PINS
2.1.1
INPUTS
2.1.2
OUTPUTS
Control Pins
Status Pins
All control pins have internal pull-ups or pull-downs; additional resis-
tance is not required but can be added for additional protection. A 1kΩ
resistor can be used.
For applications not requiring the use of a status pin, we recommend
bringing out to a test point for debugging purposes.
Single-Ended Clock Outputs
Single-Ended Clock Inputs
All unused single-ended clock outputs can be left floating, or can be
brought out to a test point for debugging purposes.
For protection, unused single-ended clock inputs should be tied to
ground.
Differential Clock Outputs
Differential Clock Inputs
All unused differential outputs can be left floating. We recommend
that there is no trace attached. Both sides of the differential output pair
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82P33814 Datasheet
PACKAGE DIMENSIONS
Figure 3. 72-Pin QFN Package Outline Page 1 (SAWN Option)
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82P33814 Datasheet
Figure 4. 72-Pin QFN Package Outline Page 2 (SAWN Option)
©2017 Integrated Device Technology, Inc. 14
Revision 7, January 9, 2017
82P33814 Datasheet
Figure 5. 72-Pin QFN Package Recommended Land Pattern
©2017 Integrated Device Technology, Inc. 15
Revision 7, January 9, 2017
82P33814 Datasheet
ORDERING INFORMATION
Table 2: Ordering Information
Part/Order Number
Package
Shipping Packaging
Tray
Temperature
-40o to +85oC
-40o to +85oC
-40o to +85oC
82P33814ANLG
82P33814ANLG8
82P33814ANLG/W
72-pin QFN green package
72-pin QFN green package
72-pin QFN green package
Tape & Reel, Pin 1 Orientation: EIA-481-C
Tape & Reel, Pin 1 Orientation: EIA-481-D
"G" after the two-letter package code denotes Pb-Free configuration, RoHS compliant.
Table 3: Pin 1 Orientation in Tape and Reel Packaging
Part Number Suffix
Pin 1 Orientation
Illustration
CARRIER TAPE TOPSIDE
(Round Sprocket Holes)
Correct Pin 1 ORIENTATION
NLG8
Quadrant 1 (EIA-481-C)
USER DIRECTION OF FEED
Correct Pin 1 ORIENTATION
CARRIER TAPE TOPSIDE
(Round Sprocket Holes)
NLG/W
Quadrant 2 (EIA-481-D)
USER DIRECTION OF FEED
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San Jose, CA 95138 USA
www.IDT.com
Sales
Tech Support
www.IDT.com/go/support
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as “IDT”) reserve the right to modify the products and/or specifications described herein at any time,
without notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same
way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability
of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not
convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be rea-
sonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc. All rights reserved.
©2017 Integrated Device Technology, Inc.
16
Revision 7, January 9, 2017
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