82V2052EPF8 [IDT]
PCM Transceiver, 1-Func, PQFP80, TQFP-80;
| 型号： | 82V2052EPF8 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | PCM Transceiver, 1-Func, PQFP80, TQFP-80 PC 电信 电信集成电路 |
| 文件： | 总70页 (文件大小：726K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DUAL CHANNEL E1
IDT82V2052E
SHORT HAUL LINE INTERFACE UNIT
FEATURES:
•
•
Dual channel E1 short haul line interfaces
Supports HPS (Hitless Protection Switching) for 1+1 protection
without external relays
- PRBS (Pseudo Random Bit Sequence) generation and detection
15
with 2 -1 PRBS polynomials
- 16-bit BPV (Bipolar Pulse Violation) / Excess Zero/ PRBS error
counter
- Analog loopback, Digital loopback, Remote loopback
Adaptive receive sensitivity up to -20 dB (Host Mode only)
Non-intrusive monitoring per ITU G.772 specification
Short circuit protection and internal protection diode for line
drivers
LOS (Loss Of Signal) detection with programmable LOS levels
(Host Mode only)
AIS (Alarm Indication Signal) detection
JTAG interface
Supports serial control interface, Motorola and Intel Non-Multi-
plexed interfaces and hardware control mode
Pin compatible to 82V2082 T1/E1/J1 Long Haul/Short Haul LIU
and 82V2042E T1/E1/J1 Short Haul LIU
Available in 80-pin TQFP
•
•
Single 3.3 V power supply with 5 V tolerance on digital interfaces
Meets or exceeds specifications in
- ANSI T1.102
- ITU I.431, G.703, G.736, G.775 and G.823
- ETSI 300-166, 300-233 and TBR12/13
•
•
•
•
Software programmable or hardware selectable on:
- Wave-shaping templates
•
- Line terminating impedance (E1: 75 Ω/120 Ω)
- Adjustment of arbitrary pulse shape
- JA (Jitter Attenuator) position (receive path or transmit path)
- Single rail/dual rail system interfaces
•
•
•
- HDB3/AMI line encoding/decoding
- Active edge of transmit clock (TCLK) and receive clock (RCLK)
- Active level of transmit data (TDATA) and receive data (RDATA)
- Receiver or transmitter power down
•
•
- High impedance setting for line drivers
Green package options available
DESCRIPTION:
The IDT82V2052E is a dual channel E1 Line Interface Unit. The
IDT82V2052Eperformsclock/datarecovery, AMI/HDB3linedecodingand
detects and reports the LOS conditions. An integrated Adaptive Equalizer
is available to increase the receive sensitivity and enable programming of
LOS levels. In transmit path, thereis anAMI/HDB3encoder andWaveform
Shaper. There is one Jitter Attenuator, which can be placed in either the
receivepathorthetransmitpath.TheJitterAttenuatorcanalsobedisabled.
The IDT82V2052E supports both Single Rail and Dual Rail system inter-
faces. Tofacilitatethenetworkmaintenance,aPRBSgeneration/detection
circuit is integrated in the chip, and different types of loopbacks can be set
accordingtotheapplications. Twodifferentkindsoflineterminatingimped-
ance, 75 Ω and 120 Ω are selectable on a per channel basis. The chip also
provides driver short-circuit protection and internal protection diode and
supports JTAG boundary scanning. The chip can be controlled by either
software or hardware.
The IDT82V2052E can be used in LAN, WAN, Routers, Wireless Base
Stations, IADs, IMAs, IMAPs, Gateways, Frame Relay Access Devices,
CSU/DSU equipment, etc.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
.
1
December 12, 2005
2005 Integrated Device Technology, Inc.
DSC-6779/1
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL BLOCK DIAGRAM
One of the Two Identical Channels
LOSn
LOS/AIS
Detector
Receiver
Internal
Termination
RCLKn
RDn/RDPn
CVn/RDNn
Data and
Clock
Recovery
Adaptive
Equalizer
RTIPn
Data
Slicer
Jitter
Attenuator
HDB3/AMI
Decoder
RRINGn
PRBS Detector
Remote
Loopback
Analog
Loopback
Digital
Loopback
TCLKn
TDn/TDPn
TDNn
TTIPn
Transmitter
Internal
Termination
Jitter
Attenuator
Line
Driver
Waveform
Shaper
HDB3/AMI
Decoder
TRINGn
PRBS Generator
TAOS
Clock
Generator
Register
Files
JTAG TAP
Software Control Interface
Pin Control
G.772
Monitor
VDDIO
VDDD
VDDA
VDDT
VDDR
Figure-1 Block Diagram
FUNCTIONAL BLOCK DIAGRAM
2
December 12, 2005
Table of Contents
1
2
3
IDT82V2052E PIN CONFIGURATIONS ....................................................................................... 8
PIN DESCRIPTION ....................................................................................................................... 9
FUNCTIONAL DESCRIPTION .................................................................................................... 17
3.1
3.2
CONTROL MODE SELECTION ....................................................................................... 17
TRANSMIT PATH ............................................................................................................. 17
3.2.1 TRANSMIT PATH SYSTEM INTERFACE.............................................................. 17
3.2.2 ENCODER.............................................................................................................. 17
3.2.3 PULSE SHAPER .................................................................................................... 17
3.2.3.1 Preset Pulse Templates .......................................................................... 17
3.2.3.2 User-Programmable Arbitrary Waveform ................................................ 18
3.2.4 TRANSMIT PATH LINE INTERFACE..................................................................... 20
3.2.5 TRANSMIT PATH POWER DOWN........................................................................ 20
3.3
RECEIVE PATH ............................................................................................................... 20
3.3.1 RECEIVE INTERNAL TERMINATION.................................................................... 20
3.3.2 LINE MONITOR...................................................................................................... 21
3.3.3 ADAPTIVE EQUALIZER......................................................................................... 22
3.3.4 RECEIVE SENSITIVITY ......................................................................................... 22
3.3.5 DATA SLICER ........................................................................................................ 22
3.3.6 CDR (Clock & Data Recovery)................................................................................ 22
3.3.7 DECODER.............................................................................................................. 22
3.3.8 RECEIVE PATH SYSTEM INTERFACE ................................................................ 22
3.3.9 RECEIVE PATH POWER DOWN........................................................................... 23
3.3.10 G.772 NON-INTRUSIVE MONITORING ................................................................ 23
JITTER ATTENUATOR .................................................................................................... 24
3.4.1 JITTER ATTENUATION FUNCTION DESCRIPTION ............................................ 24
3.4.2 JITTER ATTENUATOR PERFORMANCE ............................................................. 24
LOS AND AIS DETECTION ............................................................................................. 25
3.5.1 LOS DETECTION................................................................................................... 25
3.5.2 AIS DETECTION .................................................................................................... 26
TRANSMIT AND DETECT INTERNAL PATTERNS ........................................................ 27
3.6.1 TRANSMIT ALL ONES........................................................................................... 27
3.6.2 TRANSMIT ALL ZEROS......................................................................................... 27
3.6.3 PRBS GENERATION AND DETECTION............................................................... 27
LOOPBACK ...................................................................................................................... 27
3.7.1 ANALOG LOOPBACK ............................................................................................ 27
3.7.2 DIGITAL LOOPBACK ............................................................................................. 27
3.7.3 REMOTE LOOPBACK............................................................................................ 27
3.4
3.5
3.6
3.7
Table of Contents
3
December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
3.8
ERROR DETECTION/COUNTING AND INSERTION ...................................................... 30
3.8.1 DEFINITION OF LINE CODING ERROR ............................................................... 30
3.8.2 ERROR DETECTION AND COUNTING ................................................................ 30
3.8.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION ...................................... 31
LINE DRIVER FAILURE MONITORING ........................................................................... 31
3.9
3.10 MCLK AND TCLK ............................................................................................................. 32
3.10.1 MASTER CLOCK (MCLK) ...................................................................................... 32
3.10.2 TRANSMIT CLOCK (TCLK).................................................................................... 32
3.11 MICROCONTROLLER INTERFACES ............................................................................. 33
3.11.1 PARALLEL MICROCONTROLLER INTERFACE................................................... 33
3.11.2 SERIAL MICROCONTROLLER INTERFACE ........................................................ 33
3.12 INTERRUPT HANDLING .................................................................................................. 34
3.13 5V TOLERANT I/O PINS .................................................................................................. 35
3.14 RESET OPERATION ........................................................................................................ 35
3.15 POWER SUPPLY ............................................................................................................. 35
4
PROGRAMMING INFORMATION .............................................................................................. 36
4.1
4.2
4.3
REGISTER LIST AND MAP ............................................................................................. 36
Reserved Registers .......................................................................................................... 36
REGISTER DESCRIPTION .............................................................................................. 38
4.3.1 GLOBAL REGISTERS............................................................................................ 38
4.3.2 TRANSMIT AND RECEIVE TERMINATION REGISTER....................................... 39
4.3.3 JITTER ATTENUATION CONTROL REGISTER ................................................... 39
4.3.4 TRANSMIT PATH CONTROL REGISTERS........................................................... 40
4.3.5 RECEIVE PATH CONTROL REGISTERS ............................................................. 42
4.3.6 NETWORK DIAGNOSTICS CONTROL REGISTERS ........................................... 43
4.3.7 INTERRUPT CONTROL REGISTERS................................................................... 45
4.3.8 LINE STATUS REGISTERS................................................................................... 47
4.3.9 INTERRUPT STATUS REGISTERS ...................................................................... 48
4.3.10 COUNTER REGISTERS ........................................................................................ 49
5
6
HARDWARE CONTROL PIN SUMMARY .................................................................................. 50
IEEE STD 1149.1 JTAG TEST ACCESS PORT ........................................................................ 52
6.1
6.2
JTAG INSTRUCTIONS AND INSTRUCTION REGISTER ............................................... 53
JTAG DATA REGISTER ................................................................................................... 53
6.2.1 DEVICE IDENTIFICATION REGISTER (IDR)........................................................ 53
6.2.2 BYPASS REGISTER (BR)...................................................................................... 53
6.2.3 BOUNDARY SCAN REGISTER (BSR) .................................................................. 53
6.2.4 TEST ACCESS PORT CONTROLLER .................................................................. 53
7
8
TEST SPECIFICATIONS ............................................................................................................ 56
MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS ......................................... 65
8.1
8.2
SERIAL INTERFACE TIMING .......................................................................................... 65
PARALLEL INTERFACE TIMING ..................................................................................... 66
Table of Contents
4
December 12, 2005
List of Tables
Table-1
Pin Description................................................................................................................ 9
Transmit Waveform Value For E1 75 Ohm................................................................... 19
Transmit Waveform Value For E1 120 Ohm................................................................. 19
Impedance Matching for Transmitter ............................................................................ 20
Impedance Matching for Receiver ................................................................................ 21
Criteria of Starting Speed Adjustment........................................................................... 24
LOS Declare and Clear Criteria, Adaptive Equalizer Disabled ..................................... 25
LOS Declare and Clear Criteria, Adaptive Equalizer Enabled ...................................... 26
AIS Condition ................................................................................................................ 26
Criteria for Setting/Clearing the PRBS_S Bit ................................................................ 27
EXZ Definition ............................................................................................................... 30
Interrupt Event............................................................................................................... 34
Global Register List and Map........................................................................................ 36
Per Channel Register List and Map .............................................................................. 37
ID: Device Revision Register ........................................................................................ 38
RST: Reset Register ..................................................................................................... 38
GCF: Global Configuration Register ............................................................................. 38
INTCH: Interrupt Channel Indication Register............................................................... 38
TERM: Transmit and Receive Termination Configuration Register .............................. 39
JACF: Jitter Attenuation Configuration Register ........................................................... 39
TCF0: Transmitter Configuration Register 0 ................................................................. 40
TCF1: Transmitter Configuration Register 1 ................................................................. 40
TCF2: Transmitter Configuration Register 2 ................................................................. 41
TCF3: Transmitter Configuration Register 3 ................................................................. 41
TCF4: Transmitter Configuration Register 4 ................................................................. 41
RCF0: Receiver Configuration Register 0..................................................................... 42
RCF1: Receiver Configuration Register 1..................................................................... 42
RCF2: Receiver Configuration Register 2..................................................................... 43
MAINT0: Maintenance Function Control Register 0...................................................... 43
MAINT1: Maintenance Function Control Register 1...................................................... 44
MAINT6: Maintenance Function Control Register 6...................................................... 44
INTM0: Interrupt Mask Register 0................................................................................. 45
INTM1: Interrupt Masked Register 1............................................................................. 45
INTES: Interrupt Trigger Edge Select Register............................................................. 46
STAT0: Line Status Register 0 (real time status monitor)............................................. 47
STAT1: Line Status Register 1 (real time status monitor)............................................. 48
INTS0: Interrupt Status Register 0................................................................................ 48
INTS1: Interrupt Status Register 1................................................................................ 49
CNT0: Error Counter L-byte Register 0......................................................................... 49
CNT1: Error Counter H-byte Register 1........................................................................ 49
Hardware Control Pin Summary ................................................................................... 50
Table-2
Table-3
Table-4
Table-5
Table-6
Table-7
Table-8
Table-9
Table-10
Table-11
Table-12
Table-13
Table-14
Table-15
Table-16
Table-17
Table-18
Table-19
Table-20
Table-21
Table-22
Table-23
Table-24
Table-25
Table-26
Table-27
Table-28
Table-29
Table-30
Table-31
Table-32
Table-33
Table-34
Table-35
Table-36
Table-37
Table-38
Table-39
Table-40
Table-41
List of Tables
5
December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-42
Table-43
Table-44
Table-45
Table-46
Table-47
Table-48
Table-49
Table-50
Table-51
Table-52
Table-53
Table-54
Table-55
Table-56
Table-57
Table-58
Table-59
Instruction Register Description .................................................................................... 53
Device Identification Register Description..................................................................... 53
TAP Controller State Description .................................................................................. 54
Absolute Maximum Rating ............................................................................................ 56
Recommended Operation Conditions........................................................................... 56
Power Consumption...................................................................................................... 57
DC Characteristics ........................................................................................................ 57
Receiver Electrical Characteristics................................................................................ 58
Transmitter Electrical Characteristics............................................................................ 59
Transmitter and Receiver Timing Characteristics ......................................................... 60
Jitter Tolerance ............................................................................................................. 61
Jitter Attenuator Characteristics.................................................................................... 62
JTAG Timing Characteristics ........................................................................................ 63
Serial Interface Timing Characteristics ......................................................................... 65
Non-Multiplexed Motorola Read Timing Characteristics............................................... 66
Non-Multiplexed Motorola Write Timing Characteristics ............................................... 67
Non-Multiplexed Intel Read Timing Characteristics ...................................................... 68
Non-Multiplexed Intel Write Timing Characteristics ...................................................... 69
List of Tables
6
December 12, 2005
List of Figures
Figure-1
Block Diagram ................................................................................................................. 2
IDT82V2052E TQFP80 Package Pin Assignment .......................................................... 8
E1 Waveform Template Diagram .................................................................................. 17
E1 Pulse Template Test Circuit ..................................................................................... 18
Receive Path Function Block Diagram .......................................................................... 21
Transmit/Receive Line Circuit ....................................................................................... 21
Monitoring Receive Line in Another Chip ...................................................................... 22
Monitor Transmit Line in Another Chip .......................................................................... 22
G.772 Monitoring Diagram ............................................................................................ 23
Jitter Attenuator ............................................................................................................. 24
LOS Declare and Clear ................................................................................................. 25
Analog Loopback .......................................................................................................... 28
Digital Loopback ............................................................................................................ 28
Remote Loopback ......................................................................................................... 29
Auto Report Mode ......................................................................................................... 30
Manual Report Mode ..................................................................................................... 31
TCLK Operation Flowchart ............................................................................................ 32
Serial Microcontroller Interface Function Timing ........................................................... 33
JTAG Architecture ......................................................................................................... 52
JTAG State Diagram ..................................................................................................... 55
Transmit System Interface Timing ................................................................................ 60
Receive System Interface Timing ................................................................................. 61
E1 Jitter Tolerance Performance .................................................................................. 62
E1 Jitter Transfer Performance ..................................................................................... 63
JTAG Interface Timing .................................................................................................. 64
Serial Interface Write Timing ......................................................................................... 65
Serial Interface Read Timing with SCLKE=1 ................................................................ 65
Serial Interface Read Timing with SCLKE=0 ................................................................ 65
Non-Multiplexed Motorola Read Timing ........................................................................ 66
Non-Multiplexed Motorola Write Timing ........................................................................ 67
Non-Multiplexed Intel Read Timing ............................................................................... 68
Non-Multiplexed Intel Write Timing ............................................................................... 69
Figure-2
Figure-3
Figure-4
Figure-5
Figure-6
Figure-7
Figure-8
Figure-9
Figure-10
Figure-11
Figure-12
Figure-13
Figure-14
Figure-15
Figure-16
Figure-17
Figure-18
Figure-19
Figure-20
Figure-21
Figure-22
Figure-23
Figure-24
Figure-25
Figure-26
Figure-27
Figure-28
Figure-29
Figure-30
Figure-31
Figure-32
List of Figures
7
December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
1
IDT82V2052E PIN CONFIGURATIONS
VDDT1
TRING1
TTIP1
VDDIO
61
62
63
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
GNDIO
TCLK1
GNDT1
GNDR1
RRING1
RTIP1
TDP1 / TD1
TDN1
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
RCLK1
RDP1 / RD1
RDN1 / CV1
LOS1
VDDR1
VDDA
IDT82V2052E
IC
VDDD
REF
MCLK
GNDA
VDDR2
RTIP2
GNDD
LOS2
RDN2 / CV2
RDP2 / RD2
RCLK2
TDN2
RRING2
GNDR2
GNDT2
TTIP2
TDP2 / TD2
TCLK2
TRING2
VDDT2
RST
Figure-2 IDT82V2052E TQFP80 Package Pin Assignment
IDT82V2052E PIN CONFIGURATIONS
8
December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
2
PIN DESCRIPTION
Table-1 Pin Description
Name
Type
Pin No.
Description
TTIPn1/TRINGn: Transmit Bipolar Tip/Ring for Channel 1~2
These pins are the differential line driver outputs and can be set to high impedance state globally or individually. A logic high
TTIP1
TTIP2
Analog
Output
63
78
on THZ pin turns all these pins into high impedance state. When THZ bit (TCF1, 03H...)2 is set to ‘1’, the TTIPn/TRINGn in
the corresponding channel is set to high impedance state.
In summary, these pins will become high impedance in the following conditions:
TRING1
TRING2
62
79
•
•
•
•
THZ pin is high: all TTIPn/TRINGn enter high impedance;
THZn bit is set to 1: the corresponding TTIPn/TRINGn become high impedance;
Loss of MCLK: all TTIPn/TRINGn pins become high impedance;·
Loss of TCLKn: the corresponding TTIPn/TRINGn become HZ (exceptions: Remote Loopback; Transmit internal pat-
tern by MCLK);
•
•
Transmitter path power down: the corresponding TTIPn/TRINGn become high impedance;
After software reset; pin reset and power on: all TTIPn/TRINGn enter high impedance.
RTIP1
RTIP2
Analog
Input
67
74
RTIPn/RRINGn: Receive Bipolar Tip/Ring for Channel 1~2
These signals are the differential receiver inputs.
RRING1
RRING2
66
75
TD1/TDP1
TD2/TDP2
I
37
23
TDn: Transmit Data for Channel 1~2
When the device is in single rail mode, the NRZ data to be transmitted is input on this pin. Data on TDn pin is sampled into
the device on the active edge of TCLKn and is encoded by AMI or HDB3 line code rules before being transmitted. In this mode,
TDNn should be connected to ground.
TDN1
TDN2
36
24
TDPn/TDNn: Positive/Negative Transmit Data
When the device is in dual rail mode, the NRZ data to be transmitted for positive/negative pulse is input on these pins. Data
on TDPn/TDNn pin is sampled into the device on the active edge of TCLKn. The active polarity is also selectable. Refer to
3.2.1 TRANSMIT PATH SYSTEM INTERFACE for details. The line code in dual rail mode is as follows:
TDPn
TDNn
Output Pulse
Space
0
0
1
1
0
1
0
1
Positive Pulse
Negative Pulse
Space
TCLK1
TCLK2
I
38
22
TCLKn: Transmit Clock for Channel 1~2
This pin inputs a 2.048 MHz transmit clock. The transmit data at TDn/TDPn or TDNn is sampled into the device on the active
edge of TCLKn. If TCLKn is missing3 and the TCLKn missing interrupt is not masked, an interrupt will be generated.
Notes:
1. The footprint ‘n’ (n = 1~2) represents one of the two channels.
2. The name and address of the registers that contain the preceding bit. Only the address of channel 1 register is listed, the rest addresses are represented by ‘...’. Users can find
these omitted addresses in the Register Description section.
3. TCLKn missing: the state of TCLKn continues to be high level or low level over 70 MCLK cycles.
PIN DESCRIPTION
9
December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name
Type
O
Pin No.
Description
RD1/RDP1
RD2/RDP2
34
26
RDn: Receive Data output for Channel 1~2
In single rail mode, this pin outputs NRZ data. The data is decoded according to AMI or HDB3 line code rules.
CV1/RDN1
CV2/RDN2
33
27
CVn: Code Violation indication
In single rail mode, the BPV/CV errors in received data stream will be reported by driving the CVn pin to high level for a full
clock cycle. HDB3 line code violation can be indicated if the HDB3 decoder is enabled. When AMI decoder is selected, bipolar
violation will be indicated.
In hardware control mode, the EXZ, BPV/CV errors in received data stream are always monitored by the CVn pin if single rail
mode is chosen.
RDPn/RDNn: Positive/Negative Receive Data output for Channel 1~2
In dual rail mode, these pins output the re-timed NRZ data when CDR is enabled, or directly outputs the raw RZ slicer data
if CDR is bypassed.
Active edge and level select:
Data on RDPn/RDNn or RDn is clocked with either the rising or the falling edge of RCLKn. The active polarity is also select-
able. Refer to 3.3.8 RECEIVE PATH SYSTEM INTERFACE for details.
RCLK1
RCLK2
O
35
25
RCLKn: Receive Clock output for Channel 1~2
This pin outputs a 2.048 MHz receive clock. Under LOS conditions with AIS enabled (bit AISE=1), RCLKn is derived from
MCLK.
In clock recovery mode, this signal provides the clock recovered from the RTIPn/RRINGn signal. The receive data (RDn in
single rail mode or RDPn and RDNn in dual rail mode) is clocked out of the device on the active edge of RCLKn.
If clock recovery is bypassed, RCLKn is the exclusive OR (XOR) output of the dual rail slicer data RDPn and RDNn. This signal
can be used in applications with external clock recovery circuitry.
MCLK
I
30
MCLK: Master Clock input
A built-in clock system that accepts a 2.048 MHz reference clock. This reference clock is used to generate several internal
reference signals:
•
•
•
•
•
Timing reference for the integrated clock recovery unit.
Timing reference for the integrated digital jitter attenuator.
Timing reference for microcontroller interface.
Generation of RCLKn signal during a loss of signal condition.
Reference clock to transmit All Ones, all zeros and PRBS pattern. Note that for ATAO and AIS, MCLK is always used
as the reference clock.
•
Reference clock during Transmit All Ones (TAO) condition or sending PRBS in hardware control mode.
The loss of MCLK will turn TTIP/TRING into high impedance status.
LOS1
LOS2
O
I
32
28
LOSn: Loss of Signal Output for Channel 1~2
These pins are used to indicate the loss of received signals. When LOSn pin becomes high, it indicates the loss of received
signal in channel n. The LOS pin will become low automatically when valid received signal is detected again. The criteria of
loss of signal are described in 3.5 LOS AND AIS DETECTION.
REF
71
REF: reference resister
An external resistor (3kΩ, 1%) is used to connect this pin to ground to provide a standard reference current for internal circuit.
PIN DESCRIPTION
10
December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name
Type
I
Pin No.
Description
MODE1
MODE0
9
10
MODE[1:0]: operation mode of control interface select
The level on this pin determines which control mode is used to control the device as follows:
MODE[1:0]
Control Interface mode
Hardware interface
00
01
10
11
Serial Microcontroller Interface
Motorola non-multiplexed
Intel non-multiplexed
•
•
•
The serial microcontroller interface consists of CS, SCLK, SCLKE, SDI, SDO and INT pins. SCLKE is used for the
selection of the active edge of SCLK.
The parallel non-multiplexed microcontroller interface consists of CS, A[5:0], D[7:0], DS/RD, R/W/WR and INT pins.
(Refer to 3.11 MICROCONTROLLER INTERFACES for details)
Hardware interface consists of PULSn, THZ, RCLKE, LPn[1:0], PATTn[1:0], JA[1:0], MONTn, TERMn, RPDn,
MODE[1:0] and RXTXM[1:0] (n=1, 2).
RCLKE
I
I
11
RCLKE: the active edge of RCLKn select
In hardware control mode, this pin selects the active edge of RCLKn
•
•
L= update RDPn/RDNn on the rising edge of RCLKn
H= update RDPn/RDNn on the falling edge of RCLKn
In software control mode, this pin should be connected to GNDIO.
RXTXM1
RXTXM0
14
15
RXTXM[1:0]: Receive and transmit path operation mode select
In hardware control mode, these pins are used to select the single rail or dual rail operation modes as well as AMI or HDB3
line coding:
•
•
•
•
00= single rail with HDB3 coding
01= single rail with AMI coding
10= dual rail interface with CDR enabled
11= slicer mode (dual rail interface with CDR disabled)
In software control mode, these pins should be connected to ground.
CS
I
42
CS: Chip Select
In serial or parallel microcontroller interface mode, this is the active low enable signal. A low level on this pin enables serial
or parallel microcontroller interface.
LP11
LP11/LP10: Loopback mode select for channel 1
When the chip is configured by hardware, this pin is used to select loopback operation modes for channel 1.:
•
•
•
•
00 = no loopback
01 = analog loopback
10 = digital loopback
11 = remote loopback
INT
O
41
INT: Interrupt Request
In software control mode, this pin outputs the general interrupt request for all interrupt sources. If INTM_GLB bit (GCF, 20H)
is set to ‘1’, all the interrupt sources will be masked. These interrupt sources can be masked individually via registers (INTM0,
13H...) and (INTM1, 14H...). The interrupt status is reported via the registers (INTCH, 21H), (INTS0, 18H...) and (INTS1,
19H...).
Output characteristics of this pin can be defined to be push-pull (active high or active low) or open-drain (active low) by setting
bits INT_PIN[1:0] (GCF, 20H)
LP10
I
LP11/LP10: Loopback mode select for channel 1
See above LP11.
PIN DESCRIPTION
11
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name
SCLK
Type
I
Pin No.
46
Description
SCLK: Shift Clock
In serial microcontroller interface mode, this signal is the shift clock for the serial interface. Configuration data on SDI pin is
sampled on the rising edge of SCLK. Configuration and status data on SDO pin is clocked out of the device on the rising edge
of SCLK if SCLKE pin is low, or on the falling edge of SCLK if SCLKE pin is high.
In parallel non-multiplexed interface mode, this pin should be connected to ground.
PATT11
SCLKE
PATT11/PATT10: Transmit pattern select for channel 1
In hardware control mode, this pin selects the transmit pattern
•
•
•
•
00 = normal
01= All Ones
10= PRBS
11= transmitter power down
I
45
SCLKE: Serial Clock Edge Select
In serial microcontroller interface mode, this signal selects the active edge of SCLK for outputting SDO. The output data is
valid after some delay from the active clock edge. It can be sampled on the opposite edge of the clock. The active clock edge
which clocks the data out of the device is selected as shown below:
SCLKE
Low
SCLK
Rising edge is the active edge.
Falling edge is the active edge.
High
DS: Data Strobe
DS
RD
In Motorola parallel non-multiplexed interface mode, this signal is the data strobe of the parallel interface. In a write operation
(R/W = 0), the data on D[7:0] is sampled into the device. In a read operation (R/W = 1), the data is driven to D[7:0] by the
device.
RD: Read Strobe
In Intel parallel non-Multiplexed interface mode, the data is driven to D[7:0] by the device during low level of RD in a read oper-
ation.
PATT11/PATT10: Transmit pattern select for channel 1
See above PATT11.
PATT10
SDI
I
44
SDI: Serial Data Input
In serial microcontroller interface mode, this signal is the input data to the serial interface. Configuration data at SDI pin is sam-
pled by the device on the rising edge of SCLK.
R/W
R/W: Read/Write Select
In Motorola parallel non-multiplexed interface mode, this pin is low for write operation and high for read operation.
WR
WR: Write Strobe
In Intel parallel non-multiplexed interface mode, this pin is asserted low by the microcontroller to initiate a write cycle. The data
on D[7:0] is sampled into the device in a write operation.
LP21
LP21/LP20: loopback mode select for channel 2
When the chip is configured by hardware, this pin is used to select loopback operation modes for channel 2:.
•
•
•
•
00 = no loopback
01 = analog loopback
10 = digital loopback
11 = remote loopback
PIN DESCRIPTION
12
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name
SDO
Type
O
Pin No.
43
Description
SDO: Serial Data Output
In serial microcontroller interface mode, this signal is the output data of the serial interface. Configuration or Status data at
SDO pin is clocked out of the device on the rising edge of SCLK if SCLKE pin is low, or on the falling edge of SCLK if SCLKE
pin is high.
In parallel non-multiplexed interface mode, this pin should be left open.
LP20
D7
I
LP21/LP20: loopback mode select for channel 2
See above LP21.
I/O
54
53
52
51
D7: Data Bus bit7
In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.
In Hardware mode, this pin has to be tied to GND.
D6
D5
I/O
I/O
D6: Data Bus bit6
In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.
In Hardware mode, this pin has to be tied to GND.
D5: Data Bus bit5
In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.
In Hardware mode, this pin has to be tied to GND.
D4
I/O
I
D4: Data Bus bit4
In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.
PULS1
PULS1: This pin is used to select the following functions for Channel 1 in Hardware control mode:
•
•
Transmit pulse template
Internal termination impedance (75 Ω / 120 Ω)
Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
D3
D2
D1
I/O
I/O
I/O
50
49
48
D3: Data Bus bit3
In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.
In Hardware mode, this pin has to be tied to GND.
D2: Data Bus bit2
In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.
In Hardware mode, this pin has to be tied to GND.
D1: Data Bus bit1
In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.
In Hardware mode, this pin has to be tied to GND.
PIN DESCRIPTION
13
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name
D0
Type
I/O
Pin No.
47
Description
D0: Data Bus bit0
In Intel/Motorola non-multiplexed interface mode, this signal is the bi-directional data bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground through a 10 kΩ resistor.
PULS2
A5
I
I
PULS2: This pin is used to select the following functions for Channel 2 in Hardware control mode:
•
•
Transmit pulse template
Internal termination impedance (75 Ω / 120 Ω)
Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
60
59
A5: Address Bus bit5
In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground.
In Hardware mode, this pin has to be tied to GND.
A4
I
A4: Address Bus bit4
In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground.
RPD2
A3
RPD2: Power down control for receiver2 in hardware control mode
0= receiver 2 normal operation
1= receiver 2 power down
I
I
58
57
A3: Address Bus bit3
In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground.
In Hardware mode, this pin has to be tied to GND.
A2
A2: Address Bus bit2
In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground.
RPD1
A1
RPD1: Power down control for receiver1 in hardware control mode
0= receiver 1 normal operation
1= receiver 1 power down
I
56
A1: Address Bus bit1
In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground.
PATT21
PATT21/PATT20: Transmit pattern select for channel 2
In hardware control mode, this pin selects the transmit pattern
00 = normal
01= All Ones
10= PRBS
11= transmitter power down
A0
I
I
55
A0: Address Bus bit 0
In Intel/Motorola non-multiplexed interface mode, this signal is the address bus of the microcontroller interface.
In serial microcontroller interface mode, this pin should be connected to ground.
PATT20
See above
TERM1
TERM2
13
12
TERMn: Selects internal or external impedance matching for channel 1 and channel 2 in hardware control mode
0 = ternary interface with internal impedance matching network
1 = ternary interface with external impedance matching network
In software control mode, this pin should be connected to ground.
PIN DESCRIPTION
14
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name
JA1
Type
I
Pin No.
16
Description
JA[1:0]: Jitter attenuation position, bandwidth and the depth of FIFO select for channel 1 and channel 2 (only used
in hardware control mode)
•
•
•
•
00 = JA is disabled
01= JA in receiver, broad bandwidth, FIFO=64 bits
10 = JA in receiver, narrow bandwidth, FIFO=128 bits
11= JA in transmitter, narrow bandwidth, FIFO=128 bits
In software control mode, this pin should be connected to ground.
JA0
I
I
17
18
See above.
MONT2
MONT2: Receive Monitor gain select for channel 2
In hardware control mode with ternary interface, this pin selects the receive monitor gain of receiver:
0= 0dB
1= 26dB
In software control mode, this pin should be connected to ground.
MONT1
I
19
MONT1: Receive Monitor gain select for channel 1
In hardware control mode with ternary interface, this pin selects the receive monitor gain of receiver:
0= 0dB
1= 26dB
In software control mode, this pin should be connected to ground.
RST
I
I
21
20
RST: Hardware Reset
The chip is forced to reset state if a low signal is input on this pin for more than 100ns. MCLK must be active during reset.
THZ
THZ: Transmitter Driver High Impedance Enable
This signal enables or disables all transmitter drivers on a global basis. A low level on this pin enables the driver while a high
level on this pin places all drivers in high impedance state. Note that the functionality of the internal circuits is not affected by
this signal.
JTAG Signals
TRST
I
1
TRST: JTAG Test Port Reset
Pullup
This is the active low asynchronous reset to the JTAG Test Port. This pin has an internal pull-up resistor. To ensure determin-
istic operation of the test logic, TMS should be held high while the signal applied to TRST changes from low to high.
For normal signal processing, this pin should be connected to ground.
If JTAG is not used, this pin must be connected to ground.
TMS
TCK
I
2
3
TMS: JTAG Test Mode Select
This pin is used to control the test logic state machine and is sampled on the rising edge of TCK. TMS has an internal pull-
up resistor.
Pullup
If JTAG is not used, this pin may be left unconnected.
I
TCK: JTAG Test Clock
This is the input clock for JTAG. The data on TDI and TMS are clocked into the device on the rising edge of TCK while the
data on TDO is clocked out of the device on the falling edge of TCK. When TCK is idle at low state, all the stored-state devices
contained in the test logic will retain their state indefinitely.
If JTAG is not used, this pin may be left unconnected.
TDO
TDI
O
4
5
TDO: JTAG Test Data Output
This output pin is high impedance normally and is used for reading all the serial configuration and test data from the test logic.
The data on TDO is clocked out of the device on the falling edge of TCK.
If JTAG is not used, this pin should be left unconnected.
I
TDI: JTAG Test Data Input
Pullup
This pin is used for loading instructions and data into the test logic and has an internal pull-up resistor. The data on TDI is
clocked into the device on the rising edge of TCK.
If JTAG is not used, this pin may be left unconnected.
Power Supplies and Grounds
3.3 V I/O power supply
VDDIO
GNDIO
-
-
7,40
8,39
I/O ground
PIN DESCRIPTION
15
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-1 Pin Description (Continued)
Name
Type
-
Pin No.
Description
VDDT1
VDDT2
61
80
3.3 V power supply for transmitter driver
Analog ground for transmitter driver
Power supply for receive analog circuit
Analog ground for receive analog circuit
GNDT1
GNDT2
-
-
-
64
77
VDDR1
VDDR2
68
73
GNDR1
GNDR2
65
76
VDDD
GNDD
VDDA
GNDA
-
-
-
-
31
29
69
72
3.3V digital core power supply
Digital core ground
Analog core circuit power supply
Analog core circuit ground
Others
IC
IC
-
-
70
6
IC: Internal Connection
Internal Use. This pin should be left open in normal operation.
IC: Internal Connection
Internal Use. This pin should be connected to ground in normal operation.
PIN DESCRIPTION
16
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
3.2.2 ENCODER
3
FUNCTIONAL DESCRIPTION
In Single Rail mode, the Encoder can be configured to be a HDB3
encoder or an AMI encoder by setting T_MD[0] bit (TCF0, 04H...).
3.1 CONTROL MODE SELECTION
The IDT82V2052E can be configured by software or by hardware. The
softwarecontrolmodesupportsSerialControlInterface,Motorolanon-Mul-
tiplexed Control Interface and Intel non-Multiplexed Control Interface. The
Control mode is selected by MODE1 and MODE0 pins as follows:
In Dual Rail mode, the Encoder is by-passed. In Dual Rail mode, a logic
‘1’ontheTDPnpinandalogic‘0’ontheTDNnpinresultsinanegativepulse
on the TTIPn/TRINGn; a logic ‘0’ on TDPn pin and a logic ‘1’ on TDNn pin
results in a positive pulse on the TTIPn/TRINGn. If both TDPn and TDNn
are high or low, the TTIPn/TRINGn outputs a space (Refer to TDn/TDPn,
TDNn Pin Description).
Control Interface Mode
00
01
10
11
Hardware interface
In hardware control mode, the operation mode of receive and transmit
path can be selected by setting RXTXM1 and RXTXM0 pins on a global
basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
Serial Microcontroller Interface.
Parallel -non-Multiplexed -Motorola Interface
Parallel -non-Multiplexed -Intel Interface
3.2.3 PULSE SHAPER
The IDT82V2052E provides two ways of manipulating the pulse shape
before sending it. One is to use preset pulse templates; the other is to use
user-programmable arbitrary waveform template.
•
The serial microcontroller Interface consists of CS, SCLK, SCLKE,
SDI, SDO and INT pins. SCLKE is used for the selection of active
edge of SCLK.
•
•
The parallel non-Multiplexed microcontroller Interface consists of
CS, A[5:0], D[7:0], DS/RD, R/W/WR and INT pins.
Hardware interface consists of PULSn, THZ, RCLKE, LPn[1:0],
PATTn[1:0], JA[1:0], MONTn, TERMn, RPDn, MODE[1:0] and
RXTXM[1:0] (n=1, 2). Refer to 5 HARDWARE CONTROL PIN SUM-
MARY for details about hardware control.
In software control mode, the pulse shape can be selected by setting
the related registers.
In hardware control mode, the pulse shape can be selected by setting
PULSn pins on a per channel basis. Refer to 5 HARDWARE CONTROL PIN
SUMMARY for details.
3.2.3.1 Preset Pulse Templates
3.2 TRANSMIT PATH
The pulse shape is shown in Figure-3 according to the G.703 and the
measuring diagram is shown in Figure-4. In internal impedance matching
mode, if the cable impedance is 75 Ω, the PULS[3:0] bits (TCF1, 05H...)
shouldbesetto‘0000’;ifthecableimpedanceis120 Ω, thePULS[3:0]bits
(TCF1, 05H...) should be set to ‘0001’. In external impedance matching
mode,forbothE1/75ΩandE1/120Ωcableimpedance,PULS[3:0]should
be set to ‘0001’.
The transmit path of each channel of IDT82V2052E consists of an
Encoder, an optional Jitter Attenuator, a Waveform Shaper, a Line Driver
and a Programmable Transmit Termination.
3.2.1 TRANSMIT PATH SYSTEM INTERFACE
The transmit path system interface consists of TCLKn pin, TDn/TDPn
pinandTDNnpin.TCLKnisa2.048MHzclock.IfTCLKnismissingformore
than 70 MCLK cycles, an interrupt will be generated if it is not masked.
1 .20
1.00
TransmitdataissampledontheTDn/TDPnandTDNnpinsbytheactive
edge of TCLKn. The active edge of TCLKn can be selected by the
TCLK_SELbit(TCF0,04H...).AndtheactivelevelofthedataonTDn/TDPn
and TDNn can be selected by the TD_INV bit (TCF0, 04H...). In hardware
controlmode, thefallingedgeofTCLKnandtheactivehighoftransmitdata
are always used.
0.8 0
0.6 0
0.4 0
0.2 0
The transmit data from the system side can be provided in two different
ways: Single Rail and Dual Rail. In Single Rail mode, only TDn pin is used
for transmitting data and the T_MD[1] bit (TCF0, 04H...) should be set to
‘0’.InDualRailMode,bothTDPnpinandTDNnpinareusedfortransmitting
data, the T_MD[1] bit (TCF0, 04H...) should be set to ‘1’.
0.00
-0 .20
0 .6
-0 .6
-0 .4
-0 .2
0
0.2
0.4
T im e in U nit Intervals
Figure-3 E1 Waveform Template Diagram
FUNCTIONAL DESCRIPTION
17
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
User can change the wave shape and the amplitude to get the desired
pulse shape. In order to do this, firstly, users can choose a set of waveform
value from the following two tables, which is the most similar to the desired
pulse shape. Table-2 and Table-3 list the sample data and scaling data of
each of the two templates. Then modify the corresponding sample data to
get the desired transmit pulse shape.
TTIPn
IDT82V2052E
RLOAD
VOUT
TRINGn
Secondly, through the value of SCAL[5:0] bits increased or decreased
by 1, the pulse amplitude can be scaled up or down at the percentage ratio
againstthestandardpulseamplitudeifneeded. Fordifferentpulseshapes,
the value of SCAL[5:0] bits and the scaling percentage ratio are different.
The following two tables list these values.
Note: 1. For RLOAD = 75 Ω (nom), Vout (Peak)=2.37V (nom)
2. For RLOAD =120 Ω (nom), Vout (Peak)=3.00V (nom)
Figure-4 E1 Pulse Template Test Circuit
Do the followings step by step, the desired waveform can be pro-
grammed, based on the selected waveform template:
(1).Select the UI by UI[1:0] bits (TCF3, 07H...)
3.2.3.2 User-Programmable Arbitrary Waveform
WhenthePULS[3:0]bitsaresetto‘11xx’, user-programmablearbitrary
waveform generator modecanbe used in thecorresponding channel. This
allowsthetransmitterperformancetobetunedforawidevarietyoflinecon-
dition or special application.
(2).Specify the sample address in the selected UI by SAMP [3:0] bits
(TCF3, 07H...)
(3).Write sample data to WDAT[6:0] bits (TCF4, 08H...). It contains the
data to be stored in the RAM, addressed by the selected UI and the
corresponding sample address.
(4).SettheRWbit(TCF3,07H...)to‘0’toimplementwritingdatatoRAM,
or to ‘1’ to implement read data from RAM
(5).Implement the Read from RAM/Write to RAM by setting the DONE
bit (TCF3, 07H...)
Each pulse shape can extend up to 4 UIs (Unit Interval), addressed by
UI[1:0] bits (TCF3, 07H...) and each UI is divided into 16 sub-phases,
addressed by the SAMP[3:0] bits (TCF3, 07H...). The pulse amplitude of
each phase is represented by a binary byte, within the range from +63 to -
63, stored in WDAT[6:0] bits (TCF4, 08H...) in signed magnitude form. The
most positive number +63 (D) represents the maximum positive amplitude
ofthetransmitpulsewhilethemostnegativenumber-63(D)representsthe
maximum negative amplitude of the transmit pulse. Therefore, up to 64
bytes are used. For each channel, a 64 bytes RAM is available.
There are two standard templates which are stored in an on-chip ROM.
User can select one of them as reference and make some changes to get
the desired waveform.
Repeat the above steps until all the sample data are written to or read
from the internal RAM.
(6).Write the scaling data to SCAL[5:0] bits (TCF2, 06H...) to scale the
amplitude of the waveform based on the selected standard pulse
amplitude
WhenmorethanoneUIisusedtocomposethepulsetemplate,theover-
lap of two consecutive pulses could make the pulse amplitude overflow
(exceed the maximum limitation) if the pulse amplitude is not set properly.
This overflow is captured by DAC_OV_IS bit (INTS1, 19H...), and, if
enabled by the DAC_OV_IM bit (INTM1, 14H...), an interrupt will be gen-
erated.
FUNCTIONAL DESCRIPTION
18
December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
The following tables give all the sample data based on the preset pulse
templates in detail for reference. For preset pulse templates, scaling up/
down against the pulse amplitude is not supported.
Table-3 Transmit Waveform Value For E1 120 Ohm
Sample
UI 1
UI 2
UI 3
UI 4
1.Table-2 Transmit Waveform Value for E1 75 Ω
2.Table-3 Transmit Waveform Value for E1 120 Ω
1
2
0000000
0000000
0000000
0001111
0111100
0111100
0111100
0111100
0111100
0111100
0111100
0111100
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
3
Table-2 Transmit Waveform Value For E1 75 Ohm
4
Sample
UI 1
UI 2
UI 3
UI 4
5
1
2
0000000
0000000
0000000
0001100
0110000
0110000
0110000
0110000
0110000
0110000
0110000
0110000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
0000000
6
7
3
8
4
9
5
10
11
12
13
14
15
16
6
7
8
9
10
11
12
13
14
15
16
SCAL[5:0] = 100001 (default), One step change of this value of SCAL[5:0]
results in 3% scaling up/down against the pulse amplitude.
SCAL[5:0] = 100001 (default), One step change of this value of SCAL[5:0]
results in 3% scaling up/down against the pulse amplitude.
FUNCTIONAL DESCRIPTION
19
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
3.2.4 TRANSMIT PATH LINE INTERFACE
workisused,PULSnpinsshouldbesettoselectthespecificinternalimped-
ance in the corresponding channel. Refer to 5 HARDWARE CONTROL PIN
SUMMARY for details.
The transmit line interface consists of TTIPn and TRINGn pins. The
impedance matching can be realized by the internal impedance matching
circuit or the external impedance matching circuit. If T_TERM[2] is set to
‘0’, the internal impedance matching circuit will be selected. In this case,
the T_TERM[1:0] bits (TERM, 02H...) can be set to choose 75 Ω or 120 Ω
internalimpedanceofTTIPn/TRINGn.IfT_TERM[2]issetto‘1’,theinternal
impedance matching circuit will be disabled. In this case, the external
impedancematchingcircuitwillbeusedtorealizetheimpedancematching.
The TTIPn/TRINGn can also be turned into high impedance globally by
pulling THZ pin to high or individually by setting the THZ bit (TCF1, 05H...)
to ‘1’. In this state, the internal transmit circuits are still active.
In hardware control mode, TTIPn/TRINGn pins can be turned into high
impedance globally by pulling THZ pin to high. Refer to 5 HARDWARE CON-
TROL PIN SUMMARY for details.
Figure-6 shows the appropriate external components to connect with
the cable for one channel. Table-4 is the list of the recommended imped-
ance matching for transmitter.
Besides, in the following cases, TTIPn/TRINGn will also become high
impedance:
•
•
Loss of MCLK;
Inhardwarecontrolmode, TERMnpincanbeusedtoselectimpedance
matchingforbothreceiverandtransmitteronaperchannelbasis.IfTERMn
pin is low, internal impedance network will be used. If TERMn pin is high,
external impedance network will be used. When internal impedance net-
Loss of TCLKn (exceptions: Remote Loopback; Transmit internal
pattern by MCLK);
•
•
Transmit path power down;
After software reset; pin reset and power on.
Table-4 Impedance Matching for Transmitter
Cable
Internal Termination
PULS[3:0]
External Termination
Configuration
T_TERM[2:0]
RT
T_TERM[2:0]
PULS[3:0]
RT
E1 / 75 Ω
000
001
0000
0001
0 Ω
1XX
0001
0001
9.4 Ω
E1 / 120 Ω
Note: The precision of the resistors should be better than ± 1%
3.2.5 TRANSMIT PATH POWER DOWN
3.3 RECEIVE PATH
The transmit path can be powered down individually by setting the
T_OFF bit (TCF0, 04H...) to ‘1’. In this case, the TTIPn/TRINGn pins are
turned into high impedance.
The receive path consists of Receive Internal Termination, Monitor
Gain,Amplitude/WaveShapeDetector,DigitalTuningController,Adaptive
Equalizer,DataSlicer,CDR(Clock&DataRecovery),OptionalJitterAtten-
uator, Decoder and LOS/AIS Detector. Refer to Figure-5.
In hardware control mode, the transmit path can be powered down by
setting PATTn[1:0] pins to ‘11’ on a per channel basis. Refer to 5 HARD-
WARE CONTROL PIN SUMMARY for details.
3.3.1 RECEIVE INTERNAL TERMINATION
The impedance matching can be realized by the internal impedance
matching circuit or the external impedance matching circuit. If R_TERM[2]
is set to ‘0’, the internal impedance matching circuit will be selected. In this
case, the R_TERM[1:0] bits (TERM, 02H...) can be set to choose 75 Ω or
120ΩinternalimpedanceofRTIPn/RRINGn.IfR_TERM[2]issetto‘1’,the
internalimpedancematching circuitwillbedisabled. Inthiscase, theexter-
nal impedance matching circuit will be used to realize the impedance
matching.
Figure-6 shows the appropriate external components to connect with
the cable for one channel. Table-5 is the list of the recommended imped-
ance matching for receiver.
FUNCTIONAL DESCRIPTION
20
December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
LOS/AIS
LOS
Detector
RCLK
Receive
Internal
termination
Clock
Jitter
RTIP
Monitor Gain/
Adaptive Equalizer
Data Slicer
Decoder
RDP
RDN
and Data
Recovery
Attenuator
RRING
Figure-5 Receive Path Function Block Diagram
Table-5 Impedance Matching for Receiver
Cable Configuration
Internal Termination
R_TERM[2:0]
External Termination
RR
R_TERM[2:0]
RR
E1 / 75 Ω
000
001
120 Ω
1XX
75 Ω
E1 / 120 Ω
120 Ω
VDDRn
One of the Two Identical Channels
D8
1:1
·
•
•
3.3 V
68µF1
•
•
•
RTIPn
A
VDDRn
D7
RX Line
4
VDDRn
RR
0.1µF
0.1µF
D6
GNDRn
RRINGn
•
•
·
•
B
VDDTn
D4
D5
4
2:1
RT
•
•
•·
TTIPn
3.3 V
68µF1
D3
VDDTn
2
Cp
TX Line
VDDTn
D2
GNDTn
TRINGn
•
·
D13
4
RT
Note:
1. Common decoupling capacitor. One per chip
2. Cp 0-560 (pF)
3. D1 - D8, Motorola - MBR0540T1; International Rectifier - 11DQ04 or 10BQ060
4. RT/ RR: refer to Table-4 and Table-5 respecivley for RT and RR values
Figure-6 Transmit/Receive Line Circuit
In hardware control mode, TERMn, PULSn pins can be used to select
impedance matching for both receiver and transmitter on a per channel
basis. If TERMn pin is low, internal impedance network will be used. If
TERMnpinishigh,externalimpedancenetworkwillbeused.Wheninternal
impedance network is used, PULSn pins should be set to select specific
internal impedance for the corresponding channel. Refer to 5 HARDWARE
CONTROL PIN SUMMARY for details.
After a high resistance bridging circuit, the signal arriving at the RTIPn/
RRINGn is dramatically attenuated. To compensate this attenuation, the
Monitor Gain can be used to boost the signal by 22 dB, 26 dB and 32 dB,
selectedbyMG[1:0]bits(RCF2, 0BH...). Fornormaloperation, theMonitor
Gain should be set to 0 dB.
In hardware control mode, MONTn pin can be used to set the Monitor
Gain on a per channel basis. When MONTn pin is low, the Monitor Gain for
the specific channel is 0 dB. When MONTn pin is high, the Monitor Gain for
the specific channel is 26 dB. Refer to 5 HARDWARE CONTROL PIN SUM-
MARY for details.
3.3.2 LINE MONITOR
The non-intrusive monitoring on channels located in other chips can be
performed by tapping the monitored channel through a high impedance
bridging circuit. Refer to Figure-7 and Figure-8.
FUNCTIONAL DESCRIPTION
21
December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
3.3.3 ADAPTIVE EQUALIZER
DSX cross connect
point
The Adaptive Equalizer can be enabled to increase the receive sensi-
tivity and to allow programming of the LOS level up to -24 dB. See section
3.5 LOS AND AIS DETECTION. It can be enabled or disabled by setting
EQ_ON bit to ‘1’ or ‘0’ (RCF1, 0AH...).
RTIP
monitor
gain=0dB
RRING
R
3.3.4 RECEIVE SENSITIVITY
normal receive mode
InHostmode,theReceiveSensitivityis-10dB.WiththeAdaptiveEqual-
izer enabled, the receive sensitivity will be -20 dB.
RTIP
monitor gain
=22/26/32dB
In Hardware mode, the Adaptive Equalizer can not be enabled and the
receive sensitivity is fixed at -10 dB. Refer to 5 HARDWARE CONTROL PIN
SUMMARY for details.
RRING
monitor mode
3.3.5 DATA SLICER
Figure-7 Monitoring Receive Line in Another Chip
The Data Slicer is used to generate a standard amplitude mark or a
space according to the amplitude of the input signals. The threshold can
be 40%, 50%, 60% or 70%, as selected by the SLICE[1:0] bits (RCF2,
0BH...).TheoutputoftheDataSlicerisforwardedtotheCDR(Clock&Data
Recovery) unit or to the RDPn/RDNn pins directly if the CDR is disabled.
DSX cross connect
point
TTIP
3.3.6 CDR (Clock & Data Recovery)
TRING
R
TheCDRisusedtorecovertheclockanddatafromthereceivedsignal.
The recovered clock tracks the jitter in the data output from the Data Slicer
and keeps the phase relationship between data and clock during the
absenceoftheincomingpulse.TheCDRcanalsobeby-passedintheDual
Railmode. WhenCDRisby-passed, the data fromtheDataSlicer isoutput
to the RDPn/RDNn pins directly.
normal transmit mode
RTIP
monitor gain
=22/26/32dB
RRING
monitor mode
3.3.7 DECODER
Figure-8 Monitor Transmit Line in Another Chip
The R_MD[1:0] bits (RCF0, 09H...) are used to select the AMI decoder
or HDB3 decoder.
Whenthechipisconfiguredbyhardware,theoperationmodeofreceive
and transmit path can be selected by setting RXTXM[1:0] pins on a global
basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
3.3.8 RECEIVE PATH SYSTEM INTERFACE
The receive path system interface consists of RCLKn pin, RDn/RDPn
pin and RDNn pin. The RCLKn outputs a recovered 2.048 MHz clock. The
received data is updated on the RDn/RDPn and RDNn pins on the active
edge of RCLKn. The active edge of RCLKn can be selected by the
RCLK_SEL bit (RCF0, 09H...). And the active level of the data on RDn/
RDPn and RDNn can be selected by the RD_INV bit (RCF0, 09H...).
In hardware control mode, only the active edge of RCLKn can be
selected.IfRCLKEissettohigh,thefallingedgewillbechosenastheactive
edge of RCLKn. If RCLKE is set to low, the rising edge will be chosen as
the active edge of RCLKn. The active level of the data on RDn/RDPn and
RDNn is the same as that in software control mode.
Thereceiveddatacanbeoutputtothesystemsideintwodifferentways:
Single Rail or Dual Rail, as selected by R_MD bit [1] (RCF0, 09H...). In Sin-
gle Rail mode, only RDn pin is used to output data and the RDNn/CVn pin
is used to report the received errors. In Dual Rail Mode, both RDPn pin and
RDNn pin are used for outputting data.
FUNCTIONAL DESCRIPTION
22
December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
InthereceiveDualRailmode,theCDRunitcanbeby-passedbysetting
R_MD[1:0] to ‘11’ (binary). In this situation, the output data from the Data
Slicer will be output to the RDPn/RDNn pins directly, and the RCLKn out-
putstheexclusiveOR(XOR)oftheRDPnandRDNn.Thisiscalledreceiver
slicer mode. In this case, the transmit path is still operating in Dual Rail
mode.
3.3.10 G.772 NON-INTRUSIVE MONITORING
In applications using only one channel, channel 1 can be configured to
monitor the data received or transmitted in channel 2. The MONT[1:0] bits
(GCF, 20H)determinewhichdirection(transmit/receive)willbemonitored.
The monitoring is non-intrusive per ITU-T G.772. Figure-9 illustrates the
concept.
3.3.9 RECEIVE PATH POWER DOWN
The monitored line signal (transmit or receive) goes through Channel
1’s Clock and Data Recovery. The signal can be observed digitally at the
RCLK1,RD1/RDP1andRDN1.IfChannel1isconfiguredtoRemoteLoop-
back while in the Monitoring mode, the monitored data will be output on
TTIP1/TRING1.
The receive path can be powered down individually by setting R_OFF
bit (RCF0, 09H...) to ‘1’. In this case, the RCLKn, RDn/RDPn, RDNn and
LOSn will be logic low.
Inhardwarecontrolmode,receiverpowerdowncanbeselectedbypull-
ing RPDn pin to high on a per channel basis. Refer to 5 HARDWARE CON-
TROL PIN SUMMARY for more details.
Channel 2
LOS/AIS
LOS2
Detection
Receiver
RTIP2
RCLK2
RD2/RDP2
CV2/RDN2
Clock and
Data
Recovery
HDB3/AMI
Decoder
Jitter
Attenuator
Data
Slicer
Adaptive
Equalizer
Internal
RRING2
Termination
TTIP2
Transmitter
Internal
Termination
TCLK2
TD2/TDP2
TDN2
Line
Driver
HDB3/AMI
Encoder
Jitter
Attenuator
Waveform
Shaper
TRING2
Channel 1
G.772
DLOS/AIS
Detection
ALOS
Detection
Monitor
LOS1
Receiver
Internal
Termination
RCLK1
RD1/RDP1
CV1/RDN1
Clock and
Data
Recovery
RTIP1
HDB3/AMI
Decoder
Jitter
Attenuator
Data
Slicer
Adaptive
Equalizer
RRING1
Remote
Loopback
TTIP1
Transmitter
Internal
Termination
TCLK1
TD1/TDP1
TDN1
Line
Driver
HDB3/AMI
Encoder
Jitter
Attenuator
Waveform
Shaper
TRING1
Figure-9 G.772 Monitoring Diagram
FUNCTIONAL DESCRIPTION
23
December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
TheCornerFrequencyoftheDPLLcanbe0.9Hzor6.8Hz, asselected
by the JABW bit (JACF, 03H...). The lower the Corner Frequency is, the
longer time is needed to achieve synchronization.
3.4 JITTER ATTENUATOR
ThereisoneJitterAttenuatorineachchanneloftheLIU.TheJitterAtten-
uatorcanbedeployedinthetransmitpathorthereceivepath, andcanalso
be disabled. This is selected by the JACF[1:0] bits (JACF, 03H...).
When the incoming data moves faster than the outgoing data, the FIFO
will overflow. This overflow is captured by the JAOV_IS bit (INTS1, 19H...).
If the incoming data moves slower than the outgoing data, the FIFO will
underflow. This underflow is captured by the JAUD_IS bit (INTS1, 19H...).
For some applications that are sensitive to data corruption, the JA limit
mode can be enabled by setting JA_LIMIT bit (JACF, 03H...) to ‘1’. In the
JAlimitmode, thespeedoftheoutgoingdatawillbeadjustedautomatically
whenthe FIFO is close to its fullor emptiness. The criteria ofstarting speed
adjustment are shown in Table-6. The JA limit mode can reduce the pos-
sibility of FIFO overflow and underflow, but the quality of jitter attenuation
is deteriorated.
In hardware control mode, Jitter Attenuator position, bandwidth and the
depth of FIFO can be selected by JA[1:0] pins on a global basis. Refer to 5
HARDWARE CONTROL PIN SUMMARY for details.
3.4.1 JITTER ATTENUATION FUNCTION DESCRIPTION
The Jitter Attenuator is composed of a FIFO and a DPLL, as shown in
Figure-10. The FIFO is used as a pool to buffer the jittered input data, then
the data is clocked out of the FIFO by a de-jittered clock. The depth of the
FIFO can be 32 bits, 64 bits or 128 bits, as selected by the JADP[1:0] bits
(JACF,03H...).Inhardwarecontrolmode,thedepthofFIFOcanbeselected
byJA[1:0]pinsonaglobalbasis.Referto5HARDWARECONTROLPINSUM-
MARY for details. Consequently, the constant delay of the Jitter Attenuator
will be 16 bits, 32 bits or 64 bits. Deeper FIFO can tolerate larger jitter, but
at the cost of increasing data latency time.
Table-6 Criteria of Starting Speed Adjustment
FIFO Depth
Criteria for Adjusting Data Outgoing Speed
2 bits close to its full or emptiness
3 bits close to its full or emptiness
4 bits close to its full or emptiness
32 Bits
RDn/RDPn
FIFO
3.4.2 JITTER ATTENUATOR PERFORMANCE
Jittered Data
Jittered Clock
De-jittered Data
RDNn
32/64/128
TheperformanceoftheJitterAttenuatorintheIDT82V2052Emeetsthe
ITU-TI.431,G.703,G.736-739,G.823,G.824, ETSI300011,ETSITBR12/
13 specifications. Details of the Jitter Attenuator performance is shown in
Table-52 Jitter Tolerance and Table-53 Jitter Attenuator Characteristics.
W
R
De-jittered Clock
RCLKn
DPLL
MCLK
Figure-10 Jitter Attenuator
FUNCTIONAL DESCRIPTION
24
December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
LOS detect level threshold
•
3.5 LOS AND AIS DETECTION
With the Adaptive Equalizer off, the amplitude threshold Q is fixed on
800 mVpp, while P=Q+200 mVpp (200 mVpp is the LOS level detect hys-
teresis).
3.5.1 LOS DETECTION
TheLossofSignalDetectormonitorstheamplitudeoftheincomingsig-
nal level and pulse density of the received signal on RTIPn and RRINGn.
With the Adaptive Equalizer on, the value of Q can be selected by
LOS[4:0] bit (RCF1, 0AH...), while P=Q+4 dB (4 dB is the LOS level detect
hysteresis). RefertoTable 27, “RCF1: ReceiverConfigurationRegister1,”
on page 42 for LOS[4:0] bit values available.
•
LOS declare (LOS=1)
A LOS is detected when the incoming signal has “no transitions”, i.e.,
when the signal level is less than Q dB below nominal for N consecutive
pulse intervals. Here N is defined by LAC bit (MAINT0, 0CH...). LOS will be
declaredbypullingLOSnpintohigh(LOS=1)andLOSinterruptwillbegen-
erated if it is not masked.
When the chip is configured by hardware, the Adaptive Equalizer can
not be enabled and Programmable LOS levels are not available (pin 58 &
pin 60 have to be set to ‘0’).
•
LOS clear (LOS=0)
•
Criteria for declare and clear of a LOS detect
The LOS is cleared when the incoming signal has “transitions”, i.e.,
when the signal level is greater than P dB below nominal and has an aver-
age pulse density of at least 12.5% forM consecutive pulse intervals, start-
ing with the receipt of a pulse. Here M is defined by LAC bit (MAINT0,
0CH...). LOS status is cleared by pulling LOSn pin to low.
The detection supports G.775 and ETSI 300233/I.431. The criteria can
be selected by LAC bit (MAINT0, 0CH...).
Table-7 and Table-8 summarize LOS declare and clear criteria for both
with and without the Adaptive Equalizer enabled.
•
All Ones output during LOS
On the system side, the RDPn/RDNn will reflect the input pulse “transi-
tion”attheRTIPn/RRINGnside andoutputrecoveredclock(butthequality
of theoutput clock can not be guaranteed when theinputlevel islowerthan
the maximum receive sensitivity) when AISE bit (MAINT0, 0CH...) is 0; or
output All Ones as AIS when AISE bit (MAINT0, 0CH...) is 1. In this case
RCLKn output is replaced by MCLK.
LOS=1
signal level>P
density=OK
signal level<Q
On the line side, the TTIPn/TRINGn will output All Ones as AIS when
ATAO bit (MAINT0, 0CH...) is 1. The All Ones pattern uses MCLK as the
reference clock.
(observing windows= M)
(observing windows= N)
LOS indicator is always active for all kinds of loopback modes.
LOS=0
Figure-11 LOS Declare and Clear
Table-7 LOS Declare and Clear Criteria, Adaptive Equalizer Disabled
Control bit (LAC)
0 = G.775
1 = I.431/ETSI
LOS declare threshold
Level < 800 mVpp; N=32 bits
Level < 800 mVpp; N=2048 bits
LOS clear threshold
Level > 1 Vpp; M=32 bits; 12.5% mark density; <16 consecutive zeroes
Level > 1 Vpp; M=32 bits; 12.5% mark density; <16 consecutive zeroes
FUNCTIONAL DESCRIPTION
25
December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-8 LOS Declare and Clear Criteria, Adaptive Equalizer Enabled
Control bit
LOS declare threshold
LOS clear threshold
Note
LAC
LOS[4:0]
Q (dB)
00000
…
00010
-4
…
-8
-
Level > Q+ 4dB
Level < Q
N=32 bits
M=32 bits
12.5% mark density
<16 consecutive zeroes
0
1
G.775 Level detect range is -9 to -35 dB.
00011
…
01010
01011 - 11111
-10
…
-24
G.775
-
Reserved
00000
-4
Level > Q+ 4dB
M=32 bits
12.5% mark density
<16 consecutive zeroes
00001
…
01010
01011 - 11111
-6
…
Level < Q
N=2048 bits
I.431 Level detect range is -6 to -20 dB.
I.431/ETSI
-24
Reserved
3.5.2 AIS DETECTION
AIS detection comply with the ITU G.775 or the ETSI 300233, as selected
by the LAC bit (MAINT0, 0CH...). Table-9 summarizes different criteria for
AIS detection Declaring/Clearing.
TheAlarmIndicationSignalcanbedetectedbytheIDT82V2052Ewhen
the Clock & Data Recovery unit is enabled. The status of AIS detection is
reflectedintheAIS_Sbit(STAT0,16H...).Thecriteriafordeclaring/clearing
Table-9 AIS Condition
ITU G.775 (LAC bit is set to ‘0’ by default)
ETSI 300233 (LAC bit is set to ‘1’)
Less than 3 zeros contained in each of two consecutive 512-bit streams are received Less than 3 zeros contained in a 512-bit stream are received
3 or more zeros contained in each of two consecutive 512-bit streams are received 3 or more zeros contained in a 512-bit stream are received
AIS Detected
AIS Cleared
FUNCTIONAL DESCRIPTION
26
December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
PRBSdatacanbeinvertedthroughsettingthePRBS_INVbit(MAINT0,
0CH...).
3.6 TRANSMIT AND DETECT INTERNAL PATTERNS
Theinternalpatterns(AllOnes,AllZerosandPRBSpattern)willbegen-
erated and detected by IDT82V2052E. TCLKn is used as the reference
clock by default. MCLK can also be used as the reference clock by setting
the PATT_CLK bit (MAINT0, 0CH...) to ‘1’.
Any change of PRBS_S bit will be captured by PRBS_IS bit (INTS0,
18H...). The PRBS_IES bit (INTES, 15H...) can be used to determine
whetherthe‘0’to‘1’changeofPRBS_SbitwillbecapturedbythePRBS_IS
bitoranychangesofPRBS_SbitwillbecapturedbythePRBS_ISbit.When
the PRBS_IS bit is ‘1’, an interrupt will be generated if the PRBS_IM bit
(INTM0, 13H...) is set to ‘1’.
IfthePATT_CLKbit(MAINT0,0CH...)issetto‘0’andthePATT[1:0]bits
(MAINT0, 0CH...) are set to ‘00’, the transmit path will operate in normal
mode.
ThereceivedPRBS logic errorscan becounted in a16-bitcounterifthe
ERR_SEL [1:0] bits (MAINT6, 12H...) are set to ‘00’. Refer to 3.8 ERROR
DETECTION/COUNTING AND INSERTION for the operation of the error
counter.
When the chip is configured by hardware, the transmit path will operate
in normal mode by setting PATTn[1:0] pins to ‘00’ on a per channel basis.
Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
3.6.1 TRANSMIT ALL ONES
3.7 LOOPBACK
In transmit direction, the All Ones data can be inserted into the data
streamwhenthePATT[1:0]bits(MAINT0,0CH...)aresetto‘01’.Thetrans-
mit data stream is output from TTIPn/TRINGn. In this case, either TCLKn
or MCLK can be used as the transmit clock, as selected by the PATT_CLK
bit (MAINT0, 0CH...).
Tofacilitatetestinganddiagnosis,theIDT82V2052Eprovidesthreedif-
ferent loopback configurations: Analog Loopback, Digital Loopback and
Remote Loopback.
3.7.1 ANALOG LOOPBACK
Inhardwarecontrolmode,theAllOnesdatacanbeinsertedintothedata
streamintransmitdirectionbysettingPATTn[1:0]pinsto‘01’onaperchan-
nel basis. Refer to 5 HARDWARE CONTROL PIN SUMMARY for details.
WhentheALPbit(MAINT1,0DH...)issetto‘1’,thecorrespondingchan-
nel is configured in Analog Loopback mode. In this mode, the transmit sig-
nals are looped back to the Receiver Internal Termination in the receive
paththenoutputfromRCLKn,RDn,RDPn/RDNn. Theall-onespatterncan
be generated during analog loopback. At the same time, the transmit sig-
nalsarestilloutputtoTTIPn/TRINGnintransmitdirection.Figure-12shows
the process.
3.6.2 TRANSMIT ALL ZEROS
If the PATT_CLK bit (MAINT0, 0CH...) is set to ‘1’, the All Zeros will be
inserted into the transmit data stream when the PATT[1:0] bits (MAINT0,
0CH...) are set to ‘00’.
In hardware control mode, Analog Loopback can be selected by setting
LPn[1:0] pins to ‘01’ on a per channel basis.
3.6.3 PRBS GENERATION AND DETECTION
A PRBS will be generated in the transmit direction and detected in the
3.7.2 DIGITAL LOOPBACK
15
receivedirectionbyIDT82V2052E.ThePRBSis2 -1,withmaximumzero
WhentheDLPbit(MAINT1,0DH...)issetto‘1’,thecorrespondingchan-
nel is configured in Digital Loopback mode. In this mode, the transmit sig-
nals are looped back to the jitter attenuator (if enabled) and decoder in
receive path, then output from RCLKn, RDn, RDPn/RDNn. At the same
time,thetransmitsignalsarestilloutputtoTTIPn/TRINGnintransmitdirec-
tion. Figure-13 shows the process.
restrictions according to ITU-T O.151.
WhenthePATT[1:0]bits(MAINT0,0CH...)aresetto‘10’,thePRBSpat-
tern will be inserted into the transmit data stream with the MSB first. The
PRBS pattern will be transmitted directly or invertedly.
Inhardwarecontrolmode,thePRBSdatawillbegeneratedinthetrans-
mit direction and inserted into the transmit data stream by setting
PATTn[1:0]pinsto‘10’onaperchannelbasis. Referto5HARDWARECON-
TROL PIN SUMMARY for details.
Both Analog Loopback mode and Digital Loopback mode allow the
sending of the internal patterns (All Ones, All Zeros, PRBS, etc.) which will
overwrite the transmit signals. In this case, either TCLKn or MCLK can be
used as the reference clock for internal patterns transmission.
The PRBS in the received data stream will be monitored. If the PRBS
has reached synchronization status, the PRBS_S bit (STAT0, 16H...) will
be set to ‘1’, even in the presence of a logic error rate less than or equal to
In hardware control mode, Digital Loopback can be selected by setting
LPn[1:0] pins to ‘10’ on a per channel basis.
-1
10 .Thecriteriaforsetting/clearingthePRBS_SbitareshowninTable-10.
3.7.3 REMOTE LOOPBACK
WhentheRLPbit(MAINT1,0DH...)issetto‘1’,thecorrespondingchan-
nel is configured in Remote Loopback mode. In this mode, the recovered
clock and data output from Clock and Data Recovery on the receive path
is looped back to the jitter attenuator (if enabled) and Waveform Shaper in
transmit path. Figure-14 shows the process.
Table-10 Criteria for Setting/Clearing the PRBS_S Bit
6 or less than 6 bit errors detected in a 64 bits hopping win-
dow.
PRBS Detection
More than 6 bit errors detected in a 64 bits hopping window.
PRBS Missing
Inhardwarecontrolmode,RemoteLoopbackcanbeselectedbysetting
LPn[1:0] pins to ‘11’ on a per channel basis.
FUNCTIONAL DESCRIPTION
27
December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
One of the Two Identical Channels
LOS/AIS
Detection
LOSn
Receiver
RTIPn
Clock and
Data
Recovery
RCLKn
RDn/RDPn
CVn/RDNn
HDB3/AMI
Decoder
Jitter
Attenuator
Data
Slicer
Adaptive
Equalizer
Internal
RRINGn
Termination
Analog
Loopback
Transmitter
Internal
Termination
TTIPn
TCLKn
TDn/TDPn
TDNn
Line
Driver
HDB3/AMI
Encoder
Jitter
Attenuator
Waveform
Shaper
TRINGn
Figure-12 Analog Loopback
One of the Two Identical Channels
LOS/AIS
Detection
LOSn
Receiver
Clock and
Data
RCLKn
RDn/RDPn
CVn/RDNn
RTIPn
HDB3/AMI
Decoder
Jitter
Attenuator
Adaptive
Internal
Data
Slicer
Equalizer
Termination
RRINGn
Recovery
Digital
Loopback
TCLKn
TDn/TDPn
TDNn
Transmitter
Internal
Termination
TTIPn
HDB3/AMI
Encoder
Jitter
Attenuator
Waveform
Shaper
Line
Driver
TRINGn
Figure-13 Digital Loopback
FUNCTIONAL DESCRIPTION
28
December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
One of the Two Identical Channels
LOS/AIS
Detection
LOSn
Receiver
RTIPn
Clock and
Data
Recovery
RCLKn
RDn/RDPn
CVn/RDNn
HDB3/AMI
Decoder
Jitter
Attenuator
Data
Slicer
Adaptive
Equalizer
Internal
Termination
RRINGn
Remote
Loopback
TTIPn
Transmitter
Internal
Termination
TCLKn
TDn/TDPn
TDNn
Waveform
Shaper
HDB3/AMI
Encoder
Jitter
Attenuator
Line
Driver
TRINGn
Figure-14 Remote Loopback
FUNCTIONAL DESCRIPTION
29
December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
pulses that have the same polarity as the previous pulse are not the
HDB3 zero substitution pulses.
3.8 ERROR DETECTION/COUNTING AND INSERTION
3.8.1 DEFINITION OF LINE CODING ERROR
•
Excess Zero (EXZ) Error: There are two standards defining the
EXZ errors: ANSI and FCC. The EXZ_DEF bit (MAINT6, 12H...)
chooses which standard will be adopted by the corresponding
channel to judge the EXZ error. Table-11 shows definition of EXZ.
In hardware control mode, only ANSI standard is adopted.
The following line encoding errors can be detected and counted by the
IDT82V2052E:
•
Received Bipolar Violation (BPV) Error: In AMI coding, when two
consecutive pulses of the same polarity are received, a BPV error
is declared.
•
HDB3 Code Violation (CV) Error: In HDB3 coding, a CV error is
declared when two consecutive BPV errors are detected, and the
Table-11 EXZ Definition
EXZ Definition
ANSI
FCC
AMI
More than 15 consecutive zeros are detected
More than 3 consecutive zeros are detected
More than 80 consecutive zeros are detected
More than 3 consecutive zeros are detected
HDB3
3.8.2 ERROR DETECTION AND COUNTING
Auto Report Mode
(CNT_MD=1)
Which type of the receiving errors (Received CV/BPV errors, excess
zero errors and PRBS logic errors) will be counted is determined by
ERR_SEL[1:0] bits (MAINT6, 12H...). Only one type of receiving error can
becountedatatimeexceptthatwhentheERR_SEL[1:0]bitsaresetto‘11’,
both CV/BPV and EXZ errors will be detected and counted.
counting
next second
repeats the
same process
N
Theselectedtypeofreceivingerrorsiscountedinaninternal16-bitError
Counter. Once an error is detected, an error interrupt which is indicated by
corresponding bit in (INTS1, 19H...) will be generated if it is not masked.
This Error Counter can be operated in two modes: Auto Report Mode and
Manual Report Mode, as selected by the CNT_MD bit (MAINT6, 12H...).
In Single Rail mode, once BPV or CV errors are detected, the CVn pin will
be driven to high for one RCLK period.
One-Second Timer expired?
Y
CNT0, CNT1
counter
data in counter
0
Bit TMOV_IS is set to '1'
• Auto Report Mode
In Auto Report Mode, the internal counter starts to count the received
errors when the CNT_MD bit (MAINT6, 12H...) is set to ‘1’. A one-second
timer is used to set the counting period. The received errors are counted
within onesecond. If the one-secondtimer expires, the valueinthe internal
counter will be transferred to (CNT0, 1AH...) and (CNT1, 1BH...), then the
internal counter will be reset and start to count received errors for the next
second. The errors occurred during the transfer will be accumulated to the
next round. The expiration of the one-second timer will set TMOV_IS bit
(INTS1, 19H...) to ‘1’, and will generate an interrupt if the TIMER_IM bit
(INTM1,14H...)issetto‘0’.TheTMOV_ISbit(INTS1,19H...)willbecleared
after the interrupt register is read. The content in the (CNT0, 1AH...) and
(CNT1, 1BH...) should be read within the next second. If the counter over-
flows, a counter overflow interrupt which is indicated by CNT_OV_IS bit
(INTS1, 19H...) will be generated if it is not masked by CNT_IM bit (INTM1,
14H...).
read the data in CNT0, CNT1 within
the next second
Bit TMOV_IS is cleared after
the interrupt register is read
Figure-15 Auto Report Mode
• Manual Report Mode
In Manual Report Mode, the internal Error Counter starts to count the
received errors when the CNT_MD bit (MAINT6, 12H...) is set to ‘0’. When
there is a‘0’ to‘1’ transition onthe CNT_TRF bit (MAINT6, 12H...), thedata
inthecounterwillbetransferredto(CNT0,1AH...)and(CNT1,1BH...),then
the counter will be reset. The errors occurred during the transfer will be
accumulated to thenextround. If the counter overflows, acounter overflow
interrupt indicated by CNT_OV_IS bit (INTS1, 19H...) will be generated if
it is not masked by CNT_IM bit (INTM1, 14H...).
FUNCTIONAL DESCRIPTION
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
3.8.3 BIPOLAR VIOLATION AND PRBS ERROR INSERTION
Manual Report mode
(CNT_MD=0)
Only when three consecutive ‘1’s are detected in the transmit data
stream, will a ‘0’ to ‘1’ transition on the BPV_INS bit (MAINT6, 12H...) gen-
erateabipolarviolationpulse, andthepolarityofthesecond‘1’intheseries
will be inverted.
counting
A ‘0’ to ‘1’ transition on the EER_INS bit (MAINT6, 12H...) will generate
a logic error during the PRBS transmission.
N
A '0' to '1' transition
on CNT_TRF?
3.9 LINE DRIVER FAILURE MONITORING
next round
repeat the
same process
Y
Thetransmitdriverfailuremonitorcanbeenabledordisabledbysetting
DFM_OFF bit (TCF1, 05H...). If the transmit driver failure monitor is
enabled, the transmit driver failure will be captured by DF_S bit (STAT0,
16H...). The transition of the DF_S bit is reflected by DF_IS bit (INTS0,
18H...), and, ifenabledbyDF_IMbit(INTM0, 13H...), willgenerateaninter-
rupt.WhenthereisashortcircuitontheTTIPn/TRINGnport,theoutputcur-
rent will be limited to 100 mA (typical), and an interrupt will be generated.
CNT0, CNT1
counter
data in
counter
0
Read the data in CNT0,
CNT1 within next round1
Reset CNT_TRF for the
next '0' to '1' transition
In hardware control mode, the transmit driver failure monitor is always
enabled.
Figure-16 Manual Report Mode
Note: It is recommended that users shoulddo thefollowings within next roundof errorcount-
ing: Read the data in CNT0 and CNT1; Reset CNT_TRF bit for the next ‘0’ to ‘1’ tran-
sition on this bit.
FUNCTIONAL DESCRIPTION
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
3.10.2 TRANSMIT CLOCK (TCLK)
3.10 MCLK AND TCLK
TCLKn is used to sample the transmit data on TDn/TDPn, TDNn. The
activeedgeofTCLKncanbeselectedbytheTCLK_SELbit(TCF0,04H...).
During Transmit All Ones or PRBS pattern, either TCLKn or MCLK can be
used as the reference clock. This is selected by the PATT_CLK bit
(MAINT0, 0CH...).
3.10.1 MASTER CLOCK (MCLK)
MCLK is an independent, free-running reference clock. MCLK is 2.048
MHz. This reference clock is used to generate several internal reference
signals:
•
•
•
•
Timing reference for the integrated clock recovery unit.
Timing reference for the integrated digital jitter attenuator.
Timing reference for microcontroller interface.
Generation of RCLK signal during a loss of signal condition if AIS is
enabled.
But for Automatic Transmit All Ones and AIS, only MCLK is used as the
reference clock and the PATT_CLK bit is ignored. In Automatic Transmit
All Ones condition, the ATAO bit (MAINT0, 0CH) is set to ‘1’. In AIS condi-
tion, the AISE bit (MAINT0, 0CH) is set to ‘1’.
•
•
Reference clock during Transmit All Ones (TAOS), all zeros and
PRBS if it is selected as the reference clock. For ATAO and AIS,
MCLK is always used as the reference clock.
Reference clock during Transmit All Ones (TAO) condition or send-
ing PRBS in hardware control mode.
If TCLKn has been missing for more than 70 MCLK cycles, TCLK_LOS
bit (STAT0, 16H...) will be set, and the corresponding TTIPn/TRINGn will
become high impedance if this channel is not used for remote loopback or
is not using MCLK to transmit internal patterns (TAOS, All Zeros and
PRBS). When TCLK is detected again, TCLK_LOS bit (STAT0, 16H...) will
be cleared. The reference frequency to detect a TCLK loss is derived from
MCLK.
Figure-17 shows the chip operation status in different conditions of
MCLK and TCLKn. The missing of MCLK will set all the TTIPn/TRINGn to
high impedance state.
Clocked
MCLK=H/L?
yes
clocked
L/H
TCLKn status?
generate transmit clock loss
interrupt if not masked in
software control mode;
both the transmitters high
impedance
normal operation
transmitter n high impedance
Figure-17 TCLK Operation Flowchart
FUNCTIONAL DESCRIPTION
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
isselected.WhenMODE[1:0]pinsaresetto‘11’,Parallel-non-Multiplexed-
Intel Interface is selected. Refer to 8 MICROCONTROLLER INTERFACE
TIMING CHARACTERISTICS for details.
3.11 MICROCONTROLLER INTERFACES
Themicrocontrollerinterfaceprovidesaccesstoreadandwritethereg-
isters in the device. The chip supports serial microcontroller interface and
two kinds of parallel microcontroller interface: Motorola non-Multiplexed
mode and Intel non-Multiplexed mode. Different microcontroller interfaces
can be selected by setting MODE[1:0] pins to different values. Refer to
MODE1 and MODE0 in pin description and 8 MICROCONTROLLER
INTERFACE TIMING CHARACTERISTICS for details
3.11.2 SERIAL MICROCONTROLLER INTERFACE
When MODE[1:0] pins are set to‘01’, Serial Interface is selected. In this
mode, the registers are programmed through a 16-bit word which contains
an 8-bit address/command byte (6 address bits A0~A5 and bit R/W) and
an 8-bit data byte (D0~D7). When bit R/W is ‘1’, data is read out from pin
SDO. When bit R/W is ‘0’, data is written into SDI pin. Refer to Figure-18.
3.11.1 PARALLEL MICROCONTROLLER INTERFACE
TheinterfaceiscompatiblewithMotorolaorIntelmicrocontroller. When
MODE[1:0]pinsaresetto‘10’,Parallel-non-Multiplexed-Motorolainterface
CS
SCLK
SDI
-
A0 A1 A2 A3 A4 A5
R/W
D7
D7
D0
D0
D2 D3
D6
D1
D4 D5
address/command byte
input data byte (R/W=0)
SDO
D2
D3
D5 D6
D1
D4
remains high impedance
output data byte (R/W=1)
Figure-18 Serial Microcontroller Interface Function Timing
FUNCTIONAL DESCRIPTION
33
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
interrupt is acknowledged through reading the Interrupt Status Registers
of all the channels (INTS0, 18H...) or (INTS1, 19H...) will all the bits in the
INTCH register (21H) be reset and the INT pin become inactive.
3.12 INTERRUPT HANDLING
All kinds of interrupt of the IDT82V2052E are indicated by the INT pin.
When the INT_PIN[0] bit (GCF, 20H) is ‘0’, the INT pin is open drain active
low, with a 10 KΩ external pull-up resistor. When the INT_PIN[1:0] bits
(GCF, 20H) are ‘01’, the INT pin is push-pull active low; when the
INT_PIN[1:0] bits are ‘10’, the INT pin is push-pull active high.
Therearetotallytwelvekindsofeventsthatcouldbetheinterruptsource
for one channel:
(1).LOS Detected
(2).AIS Detected
(3).Driver Failure Detected
(4).TCLK Loss
(5).Synchronization Status of PRBS
(6).PRBS Error Detected
AlltheinterruptcanbedisabledbytheINTM_GLBbit(GCF,20H).When
the INTM_GLB bit (GCF, 20H) is set to ‘0’, an active level on the INT pin
representsaninterruptoftheIDT82V2052E. TheINT_CH[1:0](GCF, 20H)
should be read to identify which channel(s) generate the interrupt.
The interrupt event is captured by the corresponding bit in the Interrupt
Status Register (INTS0, 18H...) or (INTS1, 19H...). Every kind of interrupt
canbeenabled/disabledindividuallybythecorrespondingbitintheregister
(INTM0, 13H...) or (INTM1, 14H...). Some event is reflected by the corre-
spondingbitintheStatusRegister(STAT0,16H...)or(STAT1,17H...),and
theInterruptTriggerEdgeSelectionRegistercanbeusedtodeterminehow
the Status Register sets the Interrupt Status Register.
(7).Code Violation Received
(8).Excessive Zeros Received
(9).JA FIFO Overflow/Underflow
(10).One-Second Timer Expired
(11). Error Counter Overflow
(12).Arbitrary Waveform Generator Overflow
Table-12isasummaryofallkindsofinterruptandtheassociatedStatus
bit, Interrupt Status bit, Interrupt Trigger Edge Selection bit and Interrupt
Mask bit.
After the Interrupt Status Register (INTS0, 18H...) or (INTS1, 19H...) is
read, the corresponding bit indicating which channel generates the inter-
rupt in the INTCH register (21H) will be reset. Only when all the pending
Table-12 Interrupt Event
Interrupt Event
Status bit
(STAT0, STAT1)
Interrupt Status bit
(INTS0, INTS1)
Interrupt Edge Selection
Interrupt Mask bit
(INTM0, INTM1)
bit
(INTES)
LOS Detected
AIS Detected
LOS_S
AIS_S
LOS_IS
AIS_IS
LOS_IES
AIS_IES
LOS_IM
AIS_IM
Driver Failure Detected
TCLK Loss
DF_S
DF_IS
DF_IES
DF_IM
TCLK_LOS
PRBS_S
TCLK_LOS_IS
PRBS_IS
ERR_IS
TCLK_IES
PRBS_IES
TCLK_IM
PRBS_IM
ERR_IM
CV_IM
Synchronization Status of PRBS
PRBS Error
Code Violation Received
Excessive Zeros Received
JA FIFO Overflow
CV_IS
EXZ_IS
EXZ_IM
JAOV_IS
JAUD_IS
TMOV_IS
CNT_OV_IS
DAC_OV_IS
JAOV_IM
JAUD_IM
TIMER_IM
CNT_IM
DAC_OV_IM
JA FIFO Underflow
One-Second Timer Expired
Error Counter Overflow
Arbitrary Waveform Generator Overflow
FUNCTIONAL DESCRIPTION
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December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
•
Hardware Reset: Asserting the RST pin low for a minimum of 100 ns
3.13 5V TOLERANT I/O PINS
will reset the chip.
All digital input pins willtolerate5.0 ± 10% voltsand are compatible with
TTL logic.
Afterreset, alldriversoutputareinhighimpedancestate, alltheinternal
flip-flops are reset, and all the registers are initialized to default values.
3.14 RESET OPERATION
3.15 POWER SUPPLY
The chip can be reset in two ways:
This chip uses a single 3.3 V power supply.
•
Software Reset: Writing to the RST register (01H) will reset the chip
in 1 µs.
FUNCTIONAL DESCRIPTION
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December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
4
PROGRAMMING INFORMATION
4.1 REGISTER LIST AND MAP
The IDT82V2052E registers can be divided into Global Registers and
Local Registers. The operation on the Global Registers affects both of the
two channels while the operation on Local Registers only affects the spe-
cific channel. For different channel, the address of Local Register is differ-
ent. Table-13 is the map of Global Registers and Table-14 is the map of
LocalRegisters.Iftheconfigurationofbothofthetwochannelsisthesame,
the COPY bit (GCF, 20H) can be set to ‘1’ to establish the Broadcasting
mode. In the Broadcasting mode, the Writing operation on any of the two
channels’registerswillbecopiedtothecorrespondingregistersoftheother
channel.
4.2 Reserved Registers
When writing to registers with reserved bit locations, the default state
must be written to the reserved bits to ensure proper device operation.
Table-13 Global Register List and Map
Address (hex) Register
R/W
MAP
CH1
00
CH2
b7
b6
b5
b4
b3
b2
b1
b0
ID
R
W
ID7
ID6
ID5
ID4
ID3
ID2
ID1
ID0
01
RST
20
GCF
INTCH
R/W
R
MONT1
-
MONT0
-
-
-
-
-
COPY
-
INTM_GLB
-
INT_PIN1
INT_CH2
INT_PIN0
INT_CH1
21
PROGRAMMING INFORMATION
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-14 Per Channel Register List and Map
Address (hex) Register
CH1 CH2
Transmit and receive termination register
R/W
MAP
b7
-
b6
-
b5
b4
b3
b2
b1
b0
02
Jitter attenuation control register
03 23 JACF
Transmit path control registers
22
TERM
R/W
T_TERM2
JA_LIMIT
T_TERM1
JACF1
T_TERM0
JACF0
R_TERM2
JADP1
R_TERM1
JADP0
R_TERM0
JABW
R/W
-
-
04
05
06
07
08
24
25
26
27
28
TCF0
TCF1
TCF2
TCF3
TCF4
R/W
R/W
R/W
R/W
R/W
-
-
-
T_OFF
THZ
TD_INV
PULS3
SCAL3
SAMP3
WDAT3
TCLK_SEL
PULS2
T_MD1
PULS1
SCAL1
SAMP1
WDAT1
T_MD0
PULS0
SCAL0
SAMP0
WDAT0
-
-
-
DFM_OFF
SCAL5
UI1
-
DONE
-
SCAL4
UI0
SCAL2
RW
SAMP2
WDAT2
WDAT6
WDAT5
WDAT4
Receive path control registers
09
0A
0B
29
2A
2B
RCF0
RCF1
RCF2
R/W
R/W
R/W
-
-
-
-
-
R_OFF
LOS4
RD_INV
LOS3
-
RCLK_SEL
R_MD1
LOS1
MG1
R_MD0
LOS0
MG0
EQ_ON
-
-
LOS2
-
SLICE1
SLICE0
Network Diagnostics control registers
0C
0D
2C
2D
MAINT0
MAINT1
R/W
-
-
PATT1
PATT0
PATT_CLK
PRBS_INV
LAC
RLP
-
AISE
ALP
-
ATAO
DLP
-
-
-
-
-
-
-
-
-
0E-11 2E-31 MAINT2-
MAINT5
R/W
R/W
-
12
32
MAINT6
-
-
BPV_INS
-
ERR_INS
EXZ_DEF
ERR_SEL1
ERR_SEL0
CNT_MD
CNT_TRF
Interrupt control registers
13
14
15
33
34
35
INTM0
INTM1
INTES
R/W
R/W
R/W
-
PRBS_IM
ERR_IM
TCLK_IM
EXZ_IM
DF_IM
CV_IM
DF_IES
AIS_IM
TIMER_IM
AIS_IES
LOS_IM
CNT_IM
LOS_IES
DAC_OV_IM JAOV_IM
JAUD_IM
-
-
-
PRBS_IES
TCLK_IES
Line status registers
16
17
36
37
STAT0
STAT1
R
R
-
-
-
-
-
PRBS_S
-
TCLK_LOS
-
DF_S
-
AIS_S
-
LOS_S
-
RLP_S
Interrupt status registers
18
19
38
39
INTS0
INTS1
R
R
-
-
-
PRBS_IS TCLK_LOS_IS
DF_IS
CV_IS
AIS_IS
LOS_IS
DAC_OV_IS JAOV_IS
JAUD_IS
ERR_IS
EXZ_IS
TMOV_IS CNT_OV_IS
Counter registers
1A
1B
3A
3B
CNT0
CNT1
R
R
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit9
Bit0
Bit8
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
PROGRAMMING INFORMATION
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
4.3 REGISTER DESCRIPTION
4.3.1 GLOBAL REGISTERS
Table-15 ID: Device Revision Register
(R, Address = 00H)
Symbol
Bit
Default
Description
Description
ID[7:0]
7-0
00H
Current Silicon Chip ID.
Table-16 RST: Reset Register
(W, Address = 01H)
Symbol
Bit
Default
RST[7:0]
7-0
00H
Software reset. A write operation on this register will reset all internal registers to their default values, and the status
of all ports are set to the default status. The content in this register can not be changed. After reset, all drivers output
are in high impedance state.
Table-17 GCF: Global Configuration Register
(R/W, Address = 20H)
Symbol
Bit
Default
Description
MONT[1:0]
7-6
00
G.772 monitor
= 00/10: Normal
= 01: Receiver 1 monitors the receive path of channel 2
= 11: Receiver 1 monitors the transmit path of channel 2
-
5-4
3
00
0
Reserved.
COPY
Enable broadcasting mode.
= 0: Broadcasting mode disabled
= 1: Broadcasting mode enabled. Writing operation on one channel's register will be copied exactly to the corre-
sponding registers in other channel.
INTM_GLB
2
1
Global interrupt enable
= 0: Interrupt is globally enabled. But for each individual interrupt, it still can be disabled by its corresponding Inter-
rupt mask Bit.
= 1: All the interrupts are disabled for both channels.
INT_PIN[1:0]
1-0
00
Interrupt pin control
= x0: Open drain, active low (with an external pull-up resistor)
= 01: Push-pull, active low
= 11: Push-pull, active high
Table-18 INTCH: Interrupt Channel Indication Register
(R, Address =21H)
Symbol
-
Bit
7-2
1-0
Default
000000
00
Description
Reserved.
INT_CH[1:0]
INT_CH[n]=0 indicates that an interrupt was generated by channel [n+1].
PROGRAMMING INFORMATION
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
4.3.2 TRANSMIT AND RECEIVE TERMINATION REGISTER
Table-19 TERM: Transmit and Receive Termination Configuration Register
(R/W, Address = 02H, 22H)
Symbol
Bit
7-6
5-3
Default
00
Description
-
Reserved.
T_TERM[2:0]
000
These bits select the internal termination for transmit line impedance matching.
= 000: Internal 75 Ω impedance matching
= 001: Internal 120 Ω impedance matching
= 010 / 011: Reserved
= 1xx: Selects external impedance matching resistors (see Table-4).
R_TERM[2:0]
2-0
000
These bits select the internal termination for receive line impedance matching.
= 000: Internal 75 Ω impedance matching
= 001: Internal 120 Ω impedance matching
= 010 / 011: Reserved
= 1xx: Selects external impedance matching resistors (see Table-5).
4.3.3 JITTER ATTENUATION CONTROL REGISTER
Table-20 JACF: Jitter Attenuation Configuration Register
(R/W, Address = 03H, 23H)
Symbol
-
Bit
7-6
5
Default
Description
00
1
Reserved.
JA_LIMIT
= 0: Normal mode
= 1: JA limit mode
JACF[1:0]
JADP[1:0]
JABW
4-3
2-1
0
00
00
0
Jitter Attenuation configuration
= 00/10: JA not used
= 01: JA in transmit path
= 11: JA in receive path
Jitter Attenuation depth select
= 00: 128 bits
= 01: 64 bits
= 1x: 32 bits
Jitter transfer function bandwidth select
= 0: 6.8 Hz
= 1: 0.9 Hz
PROGRAMMING INFORMATION
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
4.3.4 TRANSMIT PATH CONTROL REGISTERS
Table-21 TCF0: Transmitter Configuration Register 0
(R/W, Address = 04H, 24H)
Symbol
-
Bit
7-5
4
Default
000
Description
Reserved
T_OFF
0
Transmitter power down enable
= 0: Transmitter power up
= 1: Transmitter power down (line driver high impedance)
TD_INV
TCLK_SEL
T_MD[1:0]
3
2
0
0
Transmit data invert
= 0: Data on TDn or TDPn/TDNn is active high
= 1: Data on TDn or TDPn/TDNn is active low
Transmit clock edge select
= 0: Data on TDPn/TDNn is sampled on the falling edge of TCLKn
= 1: Data on TDPn/TDNn is sampled on the rising edge of TCLKn
0-1
00
Transmitter operation mode control
T_MD[1:0] select different stages of the transmit data path
= 00: Enable HDB3 encoder and waveform shaper blocks. Input on pin TDn is single rail NRZ data
= 01: Enable AMI encoder and waveform shaper blocks. Input on pin TDn is single rail NRZ data
= 1x: Encoder is bypassed, dual rail NRZ transmit data input on pin TDPn/TDNn
Table-22 TCF1: Transmitter Configuration Register 1
(R/W, Address = 05H, 25H)
Symbol
-
Bit
7-6
5
Default
Description
00
0
Reserved. This bit should be ‘0’ for normal operation.
DFM_OFF
Transmit driver failure monitor disable
= 0: DFM is enabled
= 1: DFM is disabled
THZ
4
1
Transmit line driver high impedance enable
= 0: Normal state
= 1: Transmit line driver high impedance enable (other transmit path still work normally).
PULS[3:0]
3-0
0000 These bits select the transmit template:
TCLK
Cable impedance
Allowable Cable loss
0-24 dB
00001
0001
2.048 MHz
75 Ω
2.048 MHz
120 Ω
0-24 dB
0010 - 1011
11xx
Reserved
User programmable waveform setting
1. In internal impedance matching mode, for E1/75 Ω cable impedance, the PULS[3:0] bits (TCF1, 05H...) should be set to ‘0000’. In external impedance matching
mode, for E1/75 Ω cable impedance, the PULS[3:0] bits should be set to ‘0001’.
PROGRAMMING INFORMATION
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Table-23 TCF2: Transmitter Configuration Register 2
(R/W, Address = 06H, 26H)
Symbol
-
Bit
7-6
5-0
Default
00
Description
Reserved.
SCAL[5:0]
100001
SCAL specifies a scaling factor to be applied to the amplitude of the user-programmable arbitrary pulses which is
to be transmitted if needed. The default value of SCAL[5:0] is ‘100001’. Refer to 3.2.3.2 User-Programmable Arbi-
trary Waveform.
= 100001: Default value for 75 Ω and 120 Ω. One step change of this value results in 3% scaling up/down against
the pulse amplitude.
Table-24 TCF3: Transmitter Configuration Register 3
(R/W, Address = 07H, 27H)
Symbol
DONE
RW
Bit
7
Default
Description
0
0
After ‘1’ is written to this bit, a read or write operation is implemented.
6
This bit selects read or write operation
= 0: Write to RAM
= 1: Read from RAM
UI[1:0]
5-4
3-0
00
These bits specify the unit interval address. There are totally 4 unit intervals.
= 00: UI address is 0 (The most left UI)
= 01: UI address is 1
= 10: UI address is 2
= 11: UI address is 3
SAMP[3:0]
0000
These bits specify the sample address. Each UI has totally 16 samples.
= 0000: Sample address is 0 (The most left sample)
= 0001: Sample address is 1
= 0010: Sample address is 2
……
= 1110: Sample address is 14
= 1111: Sample address is 15
Table-25 TCF4: Transmitter Configuration Register 4
(R/W, Address = 08H, 28H)
Symbol
-
Bit
7
Default
Description
0
Reserved
WDAT[6:0]
6-0
0000000 In Indirect Write operation, the WDAT[6:0] will be loaded to the pulse template RAM, specifying the amplitude of
the Sample.
After an Indirect Read operation, the amplitude data of the Sample in the pulse template RAM will be output to the
WDAT[6:0].
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4.3.5 RECEIVE PATH CONTROL REGISTERS
Table-26 RCF0: Receiver Configuration Register 0
(R/W, Address = 09H, 29H)
Symbol
-
Bit
7-5
4
Default
000
Description
Reserved
R_OFF
0
Receiver power down enable
= 0: Receiver power up
= 1: Receiver power down
RD_INV
RCLK_SEL
R_MD[1:0]
3
2
0
0
Receive data invert
= 0: Data on RDn or RDPn/RDNn is active high
= 1: Data on RDn or RDPn/RDNn is active low
Receive clock edge select (this bit is ignored in slicer mode)
= 0: Data on RDn or RDPn/RDNn is updated on the rising edge of RCLKn
= 1: Data on RDn or RDPn/RDNn is updated on the falling edge of RCLKn
1-0
00
Receive path decoding selection
= 00: Receive data is HDB3 decoded and output on RDn pin with single rail NRZ format
= 01: Receive data is AMI decoded and output on RDn pin with single rail NRZ format
= 10: Decoder is bypassed, re-timed dual rail data with NRZ format output on RDPn/RDNn (dual rail mode with clock
recovery)
= 11: CDR and decoder are bypassed, slicer data with RZ format output on RDPn/RDNn (slicer mode)
Table-27 RCF1: Receiver Configuration Register 1
(R/W, Address= 0AH, 2AH)
Symbol
-
Bit
7
Default
Description
0
0
Reserved
EQ_ON
6
= 0: Receive equalizer off
= 1: Receive equalizer on (LOS programming enabled)
-
5
0
Reserved.
LOS[4:0]
4:0
10101
LOS Clear Level (dB)
LOS Declare Level (dB)
00000
00001
0
<-4
>-2
<-6
00010
>-4
<-8
00011
>-6
<-10
<-12
<-14
<-16
<-18
<-20
<-22
<-24
00100
>-8
00101
>-10
>-12
>-14
>-16
>-18
>-20
Reserved
00110
00111
01000
01001
01010
01011 - 11111
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Table-28 RCF2: Receiver Configuration Register 2
(R/W, Address = 0BH, 2BH)
Symbol
-
Bit
7-6
5-4
Default
00
Description
Reserved.
SLICE[1:0]
01
Receive slicer threshold
= 00: The receive slicer generates a mark if the voltage on RTIPn/RRINGn exceeds 40% of the peak amplitude.
= 01: The receive slicer generates a mark if the voltage on RTIPn/RRINGn exceeds 50% of the peak amplitude.
= 10: The receive slicer generates a mark if the voltage on RTIPn/RRINGn exceeds 60% of the peak amplitude.
= 11: The receive slicer generates a mark if the voltage on RTIPn/RRINGn exceeds 70% of the peak amplitude.
-
3-2
1-0
10
00
Reserved
MG[1:0]
Monitor gain setting: these bits select the internal linear gain boost
= 00: 0 dB
= 01: 22 dB
= 10: 26 dB
= 11: 32 dB
4.3.6 NETWORK DIAGNOSTICS CONTROL REGISTERS
Table-29 MAINT0: Maintenance Function Control Register 0
(R/W, Address = 0CH, 2CH)
Symbol
-
Bit
7
Default
Description
0
Reserved.
PATT[1:0]
6-5
00
These bits select the internal pattern and insert it into transmit data stream.
= 00: Normal operation (PATT_CLK = 0) / insert all zeros (PATT_CLK = 1)
= 01: Insert All Ones
= 10: Insert PRBS (E1: 215-1)
= 11: Reserved
PATT_CLK
PRBS_INV
LAC
4
3
2
1
0
0
0
0
0
0
Selects reference clock for transmitting internal pattern
= 0: Uses TCLKn as the reference clock
= 1: Uses MCLK as the reference clock
Inverts PRBS
= 0: The PRBS data is not inverted
= 1: The PRBS data is inverted before transmission and detection
LOS/AIS criterion is selected as below:
= 0: G.775
= 1: ETSI 300233& I.431
AISE
AIS enable during LOS
= 0: AIS insertion on RDPn/RDNn/RCLKn is disabled during LOS
= 1: AIS insertion on RDPn/RDNn/RCLKn is enabled during LOS
ATAO
Automatically Transmit All Ones (enabled only when PATT[1:0] = 00)
= 0: Disabled
= 1: Automatically Transmit All Ones pattern at TTIPn/TRINGn during LOS
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Table-30 MAINT1: Maintenance Function Control Register 1
(R/W, Address= 0DH, 2DH)
Symbol
Bit
7-3
2
Default
00000
0
Description
-
Reserved
RLP
Remote loopback enable
= 0: Disables remote loopback (normal transmit and receive operation)
= 1: Enables remote loopback
ALP
DLP
1
0
0
0
Analog loopback enable
= 0: Disables analog loopback (normal transmit and receive operation)
= 1: Enables analog loopback
Digital loopback enable
= 0: Disables digital loopback (normal transmit and receive operation)
= 1: Enables digital loopback
Table-31 MAINT6: Maintenance Function Control Register 6
(R/W, Address = 12H, 32H)
Symbol
-
Bit
7
Default
Description
0
0
Reserved.
BPV_INS
6
BPV error insertion
A ‘0’ to ‘1’ transition on this bit will cause a single bipolar violation error to be inserted into the transmit data stream.
This bit must be cleared and set again for a subsequent error to be inserted.
ERR_INS
EXZ_DEF
ERR_SEL
5
4
0
0
PRBS logic error insertion
A ‘0’ to ‘1’ transition on this bit will cause a single PRBS logic error to be inserted into the transmit PRBS data stream.
This bit must be cleared and set again for a subsequent error to be inserted.
EXZ definition select
= 0: ANSI
= 1: FCC
3-2
00
These bits choose which type of error will be counted
= 00: The PRBS logic error is counted by a 16-bit error counter
= 01: The EXZ error is counted by a 16-bit error counter
= 10: The Received CV (BPV) error is counted by a 16-bit error counter
= 11: Both CV (BPV) and EXZ errors are counted by a 16-bit error counter.
CNT_MD
CNT_TRF
1
0
0
0
Counter operation mode select
= 0: Manual Report mode
= 1: Auto Report mode
= 0: Clear this bit for the next ‘0’ to ‘1’ transition on this bit.
= 1: Error counting result is transferred to CNT0 and CNT1 and the error counter is reset.
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4.3.7 INTERRUPT CONTROL REGISTERS
Table-32 INTM0: Interrupt Mask Register 0
(R/W, Address = 13H, 33H)
Symbol
-
Bit
7-5
4
Default
111
Description
Reserved
PRBS_IM
1
PRBS synchronic signal detect interrupt mask
= 0: PRBS synchronic signal detect interrupt enabled
= 1: PRBS synchronic signal detect interrupt masked
TCLK_IM
DF_IM
3
2
1
0
1
1
1
1
TCLK loss detect interrupt mask
= 0: TCLK loss detect interrupt enabled
= 1: TCLK loss detect interrupt masked
Driver Failure interrupt mask
= 0: Driver Failure interrupt enabled
= 1: Driver Failure interrupt masked
AIS_IM
LOS_IM
Alarm Indication Signal interrupt mask
= 0: Alarm Indication Signal interrupt enabled
= 1: Alarm Indication Signal interrupt masked
Loss Of Signal interrupt mask
= 0: Loss Of Signal interrupt enabled
= 1: Loss Of Signal interrupt masked
Table-33 INTM1: Interrupt Masked Register 1
(R/W, Address = 14H, 34H)
Symbol
Bit
Default
Description
DAC_OV_IM
7
1
DAC arithmetic overflow interrupt mask
= 0: DAC arithmetic overflow interrupt enabled
= 1: DAC arithmetic overflow interrupt masked
JAOV_IM
JAUD_IM
ERR_IM
EXZ_IM
CV_IM
6
5
4
3
2
1
0
1
1
1
1
1
1
1
JA overflow interrupt mask
= 0: JA overflow interrupt enabled
= 1: JA overflow interrupt masked
JA underflow interrupt mask
= 0: JA underflow interrupt enabled
= 1: JA underflow interrupt masked
PRBS logic error detect interrupt mask
= 0: PRBS logic error detect interrupt enabled
= 1: PRBS logic error detect interrupt masked
Receive excess zeros interrupt mask
= 0: Receive excess zeros interrupt enabled
= 1: Receive excess zeros interrupt masked
Receive error interrupt mask
= 0: Receive error interrupt enabled
= 1: Receive error interrupt masked
TIMER_IM
CNT_IM
One-Second Timer expiration interrupt mask
= 0: One-Second Timer expiration interrupt enabled
= 1: One-Second Timer expiration interrupt masked
Counter overflow interrupt mask
= 0: Counter overflow interrupt enabled
= 1: Counter overflow interrupt masked
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Table-34 INTES: Interrupt Trigger Edge Select Register
(R/W, Address = 15H, 35H)
Symbol
-
Bit
7-5
4
Default
000
Description
Reserved
PRBS_IES
0
This bit determines the PRBS synchronization status interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the PRBS_S bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the PRBS_S bit in STAT0
status register
TCLK_IES
DF_IES
3
2
1
0
0
0
0
0
This bit determines the TCLK Loss interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the TCLK_LOS bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the TCLK_LOS bit in STAT0
status register
This bit determines the Driver Failure interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the DF_S bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the DF_S bit in STAT0 status
register
AIS_IES
LOS_IES
This bit determines the AIS interrupt event.
= 0: Interrupt event is generated as a ‘0’ to ‘1’ transition of the AIS_S bit in STAT0 status register
= 1: Interrupt event is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the AIS_S bit in STAT0 status
register
This bit determines the LOS interrupt event.
= 0: Interrupt is generated as a ‘0’ to ‘1’ transition of the LOS_S bit in STAT0 status register
= 1: Interrupt is generated as either a ‘0’ to ‘1’ transition or a ‘1’ to ‘0’ transition of the LOS_S bit in STAT0 status
register
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4.3.8 LINE STATUS REGISTERS
Table-35 STAT0: Line Status Register 0 (real time status monitor)
(R, Address = 16H, 36H)
Symbol
-
Bit
7-5
4
Default
000
Description
Reserved
PRBS_S
0
Synchronous status indication of PRBS (real time)
= 0: 215-1 PRBS not detected
= 1: 215-1 PRBS detected
Note:
If PRBS_IM=0:
A ‘0’ to ‘1’ transition on this bit causes a synchronous status detected interrupt if PRBS _IES bit is ‘0’.
Any changes of this bit causes an interrupt if PRBS_IES bit is set to ‘1’.
TCLK_LOS
3
2
1
0
0
0
0
0
TCLKn loss indication
= 0: Normal
= 1: TCLK pin has not toggled for more than 70 MCLK cycles
Note:
If TCLK_IM=0:
A ‘0’ to ‘1’ transition on this bit causes an interrupt if TCLK _IES bit is ‘0’.
Any changes of this bit causes an interrupt if TCLK_IES bit is set to ‘1’.
DF_S
Line driver status indication
= 0: Normal operation
= 1: Line driver short circuit is detected.
Note:
If DF_IM=0
A ‘0’ to ‘1’ transition on this bit causes an interrupt if DF _IES bit is ‘0’.
Any changes of this bit causes an interrupt if DF_IES bit is set to ‘1’.
AIS_S
Alarm Indication Signal status detection
= 0: No AIS signal is detected in the receive path
= 1: AIS signal is detected in the receive path
Note:
If AIS_IM=0
A ‘0’ to ‘1’ transition on this bit causes an interrupt if AIS _IES bit is ‘0’.
Any changes of this bit causes an interrupt if AIS_IES bit is set to ‘1’.
LOS_S
Loss Of Signal status detection
= 0: Loss of signal on RTIPn/RRINGn is not detected
= 1: Loss of signal on RTIPn/RRINGn is detected.
Note:
If LOS_IM=0
A ‘0’ to ‘1’ transition on this bit causes an interrupt if LOS _IES bit is ‘0’.
Any changes of this bit causes an interrupt if LOS_IES bit is set to ‘1’.
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Table-36 STAT1: Line Status Register 1 (real time status monitor)
(R, Address = 17H, 37H)
Symbol
-
Bit
7-6
5
Default
Description
00
0
Reserved.
RLP_S
Indicating the status of Remote Loopback
= 0: The remote loopback is inactive.
= 1: The remote loopback is active (closed).
-
4-0
00000
Reserved
4.3.9 INTERRUPT STATUS REGISTERS
Table-37 INTS0: Interrupt Status Register 0
(R, Address = 18H, 38H) (this register is reset and relevant interrupt request is cleared after a read)
Symbol
-
Bit
7-5
4
Default
000
Description
Reserved
PRBS_IS
0
This bit indicates the occurrence of the interrupt event generated by the PRBS synchronization status.
= 0: No PRBS synchronization status interrupt event occurred
= 1: PRBS synchronization status interrupt event occurred
TCLK_LOS_IS
DF_IS
3
2
1
0
0
0
0
0
This bit indicates the occurrence of the interrupt event generated by the TCLK loss detection.
= 0: No TCLK loss interrupt event.
= 1:TCLK loss interrupt event occurred.
This bit indicates the occurrence of the interrupt event generated by the Driver Failure.
= 0: No Driver Failure interrupt event occurred
= 1: Driver Failure interrupt event occurred
AIS_IS
This bit indicates the occurrence of the AIS (Alarm Indication Signal) interrupt event.
= 0: No AIS interrupt event occurred
= 1: AIS interrupt event occurred
LOS_IS
This bit indicates the occurrence of the LOS (Loss of signal) interrupt event.
= 0: No LOS interrupt event occurred
= 1: LOS interrupt event occurred
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Table-38 INTS1: Interrupt Status Register 1
(R, Address = 19H, 39H) (this register is reset and the relevant interrupt request is cleared after a read)
Symbol
Bit
Default
Description
DAC_OV_IS
7
0
This bit indicates the occurrence of the pulse amplitude overflow of Arbitrary Waveform Generator interrupt event.
= 0: No pulse amplitude overflow of Arbitrary Waveform Generator interrupt event occurred
= 1: The pulse amplitude overflow of Arbitrary Waveform Generator interrupt event occurred
JAOV_IS
JAUD_IS
ERR_IS
6
5
4
3
2
1
0
0
0
0
0
0
0
0
This bit indicates the occurrence of the Jitter Attenuator Overflow interrupt event.
= 0: No JA Overflow interrupt event occurred
= 1: JA Overflow interrupt event occurred
This bit indicates the occurrence of the Jitter Attenuator Underflow interrupt event.
= 0: No JA Underflow interrupt event occurred
= 1: JA Underflow interrupt event occurred
This bit indicates the occurrence of the interrupt event generated by the detected PRBS logic error.
= 0: No PRBS logic error interrupt event occurred
= 1: PRBS logic error interrupt event occurred
EXZ_IS
This bit indicates the occurrence of the Excessive Zeros interrupt event.
= 0: No Excessive Zeros interrupt event occurred
= 1: EXZ interrupt event occurred
CV_IS
This bit indicates the occurrence of the Code Violation interrupt event.
= 0: No Code Violation interrupt event occurred
= 1: Code Violation interrupt event occurred
TMOV_IS
CNT_OV_IS
This bit indicates the occurrence of the One-Second Timer Expiration interrupt event.
= 0: No One-Second Timer Expiration interrupt event occurred
= 1: One-Second Timer Expiration interrupt event occurred
This bit indicates the occurrence of the Counter Overflow interrupt event.
= 0: No Counter Overflow interrupt event occurred
= 1: Counter Overflow interrupt event occurred
4.3.10 COUNTER REGISTERS
Table-39 CNT0: Error Counter L-byte Register 0
(R, Address = 1AH, 3AH)
Symbol
Bit
Default
Description
CNT_L[7:0]
7-0
00H
This register contains the lower eight bits of the 16-bit error counter. CNT_L[0] is the LSB.
Table-40 CNT1: Error Counter H-byte Register 1
(R, Address = 1BH, 3BH)
Symbol
Bit
Default
Description
CNT_H[7:0]
7-0
00H
This register contains the upper eight bits of the 16-bit error counter. CNT_H[7] is the MSB.
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5
HARDWARE CONTROL PIN SUMMARY
Table-41 Hardware Control Pin Summary
Pin No.
TQFP
Symbol
Description
9
10
MODE1
MODE0
MODE[1:0]: Operation mode of Control interface select (global control)
00= Hardware interface
01= Serial interface
10= Parallel - non-Multiplexed - Motorola Interface
11= Parallel - non-Multiplexed - Intel Interface
13
12
TERM1
TERM2
TERMn: Termination interface select (per channel control)
These pins select internal or external impedance matching for channel n (n=1 or 2)
0 = ternary interface with internal impedance matching network.
1 = ternary interface with external impedance matching network
14
15
RXTXM1
RXTXM0
RXTXM[1:0]: Receive and transmit path operation mode select (global control)
00= single rail with HDB3 coding
01= single rail with AMI coding
10= dual rail interface with CDR enable
11= slicer mode
51
47
PULS1
PULS2
PULSn: These pins are used to select the following functions (per channel control):
•
•
Transmit pulse template
Internal termination impedance (75 Ω / 120 Ω)
PULSn
TCLK
Cable impedance (internal
matching impedance)
Cable loss
0
1
2.048 MHz
2.048 MHz
75Ω
0-24 dB
0-24 dB
120Ω
57
59
RPD1
RPD2
RPDn: Receiver power down control (per channel control)
0= Normal operation
1= receiver power down
46
45
PATT11
PATT10
PATTn[1:0]: Transmit test pattern select (per channel control)
In hardware control mode, these pins select the transmit pattern for channel n (n=1 or 2)
00 = normal
56
55
PATT21
PATT20
01= All Ones
10= PRBS
11= transmitter power down
16
17
JA1
JA0
JA[1:0]: Jitter attenuation position, bandwidth and the depth of FIFO select (global control)
00= JA is disabled
01= JA in receiver, broad bandwidth, FIFO=64 bits
10= JA in receiver, narrow bandwidth, FIFO=128 bits
11= JA in transmitter, narrow bandwidth, FIFO=128 bits
19
18
MONT1
MONT2
MONTn: Receive Monitor n gain select (per channel control)
In hardware control mode with ternary interface, this pin selects the receive monitor gain for receiver n (n=1 or 2)
0= 0 dB
1= 26 dB
42
41
LP11
LP10
LPn[1:0]: Loopback mode select (per channel control)
When the chip is configured by hardware, these pins are used to select loopback operation modes for channel n.
00= no loopback
44
43
LP21
LP20
01= analog loopback
10= digital loopback
11= remote loopback
20
THZ
THZ: Transmitter Driver High Impedance Enable (global control)
This signal enables or disables both of the transmitter drivers. A low level on this pin enables both of the two drivers while a high
level on this pin places both of the two drivers in high impedance state.
HARDWARE CONTROL PIN SUMMARY
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Table-41 Hardware Control Pin Summary (Continued)
Pin No.
TQFP
Symbol
Description
11
RCLKE
RCLKE: the active edge of RCLKn select when hardware control mode is used (global control)
0= select the rising edge as active edge of RCLKn
1= select the falling edge as active edge of RCLKn
48
49
50
52
53
54
58
60
-
In Hardware mode, these pins have to be tied to GND.
HARDWARE CONTROL PIN SUMMARY
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6
IEEE STD 1149.1 JTAG TEST ACCESS PORT
TheIDT82V2052EsupportsthedigitalBoundaryScanSpecificationas
described in the IEEE 1149.1 standards.
(TDI) pin, and shifted out of the registers via the Test Data Output (TDO)
pin. Both TDI and TDO are clocked at a rate determined by TCK.
The boundary scan architecture consists of data and instruction regis-
ters plus a Test Access Port (TAP) controller. Control of the TAP is per-
formed through signals applied to the Test Mode Select (TMS) and Test
Clock (TCK) pins. Data is shifted into the registers via the Test Data Input
The JTAG boundary scan registers include BSR (Boundary Scan Reg-
ister), IDR (Device Identification Register), BR (Bypass Register) and IR
(InstructionRegister).Thesewillbedescribedinthefollowingpages.Refer
to Figure-19 for architecture.
Digital output pins
Digital input pins
parallel latched output
BSR (Boundary Scan Register)
MUX
IDR (Device Identification Register)
BR (Bypass Register)
TDI
TDO
IR (Instruction Register)
Control<6:0>
TMS
TAP
Select
TRST
(Test Access Port)
Controller
high impedance enable
TCK
Figure-19 JTAG Architecture
IEEE STD 1149.1 JTAG TEST ACCESS PORT
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6.1 JTAG INSTRUCTIONS AND INSTRUCTION REG-
ISTER
The IR (Instruction Register) with instruction decode block is used to
select the test to be executed or the data register to be accessed or both.
The instructions are shifted in LSB first to this 3-bit register. See Table-
42 for details of the codes and the instructions related.
Table-42 Instruction Register Description
IR CODE
INSTRUCTION
COMMENTS
000
Extest
The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST
instruction, the boundary scan register is placed between TDI and TDO. The signal on the input pins can be sampled by load-
ing the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary
scan register using the Shift-DR state. The signal on the output pins can be controlled by loading patterns shifted in through
input TDI into the boundary scan register using the Update-DR state.
100
Sample / Preload The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed
between TDI and TDO. The normal path between IDT82V2052E logic and the I/O pins is maintained. Primary device inputs
and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then
be viewed by shifting the boundary scan register using the Shift-DR state.
110
111
Idcode
The identification instruction is used to connect the identification register between TDI and TDO. The device's identification
code can then be shifted out using the Shift-DR state.
Bypass
The bypass instruction shifts data from input TDI to output TDO with one TCK clock period delay. The instruction is used to
bypass the device.
6.2.2 BYPASS REGISTER (BR)
6.2 JTAG DATA REGISTER
The BR consists of a single bit. It can provide a serial path between the
TDI input andTDOoutput, bypassing theBSR to reduce test access times.
6.2.1 DEVICE IDENTIFICATION REGISTER (IDR)
TheIDR canbe set todefine theproducer number, partnumber andthe
device revision, which can be used to verify the proper version or revision
numberthathasbeenusedinthesystemundertest. TheIDRis32bitslong
and is partitioned as in Table-43. Data from the IDR is shifted out to TDO
LSB first.
6.2.3 BOUNDARY SCAN REGISTER (BSR)
The BSR can apply and read test patterns in parallel to or from all the
digital I/O pins. The BSR is a 98 bits long shift register and is initialized and
read using the instruction EXTEST or SAMPLE/PRELOAD. Each pin is
related to one or more bits in the BSR. For details, please refer to the BSDL
file.
Table-43 Device Identification Register Description
Bit No.
0
Comments
Set to ‘1’
6.2.4 TEST ACCESS PORT CONTROLLER
The TAP controller is a 16-state synchronous state machine. Figure-20
shows its state diagram following the description of each state. Note that
the figure contains two main branches to access either the data or instruc-
tion registers. The value shown next to each state transition in this figure
states the value present at TMS at each rising edge of TCK. Please refer
to Table-44 for details of the state description.
1-11
Producer Number
Part Number
12-27
28-31
Device Revision
IEEE STD 1149.1 JTAG TEST ACCESS PORT
53
December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-44 TAP Controller State Description
STATE
DESCRIPTION
Test Logic Reset
In this state, the test logic is disabled. The device is set to normal operation. During initialization, the device initializes the instruction register
with the IDCODE instruction. Regardless of the original state of the controller, the controller enters the Test-Logic-Reset state when the TMS
input is held high for at least 5 rising edges of TCK. The controller remains in this state while TMS is high. The device processor automatically
enters this state at power-up.
Run-Test/Idle
This is a controller state between scan operations. Once in this state, the controller remains in the state as long as TMS is held low. The
instruction register and all test data registers retain their previous state. When TMS is high and a rising edge is applied to TCK, the controller
moves to the Select-DR state.
Select-DR-Scan
This is a temporary controller state and the instruction does not change in this state. The test data register selected by the current instruction
retains its previous state. If TMS is held low and a rising edge is applied to TCK when in this state, the controller moves into the Capture-DR
state and a scan sequence for the selected test data register is initiated. If TMS is held high and a rising edge applied to TCK, the controller
moves to the Select-IR-Scan state.
Capture-DR
Shift-DR
In this state, the Boundary Scan Register captures input pin data if the current instruction is EXTEST or SAMPLE/PRELOAD. The instruction
does not change in this state. The other test data registers, which do not have parallel input, are not changed. When the TAP controller is in
this state and a rising edge is applied to TCK, the controller enters the Exit1-DR state if TMS is high or the Shift-DR state if TMS is low.
In this controller state, the test data register connected between TDI and TDO as a result of the current instruction shifts data on stage toward
its serial output on each rising edge of TCK. The instruction does not change in this state. When the TAP controller is in this state and a rising
edge is applied to TCK, the controller enters the Exit1-DR state if TMS is high or remains in the Shift-DR state if TMS is low.
Exit1-DR
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-DR
state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-DR state.
The test data register selected by the current instruction retains its previous value and the instruction does not change during this state.
Pause-DR
The pause state allows the test controller to temporarily halt the shifting of data through the test data register in the serial path between TDI
and TDO. For example, this state could be used to allow the tester to reload its pin memory from disk during application of a long test
sequence. The test data register selected by the current instruction retains its previous value and the instruction does not change during this
state. The controller remains in this state as long as TMS is low. When TMS goes high and a rising edge is applied to TCK, the controller moves
to the Exit2-DR state.
Exit2-DR
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-DR
state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-DR state.
The test data register selected by the current instruction retains its previous value and the instruction does not change during this state.
Update-DR
The Boundary Scan Register is provided with a latched parallel output to prevent changes while data is shifted in response to the EXTEST
and SAMPLE/PRELOAD instructions. When the TAP controller is in this state and the Boundary Scan Register is selected, data is latched
into the parallel output of this register from the shift-register path on the falling edge of TCK. The data held at the latched parallel output
changes only in this state. All shift-register stages in the test data register selected by the current instruction retain their previous value and
the instruction does not change during this state.
Select-IR-Scan
Capture-IR
Shift-IR
This is a temporary controller state. The test data register selected by the current instruction retains its previous state. If TMS is held low and
a rising edge is applied to TCK when in this state, the controller moves into the Capture-IR state, and a scan sequence for the instruction reg-
ister is initiated. If TMS is held high and a rising edge is applied to TCK, the controller moves to the Test-Logic-Reset state. The instruction
does not change during this state.
In this controller state, the shift register contained in the instruction register loads a fixed value of '100' on the rising edge of TCK. This supports
fault-isolation of the board-level serial test data path. Data registers selected by the current instruction retain their value and the instruction
does not change during this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-IR
state if TMS is held high, or the Shift-IR state if TMS is held low.
In this state, the shift register contained in the instruction register is connected between TDI and TDO and shifts data one stage towards its
serial output on each rising edge of TCK. The test data register selected by the current instruction retains its previous value and the instruction
does not change during this state. When the controller is in this state and a rising edge is applied to TCK, the controller enters the Exit1-IR
state if TMS is held high, or remains in the Shift-IR state if TMS is held low.
Exit1-IR
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR
state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Pause-IR state.
The test data register selected by the current instruction retains its previous value and the instruction does not change during this state.
Pause-IR
The pause state allows the test controller to temporarily halt the shifting of data through the instruction register. The test data register selected
by the current instruction retains its previous value and the instruction does not change during this state. The controller remains in this state
as long as TMS is low. When TMS goes high and a rising edge is applied to TCK, the controller moves to the Exit2-IR state.
IEEE STD 1149.1 JTAG TEST ACCESS PORT
54
December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-44 TAP Controller State Description (Continued)
STATE
DESCRIPTION
Exit2-IR
This is a temporary state. While in this state, if TMS is held high, a rising edge applied to TCK causes the controller to enter the Update-IR
state, which terminates the scanning process. If TMS is held low and a rising edge is applied to TCK, the controller enters the Shift-IR state.
The test data register selected by the current instruction retains its previous value and the instruction does not change during this state.
Update-IR
The instruction shifted into the instruction register is latched into the parallel output from the shift-register path on the falling edge of TCK.
When the new instruction has been latched, it becomes the current instruction. The test data registers selected by the current instruction retain
their previous value.
1
Test-logic Reset
0
0
1
1
1
Run Test/Idle
Select-DR
0
Select-IR
0
1
1
Capture-DR
0
Capture-IR
0
0
0
Shift-DR
1
Shift-IR
1
1
1
0
Exit1-DR
0
Exit1-IR
0
0
Pause-DR
1
Pause-IR
1
0
0
Exit2-DR
1
Exit2-IR
1
Update-DR
Update-IR
0
0
1
1
Figure-20 JTAG State Diagram
IEEE STD 1149.1 JTAG TEST ACCESS PORT
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December 12, 2005
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DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
7
TEST SPECIFICATIONS
Table-45 Absolute Maximum Rating
Symbol
Parameter
Min
-0.5
Max
4.6
Unit
V
VDDA, VDDD
VDDIO
Core Power Supply
I/O Power Supply
-0.5
4.6
V
VDDT1-2
VDDR1-2
Transmit Power Supply
Receive Power Supply
-0.5
4.6
V
-0.5
4.6
V
Input Voltage, Any Digital Pin
GND-0.5
GND-0.5
5.5
V
Input Voltage, Any RTIPn and RRINGn pin1
ESD Voltage, any pin
VDDR+0.5
V
Vin
Iin
2000 2
500 3
V
V
Transient latch-up current, any pin
Input current, any digital pin 4
100
10
mA
mA
-10
DC Input current, any analog pin 4
Maximum power dissipation in package
Case Temperature
±100
mA
Pd
1.23
120
W
°C
°C
Tc
Ts
Storage Temperature
-65
+150
CAUTION:
Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
1.Reference to ground
2.Human body model
3.Charge device model
4.Constant input current
Table-46 Recommended Operation Conditions
Symbol
Parameter
Min
3.13
3.13
3.13
3.13
-40
Typ
3.3
3.3
3.3
3.3
25
Max
3.47
3.47
3.47
3.47
85
Unit
V
VDDA,VDDD
VDDIO
VDDT
Core Power Supply
I/O Power Supply
V
Transmitter Power Supply
Receive Power Supply
Ambient operating temperature
75 Ω load
V
VDDR
V
TA
°C
50% ones density data
100% ones density data
-
-
100
130
110
140
mA
mA
Total current dissipation1,2,3
120 Ω Load
50% ones density data
100% ones density data
-
-
110
130
120
140
1.Power consumption includes power consumption on device and load. Digital levels are 10% of the supply rails and digital outputs driving a 50 pF capacitive load.
2.Maximum power consumption over the full operating temperature and power supply voltage range.
3.In short haul mode, if internal impedance matching is chosen, 75Ω power dissipation values are measured with template PULS[3:0] = 0000; 120Ω power dissipation values are measured
with template PULS[3:0] = 0001.
TEST SPECIFICATIONS
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DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-47 Power Consumption
Symbol
Max1,2
Parameter
Min
Typ
Unit
3.3 V, 75 Ω Load
50% ones density data:
100% ones density data:
-
-
330
430
-
mW
490
3.3 V, 120 Ω Load
50% ones density data:
100% ones density data:
-
-
370
430
-
mW
490
1.Maximum power and current consumption over the full operating temperature and power supply voltage range. Includes all channels.
2.Power consumption includes power absorbed by line load and external transmitter components.
Table-48 DC Characteristics
Symbol
Parameter
Input Low Level Voltage
Min
Typ
Max
Unit
VIL
VIH
-
-
0.8
V
V
V
V
V
Input High Voltage
2.0
-
-
-
-
VOL
VOH
VMA
Output Low level Voltage (Iout=1.6mA)
Output High level Voltage (Iout=400µA)
0.4
2.4
-
VDDIO
Analog Input Quiescent Voltage (RTIPn, RRINGn
pin while floating)
1.5
II
Input Leakage Current
TMS, TDI, TRST
All other digital input pins
50
10
µA
µA
-10
-10
IZL
High Impedance Leakage Current
10
µA
Ci
Input capacitance
15
50
pF
pF
pF
Co
Co
Output load capacitance
Output load capacitance (bus pins)
100
TEST SPECIFICATIONS
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Table-49 Receiver Electrical Characteristics
Symbol
Parameter
Receiver sensitivity
Min
Typ
Max
Unit
Test conditions
Adaptive Equalizer disabled:
Adaptive Equalizer enabled:
-10
-20
dB
Analog LOS level
A LOS level is programmable with Adaptive
Adaptive Equalizer disabled:
Adaptive Equalizer enabled:
800
mVp-p Equalizer enabled. Not available in Hardware
dB mode.
-4
-24
0.05
±1%
Allowable consecutive zeros before LOS
G.775:
32
2048
I.431/ETSI300233:
LOS reset
12.5
% ones G.775, ETSI 300 233
Receive Intrinsic Jitter
20Hz - 100kHz
JA enabled
U.I.
Input Jitter Tolerance
1 Hz – 20 Hz
37
5
2
U.I.
U.I.
U.I.
G.823, with 6 dB cable attenuation
20 Hz – 2.4 KHz
18 KHz – 100 KHz
ZDM
Receiver Differential Input Impedance
Input termination resistor tolerance
20
KΩ
Internal mode
Receive Return Loss
51 KHz – 102 KHz
RRX
RPD
20
20
20
dB
dB
dB
G.703 Internal termination
102 KHz - 2.048 MHz
2.048 MHz – 3.072 MHz
Receive path delay
Single rail
Dual rail
7
2
U.I.
U.I.
JA disabled
TEST SPECIFICATIONS
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DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-50 Transmitter Electrical Characteristics
Symbol
Vo-p
Parameter
Min
Typ
Max
Unit
Output pulse amplitudes
75Ω load
2.14
2.7
2.37
3.0
2.60
3.3
V
V
120Ω load
Vo-s
Zero (space) level
75Ω load
-0.237
-0.3
0.237
0.3
V
V
120Ω load
Transmit amplitude variation with supply
-1
+1
%
mV
ns
Difference between pulse sequences for 17 consecutive pulses (T1.102)
Output Pulse Width at 50% of nominal amplitude
200
256
1.05
Tpw
RTX
232
244
Ratio of the amplitudes of Positive and Negative Pulses at the center of the pulse interval
(G.703)
0.95
Ratio of the width of Positive and Negative Pulses at the center of the pulse interval (G.703)
Transmit Return Loss (G.703)
0.95
1.05
51 KHz – 102 KHz
102 KHz - 2.048 MHz
2.048 MHz – 3.072 MHz
20
15
12
dB
dB
dB
JTXp-p
Td
Intrinsic Transmit Jitter (TCLK is jitter free)
20 Hz – 100 KHz
0.050
U.I.
Transmit path delay (JA is disabled)
Single rail
Dual rail
8.5
4.5
U.I.
U.I.
Isc
Line short circuit current; tested on the TTIP/TRING pins
100
mAp
TEST SPECIFICATIONS
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December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-51 Transmitter and Receiver Timing Characteristics
Symbol
Parameter
Min
Typ
Max
Unit
MHz
ppm
%
MCLK frequency
MCLK tolerance
MCLK duty cycle
2.048
-100
30
100
70
Transmit path
TCLK frequency
TCLK tolerance
TCLK Duty Cycle
2.048
MHz
ppm
%
-50
10
40
40
+50
90
t1
t2
Transmit Data Setup Time
ns
Transmit Data Hold Time
ns
Delay time of THZ low to driver high impedance
Delay time of TCLK low to driver high impedance
10
us
75
U.I.
Receive path
Clock recovery capture range 1
RCLK duty cycle 2
± 80
50
ppm
%
40
60
RCLK pulse width 2
t4
457
488
519
ns
t5
t6
RCLK pulse width low time
RCLK pulse width high time
203
203
244
244
285
285
20
ns
ns
ns
Rise/fall time 3
t7
t8
Receive Data Setup Time
Receive Data Hold Time
200
200
244
244
ns
ns
1.Relative to nominal frequency, MCLK= ± 100 ppm
2.RCLK duty cycle widths will vary depending on extent of received pulse jitter displacement. Maximum and minimum RCLK duty cycles are for worst case jitter conditions (0.2UI displacement
for E1 per ITU G.823).
3.For all digital outputs. C load = 15pF
TCLKn
t1
t2
TDn/TDPn
TDNn
Figure-21 Transmit System Interface Timing
TEST SPECIFICATIONS
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DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
t4
RCLKn
t6
t7
t5
t8
RDPn/RDn
(RCLK_SEL = 0 software mode)
(RCLKE = 0 hardware mode)
RDNn/CVn
t7
t8
RDPn/RDn
(RCLK_SEL = 1 software mode)
(RCLKE = 1 hardware mode)
RDNn/CVn
Figure-22 Receive System Interface Timing
Table-52 Jitter Tolerance
Jitter Tolerance
Min
Typ
Max
Unit
Standard
1 Hz
20 Hz – 2.4 KHz
18 KHz – 100 KHz
37
1.5
0.2
U.I.
U.I.
U.I.
G.823
Cable attenuation is 6dB
TEST SPECIFICATIONS
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Figure-23 E1 Jitter Tolerance Performance
Table-53 Jitter Attenuator Characteristics
Parameter
Min
Typ
Max
Unit
Jitter Transfer Function Corner (-3dB) Frequency
32/64/128 bits FIFO
JABW = 0:
6.8
0.9
Hz
Hz
JABW = 1:
Jitter Attenuator
(G.736)
@ 3 Hz
-0.5
-0.5
+19.5
+19.5
@ 40 Hz
@ 400 Hz
@ 100 kHz
dB
Jitter Attenuator Latency Delay
32 bits FIFO:
64 bits FIFO:
128 bits FIFO:
16
32
64
U.I.
U.I.
U.I.
Input jitter tolerance before FIFO overflow or underflow
32 bits FIFO:
64 bits FIFO:
128 bits FIFO:
28
58
120
U.I.
U.I.
U.I.
TEST SPECIFICATIONS
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Figure-24 E1 Jitter Transfer Performance
Table-54 JTAG Timing Characteristics
Symbol
Parameter
Min
100
25
Typ
Max
Unit
ns
t1
t2
TCK Period
TMS to TCK setup Time
TDI to TCK Setup Time
ns
t3
t4
TCK to TMS Hold Time
TCK to TDI Hold Time
25
ns
ns
TCK to TDO Delay Time
50
TEST SPECIFICATIONS
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December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
t1
TCK
t2
t3
TMS
TDI
t4
TDO
Figure-25 JTAG Interface Timing
TEST SPECIFICATIONS
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
8
MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS
8.1 SERIAL INTERFACE TIMING
Table-55 Serial Interface Timing Characteristics
Symbol
t1
Parameter
Min
100
100
5
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Comments
SCLK High Time
t2
SCLK Low Time
t3
Active CS to SCLK Setup Time
t4
Last SCLK Hold Time to Inactive CS Time
CS Idle Time
41
41
0
t5
t6
SDI to SCLK Setup Time
t7
SCLK to SDI Hold Time
82
t10
t11
SCLK to SDO Valid Delay Time
Inactive CS to SDO High Impedance Hold Time
95
90
CS
t4
t5
t3
t6
t1
t2
SCLK
SDI
t7
t7
LSB
LSB
Figure-26 Serial Interface Write Timing
MSB
13
1
2
3
4
5
6
7
8
9
10
11
12
3
14
15
16
SCLK
CS
t4
t10
t11
SDO
0
1
2
4
5
6
7
Figure-27 Serial Interface Read Timing with SCLKE=1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SCLK
CS
t4
t10
t11
7
SDO
0
1
2
3
4
5
6
Figure-28 Serial Interface Read Timing with SCLKE=0
MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS65
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
8.2 PARALLEL INTERFACE TIMING
Table-56 Non-Multiplexed Motorola Read Timing Characteristics
Symbol
tRC
Parameter
Min
190
180
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read Cycle Time
tDW
Valid DS Width
tRWV
tRWH
tAV
Delay from DS to Valid Read Signal
15
15
65
65
R/W to DS Hold Time
Delay from DS to Valid Address
Address to DS Hold Time
tADH
tPRD
DS to Valid Read Data Propagation Delay
Delay from DS inactive to data bus High Impedance
Recovery Time from Read Cycle
175
20
tDAZ
5
5
tRecovery
tRC
tRecovery
tDW
DS+CS
R/W
tRWH
tRWV
tAV
tADH
A[x:0]
Valid Address
tDAZ
tPRD
READ D[7:0]
Valid Data
Figure-29 Non-Multiplexed Motorola Read Timing
MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS66
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-57 Non-Multiplexed Motorola Write Timing Characteristics
Symbol
tWC
Parameter
Min
120
100
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle Time
tDW
Valid DS Width
tRWV
tRWH
tAV
Delay from DS to Valid Write Signal
15
15
15
65
65
R/W to DS Hold Time
Delay from DS to Valid Address
Address to DS Hold Time
Delay from DS to Valid Write Data
Write Data to DS Hold Time
Recovery Time from Write Cycle
tAH
tDV
tDHW
tRecovery
65
5
tWC
tRecovery
tDW
DS+CS
R/W
tRWH
tRWV
tAH
tAV
A[x:0]
Valid Address
tDHW
tDV
Valid Data
Write D[7:0]
Figure-30 Non-Multiplexed Motorola Write Timing
MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS67
December 12, 2005
IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-58 Non-Multiplexed Intel Read Timing Characteristics
Symbol
tRC
Parameter
Min
190
180
Max
Unit
ns
Read Cycle Time
tRDW
tAV
Valid RD Width
ns
Delay from RD to Valid Address
15
ns
tAH
Address to RD Hold Time
65
ns
tPRD
RD to Valid Read Data Propagation Delay
Delay from RD inactive to data bus High Impedance
Recovery Time from Read Cycle
175
20
ns
tDAZ
5
5
ns
tRecovery
ns
tRC
tRecovery
tRDW
CS+RD
tAH
tAV
A[x:0]
Valid Address
tDAZ
tPRD
Valid Data
READ D[7:0]
Note: WR should be tied to high
Figure-31 Non-Multiplexed Intel Read Timing
MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS68
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Table-59 Non-Multiplexed Intel Write Timing Characteristics
Symbol
tWC
Parameter
Min
120
100
Max
Unit
ns
Write Cycle Time
tWRW
tAV
Valid WR Width
ns
Delay from WR to Valid Address
Address to WR Hold Time
15
15
ns
tAH
65
ns
tDV
Delay from WR to Valid Write Data
Write Data to WR Hold Time
Recovery Time from Write Cycle
ns
tDHW
tRecovery
65
5
ns
ns
tRecovery
tWC
tWRW
WR+ CS
tAH
tAV
A[x:0]
Valid Address
tDHW
tDV
Write D[7:0]
Valid Data
Note: RD should be tied to high
Figure-32 Non-Multiplexed Intel Write Timing
MICROCONTROLLER INTERFACE TIMING CHARACTERISTICS69
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IDT82V2052E
DUAL CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
ORDERING INFORMATION
XXXXXXX
Device Type
XX
X
IDT
Process/
Temperature
Range
Blank
Industrial (-40 °C to +85 °C)
Thin Quad Flatpack
(TQFP, PN80)
PF
Green Thin Quad Flatpack
(TQFP, PNG80)
PFG
82V2052E Short Haul LIU
DATASHEET DOCUMENT HISTORY
12/12/2005 pgs. 1, 15, 21, 27, 35, 36, 43, 59, 70
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