8344AY-01 [IDT]
LOW SKEW, 1-TO-24 DIFFERENTIALTO-LVCMOS/LVTTL FANOUT BUFFER; 低偏移， 1至24 DIFFERENTIALTO - LVCMOS / LVTTL扇出缓冲器
| 型号： | 8344AY-01 |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | LOW SKEW, 1-TO-24 DIFFERENTIALTO-LVCMOS/LVTTL FANOUT BUFFER |
| 文件： | 总17页 (文件大小：275K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LOW SKEW, 1-TO-24 DIFFERENTIAL-
TO-LVCMOS/LVTTL FANOUT BUFFER
ICS8344-01
GENERAL DESCRIPTION
FEATURES
The ICS8344-01 is a low voltage, low skew
• Twenty-four LVCMOS/LVTTL outputs,
7Ω typical output impedance
ICS
HiPerClockS™
fanout buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
• Two selectable differential CLKx, nCLKx inputs
IDT. The ICS8344-01 has two selectable clock in-
puts. The CLKx, nCLKx pairs can accept most
• CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the
following input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
standard differential input levels. The ICS8344-01 is designed
to translate any differential signal level to LVCMOS/LVTTL lev-
els. The low impedance LVCMOS/LVTTL outputs are designed
to drive 50Ω series or parallel terminated transmission lines.
The effective fanout can be increased to 48 by utilizing the
ability of the outputs to drive two series terminated lines.
Redundant clock applications can make use of the dual clock
inputs which also facilitate board level testing. The clock
enable is internally synchronized to eliminate runt pulses on
the outputs during asynchronous assertion/deassertion of the
clock enable pin. The outputs are driven low when disabled.
The ICS8344-01 is characterized at full 3.3V, full 2.5V and mixed
3.3V input and 2.5V output operating supply modes.
• Output frequency up to 250MHz
• Translates any single ended input signal to LVCMOS/LVTTL
with resistor bias on nCLK input
• Synchronous clock enable
• Additive phase jitter RMS: 0.21ps (typical)
• Output skew: 200ps (maximum)
• Part-to-part skew: 900ps (maximum)
• Bank skew: 85ps (maximum)
• Propagation delay: 5ns (maximum)
Guaranteed output and part-to-part skew characteristics make
the ICS8344-01 ideal for those clock distribution applications
demanding well defined performance and repeatability.
• Output supply modes:
Core/Output
3.3V/3.3V
2.5V/2.5V
3.3V/2.5V
• 0°C to 70°C ambient operating temperature
• Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Pulldown
CLK_SEL
Pulldown
CLK0
48 47 46 45 44 43 42 41 40 39 38 37
Pullup
0
1
nCLK0
Q16
Q17
VDDO
GND
Q18
Q19
Q20
Q21
VDDO
1
2
3
4
5
6
7
8
9
36
35
34
33
32
31
30
29
28
27
26
25
Q7
Pulldown
Pullup
CLK1
nCLK1
Q6
VDDO
GND
Q5
Q0:Q7
ICS8344-01
48-Lead LQFP
7mm x 7mm x 1.4mm
package body
Y Package
Q4
Q8:Q15
Q16:Q23
Q3
Q2
VDDO
GND
Q1
Top View
GND 10
Q22 11
Q23 12
Q0
LE
nD
13 14 15 16 17 1819 20 21 22 23 24
Q
Pullup
Pullup
CLK_EN
OE
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TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2, 5, 6
7, 8, 11, 12
Q16, Q17, Q18, Q19
Q20, Q21, Q22, Q23
Output
Q16 thru Q23 outputs. 7Ω typical output impedance.
3, 9, 28,
34, 39, 45
4, 10, 14,18,
27, 33, 40, 46
VDDO
Power
Power
Output supply pins. Connect 3.3V or 2.5V.
GND
Power supply ground. Connect to ground.
Clock select input. When HIGH, selects CLK1, nCLK inputs,
13
CLK_SEL
Input
Pulldown When LOW, selects CLK0, nCLK0 inputs.
LVCMOS / LVTTL interface levelss.
15, 19
16
VDD
Power
Input
Input
Input
Input
Positive supply pins. Connect 3.3V or 2.5V.
nCLK1
CLK1
nCLK0
CLK0
Pullup
Pulldown Non-inverting differential LVPECL clock input.
Pullup Inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
17
20
21
Pulldown Non-inverting differential LVPECL clock input.
Synchronizing control for enabling and disabling clock outputs.
LVCMOS interface levels.
22
CLK_EN
Input
Pullup
Output enable. Controls enabling and disabling of outputs
Q0 thru Q23.
23
24
OE
nc
Input
Unused
Output
Pullup
No connect.
25, 26, 29, 30
31, 32, 35, 36
37, 38, 41, 42
Q0, Q1, Q2, Q3
Q4, Q5, Q6, Q7
Q8, Q9, Q10, Q11
Q0 thru Q7 outputs. 7Ω typical output impedance.
Output
Q8 thru Q15 outputs. 7Ω typical output impedance.
43, 44, 47, 48 Q12, Q13, Q14, Q15
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CLK0, nCLK0,
CLK1, nCLK1
CLK_SEL,
4
4
pF
pF
CIN
Input Capacitance
CLK_EN, OE
VDDO = 3.465V
23
16
51
51
7
pF
pF
kΩ
kΩ
Ω
Power Dissipation Capacitance
(per output)
CPD
V
DDO = 2.675V
RPULLUP
RPULLDOWN
ROUT
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
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TABLE 3A. OUTPUT ENABLE FUNCTION TABLE
Banks 1, 2, 3
Inputs
Outputs
Q0-Q23
OE
CLK_EN
0
1
X
0
Hi-Z
Disabled in logic LOW state. NOTE 1
Enabled. NOTE 1
1 (default)
1 (default)
NOTE 1: The clock enable and disable function is synchronous to the falling
edge of the selected reference clock.
TABLE 3B. CLOCK SELECT FUNCTION TABLE
Control Input
CLK_SEL
0 (default)
1
Clock
CLK0, nCLK0
Selected
CLK1, nCLK1
De-selected
Selected
De-selected
TABLE 3C. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Q0 thru Q23
LOW
Input to Output Mode
Polarity
OE
CLK0, CLK1
nCLK0, nCLK1
1 (default)
0 (default)
1 (default)
0
Differential to Single Ended
Differential to Single Ended
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
1
1
1
1
1
HIGH
0
Biased; NOTE 1
LOW
HIGH
HIGH
LOW
1
Biased; NOTE 1
Biased; NOTE 1
Biased; NOTE 1
0
1
Inverting
NOTE 1: Please refer to the Application Information section on page 8, Figure 1, which discusses Wiring the Differential
Input to Accept Single-Ended Levels.
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ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only. Functional op-
eration of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
I
Outputs, VO
Package Thermal Impedance, θJA 47.9°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDO
IDD
Positive Supply Voltage
3.135
3.135
3.3
3.3
3.465
3.465
95
V
V
Output Supply Voltage
Quiescent Power Supply Current
mA
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDO
IDD
Positive Supply Voltage
3.135
2.375
3.3
2.5
3.465
2.625
95
V
V
Output Supply Voltage
Quiescent Power Supply Current
mA
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDO
IDD
Positive Supply Voltage
2.375
2.375
2.5
2.5
2.625
2.625
95
V
V
Output Supply Voltage
Quiescent Power Supply Current
mA
TABLE 4D. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CLK_SEL, CLK_EN,
OE
CLK_SEL, CLK_EN,
OE
VIH
VIL
Input High Voltage
2
3.8
0.8
V
V
Input Low Voltage
Input High Current
-0.3
CLK_EN, OE
CLK_SEL
VDD = VIN = 3.465V
5
µA
µA
µA
µA
IIH
V
DD = VIN = 3.465V
150
CLK_EN, OE
CLK_SEL
VDD = 3.465, VIN = 0V
VDD = 3.465, VIN = 0V
VDD = VDDO = 3.135V
-150
-5
IIL
Input Low Current
VOH
VOL
Output High Voltage
Output Low Voltage
2.7
V
V
IOH = -36mA
VDD = VDDO = 3.135V
0.5
IOL = 36mA
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TABLE 4E. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CLK_SEL, CLK_EN,
OE
CLK_SEL, CLK_EN,
OE
VIH
VIL
Input High Voltage
2
3.8
0.8
V
V
Input Low Voltage
Input High Current
-0.3
CLK_EN, OE
CLK_SEL
VDD = VIN = 3.465V
5
µA
µA
µA
µA
IIH
V
DD = VIN = 3.465V
150
CLK_EN, OE
CLK_SEL
VDD = 3.465, VIN = 0V
VDD = 3.465, VIN = 0V
VDD = 3.135V
-150
-5
IIL
Input Low Current
VOH
Output High Voltage
V
DDO = 2.375V
1.9
V
V
IOH = -27mA
VDD = 3.135V
VOL
Output Low Voltage
VDDO = 2.375V
0.4
IOL = 27mA
TABLE 4F. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CLK_SEL, CLK_EN,
OE
CLK_SEL, CLK_EN,
OE
VIH
VIL
Input High Voltage
2
2.9
0.8
V
V
Input Low Voltage
Input High Current
-0.3
CLK_EN, OE
CLK_SEL
VDD = VIN = 2.625V
5
µA
µA
µA
µA
IIH
VDD = VIN = 2.625V
150
CLK_EN, OE
CLK_SEL
VDD = 2.625, VIN = 0V
-150
-5
IIL
Input Low Current
VDD = 2.625, VIN =0V
VDD = VDDO = 2.375V
IOH = -27mA
VOH
VOL
Output High Voltage
Output Low Voltage
1.9
V
V
VDD = VDDO = 2.375V
0.4
IOL = 27mA
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TABLE 4G. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
Minimum
Typical
Maximum Units
nCLK0, nCLK1
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
VDD = VIN = 3.465V
5
µA
µA
µA
µA
V
VDD = VIN = 3.465V
150
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
-150
-5
IIL
Input Low Current
VPP
Peak-toPeak Input Voltage
0.3
0.9
1.3
2
VCMR
Common Mode Input Voltage: NOTE 1, 2
V
NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 4H. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
nCLK0, nCLK1
CLK0, CLK1
VDD = VIN = 3.465V
5
µA
µA
IIH Input High Current
VDD = VIN = 3.465V
VDD = 3.465V,
150
nCLK0, nCLK1
CLK0, CLK1
-150
-5
µA
µA
V
IN = 0V
DD = 3.465V,
IN = 0V
IIL
Input Low Current
V
V
VPP
Peak-to-Peak Input Voltage
0.3
0.9
1.3
2
V
V
VCMR
Common Mode Input Voltage; NOTE 1, 2
NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 4I. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
Minimum Typical Maximum Units
nCLK0, nCLK1
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
VDD = VIN = 2.625V
5
µA
µA
µA
µA
V
VDD = VIN = 2.625V
150
V
DD = 2.625V, VIN = 0V
DD = 2.625V, VIN = 0V
-150
-5
IIL
Input Low Current
V
VPP
Peak-to-Peak Input Voltage
0.3
0.9
1.3
2
VCMR
Common Mode Input Voltage; NOTE 1, 2
V
NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ; VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ;
VDD = VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
fMAX Maximum Output Frequency
tPD
Test Conditions
Minimum
Typical
Maximum
Units
MHz
ns
250
5
Propagation Delay, NOTE 1
f ≤ 200MHz
2.5
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
Jitter Section
155.52MHz, Integration Range:
12kHz - 20MHz
tjit
0.21
ps
Q[0:7]
85
ps
ps
ps
Bank Skew;
NOTE 2, 6
Measured on the rising edge
of VDDO/2
tsk(b)
tsk(o)
Q[8:15]
180
100
Q[16:23]
Measured on the rising edge
of VDDO/2
Output Skew; NOTE 3, 6
200
900
ps
ps
Measured on the rising edge
of VDDO/2
tsk(pp) Part-to-Part Skew; NOTE 4, 6
tR
tF
Output Rise Time; NOTE 5
Output Fall Time; NOTE 5
30ꢀ to 70ꢀ
30ꢀ to 70ꢀ
200
200
800
800
ps
ps
f ≤ 200MHz
tCYCLE/2 - 0.25 tCYCLE/2 tCYCLE/2 + 0.25
ꢀ
odc
Output Duty Cycle
f = 200MHz
f = 10MHz
f = 10MHz
2.25
2.5
2.75
5
ns
ns
ns
tEN
Output Enable Time; NOTE 5
Output Disable TIme; NOTE 5
tDIS
4
All parameters measured at 200MHz and VPPtyp unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to VDDO/2.
NOTE 2: Defined as skew within a bank of outputs at the same voltage and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltage and with equal load conditions.
NOTE 4: Defined as between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
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ADDITIVE PHASE JITTER
band to the power in the fundamental. When the required offset
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is called
the dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise power
present in a 1Hz band at a specified offset from the fundamental
frequency to the power value of the fundamental. This ratio is
expressed in decibels (dBm) or a ratio of the power in the 1Hz
is specified, the phase noise is called a dBc value, which simply
means dBm at a specified offset from the fundamental. By
investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the
entire time record of the signal. It is mathematically possible to
calculate an expected bit error rate given a phase noise plot.
Additive Phase Jitter @
155.52MHz (12kHz to 20MHz) = 0.21ps typical
As with most timing specifications, phase noise measurements
has issues relating to the limitations of the equipment. Often the
noise floor of the equipment is higher than the noise floor of the
device. This is illustrated above. The device meets the noise floor
of what is shown, but can actually be lower. The phase noise is
dependent on the input source and measurement equipment.
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PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
2.05V 5ꢀ
1.25V 5ꢀ
SCOPE
VDD
VDDO
,
SCOPE
VDD
Qx
VDDO
Qx
LVCMOS
GND
GND
LVCMOS
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.25V 5ꢀ
VDD
SCOPE
nCLK0,
nCLK1
VDD
VDDO
,
VPP
VCMR
Cross Points
Qx
LVCMOS
GND
CLK0,
CLK1
GND
-1.25V 5ꢀ
2.5V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
VDDO
VDDO
Qx
2
Qx
2
PART 2
VDDO
VDDO
Qy
Qy
2
2
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
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nCLK0,
nCLK1
VDDO
2
CLK0,
CLK1
Q0:Q23
tPW
tPERIOD
Q0:Q23
tPD
tPW
x 100ꢀ
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
PROPAGATION DELAY
80ꢀ
tF
80ꢀ
20ꢀ
20ꢀ
Clock
Outputs
tR
OUTPUT RISE/FALL TIME
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APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V /2 is
generated by the bias resistors R1, R2 and C1. This bias DcDircuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V
DD
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
CLKx
nCLKx
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
LVCMOS OUTPUT:
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required, but
for additional protection, a 1kΩ resistor can be tied from CLK to
ground.
All unused LVCMOS output can be left floating. There should be
no trace attached.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
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DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL
and other differential signals. Both VSWING and VOH must meet the
VPP and VCMR input requirements. Figures 2A to 2E show interface
examples for the HiPerClockS CLK/nCLK input driven by the most
common driver types. The input interfaces suggested here are
examples only. Please consult with the vendor of the driver
component to confirm the driver termination requirements. For
example in Figure 2A, the input termination applies for IDT
HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
LVPECL
Input
nCLK
HiPerClockS
LVHSTL
Input
R1
50
R2
50
ICS
R1
50
R2
50
HiPerClockS
LVHSTL Driver
R3
50
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
IDT HIPERCLOCKS LVHSTL DRIVER
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
R4
125
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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RELIABILITY INFORMATION
TABLE 6. θ VS. AIR FLOW TABLE FOR 48 LEAD LQFP
JA
θ by Velocity (Linear Feet per Minute)
JA
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8344-01 is: 1503
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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PACKAGE OUTLINE - Y SUFFIX FOR 48 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
48
--
--
--
1.60
0.15
1.45
0.27
0.20
A1
A2
b
0.05
1.35
0.17
0.09
1.40
0.22
c
--
D
9.00 BASIC
7.00 BASIC
5.50 Ref.
9.00 BASIC
7.00 BASIC
5.50 Ref.
0.50 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
IDT™ / ICS™ LVCMOS/LVTTL FANOUT BUFFER
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TABLE 8. ORDERING INFORMATION
Part/Order Number
8344AY-01
Marking
Package
Shipping Packaging
tray
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS8344AY-01
ICS8344AY-01
ICS8344AY0lL
ICS8344AY0lL
48 Lead LQFP
8344AY-01T
48 Lead LQFP
1000 tape & reel
tray
8344AY-01LF
8344AY-01LFT
48 lead "Lead-Free" LQFP
48 lead "Lead-Free" LQFP
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional
processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical
instruments.
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REVISION HISTORY SHEET
Rev
Table
4A
Page
4
5
Description of Change
Revised IDD row from 60mA Max. to 95mA Max.
Revised IDD row from 60mA Max. to 95mA Max.
Revised IDD row from 60mA Max. to 95mA Max.
Revised Note 1 and Note 4.
Date
B
4D
8/6/01
4G
6
7
B
5A
Updated Parameter Measurement Figures.
Deleted Power Consideration notes.
12/13/01
8-10
B
B
1
Updated Block Diagram.
12/18/01
7/24/02
On April 18, 2001 a typo was corrected in the Ordering Information Table.
The correction was ICS8344AY-01 from ICS8344BY-01.
Features Section - added lead-free bullet.
8
14
1
10
11
14
Added Recommendations for Unused Input and Output Pins.
Added Differential Clock Input Interface.
Ordering Information Table - added lead-free part number, marking and note.
Updated datasheet format.
B
B
10/26/06
5/10/07
3A
3
Output Enable Function Table - updated table.
1
1
2
3
7
Added Pullup and Pulldown to Block Diagram.
Features Section - added Additive Phase Jitter bullet.
Pin Characteristics Table - add CPD specs.
Function Tables - added default to conditions.
AC Characteristics Table - added Additive Phase Jitter row.
Added Additive Phase Jitter Plot.
T3A - T3C
5
C
C
9/8/08
9/9/08
8
8
15
Ordering Information Table - removed ICS prefix from part/order number
column.
In CIN row, replaced CLK-SEL with CLK_SEL.
T2
2
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