83904AG-02LF [IDT]
Low Skew, 1-to-4, Crystal-to-LVCMOS/LVTTL Fanout Buffer;
| 型号： | 83904AG-02LF |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew, 1-to-4, Crystal-to-LVCMOS/LVTTL Fanout Buffer 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总16页 (文件大小：175K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Skew, 1-to-4, Crystal-to-LVCMOS/
LVTTL Fanout Buffer
83904-02
Data Sheet
GENERAL DESCRIPTION
FEATURES
The 83904-02 is a low skew, high performance 1-to-4 Crystal-to-
LVCMOS Fanout Buffer.The 83904-02 has selectable single-ended
clock or two crystal-oscillator inputs. There is an output enable to
disable the outputs by placing them into a high-impedance state.
• Four LVCMOS/LVTTL outputs,
19Ω typical output impedance @ V = V = 3.3V
DD
DDO
• Two Crystal oscillator input pairs
One LVCMOS/LVTTL clock input
Guaranteed output and part-to-part skew characteristics
make the 83904-02 ideal for those applications demand-
ing well defined performance and repeatability.
• Crystal input frequencry range: 12MHz – 38.88MHz
• Output frequency: 200MHz (maximum)
• Output Skew: 40ps (maximum) @ V = V = 3.3V
DD
DDO
• RMS phase jitter @ 25MHz output, using a 25MHz crystal
(100Hz – 1MHz): 0.16ps (typical) @ V = V = 3.3V
DD
DDO
• RMS phase noise at 25MHz:
Offset
Noise Power
100Hz ..............-118.4 dBc/Hz
1kHz ..............-141.5 dBc/Hz
10kHz ..............-157.2 dBc/Hz
100kHz ..............-157.2 dBc/Hz
• Supply Voltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• 0°C to 70°C ambient operating temperature
• Available in lead-free (RoHS 6) package
BLOCK DIAGRAM
Pullup
OE
Pulldown
CLK_SEL0
Pulldown
CLK_SEL1
PIN ASSIGNMENT
XTAL_IN0
OSC
Q0
Q1
Q2
Q3
CLK_SEL0
XTAL_OUT0
XTAL_IN0
VDD
XTAL_IN1
XTAL_OUT1
CLK_SEL1
CLK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDO
Q0
Q1
GND
Q2
Q3
0 0
XTAL_OUT0
VDDO
OE
XTAL_IN1
OSC
0 1
83904-02
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
XTAL_OUT1
1 0
Pulldown
CLK
1 1
G Package
Top View
©2016 Integrated Device Technology, Inc
1
Revision A March 17, 2016
83904-02 Data Sheet
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
CLK_SEL0,
CLK_SEL1
Clock select inputs. See Table 3, Input Reference Function Table.
LVCMOS / LVTTL interface levels.
1, 7
Input Pulldown
XTAL_OUT0,
XTAL_IN0
Crystal oscillator interface. XTAL_IN0 is the input.
XTAL_OUT0 is the output.
2, 3
4
Input
Power
Input
V
Positive supply pin.
DD
XTAL_IN1,
XTAL_OUT1
Crystal oscillator interface. XTAL_IN1 is the input.
XTAL_OUT1 is the output.
5, 6
8
CLK
Input Pulldown Single-ended clock input. LVCMOS/LVTTL interface levels.
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
Output supply pins.
9
OE
Input
Pullup
10, 16
V
Power
DDO
11, 12, 14, 15 Q3, Q2, Q1, Q0 Output
13 GND Power
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
Power supply ground.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical Maximum Units
C
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
51
51
8
pF
kΩ
kΩ
pF
pF
pF
Ω
IN
R
PULLUP
R
PULLDOWN
V
V
= 3.465V
= 2.625V
= 2.0V
DDO
DDO
Power Dissipation Capacitance
(per output)
C
7
PD
V
V
V
V
7
DDO
= 3.3V
= 2.5V
= 1.8V
19
21
32
DDO
DDO
DDO
R
Output Impedance
Ω
OUT
Ω
TABLE 3. INPUT REFERENCE FUNCTION TABLE
Control Inputs
Reference
CLK_SEL1
CLK_SEL0
0
0
1
1
0
1
0
1
XTAL0 (default)
XTAL1
CLK
CLK
©2016 Integrated Device Technology, Inc
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Revision A March 17, 2016
83904-02 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
DD
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions beyond
those listed in the DC Characteristics or AC Characteristics is not
implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect product reliability.
Inputs, V
-0.5V to V + 0.5 V
I
DD
Outputs, V
-0.5V to V + 0.5V
O
DDO
Package Thermal Impedance, θ
100.3°C/W (0 mps)
-65°C to 150°C
JA
Storage Temperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, V = V = 3.3V 5ꢀ, TA = 0°C TO 70°C
DD
DDO
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
V
V
Power Supply Voltage
3.135
3.135
3.3
3.3
3.465
V
DD
Output Supply Voltage
Power Supply Current
Output Supply Current
3.465
V
DDO
No Load & XTALx selected @ 12MHz
No Load & CLK selected
7
1
1
mA
mA
mA
I
DD
I
No Load & CLK selected
DDO
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, V = 3.3V 5ꢀ, V = 2.5V 5ꢀ, TA = 0°C TO 70°C
DD
DDO
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
V
V
Power Supply Voltage
3.135
2.375
3.3
2.5
3.465
V
DD
Output Supply Voltage
Power Supply Current
Output Supply Current
2.625
V
DDO
No Load & XTALx selected @ 12MHz
No Load & CLK selected
7
1
1
mA
mA
mA
I
DD
I
No Load & CLK selected
DDO
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, V = 3.3V 5ꢀ, V = 1.8V 0.2V, TA = 0°C TO 70°C
DD
DDO
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
V
V
Power Supply Voltage
3.135
1.6
3.3
1.8
3.465
V
DD
Output Supply Voltage
Power Supply Current
Output Supply Current
2.0
7
V
DDO
No Load & XTALx selected @ 12MHz
No Load & CLK selected
mA
mA
mA
I
DD
1
I
No Load & CLK selected
1
DDO
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, V = V = 2.5V 5ꢀ, TA = 0°C TO 70°C
DD
DDO
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
V
V
Power Supply Voltage
2.375
2.375
2.5
2.5
2.625
V
DD
Output Supply Voltage
Power Supply Current
Output Supply Current
2.625
V
DDO
No Load & XTALx selected @ 12MHz
No Load & CLK selected
3
1
1
mA
mA
mA
I
DD
I
No Load & CLK selected
DDO
©2016 Integrated Device Technology, Inc
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Revision A March 17, 2016
83904-02 Data Sheet
TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, V = 2.5V 5ꢀ, V = 1.8V 0.2V, TA = 0°C TO 70°C
DD
DDO
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
V
V
Power Supply Voltage
2.375
1.6
2.5
1.8
2.625
V
DD
Output Supply Voltage
Power Supply Current
Output Supply Current
2.0
3
V
DDO
No Load & XTALx selected @ 12MHz
No Load & CLK selected
mA
mA
mA
I
DD
1
I
No Load & CLK selected
1
DDO
TABLE 4F. DC CHARACTERISTICS, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
V
V
V
V
= 3.3V 5ꢀ
= 2.5V 5ꢀ
= 3.3V 5ꢀ
= 2.5V 5ꢀ
2.2
1.6
V
V
+ 0.3
+ 0.3
V
V
V
V
DD
DD
DD
DD
DD
V
V
Input High Voltage
Input Low Voltage
IH
DD
-0.3
-0.3
1.3
IL
0.9
150
5
CLK, CLK_
SEL0:1
V
V
V
V
= 3.3V or 2.5V 5ꢀ
= 3.3V or 2.5V 5ꢀ
= 3.3V or 2.5V 5ꢀ
µA
µA
µA
DD
DD
DD
DD
I
Input High Current
Input Low Current
IH
OE
CLK, CLK_
SEL0:1
-5
I
IL
OE
= 3.3V or 2.5V 5ꢀ
= 3.3V 5ꢀ% NOTE 1
= 2.5V 5ꢀ% NOTE 1
= 1.8V 0.2V% NOTE 1
= 3.3V 5ꢀ% NOTE 1
= 2.5V 5ꢀ% NOTE 1
= 1.8V 0.2V% NOTE 1
-150
2.6
µA
V
V
DDO
V
Output HighVoltage
Output Low Voltage
V
1.8
V
OH
DDO
V
1.2
V
DDO
V
V
0.6
0.5
0.4
V
DDO
DDO
V
V
OL
V
V
DDO
NOTE 1: Outputs terminated with 50Ω to V /2. See Parameter Measurement section, “Load Test Circuit” diagrams.
DDO
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
12
38.88
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
©2016 Integrated Device Technology, Inc
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Revision A March 17, 2016
83904-02 Data Sheet
TABLE 6A. AC CHARACTERISTICS, V = V = 3.3V 5ꢀ, TA = 0°C TO 70°C
DD
DDO
Symbol Parameter
Output Frequency
Test Conditions
Minimum Typical Maximum Units
w/external XTAL
w/external CLK
12
38.88
200
MHz
MHz
f
MAX
Propagation Delay, Low-to-High% NOTE
1
tp
1.4
1.9
2.4
ns
LH
tsk(o)
Output Skew% NOTE 2
40
ps
ps
tsk(pp)
Part-to-Part Skew% NOTE 2, 3
700
RMS Phase Jitter, Random%
NOTE 2, 4
25MHz, Integration Range:
100Hz – 1MHz
tjit(Ø)
0.16
ps
t / t
Output Rise/Fall Time
20ꢀ to 80ꢀ
100
45
800
55
54
10
10
ps
ꢀ
R
F
w/external XTAL
w/external CLK
Output
Duty Cycle
odc
ƒ < 150MHz
46
ꢀ
t
Output Enable Time% NOTE 5
Output Disable Time% NOTE 5
ns
ns
EN
t
DIS
NOTE 1: Measured from V /2 of the input to V /2 of the output.
DDO
NOTE 2: This parameter isDdD efined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V /2.
DDO
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
TABLE 6B. AC CHARACTERISTICS, V = 3.3V 5ꢀ, V = 2.5V 5ꢀ, TA = 0°C TO 70°C
DD
DDO
Symbol Parameter
Output Frequency
Test Conditions
Minimum Typical Maximum Units
w/external XTAL
w/external CLK
12
38.88
200
MHz
MHz
f
MAX
Propagation Delay, Low-to-High% NOTE
1
tp
1.5
2.0
2.5
ns
LH
tsk(o)
Output Skew% NOTE 2
40
ps
ps
tsk(pp)
Part-to-Part Skew% NOTE 2, 3
700
RMS Phase Jitter, Random%
NOTE 2, 4
25MHz, Integration Range:
100Hz - 1MHz
tjit(Ø)
0.16
ps
t / t
Output Rise/Fall Time
20ꢀ to 80ꢀ
100
45
800
55
54
10
10
ps
ꢀ
R
F
w/external XTAL
w/external CLK
Output
Duty Cycle
odc
ƒ < 150MHz
46
ꢀ
t
Output Enable Time% NOTE 5
Output Disable Time% NOTE 5
ns
ns
EN
t
DIS
NOTE 1: Measured from V /2 of the input to V /2 of the output.
DDO
NOTE 2: This parameter isDdD efined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V /2.
DDO
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
©2016 Integrated Device Technology, Inc
5
Revision A March 17, 2016
83904-02 Data Sheet
TABLE 6C. AC CHARACTERISTICS, V = 3.3V 5ꢀ, V = 1.8V 0.2V, TA = 0°C TO 70°C
DD
DDO
Symbol Parameter
Output Frequency
Test Conditions
Minimum Typical Maximum Units
w/external XTAL
w/external CLK
12
38.88
200
MHz
MHz
f
MAX
Propagation Delay, Low-to-High% NOTE
1
tp
1.7
2.2
2.7
ns
LH
tsk(o)
Output Skew% NOTE 2
40
ps
ps
tsk(pp)
Part-to-Part Skew% NOTE 2, 3
700
RMS Phase Jitter, Random%
NOTE 2, 4
25MHz, Integration Range:
100Hz - 1MHz
tjit(Ø)
0.16
ps
t / t
Output Rise/Fall Time
20ꢀ to 80ꢀ
100
45
1000
55
ps
ꢀ
R
F
w/external XTAL
w/external CLK
Output
Duty Cycle
odc
ƒ < 150MHz
46
54
ꢀ
t
Output Enable Time% NOTE 5
Output Disable Time% NOTE 5
10
ns
ns
EN
t
10
DIS
NOTE 1: Measured from V /2 of the input to V /2 of the output.
DDO
NOTE 2: This parameter isDdD efined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V /2.
DDO
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
TABLE 6D. AC CHARACTERISTICS, V = V = 2.5V 5ꢀ, TA = 0°C TO 70°C
DD
DDO
Symbol Parameter
Output Frequency
Test Conditions
Minimum Typical Maximum Units
w/external XTAL
w/external CLK
12
38.88
200
MHz
MHz
f
MAX
Propagation Delay, Low-to-High% NOTE
1
tp
1.5
2.2
3.0
ns
LH
tsk(o)
Output Skew% NOTE 2
40
ps
ps
tsk(pp)
Part-to-Part Skew% NOTE 2, 3
700
RMS Phase Jitter, Random%
NOTE 2, 4
25MHz, Integration Range:
100Hz - 1MHz
tjit(Ø)
0.20
ps
t / t
Output Rise/Fall Time
20ꢀ to 80ꢀ
100
45
800
55
52
10
10
ps
ꢀ
R
F
w/external XTAL
w/external CLK
Output
Duty Cycle
odc
ƒ < 150MHz
48
ꢀ
t
Output Enable Time% NOTE 5
Output Disable Time% NOTE 5
ns
ns
EN
t
DIS
NOTE 1: Measured from V /2 of the input to V /2 of the output.
DDO
NOTE 2: This parameter isDdD efined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V /2.
DDO
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
©2016 Integrated Device Technology, Inc
6
Revision A March 17, 2016
83904-02 Data Sheet
TABLE 6E. AC CHARACTERISTICS, V = 2.5V 5ꢀ, V = 1.8V 0.2V, TA = 0°C TO 70°C
DD
DDO
Symbol Parameter
Output Frequency
Test Conditions
Minimum Typical Maximum Units
w/external XTAL
w/external CLK
12
38.88
200
MHz
MHz
f
MAX
Propagation Delay, Low-to-High% NOTE
1
tp
1.7
2.5
3.3
ns
LH
tsk(o)
Output Skew% NOTE 2
40
ps
ps
tsk(pp)
Part-to-Part Skew% NOTE 2, 3
700
RMS Phase Jitter, Random%
NOTE 2, 4
25MHz, Integration Range:
100Hz - 1MHz
tjit(Ø)
0.19
ps
t / t
Output Rise/Fall Time
20ꢀ to 80ꢀ
100
45
1000
55
ps
ꢀ
R
F
w/external XTAL
w/external CLK
Output
Duty Cycle
odc
ƒ < 150MHz
46
54
ꢀ
t
Output Enable Time% NOTE 5
Output Disable Time% NOTE 5
10
ns
ns
EN
t
10
DIS
NOTE 1: Measured from V /2 of the input to V /2 of the output.
DDO
NOTE 2: This parameter isDdD efined in accordance with JEDEC Standard 65.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at V /2.
DDO
NOTE 4: Phase jitter is dependent on the input source used.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
©2016 Integrated Device Technology, Inc
7
Revision A March 17, 2016
83904-02 Data Sheet
TYPICAL PHASE NOISE AT 25MHZ
0
-10
25MHz
-20
-30
RMS Phase Jitter (Random)
100Hz to 1MHz = 0.16ps (typical)
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
Raw Phase Noise Data
100
1k
10k
100k
1M
OFFSET FREQUENCY (HZ)
©2016 Integrated Device Technology, Inc
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Revision A March 17, 2016
83904-02 Data Sheet
PARAMETER MEASUREMENT INFORMATION
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
PART-TO-PART SKEW
©2016 Integrated Device Technology, Inc
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Revision A March 17, 2016
83904-02 Data Sheet
PARAMETER MEASUREMENT INFORMATION, CONTINUED
PROPAGATION DELAY
OUTPUT SKEW
80ꢀ
80ꢀ
20ꢀ
20ꢀ
Q0:Q3
tR
tF
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
©2016 Integrated Device Technology, Inc
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Revision A March 17, 2016
83904-02 Data Sheet
APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUTS
LVCMOS OUTPUTS
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1kΩ resistor can be tied
from XTAL_IN to ground.
All unused LVCMOS output can be left floating. There should be
no trace attached.
CLK INPUT
For applications not requiring the use of the clock input, it can be
left floating.Though not required, but for additional protection, a 1kΩ
resistor can be tied from the CLK input to ground.
SELECT PINS
All select pins have internal pull-ups and pull-downs% additional
resistance is not required but can be added for additional protection.
A 1kΩ resistor can be used.
©2016 Integrated Device Technology, Inc
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Revision A March 17, 2016
83904-02 Data Sheet
CRYSTAL INPUT INTERFACE
Figure 1 shows an example of 83904-02 crystal interface with
a parallel resonant crystal. The frequency accuracy can be fine
tuned by adjusting the C1 and C2 values. For a parallel crystal with
loading capacitance CL = 18pF, we suggest C1 = 15pF and C2 =
15pF to start with.These values may be slightly fine tuned further to
optimize the frequency accuracy for different board layouts.Slightly
increasing the C1 and C2 values will slightly reduce the frequency.
Slightly decreasing the C1 and C2 values will slightly increase the
frequency.For the oscillator circuit below, R1 can be used, but is not
required. For new designs, it is recommended that R1 not be used.
XTAL_IN
C1
15p
X1
18pF Parallel Crystal
0
XTAL_OU T
C2
15p
R1 (optional)
FIGURE 1. CRYSTAL INPUT INTERFACE
OVERDRIVING THE CRYSTAL INTERFACE
termination at the crystal input will attenuate the signal in half.This
can be done in one of two ways. First, R1 and R2 in parallel should
equal the transmission line impedance. For most 50Ω applications,
R1 and R2 can be 100Ω.This can also be accomplished by removing
R1 and making R2 50Ω.By overdring the crystal oscillator, the device
will be functional, but note, the device performance is guaranteed
by using a quartz crystal.
The XTAL_IN input can a single-ended LVCMOS signal through
an AC coupling capacitor. A general interface diagram is shown in
Figure 2A. The XTAL_OUT pin can be left floating. The maximum
amplitude of the input signal should not exceed 2V and the input
edge rate can be as slow as 10ns. This configuration requires that
the output impedance of the driver (Ro) plus the series resistance
(Rs) equals the transmission line impedance. In addition, matched
3.3V
3.3V
R1
100
C1
Ro ~ 7 Ohm
Zo = 50 Ohm
XTAL_IN
RS
43
0.1uF
R2
100
Driver_LVCMOS
XTAL_OUT
Crystal Input Interface
FIGURE 2A. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
VCC=3.3V
C1
Zo = 50 Ohm
XTAL_IN
0.1uF
R1
50
Zo = 50 Ohm
XTAL_OUT
LVPECL
Crystal Input Interface
R2
50
R3
50
FIGURE 2A. GENERAL DIAGRAM FOR LVPECL DRIVER TO XTAL INPUT INTERFACE
©2016 Integrated Device Technology, Inc
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Revision A March 17, 2016
83904-02 Data Sheet
RELIABILITY INFORMATION
TABLE 7. θ VS. AIR FLOW TABLE FOR 16 LEAD TSSOP
JA
θJA by Velocity (Linear Feet per Minute)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
100.3°C/W
96.0°C/W
93.9°C/W
TRANSISTOR COUNT
The transistor count for 83904-02 is: 205
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
16
--
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
©2016 Integrated Device Technology, Inc
13
Revision A March 17, 2016
83904-02 Data Sheet
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
tube
Temperature
83904AG-02LF
83904AG-02LFT
3904A02L
3904A02L
16 Lead “Lead-Free” TSSOP
16 Lead “Lead-Free” TSSOP
0°C to 70°C
0°C to 70°C
tape & reel
©2016 Integrated Device Technology, Inc
14
Revision A March 17, 2016
83904-02 Data Sheet
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
12
14
Updated Overdriving the Crystal Interface section.
Ordering Information Table - deleted the “ICS” prefix in the Part/Order Number column
and corrected the Temperature column.
T9
A
9/3/10
Updated header/footer.
T9
T9
14
14
Ordering Information - Removed leaded devices.
Updated data sheet format.
A
A
3/25/15
3/17/16
Ordering Information - Deleted LF note below table.
Updated header and footer.
©2016 Integrated Device Technology, Inc
15
Revision A March 17, 2016
83904-02 Data Sheet
Tech Support
www.idt.com/go/support
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
Sales
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and
operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided
without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringe-
ment of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expect-
ed to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or
their respective third party owners.
For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary.
Copyright ©2016 Integrated Device Technology, Inc. All rights reserved.
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