83948AYI-147LFT [IDT]
Low Skew, 1-to-1 Differential to-;
| 型号： | 83948AYI-147LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Low Skew, 1-to-1 Differential to- PC 驱动 逻辑集成电路 |
| 文件： | 总17页 (文件大小：361K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Skew, 1-to-1 Differential-
83948I-147
Data Sheet
to-LVCMOS/ LVTTL Fanout Buffer
General Description
Features
The 83948I-147 is a low skew, 1-to-12 Differential-to-LVCMOS/LVT-
TL Fanout Buffer. The 83948I-147 has two selectable clock inputs.
The CLK, nCLK pair can accept most standard differential input lev-
els. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels.
The low impedance LVCMOS/LVTTL outputs are designed to drive
50 series or parallel terminated transmission lines. The effective fa-
nout can be increased from 12 to 24 by utilizing the ability of the out-
puts to drive two series terminated lines.
• Twelve LVCMOS/LVTTL outputs
• Selectable differential CLK/nCLK or LVCMOS/LVTTL clock input
• CLK/nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• LVCMOS_CLK supports the following input types:
LVCMOS, LVTTL
• Output frequency: 350MHz
The 83948I-147 is characterized at full 3.3V, full 2.5V or mixed 3.3V
core/2.5V output operating supply modes. Guaranteed output and
part-to-part skew characteristics make the 83948I-147 ideal for those
clock distribution applications demanding well defined performance
and repeatability.
• Additive phase jitter, RMS: 0.14ps (typical)
• Output skew: 100ps (maximum), 3.3V 5%
• Part-to-part skew: 1ns (maximum), 3.3V 5%
• Operating supply modes:
• Core/Output
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) packaging
Block Diagram
Pin Assignment
CLK_EN
D
Q
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
CLK_SEL
GND
24
23
22
21
20
LVCMOS_CLK
1
Q0
LVCMOS_CLK
CLK
Q4
CLK
nCLK
0
VDDO
Q5
Q1
nCLK
CLK_SEL
Q2
CLK_EN
GND
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
OE
VDD
Q6
19
18
17
VDDO
Q7
GND
9
10 11 12 13 14 15 16
83948I-147
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
OE
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83948I-147 Data Sheet
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
Name
Type
Description
Clock select input. When HIGH, selects LVCMOS_CLK input.
When LOW, selects CLK/nCLK inputs. LVCMOS / LVTTL interface levels.
1
CLK_SEL
Input
Input
Pullup
Pullup
LVCMOS_CL
K
2
Single-ended clock input. LVCMOS/LVTTL interface levels.
3
4
5
CLK
nCLK
Input
Input
Input
Pullup
Pulldown
Pullup
Non-inverting differential clock input.
Inverting differential clock input.
CLK_EN
Clock enable pin. LVCMOS/LVTTL interface levels.
Output enable pin. When LOW, outputs are in an High-impedance state.
when HIGH, outputs are active. LVCMOS/LVTTL interface levels.
6
7
OE
VDD
GND
Input
Power
Power
Pullup
Power supply pin.
8, 12, 16,
20, 24, 28, 32
Power supply ground.
Q11, Q10,
Q9, Q8, Q7,
Q6,
Q5, Q4, Q3,
Q2, Q1, Q0
9, 11, 13,
15, 17, 19,
21, 23, 25,
27, 29, 31
Output
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
10, 14, 18,
22, 26, 30
VDDO
Power
Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum
Units
pF
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
RPULLUP
RPULLDOWN
51
51
k
k
Power Dissipation Capacitance
(per output)
CPD
12
7
pF
ROUT
Output Impedance
5
12
Function Tables
Table 3A. Clock Select Function Table
Control
Input
Clock
0
1
CLK/nCLK inputs selected
LVCMOS_CLK input selected
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83948I-147 Data Sheet
Table 3B. Clock Input Function Table
Inputs
Outputs
Q[0:11]
LOW
CLK_SEL
LVCMOS_CLK
CLK
nCLK
Input to Output Mode
Polarity
0
0
0
0
0
0
1
1
–
–
–
–
–
–
0
1
0
1
Differential to Single-Ended
Differential to Single-Ended
Non-Inverting
Non-Inverting
1
0
HIGH
LOW
0
Biased; NOTE 1
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Single-Ended to Single-Ended
Non-Inverting
Non-Inverting
Inverting
1
Biased; NOTE 1
HIGH
HIGH
LOW
Biased; NOTE 1
0
1
–
–
Biased; NOTE 1
Inverting
–
–
LOW
Non-Inverting
Non-Inverting
HIGH
NOTE 1: Please refer to the Application Information Section, Wiring the Differential Input to Accept Single-ended Levels.
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Rating
Supply Voltage, VDD
Inputs, VI
4.6V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
73.6C/W (0 mps)
-65C to 150C
Outputs, VO
Package Thermal Impedance, JA
Storage Temperature, TSTG
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, V = V
= 3.3V 5%, T = -40°C to 85°C
A
DD
DDO
Symbol
VDD
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
3.465
55
Units
V
Power Supply Voltage
Output Supply Voltage
Power Supply Current
VDDO
IDD
3.135
3.3
V
mA
Table 4B. Power Supply DC Characteristics, V = V
= 2.5V 5%, T = -40°C to 85°C
A
DD
DDO
Symbol
VDD
Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum
2.625
2.625
52
Units
V
Positive Supply Voltage
Output Supply Voltage
Power Supply Current
VDDO
IDD
2.375
2.5
V
mA
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83948I-147 Data Sheet
Table 4C. Power Supply DC Characteristics, V = 3.3V 5%, V
= 2.5V 5%, T = -40°C to 85°C
A
DD
DDO
Symbol
VDD
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum
3.465
2.625
55
Units
V
Power Supply Voltage
Output Supply Voltage
Power Supply Current
VDDO
IDD
2.375
2.5
V
mA
Table 4D. DC Characteristics, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
DD = 3.465V
VDD = 2.625V
Minimum
Typical
Maximum
VDD + 0.3
VDD + 0.3
0.8
Units
V
LVCMOS
V
2
VIH
Input High Voltage
LVCMOS
LVCMOS
LVCMOS
1.7
-0.3
-0.3
V
V
V
DD = 3.465V
DD = 2.625V
V
VIL
IIN
Input Low Voltage
Input Current
0.7
V
VIN = VDD or VIN = 3.465V or 2.625V
300
µA
V
DDO = 3.3V 5%
IOH = -24mA
2.4
1.8
V
V
V
V
V
V
VOH
Output High Voltage; NOTE 1
VDDO = 2.5V 5%
IOH = -15mA
VDDO = 3.3V 5%
IOL = 24mA
0.55
0.30
0.6
VDDO = 3.3V 5%
IOL = 12mA
VOL
Output Low Voltage; NOTE 1
Peak-to-Peak Input
VDDO = 2.5V 5%
IOL = 15mA
VPP
CLK/nCLK
VDD = 3.465V or 2.625V
VDD = 3.465V or 2.625V
0.15
1.3
Voltage; NOTE 2
Common Mode
Input Voltage;
NOTE 2, 3
CLK/nCLK
VCMR
GND + 0.5
VDD – 0.85
V
NOTE 1: Outputs capable of driving 50 transmission lines terminated with 50 to VDDO/2. See Parameter Measurement section, Output
Load AC Test Circuit diagrams.
NOTE 2: VIL should not be less than -0.3V.
NOTE 3: Common mode voltage is defined as VIH.
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83948I-147 Data Sheet
AC Electrical Characteristics
Table 5A. AC Characteristics, V = V
= 3.3V 5%, T = -40°C to 85°C
DD
DDO
A
Parameter Symbol
Test Conditions
Minimum
Typical
Maximum Units
fMAX
Output Frequency
350
4
MHz
ns
CLK/nCLK; NOTE 1
ƒ 350MHz
ƒ 350MHz
2
2
Propagation
Delay
tPD
LVCMOS_CLK;
NOTE 2
4
ns
155.52MHz,
Integration Range:
12kHz – 20MHz
Buffer Additive Phase Jitter, RMS; refer
to Additive Phase Jitter Section
tjit
0.14
1
ps
Measured on the Rising Edge
@ VDDO/2
tsk(o)
Output Skew; NOTE 3, 7
100
1
ps
ns
Measured on the Rising Edge
@ VDDO/2
tsk(pp)
Part-to-Part Skew; NOTE 4, 7
tR / tF
odc
Output Rise/Fall Time
0.8V to 2V
0.2
45
1.0
55
5
ns
%
Output Duty Cycle
ƒ 150MHz, Ref = CLK/nCLK
50
tPZL, PZH
t
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
ns
ns
ns
tPLZ, PHZ
t
5
CLK_EN to CLK/nCLK
1
0
0
1
Clock Enable
Setup Time;
NOTE 6
tS
CLK_EN to
LVCMOS_CLK
ns
ns
ns
CLK/nCLK to CLK_EN
Clock Enable
Hold Time;
NOTE 6
tH
LVCMOS_CLK to
CLK_EN
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using
the same type of input on each device, the output is measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
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83948I-147 Data Sheet
Table 5B. AC Characteristics, V = V
= 2.5V 5%, T = -40°C to 85°C
DD
DDO
A
Parameter Symbol
Test Conditions
Minimum
Typical
Maximum Units
fMAX
Output Frequency
350
4.2
MHz
ns
CLK/nCLK; NOTE 1
ƒ 350MHz
ƒ 350MHz
1.5
1.7
Propagation
Delay
tPD
LVCMOS_CLK;
NOTE 2
4.4
ns
155.52MHz,
Integration Range:
12kHz – 20MHz
Buffer Additive Phase Jitter, RMS; refer
to Additive Phase Jitter Section
tjit
0.14
1
ps
Measured on the Rising Edge
@ VDDO/2
tsk(o)
Output Skew; NOTE 3, 7
160
2
ps
ns
Measured on the Rising Edge
@ VDDO/2
tsk(pp)
Part-to-Part Skew; NOTE 4, 7
tR / tF
odc
Output Rise/Fall Time
0.6V to 1.8V
0.1
40
1.0
60
5
ns
%
Output Duty Cycle
ƒ 150MHz, Ref = CLK/nCLK
tPZL, PZH
t
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
ns
ns
ns
tPLZ, PHZ
t
5
CLK_EN to CLK/nCLK
1
0
0
1
Clock Enable
Setup Time;
NOTE 6
tS
CLK_EN to
LVCMOS_CLK
ns
ns
ns
CLK/nCLK to CLK_EN
Clock Enable
Hold Time;
NOTE 6
tH
LVCMOS_CLK to
CLK_EN
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using
the same type of input on each device, the output is measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
©2016 Integrated Device Technology, Inc
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83948I-147 Data Sheet
Table 5C. AC Characteristics, V = 3.3V 5%, V
= 2.5V 5%, T = -40°C to 85°C
A
DD
DDO
Parameter Symbol
Test Conditions
Minimum
Typical
Maximum Units
fMAX
Output Frequency
350
4
MHz
ns
CLK/nCLK; NOTE 1
ƒ 350MHz
ƒ 350MHz
2
2
Propagation
Delay
tPD
LVCMOS_CLK;
NOTE 2
4
ns
155.52MHz,
Integration Range:
12kHz – 20MHz
Buffer Additive Phase Jitter, RMS; refer
to Additive Phase Jitter Section
tjit
0.14
1
ps
Measured on the Rising Edge
@ VDDO/2
tsk(o)
Output Skew; NOTE 3, 7
100
1
ps
ns
Measured on the Rising Edge
@ VDDO/2
tsk(pp)
Part-to-Part Skew; NOTE 4, 7
tR / tF
odc
Output Rise/Fall Time
0.8V to 2V
0.1
45
1.0
55
5
ns
%
Output Duty Cycle
ƒ 200MHz, Ref = CLK/nCLK
tPZL, PZH
t
Output Enable Time; NOTE 5
Output Disable Time; NOTE 5
ns
ns
ns
tPLZ, PHZ
t
5
CLK_EN to CLK/nCLK
1
0
0
1
Clock Enable
Setup Time;
NOTE 6
tS
CLK_EN to
LVCMOS_CLK
ns
ns
ns
CLK/nCLK to CLK_EN
Clock Enable
Hold Time;
NOTE 6
tH
LVCMOS_CLK to
CLK_EN
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. Using
the same type of input on each device, the output is measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
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83948I-147 Data Sheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the
fundamental. When the required offset is specified, the phase noise
is called a dBc value, which simply means dBm at a specified offset
from the fundamental. By investigating jitter in the frequency
domain, we get a better understanding of its effects on the desired
application over the entire time record of the signal. It is
mathematically possible to calculate an expected bit error rate given
a phase noise plot.
fundamental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a Phase
noise plot and is most often the specified plot in many applications.
Phase noise is defined as the ratio of the noise power present in a
1Hz band at a specified offset from the fundamental frequency to the
power value of the fundamental. This ratio is expressed in decibels
(dBm) or a ratio of the power in the 1Hz band to the power in the
Additive Phase Jitter, RMS
@ 155.52MHz (12kHz to 20MHz) =
0.14ps (typical)
Offset From Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device.
This is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
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83948I-147 Data Sheet
Parameter Measurement Information
1.65V 5%
1.25V 5%
SCOPE
SCOPE
V
DD,
V
V
DD,
V
DDO
DDO
Qx
Qx
GND
GND
-1.65V 5%
-1.25V 5%
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
2.5V Core/2.5V LVCMOS Output Load AC Test Circuit
2.05V 5%
1.25V 5%
V
DD
SCOPE
V
DD
nCLK
CLK
V
VPP
VCMR
DDO
Cross Points
Qx
GND
GND
-1.25V 5%
3.3V Core/2.5V LVCMOS Output Load AC Test Circuit
Differential Input Level
Part 1
VDDO
VDDO
Qx
Qy
2
Qx
Qy
2
Part 2
VDDO
2
VDDO
2
tsk(o)
tsk(pp)
Part-to-Part Skew
Output Skew
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83948I-147 Data Sheet
Parameter Measurement Information, continued
2V
1.8V
2V
1.8V
tR
0.8V
0.6V
0.8V
0.6V
Q0:Q11
Q0:Q11
tR
tF
tF
3.3V Output Rise/Fall Time
2.5V Output Rise/Fall Time
VDD
2
CLK
VDDO
2
Q0:Q11
nCLK
CLK
tPW
tPERIOD
tPW
x 100%
odc =
VDDO
2
tPERIOD
Q0:Q11
➤
tPD
➤
Propagation Delay
Output Duty Cycle/Pulse Width/Period
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83948I-147 Data Sheet
Application Information
Wiring the Differential Input to Accept Single Ended Levels
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the
center of the input voltage swing. For example, if the input clock swing
is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 =
VDD
R1
1K
Single Ended Clock Input
0.609.
CLK
V_REF
nCLK
C1
0.1u
R2
1K
Figure 1. Single-Ended Signal Driving Differential Input
Recommendations for Unused Input and Output Pins
Inputs:
Outputs:
CLK/nCLK Inputs
LVCMOS Outputs
For applications not requiring the use of the differential input, both
CLK and nCLK can be left floating. Though not required, but for
additional protection, a 1k resistor can be tied from CLK to ground.
All unused LVCMOS output can be left floating. There should be no
trace attached.
CLK Input
For applications not requiring the use of a clock input, it can be left
floating. Though not required, but for additional protection, a 1k
resistor can be tied from the CLK input to ground.
LVCMOS Control Pins
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional protection.
A 1k resistor can be used.
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83948I-147 Data Sheet
Differential Clock Input Interface
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and
other differential signals. Both signals must meet the VPP and VCMR
input requirements. Figures 2A to 2F show interface examples for the
CLK/nCLK input driven by the most common driver types. The input
interfaces suggested here are examples only. Please consult with the
vendor of the driver component to confirm the driver termination
requirements. For example, in Figure 2A, the input termination
applies for IDT open emitter LVHSTL drivers. If you are using an
LVHSTL driver from another vendor, use their termination
recommendation.
3.3V
1.8V
Zo = 50Ω
CLK
Zo = 50Ω
nCLK
Differential
Input
LVHSTL
R1
50Ω
R2
50Ω
IDT
LVHSTL Driver
Figure 2A. CLK/nCLK Input Driven by an
IDT Open Emitter LVHSTL Driver
Figure 2B. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2C. CLK/nCLK Input Driven by a
3.3V LVPECL Driver
Figure 2D. CLK/nCLK Input Driven by a
3.3V LVDS Driver
2.5V
3.3V
3.3V
3.3V
2.5V
R3
R4
120Ω
120Ω
*R3
Zo = 60Ω
Zo = 60Ω
CLK
CLK
nCLK
nCLK
Differential
Input
Differential
Input
*R4
SSTL
HCSL
R1
R2
120Ω
120Ω
Figure 2E. CLK/nCLK Input Driven by a
3.3V HCSL Driver
Figure 2F. CLK/nCLK Input Driven by a
2.5V SSTL Driver
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83948I-147 Data Sheet
Reliability Information
Table 6. vs. Air Flow Table for a 32-Lead LQFP
JA
JA vs. Air Flow
Meters per Second
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
73.6°C/W
63.9°C/W
60.3°C/W
Transistor Count
The transistor count for 83948I-147 is: 1040
Pin compatible with the MPC9448
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83948I-147 Data Sheet
Package Outline and Package Dimension
Package Outline - Y Suffix for 32-Lead LQFP
Table 7. Package Dimensions for 32-Lead LQFP
JEDEC Variation: ABC - HD
All Dimensions in Millimeters
Symbol
Minimum
Nominal
Maximum
N
32
A
1.60
0.15
1.45
0.45
0.20
A1
A2
0.05
1.35
0.30
0.09
0.10
1.40
0.37
b
c
D & E
D1 & E1
D2 & E2
e
9.00 Basic
7.00 Basic
5.60 Ref.
0.80 Basic
0.60
L
0.45
0°
0.75
7°
ccc
0.10
Reference Document: JEDEC Publication 95, MS-026
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83948I-147 Data Sheet
Ordering Information
Table 8. Ordering Information
Part/Order Number
Marking
Package
Shipping Packaging
Tray
Temperature
-40C to 85C
-40C to 85C
83948AYI-147LF
83948AYI-147LFT
ICS948AI147L
ICS948AI147L
“Lead-Free” 32-Lead LQFP
“Lead-Free” 32-Lead LQFP
Tape & Reel
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83948I-147 Data Sheet
Revision History Sheet
Rev
Table
Page
Description of Change
Date
1
2
Features Section - added Lead-Free bullet.
Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical; and
T2
added 5 min. and 12 max to ROUT
Updated Single Ended Signal Driving Differential Input diagram.
.
B
11/21/05
7
Added Recommendations for Unused Input and Output Pins.
T8
10
Ordering Information Table - added lead-free part number, marking, and note.
1
5
6
Features Section - added Additive Phase Jitter bullet.
3.3V AC Characteristics Table - added Additive Phase Jitter.
3.3V AC Characteristics Table - added Additive Phase Jitter.
Added Additive Phase Jitter section.
T5A
T5B
C
D
7
1/15/08
4/1/09
11
12
Updated Differential Input Clock Interface section.
Updated Reliability Information.
Updated format throughout the datasheet.
T6
1
4
7
9
Features Section - added mix voltage to supply voltage bullet.
Added Mix DC Characteristics Power Supply Table.
Added Mix AC Characteristics Table.
Parameter Measurement Information Section - added 3.3V/2.5V LVCMOS
Output Load AC Test Circuit diagram.
T4C
T5C
T8
15
Ordering Information Table - deleted ICS prefix from Part/Order Number
column.
D
D
T1
T8
T8
2
Output supply pins, Changed VDD to VDDO
11/1/12
15
15
Removed leaded orderable parts from Ordering Information table
11/14/12
Fixed typo: removed extra “I” from orderable part number.
Updated Headers and Footers.
Updated Contact information.
D
D
7/17/14
3/30/16
17
Removed ICS from part number where needed.
Updated data sheet header and footer.
©2016 Integrated Device Technology, Inc
16
Revision D March 30, 2016
83948I-147 Data Sheet
Corporate Headquarters
6024 Silver Creek Valley Road
San Jose, CA 95138 USA
www.IDT.com
Sales
Tech Support
www.idt.com/go/support
1-800-345-7015 or 408-284-8200
Fax: 408-284-2775
www.IDT.com/go/sales
DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications
and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein
is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability,
or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties.
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of
IDT or their respective third party owners.
For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary.
Copyright ©2016 Integrated Device Technology, Inc. All rights reserved.
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